Pseudo-static random access memory write-in performance optimization method and device, computer equipment, storage medium and computer program product

Abstract

The invention relates to a pseudo-static random access memory write-in performance optimization method and device, computer equipment, a storage medium and a computer program product. The method comprises the steps of receiving JPEG compressed data and performing hardware decoding, writing decoded pixel data into an intermediate cache of an on-chip static random access memory according to a preset granularity, and dividing the intermediate cache into at least two logic partitions; generating a direct memory access transmission parameter aiming at each resolution and each format, a static random access memory source address fixed table and a continuous destination address mapping table of a pseudo-static random access memory frame cache; and starting direct memory access to carry data between the intermediate cache and the pseudo-static random access memory in a continuous burst mode, and controlling logic partitions of the intermediate cache to alternately receive decoded pixel data in a ping-pong mode and carry the decoded pixel data for direct memory access until all decoding and carrying processing of the JPEG compressed data is completed. By adopting the method, the write-in bandwidth utilization rate and the decoding performance can be improved.

Description

Technical Field

[0001] This application relates to the field of image processing and storage technology, and in particular to a method, apparatus, computer device, storage medium and computer program product for optimizing the write performance of pseudo-static random access memory. Background Technology

[0002] With the widespread application of embedded display systems in scenarios such as camera preview, human-computer interface interaction, and photo album browsing, the Joint Photographic Experts Group (JPEG) format has become the mainstream image compression standard in embedded systems due to its high compression ratio and good compatibility. In these systems, JPEG compressed images need to be hardware-decoded and written to the frame buffer, and then read and output to the display terminal by the display controller. The storage performance of the frame buffer directly affects the image decoding efficiency and display smoothness.

[0003] Most low- to mid-range system-on-chips (SoCs) use pseudo-static random access memory (PSRAM) as the core storage medium for their frame buffers. PSRAM offers advantages such as large capacity and low cost, but its internal row-column structure, similar to dynamic random access memory (DRAM), makes it extremely sensitive to address contiguousness and burst length. It can only achieve optimal bandwidth when write addresses are contiguous and the burst length meets requirements; if write addresses are fragmented and non-contiguous, it generates significant row switching and command overhead, resulting in a substantial decrease in bandwidth utilization.

[0004] Related technologies require changes to the PSRAM storage architecture or significant increases in hardware complexity and cost. This causes the PSRAM writing stage to become a performance bottleneck in the JPEG decoding and display chain, limiting the ability of low- and mid-range embedded systems to support high-resolution images and high refresh rate displays. Summary of the Invention

[0005] Therefore, it is necessary to provide a pseudo-static random access memory (PSRAM) write performance optimization method, apparatus, computer device, computer-readable storage medium, and computer program product that can improve write bandwidth utilization and decoding performance while maintaining the architecture, in order to address the above-mentioned technical problems.

[0006] Firstly, this application provides a method for optimizing the write performance of pseudo-static random access memory (PSRAM). The method includes:

[0007] The system receives JPEG compressed data and performs hardware decoding. The decoded pixel data is written into the on-chip static random access memory intermediate buffer according to a preset granularity. The intermediate buffer is divided into at least two logical partitions, which are used to receive the decoded pixel data transmitted in a ping-pong manner in turn.

[0008] Based on the image parameters of the JPEG compressed data and the preset decoding output pixel format, a direct memory access transmission parameter, a static random access memory source address fixed table, and a continuous destination address mapping table for pseudo-static random access memory frame buffer are generated for each resolution and format.

[0009] Based on the direct memory access transfer parameters, the static random access memory source address fixed table, and the continuous destination address mapping table, direct memory access is initiated to move data between the intermediate buffer and the pseudo-static random access memory in a continuous burst manner. The logical partitions of the intermediate buffer are controlled to alternately receive the decoded pixel data and provide it for direct memory access in a ping-pong manner until all decoding and moving of the JPEG compressed data is completed.

[0010] In some embodiments of the method, the total capacity of the static random access memory intermediate cache is 32KB, and the intermediate cache is divided into at least two logical partitions, including:

[0011] The cache is divided into two independent 16KB cache areas, each of which is further subdivided into 16 blocks of fixed size 1KB, and the addresses of the blocks are allocated in a continuously increasing manner.

[0012] The preset granularity includes one of the minimum coding unit and 16 rows of pixel blocks. The decoded pixel data is written into corresponding 1KB blocks in sequence according to the minimum coding unit or 16 rows of pixel blocks.

[0013] In some embodiments of the method, the image parameters include at least one of image height and image width. The step of generating direct memory access transfer parameters, a static random access memory source address fixed table, and a continuous destination address mapping table for each resolution and format, based on the image parameters of the JPEG compressed data and a preset decoded output pixel format, includes:

[0014] The image is divided into multiple groups based on its height, and the grouping results are determined. Each group is stored continuously in a pseudo-static random access memory.

[0015] Based on the image width and the storage capacity of the blocks, determine the number of whole blocks and the tail packet width in the width direction. Combined with the number of bytes occupied by each row of pixels corresponding to the preset decoding output pixel format and the row offset, determine the single block transmission length of direct memory access.

[0016] Based on the grouping results, the number of whole blocks, the tail packet width, and the direct memory access single block transmission length, construct a static random access memory source address fixed table and a pseudo-static random access memory frame buffer continuous destination address mapping table.

[0017] In some embodiments of the method, each element in the continuous destination address mapping table corresponds to the pseudo-static random access memory destination address starting position of a direct memory access linked list node.

[0018] In some embodiments of the method, the method further includes:

[0019] If the decoded pixel data is written to any logical partition of the intermediate buffer, a JPEG decoding interruption is triggered, and a JPEG decoding interruption flag is generated.

[0020] In response to a JPEG decoding interrupt, the JPEG decoding interrupt flag is cleared and the current JPEG decoding interrupt is temporarily masked. Based on the current block number, the address information of the corresponding group is read from the source address fixed table and the continuous destination address mapping table of the static random access memory. The linked list node of direct memory access is configured, and direct memory access is started to move data from the currently full logical partition to the pseudo-static random access memory.

[0021] In some embodiments of the method, the method further includes:

[0022] When the current batch of data is moved by direct memory access, a direct memory access interrupt is triggered, and a direct memory access interrupt flag is generated.

[0023] In response to a direct memory access interrupt, clear the direct memory access interrupt flag and increment the block number by 1;

[0024] Determine whether the incremented block number has reached the total number of groups. If not, remove the JPEG decoding interrupt mask, switch from the logical partition where the data has been transferred to another logical partition, and write the next batch of decoded pixel data to the switched logical partition; otherwise, set the data processing completion flag.

[0025] Repeat the process of JPEG decoding interrupt triggering, direct memory access configuration startup, direct memory access interrupt response and partition switching until the decoding and transfer of all batches of data are completed.

[0026] According to a second aspect of the present disclosure, a pseudo-static random access memory (PSRAM) write performance optimization apparatus is provided. The apparatus includes:

[0027] The decoding buffer module is used to receive JPEG compressed data and perform hardware decoding. The decoded pixel data is written into the on-chip static random access memory intermediate buffer according to a preset granularity. The intermediate buffer is divided into at least two logical partitions, which are used to receive the decoded pixel data transmitted in a ping-pong manner in turn.

[0028] The address table generation module is used to generate, based on the image parameters of the JPEG compressed data and the preset decoding output pixel format, direct memory access transmission parameters, static random access memory source address fixed table and pseudo static random access memory frame buffer continuous destination address mapping table for each resolution and format.

[0029] The processing module is used to initiate direct memory access to move data between the intermediate buffer and pseudo-static random access memory in a continuous burst manner based on the direct memory access transmission parameters, the static random access memory source address fixed table, and the continuous destination address mapping table. It controls the logical partitions of the intermediate buffer to alternately receive the decoded pixel data and provide it for direct memory access to move in a ping-pong manner until all decoding and moving of the JPEG compressed data is completed.

[0030] According to a third aspect of the present disclosure, a computer device is provided. The computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program implementing the above-described pseudo-static random access memory write performance optimization method.

[0031] According to a fourth aspect of the present disclosure, a computer-readable storage medium is provided. The computer-readable storage medium stores a computer program thereon, which, when executed by a processor, implements the above-described pseudo-static random access memory write performance optimization method.

[0032] According to a fifth aspect of the present disclosure, a computer program product is provided. The computer program product includes a computer program that, when executed by a processor, implements the above-described pseudo-static random access memory write performance optimization method.

[0033] The pseudo-static random access memory (PSRAM) write performance optimization scheme provided in this application embodiment can write JPEG decoding output data into the on-chip SRAM intermediate cache, then calculate the corresponding target continuous address range in the PSRAM, and configure a general-purpose DMA to write the data in the intermediate cache into the PSRAM in a continuous burst manner. This improves the PSRAM write bandwidth utilization without significantly increasing hardware complexity. By combining hardware caching, software address rearrangement, and DMA secondary transfer, write merging is achieved with minimal hardware modifications. This effectively solves the problems of low write efficiency and poor bandwidth utilization in existing JPEG decoding direct PSRAM writes, achieving JPEG decoding write performance optimization that balances performance, cost, and implementation complexity.

[0034] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0035] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure, and are not intended to unduly limit this disclosure.

[0036] Figure 1 This is a flowchart illustrating a pseudo-static random access memory (PSRAM) write performance optimization method according to an exemplary embodiment.

[0037] Figure 2 This is a block diagram illustrating the implementation architecture of a pseudo-static random access memory write performance optimization method according to an exemplary embodiment.

[0038] Figure 3 This is a schematic diagram of logical partition sequential writing in a pseudo-static random access memory write performance optimization method according to an exemplary embodiment.

[0039] Figure 4 This is an interrupt triggering flowchart illustrating a pseudo-static random access memory write performance optimization method according to an exemplary embodiment;

[0040] Figure 5 This is a DMA-JPEG handshake timing diagram illustrated according to an exemplary embodiment;

[0041] Figure 6 This is a structural block diagram of a pseudo-static random access memory write performance optimization apparatus according to an exemplary embodiment;

[0042] Figure 7 This is a diagram illustrating the internal structure of a computer device according to an exemplary embodiment. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0044] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure. The terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, product, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, product, or apparatus. Without further limitations, the presence of other identical or equivalent elements in a process, method, product, or apparatus that includes said elements is not excluded. For example, the use of terms such as "first," "second," etc., to denote names does not indicate any specific order.

[0045] In some embodiments provided in this disclosure, the execution of the pseudo-static random access memory (PSRAM) write performance optimization method can be controlled by a unified controller or by multiple controllers. These controllers may include controllers on local terminals or controllers on remote servers. In some embodiments, the controllers on local terminals and servers may jointly assist in completing the PRAM write performance optimization control processing. The local terminal mentioned in this disclosure may include, but is not limited to, various robotic devices, vehicle-mounted devices, personal computers, laptops, smartphones, tablets, wearable devices, medical devices, VR (Virtual Reality) devices, etc. The server may also be a server, server cluster, distributed subsystem, cloud processing platform, server containing blockchain nodes, or a combination thereof. The controllers described in this disclosure may include various control units capable of implementing logic processing functions, including but not limited to CPU (Central Processing Unit), PLC (Programmable Logic Controller), ECU (Electronic Control Unit), MCU (Microcontroller Unit), FPGA (Field Programmable Gate Array), and CPLD (Complex Programmable Logic Device), as well as controllers composed of one or more logic function units, chips, etc.

[0046] In some embodiments of this disclosure, a method for optimizing pseudo-static random access memory write performance is provided, combined with... Figure 1 and Figure 2 As shown, it includes the following steps:

[0047] S20. Receive JPEG compressed data and perform hardware decoding. Write the decoded pixel data into the on-chip static random access memory intermediate buffer according to a preset granularity. The intermediate buffer is divided into at least two logical partitions. The logical partitions are used to receive the decoded pixel data transmitted in a ping-pong manner in turn.

[0048] Static Random-Access Memory (SRAM) is a semiconductor memory based on bistable flip-flops. It stores data through transistor states and can maintain storage while powered on without the need for refresh circuits. Data is lost when power is off.

[0049] Intermediate buffers typically refer to high-speed static random access memory (SRAM) resources integrated within a system-on-a-chip (SoC) for temporarily storing pixel data between JPEG hardware decoding output and pseudo-static random access memory (PSRAM) writes. Logical partitioning typically refers to the logical division of the intermediate buffer, dividing the entire intermediate buffer into at least two independent storage areas. Each partition can independently receive decoded data or be used for direct memory access to move data. By alternating between partitions, a ping-pong mechanism is implemented to ensure that the decoding and data movement processes are executed in parallel.

[0050] S22. Based on the image parameters of the JPEG compressed data and the preset decoding output pixel format, generate direct memory access transmission parameters, static random access memory source address fixed table and pseudo static random access memory frame buffer continuous destination address mapping table for each resolution and format.

[0051] Image parameters typically refer to the inherent attributes of the image contained in JPEG compressed data, including image height and width, and are the core basis for calculating data transmission parameters and address mapping tables. Preset decoded output pixel format typically refers to the storage format of the JPEG decoded pixel data pre-defined according to business requirements, determining the number of bytes occupied by each pixel. Direct Memory Access (DMA) transfer parameters typically refer to the transfer-related parameters configured for the DMA controller, calculated based on image parameters and pixel format. Static Random Access Memory (SRAM) source address fixed table typically refers to a pre-defined table recording the starting addresses of each block in the intermediate buffer, with each table element corresponding one-to-one with the logical partitions and blocks of the intermediate buffer. Continuous destination address mapping table typically refers to the address mapping table constructed for the PSRAM frame buffer.

[0052] S24. Based on the direct memory access transmission parameters, the static random access memory source address fixed table, and the continuous destination address mapping table, direct memory access is initiated to move data between the intermediate buffer and the pseudo static random access memory in a continuous burst manner. The logical partitions of the intermediate buffer are controlled to alternately receive the decoded pixel data and provide it for direct memory access in a ping-pong manner until all decoding and moving of the JPEG compressed data is completed.

[0053] Based on the generated direct memory access transfer parameters, source address fixed table, and destination address mapping table, the direct memory access controller is configured to initiate data transfer in a linked list manner. When the JPEG decoder writes data to SRAM_B, the DMA reads data from SRAM_A in a continuous burst manner and writes it to the PSRAM frame buffer according to the destination address mapping table. After SRAM_B is full, the DMA switches to SRAM_B to transfer data, and the JPEG decoder switches back to SRAM_A to write the next batch of data. This process is repeated until the decoding and transfer of the entire frame are completed.

[0054] In some embodiments of this disclosure, JPEG decoding output data can be written to the on-chip SRAM intermediate buffer, and then the corresponding target continuous address range in the PSRAM can be calculated. A general-purpose DMA can be configured to write the data in the intermediate buffer to the PSRAM in a continuous burst manner, thereby improving the PSRAM write bandwidth utilization without significantly increasing hardware complexity. By combining hardware caching, software address rearrangement, and DMA secondary transfer, write merging can be achieved with minimal hardware modifications. This can effectively solve the problems of low write efficiency and poor bandwidth utilization that exist when directly writing JPEG decoding data to PSRAM, and achieve JPEG decoding write performance optimization that balances performance, cost, and implementation complexity.

[0055] In some embodiments of this disclosure, the total capacity of the static random access memory intermediate cache is 32KB, and the intermediate cache is divided into at least two logical partitions, including:

[0056] The cache is divided into two independent 16KB cache areas, each of which is further subdivided into 16 blocks of fixed size 1KB, and the addresses of the blocks are allocated in a continuously increasing manner.

[0057] The preset granularity includes one of the minimum coding unit and 16 rows of pixel blocks. The decoded pixel data is written into corresponding 1KB blocks in sequence according to the minimum coding unit or 16 rows of pixel blocks.

[0058] In some implementations, refer to Figure 3 The on-chip SRAM intermediate cache has a total capacity of 32KB, logically divided into two independent 16KB cache areas (SRAM_A and SRAM_B). Each 16KB cache area is further subdivided into 16 fixed-size 1KB blocks, with block addresses allocated in a continuously increasing order. For example, the block addresses of SRAM_A are SRAM_BASE_A+0×1K, SRAM_BASE_A+1×1K, ..., SRAM_BASE_A+15×1K, and the block addresses of SRAM_B are allocated similarly. In some examples, SRAM_A (16KB): starting at SRAM_BASE_A, is used for batches 1, 2, 3, ... of part A of the JPEG decoder output; SRAM_B (16KB): starting at SRAM_BASE_B, is used for batches 1, 2, 3, ... of part B of the JPEG decoder output.

[0059] In other implementations, the software can construct a fixed source address table during the initialization phase. For example, fixed_src[0][i] corresponds to the starting address of the i-th 1KB block of SRAM_A; fixed_src[1][i] corresponds to the starting address of the i-th 1KB block of SRAM_B. The JPEG decoding module writes data into the 16 1KB blocks of a certain SRAM half-area according to a fixed output format (e.g., 16 rows × several pixels in width as a batch). While the DMA reads data from this half-area, the JPEG decoding module can write the next batch of data to the other half-area, realizing ping-pong buffering between SRAM_A / SRAM_B and improving parallelism.

[0060] In some embodiments of this disclosure, continuously increasing block addresses provide a basis for continuous burst access of DMA, reducing DMA address switching overhead and further improving transmission efficiency; the 1KB fixed block design adapts to DMA linked list node configuration, avoiding low cache utilization due to excessively large blocks or increased DMA configuration overhead due to excessively small blocks, thereby improving cache utilization.

[0061] In some embodiments of this disclosure, the image parameters include at least one of image height and image width, and S22 includes:

[0062] The image is divided into multiple groups based on its height, and the grouping results are determined. Each group is stored continuously in a pseudo-static random access memory.

[0063] Based on the image width and the storage capacity of the blocks, determine the number of whole blocks and the tail packet width in the width direction. Combined with the number of bytes occupied by each row of pixels corresponding to the preset decoding output pixel format and the row offset, determine the single block transmission length of direct memory access.

[0064] Based on the grouping results, the number of whole blocks, the tail packet width, and the direct memory access single block transmission length, construct a static random access memory source address fixed table and a pseudo-static random access memory frame buffer continuous destination address mapping table.

[0065] In some implementations, the number of bytes per pixel can be determined based on the output format. For example, RGB565 / BGR565: 2 bytes per pixel; RGB888 / BGR888: 3 bytes per pixel; ARGB888 / ABGR888 / BGRA888 / RGBA888: 4 bytes per pixel. The number of valid pixels that can be accommodated in each 1KB block is related to the output format. Since the output of the JPEG hardware decoding module is usually in 16-line units (i.e., setting JPEG_OUT_MCU_LEN=16), the following relationship can be used to calculate how many MCU width units (fixed MCU upper limit) can be placed in each 1KB block, referring to the following formula (1):

[0066] (1)

[0067] In equation (1), 1024 is the length of a single SRAM block (bytes), and 16 is the number of rows processed per batch.

[0068] The number of whole blocks and the width of the tail packet can also be calculated. For example, if the image width is pic_w pixels, the number of whole blocks (each block transmits fixed_datatype_len × 16 pixels) can be calculated using the following formula (2):

[0069] (2)

[0070] The width of the tail bag is as follows (3):

[0071] (3)

[0072] The number of integer blocks in the height direction and the tail packet height can be set to the image height as pic_h pixels, and the number of integer blocks in the height direction can be determined by the following formula (4):

[0073] (4)

[0074] The height of the tail pack in the vertical direction can be referenced by the following formula (5):

[0075] (5)

[0076] The number of words transferred in a single DMA block [in 64-bit (8-byte) units], for a fixed-width complete packet, the DMA transfer length is given by the following formula (6):

[0077] (6)

[0078] For the tail packet in the width direction, since it may not be perfectly aligned to 8 bytes, we can check if it is divisible. If it is not divisible, we can round up to get axi_len_2, ensuring that the DMA is transmitted in 64-bit alignment.

[0079] In some implementations, to simplify processing, the frame buffer is stored compactly, and the line step size can be referred to as the following formula (7):

[0080] (7)

[0081] In another implementation, for common resolutions and pixel formats (such as 480×272RGB565, 800×480RGB888, 1280×720RGB565, etc.), the corresponding parameter structure and destination address offset table can be generated offline in advance, and then the software can directly load and superimpose the actual base address at runtime, thereby reducing the amount of runtime calculation and improving configuration efficiency.

[0082] In some embodiments of this disclosure, image height grouping and width-direction block segmentation can be combined to ensure continuous PSRAM destination addresses, completely solve the JPEG decoding output address fragmentation problem, and reduce line switching overhead; it can accurately calculate DMA transfer length, taking into account both transfer efficiency and address alignment requirements, avoiding data loss or redundant transfer, and improving transfer accuracy; it supports dynamic adaptation to arbitrary resolutions and pixel formats, without the need for customized hardware for specific resolutions.

[0083] In some embodiments of this disclosure, each element in the continuous destination address mapping table corresponds to the pseudo-static random access memory destination address starting position of a direct memory access linked list node.

[0084] In some implementations, after determining the chunking method and transmission length, a destination address mapping table fixed_dst[i][j] can be constructed. Here, dimension i represents the batch / block sequence number (0~arraylen-1) obtained by dividing the data by width × height, and dimension j represents the j-th row (0~15) within a batch of 16 rows. Each element in the table corresponds to the starting position of the PSRAM destination address of a DMA linked list node.

[0085] The construction rules can be configured as follows: In the height direction, every 16 rows are considered a group, each group is stored contiguously in PSRAM, and groups are distinguished from each other; within each height group, a row is divided into several contiguous segments in the width direction by the number of whole width blocks w16_cnt (or w16_cnt+1 including the tail packet), each segment corresponding to a DMA block; using the above axi_len_1 or axi_len_2 in conjunction with w_offset, as follows: Calculate fixed_dst[i][j], where base_addr is the starting address of the frame buffer.

[0086] During the DMA configuration phase, the software reads all elements corresponding to the current batch in the mapping table and configures a DMA linked list node for each element: the destination address field of the node is directly assigned the value fixed_dst[i][j], the source address field reads the corresponding block address from the SRAM source address fixed table, the transfer length field is assigned the preset DMA single block transfer length, and the last node is set with the "LAST" flag. The DMA controller executes the node transfer sequentially according to the linked list order, realizing the burst writing of multiple blocks of data to consecutive addresses in PSRAM.

[0087] In some embodiments of this disclosure, the mapping table can correspond one-to-one with DMA linked list nodes, simplifying DMA configuration logic and reducing software configuration overhead; the linked list nodes are executed in the order of the mapping table, ensuring that the PSRAM write addresses are continuous without jumps, maximizing PSRAM bandwidth utilization; the two-dimensional array structure of the mapping table is easy to expand, supports flexible configuration of multiple batches and multiple blocks, and adapts to different sizes of intermediate cache and transmission requirements.

[0088] In some embodiments of this disclosure, the method further includes:

[0089] If the decoded pixel data is written to any logical partition of the intermediate buffer, a JPEG decoding interruption is triggered, and a JPEG decoding interruption flag is generated.

[0090] In response to a JPEG decoding interrupt, the JPEG decoding interrupt flag is cleared and the current JPEG decoding interrupt is temporarily masked. Based on the current block number, the address information of the corresponding group is read from the source address fixed table and the continuous destination address mapping table of the static random access memory. The linked list node of direct memory access is configured, and direct memory access is started to move data from the currently full logical partition to the pseudo-static random access memory.

[0091] In some implementations, refer to Figure 4The JPEG hardware begins writing decoded pixel data from one half of SRAM_A or SRAM_B. Once the first batch of JPEG output data fills a 16KB block in the buffer, a JPEG accelerator interrupt is generated, and the JPEG decoding interrupt flag (JPEG_IRQ_FLAG=1) is set in the status register. In response to the JPEG decoding interrupt, the JPEG_IRQ_FLAG flag is cleared, temporarily disabling the JPEG decoding interrupt (to prevent repeated interrupt triggering from the same partition); the current block number (initially 0) is read; the starting addresses of the 16 blocks corresponding to SRAM_A are read from the SRAM source address fixed table; and the 16 PSRAM destination addresses corresponding to the 0th batch are read from the continuous destination address mapping table; a DMA linked list node is configured for each block, setting parameters such as source address, destination address, and transfer length to construct a complete DMA linked list; the first DMA transfer is initiated, moving the buffered data of the current batch to the corresponding location in the PSRAM.

[0092] In some embodiments of this disclosure, an interrupt is triggered based on the cache being full to ensure the integrity of the data being transferred by DMA and to avoid transmission errors caused by starting transmission before the data is fully written; the current interrupt is masked during interrupt response to prevent repeated triggering of the same partition, thereby improving the stability and reliability of the control logic; address information is read directly from the address table without real-time calculation, shortening interrupt processing time and ensuring the parallel efficiency of decoding and transfer.

[0093] In some embodiments of this disclosure, the method further includes:

[0094] When the current batch of data is moved by direct memory access, a direct memory access interrupt is triggered, and a direct memory access interrupt flag is generated.

[0095] In response to a direct memory access interrupt, clear the direct memory access interrupt flag and increment the block number by 1;

[0096] Determine whether the incremented block number has reached the total number of groups. If not, remove the JPEG decoding interrupt mask, switch from the logical partition where the data has been transferred to another logical partition, and write the next batch of decoded pixel data to the switched logical partition; otherwise, set the data processing completion flag.

[0097] Repeat the process of JPEG decoding interrupt triggering, direct memory access configuration startup, direct memory access interrupt response and partition switching until the decoding and transfer of all batches of data are completed.

[0098] In some implementations, a DMA interrupt is triggered after the DMA completes the block transfer configured in the current linked list. In response to a DMA interrupt, the DMA general and channel interrupt status is read and cleared, and it is determined whether the sequence number of the currently completed blocks has reached arraylen. If all blocks have been completed, the DMA completion flag is set, and the subsequent main process can end its waiting state accordingly. If not all blocks have been completed, the process waits for the JPEG module to indicate that the current batch of data has been written (e.g., polling the flag in the JPEG status register), clears the corresponding interrupt status of the JPEG accelerator, increments the block sequence number jpeg_w_irq, calls the DMA calculation and start function again based on the new block sequence number to configure the source / destination address for the next batch, and starts the next round of DMA transfer. This forms two processes: JPEG output data → triggering a JPEG interrupt → software configuration and DMA start; DMA transfer completion → triggering a DMA interrupt → software clearing the JPEG status and starting the next round of DMA. These two processes alternate until the entire image transfer is completed.

[0099] In some embodiments of this disclosure, automatic block number updating and partition switching are achieved based on DMA interrupts, which significantly improves processing efficiency; by calculating transport parameters and generating address rearrangement tables, DMA can be driven to perform multi-block transfers in a linked list manner, thereby enabling continuous burst writing to PSRAM.

[0100] In some implementations, refer to Figure 5 The DMA linked list and interrupt handshake mechanism can include a channel initialization phase, a linked list node configuration phase, and a DMA-JPEG alternating operation timing section. The channel initialization phase can include: resetting the AXIDMA module and enabling AXIDMA globally; configuring the channel's source / destination multi-block transfer mode to "LinkedList"; configuring the transfer type to memory to memory, source / destination address incrementing, transfer width to 64 bits, and burst length to a fixed value (e.g., 16 beats); setting registers such as BLOCK_TS and LLP start address; and enabling channel-level DMA completion interrupts.

[0101] The linked list node configuration phase may include: for 16 1KB blocks to be transferred within a batch, setting the following for each node: source address: from fixed_src[current SRAM half][node index]; destination address: from fixed_dst[current block number][node index]; BLOCK_TS: equal to axi_len_1 or axi_len_2 corresponding to the current batch; control field: marks the node as valid, and sets the "LAST" flag on the last node; NEXT_LLI: points to the next node in the linked list.

[0102] The DMA-JPEG alternating timing sequence can be as follows: JPEG fills the corresponding 1KB block in SRAM_A with the first batch of data → triggering a JPEG interrupt; the software configures the DMA list in the JPEG interrupt and starts DMA1 to move data from SRAM_A to PSRAM; DMA1 transfers data from SRAM_A, while JPEG starts writing the next batch of data to SRAM_B; DMA1 completes the current batch transfer → triggering a DMA interrupt; the software clears the JPEG status, updates the block sequence number, and reconfigures DMA in the DMA interrupt to move data from SRAM_B to PSRAM; when DMA2 is running, JPEG switches back to SRAM_A to write the next batch of data, and so on, until the entire image transfer is complete. This DMA-JPEG alternating pipeline combined with SRAM ping-pong buffering timing design can fully overlap the JPEG decoding and DMA transfer processes, improving overall throughput.

[0103] In the above embodiments, the parameter and address tables can be calculated and generated at runtime. For common image resolutions and output formats, an optimized method for pre-configured parameter tables is also provided: parameter structures are established for common resolution combinations (such as 480×272, 480×320, 640×480, 800×480, 1024×600, 1280×720, 1280×800, etc.), recording: image width, height; bytes per pixel; number of whole blocks and tail packets in the width and height directions; AXI transmission lengths axi_len_1, axi_len_2; and other necessary parameters. For each set of resolutions and output formats, a destination address offset table can be generated offline, for example, fixed_dst_800480_RGB565[i][j], whose content is the offset calculated from the start address of the frame buffer. During the software initialization phase, based on the parsed width, height, and data format, the corresponding parameter structure and address offset table are selected using width and height keys. The frame buffer base address is then added to the offset table to obtain the complete `fixed_dst[i][j]`. For resolutions not in the pre-configured table, the process reverts to the general calculation flow, dynamically calculating parameters and the mapping table. This design ensures efficient configuration for common resolutions while retaining adaptability to arbitrary resolutions.

[0104] The pseudo-static random access memory (PSRAM) write performance optimization methods disclosed herein can write JPEG decoding output data into the on-chip SRAM intermediate buffer, then calculate the corresponding target continuous address range in the PSRAM, and configure a general-purpose DMA to write the data in the intermediate buffer into the PSRAM in a continuous burst manner, thereby improving the PSRAM write bandwidth utilization without significantly increasing hardware complexity. By combining hardware caching, software address rearrangement, and DMA secondary transfer, write merging is achieved with minimal hardware modifications. This effectively solves the problems of low write efficiency and poor bandwidth utilization that exist when directly writing JPEG decoding data into the PSRAM, achieving JPEG decoding write performance optimization that balances performance, cost, and implementation complexity.

[0105] It is understood that the various embodiments of the methods described in this specification are presented in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. Related details can be found in the descriptions of other method embodiments.

[0106] It should be understood that although the steps in the flowcharts shown in the accompanying drawings are displayed sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the accompanying drawings may include multiple steps or stages, which are not necessarily completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least a portion of the steps or stages of other steps.

[0107] Based on the description of the pseudo-static random access memory (PSRAM) write performance optimization method embodiments described above, this disclosure also provides a pseudo-static random access memory (PSRAM) write performance optimization apparatus for implementing the aforementioned PPSRAM write performance optimization method. The apparatus may include a system (including a distributed system), software (application), module, component, controller, server, terminal, etc., using the method described in the embodiments of this specification, combined with necessary implementation hardware. Based on the same innovative concept, the apparatuses in one or more embodiments provided in this disclosure are as described in the following embodiments. Since the implementation schemes and methods for solving the problem by the apparatus are similar, the implementation of specific apparatuses in the embodiments of this specification can refer to the implementation of the foregoing method, and repeated details will not be repeated. As used below, the terms "unit" or "module" can refer to a combination of software and / or hardware that implements a predetermined function. Although the apparatuses described in the following embodiments are preferably implemented in software, hardware implementations, or a combination of software and hardware, are also possible and contemplated.

[0108] Figure 6 This is a schematic block diagram illustrating a pseudo-static random access memory (PSRAM) write performance optimization device according to an exemplary embodiment. The device can be the aforementioned terminal, a server, or a module, component, device, control unit, etc., integrated into the terminal. For details, please refer to... Figure 6 The device 100 may include a decoding buffer module 120, an address table generation module 140, and a processing module 160. The decoding buffer module 120 receives JPEG compressed data and performs hardware decoding, writing the decoded pixel data into an on-chip static random access memory (SRAM) intermediate buffer at a preset granularity. The intermediate buffer is divided into at least two logical partitions, which are used to alternately receive the decoded pixel data transmitted via a ping-pong method. The address table generation module 140 generates direct memory access (DMI) transfer parameters, a fixed source address table for SRAM, and a continuous destination address mapping table for pseudo-static random access memory (PSRAM) frame buffers for each resolution and format, based on the image parameters of the JPEG compressed data and a preset decoded output pixel format. The processing module 160, based on the DMI transfer parameters, the fixed source address table, and the continuous destination address mapping table, initiates direct memory access to move data between the intermediate buffer and PRAM in a continuous burst manner, controlling the logical partitions of the intermediate buffer to alternately receive the decoded pixel data and provide DMI for transfer in a ping-pong manner until all decoding and transfer processing of the JPEG compressed data is completed.

[0109] The modules in the aforementioned pseudo-static random access memory (PSRAM) write performance optimization device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the computer device's memory as software, so that the processor can call and execute the operations corresponding to each module.

[0110] In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 7 As shown, the computer device includes a processor, memory, communication interface, display screen, and input device connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, NFC (Near Field Communication), or other technologies. When the computer program is executed by the processor, it implements a pseudo-static random access memory (PSRAM) write performance optimization method.

[0111] Those skilled in the art will understand that Figure 7 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0112] Based on the foregoing description of the relevant methods and apparatus embodiments, this disclosure also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, it implements the pseudo-static random access memory write performance optimization method described in any embodiment of this specification.

[0113] Based on the foregoing description of the relevant methods and apparatus embodiments, this disclosure also provides a computer-readable storage medium that, when the instructions in the computer-readable storage medium are executed by the processor of a computer device, enables the computer device to implement the pseudo-static random access memory write performance optimization method as described in any embodiment of this disclosure.

[0114] Based on the foregoing description of the relevant methods and apparatus embodiments, this disclosure also provides a computer program product, including a computer program that, when executed by a processor, implements the pseudo-static random access memory write performance optimization method described in any embodiment of this specification.

[0115] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on its differences from other embodiments. In particular, hardware + program embodiments are relatively simple in description because they are fundamentally similar to method embodiments; relevant parts can be referred to the descriptions in the method embodiments.

[0116] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0117] It should be noted that the apparatus, computer equipment, storage medium, and computer program products described above may also include other implementation methods according to the description of the method embodiments. Specific implementation methods can be found in the description of the relevant method embodiments. Furthermore, new embodiments formed by combinations of features from various methods, apparatuses, devices, and server embodiments still fall within the scope of this disclosure and will not be elaborated upon here.

[0118] For ease of description, the above devices are described in terms of function, divided into various modules. Of course, when implementing one or more of these specifications, the functions of each module can be implemented in the same or different software and / or hardware, or a module that performs the same function can be implemented by a combination of multiple sub-modules or sub-units. The device embodiments described above are merely illustrative. For example, the division of modules or units is only a logical functional division; in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling and communication connections between the devices or units shown or described can be implemented through direct and / or indirect coupling / connection, through standard or custom interfaces or protocols, and can be implemented electrically, mechanically, or in other forms.

[0119] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0120] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope.

Claims

1. A method for optimizing write performance of pseudo-static random access memory, characterized in that, The method includes: The system receives JPEG compressed data and performs hardware decoding. The decoded pixel data is written into the on-chip static random access memory intermediate buffer according to a preset granularity. The intermediate buffer is divided into at least two logical partitions, which are used to receive the decoded pixel data transmitted in a ping-pong manner in turn. Based on the image parameters of the JPEG compressed data and the preset decoding output pixel format, a direct memory access transmission parameter, a static random access memory source address fixed table, and a continuous destination address mapping table for pseudo-static random access memory frame buffer are generated for each resolution and format. Based on the direct memory access transfer parameters, the static random access memory source address fixed table, and the continuous destination address mapping table, direct memory access is initiated to move data between the intermediate buffer and the pseudo-static random access memory in a continuous burst manner. The logical partitions of the intermediate buffer are controlled to alternately receive the decoded pixel data and provide it for direct memory access in a ping-pong manner until all decoding and moving of the JPEG compressed data is completed.

2. The method according to claim 1, characterized in that, The total capacity of the static random access memory intermediate cache is 32KB, and the intermediate cache is divided into at least two logical partitions, including: The cache is divided into two independent 16KB cache areas, each of which is further subdivided into 16 blocks of fixed size 1KB, and the addresses of the blocks are allocated in a continuously increasing manner. The preset granularity includes one of the minimum coding unit and 16 rows of pixel blocks. The decoded pixel data is written into corresponding 1KB blocks in sequence according to the minimum coding unit or 16 rows of pixel blocks.

3. The method according to claim 1, characterized in that, The image parameters include at least one of image height and image width. The step of generating direct memory access transfer parameters, a static random access memory source address fixed table, and a continuous destination address mapping table for each resolution and format, based on the image parameters of the JPEG compressed data and a preset decoded output pixel format, includes: The image is divided into multiple groups based on its height, and the grouping results are determined. Each group is stored continuously in a pseudo-static random access memory. Based on the image width and the storage capacity of the blocks, determine the number of whole blocks and the tail packet width in the width direction. Combined with the number of bytes occupied by each row of pixels corresponding to the preset decoding output pixel format and the row offset, determine the single block transmission length of direct memory access. Based on the grouping results, the number of whole blocks, the tail packet width, and the direct memory access single block transmission length, construct a static random access memory source address fixed table and a pseudo-static random access memory frame buffer continuous destination address mapping table.

4. The method according to claim 3, characterized in that, Each element in the continuous destination address mapping table corresponds to the starting position of the pseudo-static random access memory destination address of a direct memory access linked list node.

5. The method according to claim 1, characterized in that, The method further includes: If the decoded pixel data is written to any logical partition of the intermediate buffer, a JPEG decoding interruption is triggered, and a JPEG decoding interruption flag is generated. In response to a JPEG decoding interrupt, the JPEG decoding interrupt flag is cleared and the current JPEG decoding interrupt is temporarily masked. Based on the current block number, the address information of the corresponding group is read from the source address fixed table and the continuous destination address mapping table of the static random access memory. The linked list node of direct memory access is configured, and direct memory access is started to move data from the currently full logical partition to the pseudo-static random access memory.

6. The method according to claim 5, characterized in that, The method further includes: When the current batch of data is moved by direct memory access, a direct memory access interrupt is triggered, and a direct memory access interrupt flag is generated. In response to a direct memory access interrupt, clear the direct memory access interrupt flag and increment the block number by 1; Determine whether the incremented block number has reached the total number of groups. If not, remove the JPEG decoding interrupt mask, switch from the logical partition where the data has been transferred to another logical partition, and write the next batch of decoded pixel data to the switched logical partition; otherwise, set the data processing completion flag. Repeat the process of JPEG decoding interrupt triggering, direct memory access configuration startup, direct memory access interrupt response and partition switching until the decoding and transfer of all batches of data are completed.

7. A pseudo-static random access memory (PSRAM) write performance optimization device, characterized in that, The device includes: The decoding buffer module is used to receive JPEG compressed data and perform hardware decoding. The decoded pixel data is written into the on-chip static random access memory intermediate buffer according to a preset granularity. The intermediate buffer is divided into at least two logical partitions, which are used to receive the decoded pixel data transmitted in a ping-pong manner in turn. The address table generation module is used to generate, based on the image parameters of the JPEG compressed data and the preset decoding output pixel format, direct memory access transmission parameters, static random access memory source address fixed table and pseudo static random access memory frame buffer continuous destination address mapping table for each resolution and format. The processing module is used to initiate direct memory access to move data between the intermediate buffer and pseudo-static random access memory in a continuous burst manner based on the direct memory access transmission parameters, the static random access memory source address fixed table, and the continuous destination address mapping table. It controls the logical partitions of the intermediate buffer to alternately receive the decoded pixel data and provide it for direct memory access to move in a ping-pong manner until all decoding and moving of the JPEG compressed data is completed.

8. A computer device, characterized in that, It includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the steps of the method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, It stores a computer program thereon, which, when executed by a processor, implements the steps of the method according to any one of claims 1 to 6.

10. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the steps of the method according to any one of claims 1 to 6.

Images