Multiplier generation method, multiplier and multiplication system

Abstract

The invention provides a multiplier generation method, a multiplier and a multiplication system, and the method comprises the steps: obtaining a first symbol configuration signal and a second symbol configuration signal; generating a register transfer level description of the multiplier circuit; wherein the register transfer level description comprises a first part description and a second part description; the first part description is configured to be behavior-level description; the behavior level description allows the synthesizer to perform automatic optimization; the second partial description is configured as a structure retention description; the structure keeping description forbids the synthesizer to perform logic recombination; and calling a synthesizer to carry out logic synthesis on the register transfer level description to generate a gate level netlist of the multiplier circuit. According to the scheme, the unsigned multiplication core is delivered to the synthesizer in a behavior level through the hierarchical description strategy, so that the synthesizer can automatically map the optimal multiplier hard core according to the time sequence and area constraint of the target process library, and the process adaptation efficiency and the design convergence speed are improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more specifically, to a method for generating a multiplier, a multiplier, and a multiplication operation system. Background Technology

[0002] As a core and fundamental computational unit in integrated circuit design, the performance of multipliers directly determines the overall efficiency of complex systems such as digital signal processing, artificial intelligence acceleration, and aerospace computing. In the field of digital signal processing, weighted summation is essentially a multiplication operation; in the field of artificial intelligence, convolution and matrix multiplication-addition operations rely on the hardware support of large-scale parallel multiplication arrays. Since the complexity of multiplication is higher than that of addition (n-bit multiplication requires O(n²) additions), the latency, power consumption, and area of ​​multipliers have become key bottlenecks restricting chip design. To improve computational speed, parallel compression structures such as Wallace trees and Dadda trees are widely used, shortening the critical path by reducing the number of addition levels. To support signed number operations, the Baugh-Wooley algorithm transforms two's complement multiplication into the sum of unsigned partial products and avoids independent sign processing logic by inverting the sign bit and adding compensation. However, in mixed-sign multiplication scenarios (i.e., one operand is signed and the other is unsigned), existing algorithms require special modifications for sign combinations, leading to increased hardware implementation complexity.

[0003] Current hybrid symbol multiplier designs primarily rely on two approaches: manual instantiation and high-bit extension. Manual customization requires iterative partial product compression and adder tree structures for different process libraries. Furthermore, in bottom-up synthesis, the timing boundaries of the lower-level multiplier netlist are difficult to precisely match with the top-level constraints, necessitating a repetition of the entire customization process during process changes, resulting in low efficiency. While high-bit extension can replace two n-bit multipliers with an n+1-bit multiplier, it still introduces additional area overhead. More critically, existing solutions all employ fixed circuit topologies, failing to fully utilize the synthesizer's automatic optimization capabilities. This leads to difficulties in balancing timing, power consumption, and area targets at advanced process nodes, resulting in poor process adaptability and low design efficiency. Summary of the Invention

[0004] The purpose of this application is to provide a multiplier generation method, a multiplier, and a multiplication operation system to solve the above-mentioned technical problems.

[0005] In a first aspect, embodiments of this application provide a multiplier generation method, the method comprising: acquiring a first symbol configuration signal and a second symbol configuration signal; wherein the first symbol configuration signal and the second symbol configuration signal are respectively used to indicate whether a first operand and the second operand are signed numbers; generating a register transfer level description of a multiplier circuit; wherein the register transfer level description includes a first part description and a second part description; the first part description is configured to specify the lower bounds of the first operand. Bit and the low of the second operand A behavioral-level description of the bitwise operation logic; the behavioral-level description allows the synthesizer to perform automatic optimization; the second part of the description is configured to describe the bitwise operation logic involving the first operand. The bit and the second operand's first The structure of the bitwise operation logic is preserved in a description; this preserved description prevents the synthesizer from performing logic reconfiguration. The width of the first operand is the first bit width. The second bit width of the second operand is defined; the synthesizer is invoked to perform logic synthesis on the register transfer level description to generate the gate-level netlist of the multiplier circuit. In the implementation of the above scheme, the unsigned multiplier core is delivered to the synthesizer at the row level through a hierarchical description strategy, enabling the synthesizer to automatically map the optimal multiplier hard core according to the timing and area constraints of the target process library. This reduces the reliance on repeated manual instantiation and iterative optimization for specific semiconductor foundries in traditional processes, which is beneficial to improving process adaptation efficiency and design convergence speed. On the other hand, by locking the sign bit correction logic through structure-preserving description and prohibiting the synthesizer from performing logic reorganization, the same multiplier hardware resources can achieve multiple computation forms without expanding the original operand bit width. This avoids the area redundancy caused by high-bit expansion schemes and achieves a balance between performance and power consumption through the automatic optimization characteristics of the synthesizer, effectively solving the constraint problem between area, efficiency and process adaptability of hybrid sign multipliers.

[0006] In one implementation of the first aspect, the second part of the description is configured to perform: acquiring a mode distinction identifier, a first symbol correction enable signal, and a second symbol correction enable signal based on a first symbol configuration signal and a second symbol configuration signal; wherein the mode distinction identifier is obtained by an XOR operation of the first symbol configuration signal and the second symbol configuration signal; the first symbol correction enable signal is equal to the first symbol configuration signal, and the first symbol correction enable signal is used to independently control the correction path associated with the sign bit of the first operand; the second symbol correction enable signal is equal to the second symbol configuration signal, and the second symbol correction enable signal is used to independently control the correction path associated with the sign bit of the second operand; generating first symbol correction data in response to the first symbol correction enable signal being active; wherein the first symbol correction data is used to represent the cross-multiplication of the sign bit of the first operand and the numerical bit of the second operand and dynamically inverting the corrected partial product; generating second symbol correction data in response to the second symbol correction enable signal being active; wherein the second symbol correction data is used to represent the cross-multiplication of the sign bit of the second operand and the numerical bit of the first operand. The multiplier performs a partial product after dynamic inversion correction and multiplication; obtains sign cross term correction data; wherein the sign cross term correction data is used to characterize the Boolean product after dynamic inversion correction based on the sign phase AND of the first operand and the second operand according to the mode distinction identifier; in response to the first sign correction enable signal being active, a first compensation addend term is generated; wherein the first compensation addend term is used to compensate for the sign compensation introduced by the participation of the signed number in the first sign correction data; in response to the second sign correction enable signal being active, a second compensation addend term is generated; wherein the second compensation addend term is used to compensate for the sign compensation introduced by the participation of the signed number in the second sign correction data; in response to the mode distinction identifier being active, a third compensation addend term is generated; wherein the third compensation addend term is used to adjust the sign compensation introduced by the participation of the signed number in the sign cross term correction data in mixed sign mode; the first sign correction data, the second sign correction data, the sign cross term correction data, the first compensation addend term, the second compensation addend term, and the third compensation addend term are combined with the output result described in the first part through addition operation to obtain the final product of the multiplier circuit.

[0007] In one implementation of the first aspect, generating first symbol correction data in response to the first symbol correction enable signal being at an active level includes: expanding the most significant bit of the first operand to... Bit width, obtain the first symbol extension signal; combine the first symbol extension signal with the low-order bit width of the second operand. Perform a bitwise AND operation on each bit to obtain a first intermediate result; then combine the first intermediate result with the first sign correction enable signal. The bit-repeated spliced ​​signal is subjected to bit-by-bit XOR operation to obtain the first symbol correction data.

[0008] In one implementation of the first aspect, generating second symbol correction data in response to the second symbol correction enable signal being at an active level includes: expanding the most significant bit of the second operand to... Bit width, obtain the second symbol extension signal; combine the second symbol extension signal with the low-order bit width of the first operand. Perform a bitwise AND operation on each bit to obtain a second intermediate result; then combine the second intermediate result with the second sign correction enable signal. The bit-repeated spliced ​​signal is subjected to bit-by-bit XOR operation to obtain the second symbol correction data.

[0009] In one implementation of the first aspect, the second part of the description is configured to: employ bitwise logical operators, bitwise concatenation operators, and arithmetic addition operators to perform operations on the first operand's first bitwise... The bit and the second operand's first The structure of the bitwise operation logic is described.

[0010] In one implementation of the first aspect, the register transfer stage description is configured to: under the dynamic control of the first symbol configuration signal and the second symbol configuration signal, cause the multiplier circuit to perform unsigned multiplication with unsigned numbers, signed multiplication with signed numbers, and mixed multiplication of signed and unsigned numbers in different clock cycles.

[0011] In one implementation of the first aspect, the first bit width and the second bit width are positive integers configured independently of each other; the first bit width and the second bit width are configured to be equal or unequal.

[0012] In one implementation of the first aspect, the call synthesizer performs logical synthesis on the register transfer level description, including: inputting timing constraints and area constraints of the target technology library to the synthesizer so that the synthesizer generates a gate-level netlist that satisfies the timing constraints and the area constraints.

[0013] Secondly, embodiments of this application provide a multiplier, including: an adder circuit and a first arithmetic unit and a second arithmetic unit obtained by logically synthesizing a register transfer level description generated by a method provided for the first aspect or any possible implementation of the first aspect. The register transfer level description includes a first part description and a second part description, wherein the first part description is configured to access the lower bounds of a first operand. Bit and the low of the second operand The second part of the description is configured to describe the behavior-level logic of the bit operation logic involving the first operand. The bit and the second operand's first The structure of the bit operation logic is described, wherein: the first operation unit and the second operation unit are used to generate a partial product when the first operand and the second operand are multiplied; the addition circuit is coupled to the first operation unit and the second operation unit and is used to combine the output of the first operation unit and the output of the second operation unit into a final product output through addition.

[0014] Thirdly, embodiments of this application provide a multiplication system, including: an operand splitting unit, a first multiplier, a second multiplier, a third multiplier, a fourth multiplier, and a result combination unit. The second multiplier and the third multiplier are multipliers as described in the second aspect or any possible implementation of the second aspect. The operand splitting unit is configured to split an M-bit signed third operand into S-bit suboperands and T-bit suboperands, and to split an N-bit signed fourth operand into U-bit suboperands and V-bit suboperands; wherein S+T=M, U+V=N, and M, N, S, T, U, and V are all positive integers; the first multiplier, coupled to the operand splitting unit, is configured to perform the multiplication of the S-bit suboperands and the U-bit suboperands into a signed multiplication table. The system includes: a first multiplier, coupled to the operand splitting unit, configured to perform signed-to-unsigned multiplication of an S-bit suboperand and a V-bit suboperand; a third multiplier, coupled to the operand splitting unit, configured to perform unsigned-to-signed multiplication of an T-bit suboperand and a U-bit suboperand; a fourth multiplier, coupled to the operand splitting unit, configured to perform unsigned-to-unsigned multiplication of an T-bit suboperand and a V-bit suboperand; and a result combination unit, coupled to the first, second, third, and fourth multipliers, configured to perform shift and addition operations on the outputs of the first, second, third, and fourth multipliers to generate the result of the multiplication of the third and fourth operands.

[0015] Fourthly, embodiments of this application provide a multiplication system, including: an operand splitting unit, a multiplier, a time-division multiplexing control unit, and a result combination unit, wherein: the operand splitting unit is configured to split an M-bit signed third operand into S-bit suboperands and T-bit suboperands, and to split an N-bit signed fourth operand into U-bit suboperands and V-bit suboperands; wherein S+T=M, U+V=N, and M, N, S, T, U, and V are all positive integers; the multiplier is a multiplier of the second aspect or any possible implementation of the second aspect; the time-division multiplexing control unit is coupled to the operand splitting unit and the multiplier. The multiplier is configured to perform one of the following operations in different clock cycles: a signed-to-signed multiplication operation by multiplying the S-bit suboperand with the U-bit suboperand; a signed-to-unsigned multiplication operation by multiplying the S-bit suboperand with the V-bit suboperand; an unsigned-to-signed multiplication operation by multiplying the T-bit suboperand with the U-bit suboperand; and an unsigned-to-unsigned multiplication operation by multiplying the T-bit suboperand with the V-bit suboperand. The result combination unit is configured to perform shift and addition operations on the four operation results of the multiplier to generate the multiplication result of the third operand and the fourth operand.

[0016] Fifthly, embodiments of this application provide an electronic device, including: a processor, a memory, and a communication bus, wherein the processor and the memory communicate with each other through the communication bus; the memory stores computer program instructions that can be executed by the processor, and the computer program instructions are read and executed by the processor to perform the method provided in the first aspect or any possible implementation of the first aspect.

[0017] In a sixth aspect, embodiments of this application provide a computer-readable storage medium storing computer program instructions, which, when read and executed by a processor, perform the method provided in the first aspect or any possible implementation thereof.

[0018] In a seventh aspect, embodiments of this application provide a computer program product, the computer program product including a computer program, which, when executed by a processor, implements the method provided by the first aspect or any possible implementation of the first aspect. Attached Figure Description

[0019] Figure 1 A flowchart illustrating the multiplier generation method provided in this application embodiment; Figure 2A schematic diagram of the operation logic of an 8-bit unsigned number multiplier for an application scenario provided in this application embodiment; Figure 3 This is a schematic diagram of the operational logic of a hybrid multiplier in a certain application scenario provided in an embodiment of this application; Figure 4 This is a schematic diagram of the operational logic of another hybrid multiplier in a certain application scenario provided in an embodiment of this application; Figure 5 A schematic diagram of the operation logic of an 8-bit signed number multiplier in a certain application scenario provided in this application embodiment; Figure 6 A schematic diagram of the operation logic of an 8-bit signed number and a 4-bit signed number multiplier in a certain application scenario provided in this application embodiment; Figure 7 This is a schematic diagram of the structure of the multiplier provided in the embodiments of this application; Figure 8 This is a schematic diagram of the operation logic of the multiplication system provided in the embodiments of this application; Figure 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0020] As a core and fundamental computing unit in integrated circuit (IC) design, the performance of multipliers directly determines the processing power, efficiency, and applicability of various digital systems. From consumer electronics to aerospace, from traditional signal processing to artificial intelligence, multipliers have wide applications. In the field of digital signal processing (DSP), the essence of core algorithms such as audio / video encoding / decoding, filtering, and Fourier transform is weighted summation, and the weighting process is multiplication (such as the multiplication of a signal and coefficients). In the field of artificial intelligence (AI) and machine learning, the essence of convolution operations and matrix multiplication in neural networks is a large-scale parallel multiplication-addition operation of input features × weights. The design of multipliers is crucial for balancing the speed, power consumption, and area of ​​integrated circuits. The complexity of multiplication is much higher than that of addition; therefore, the latency of multipliers is often a bottleneck in digital systems. Due to their high switching activity and large capacitive load, multipliers are among the most power-consuming modules in digital circuits. The hardware implementation of multipliers requires a large number of logic gates; compact multiplier designs can improve integration density and reduce costs. Therefore, the multiplier is a crucial module in integrated circuits, bridging the computational needs of various core applications and determining the chip's performance limits and design complexity. In current integrated circuit design practices, multipliers are implemented using three main technical paths: One path involves multiplication operations on purely unsigned or purely signed numbers, which can be described at the behavioral level using arithmetic multiplication operators in RTL code. For example, for N-bit unsigned multiplication, it can be described as: `wire [2N-1:0] mul_unsigned=srca[N-1:0]*srcb[N-1:0]`. For N-bit signed multiplication, the multiplication operator can be called after the function `$signed()` has been used for sign modification, for example, described as: `wire [2N-1:0] mul_signed=$signed(srca[N-1:0])*$signed(srcb[N-1:0]`. The advantage of this implementation is that mature commercial synthesis tools (such as DesignCompiler, Genus, etc.) can fully understand such descriptions and automatically select the optimal structure such as Wallace tree, Dadda tree or carry-lookahead adder array to generate a high-quality gate-level netlist based on the timing constraints and area constraints of the target process library, without the need for the designer to intervene in the specific circuit topology. The Wallace tree mentioned above is a parallel multiplier architecture, which performs parallel compression of partial products through multi-layer cascaded full adders and half adders arrays, thereby reducing the addition level of the traditional accumulation structure from linear time complexity O(n) to a delay level close to that of addition operations, thus achieving high-speed multiplication operations. The workflow of the Wallace tree architecture includes: (1) Partial product generation stage: multiply two binary numbers, and multiply each multiplier by the multiplicand to produce a partial product, which can be achieved by a simple AND gate.(2) Partial product compression stage: The partial products are grouped by column, usually three rows per group. A full adder is used to compress the column containing three partial products into two outputs (sum bit and carry). A half adder is used to compress the column containing two partial products. The remaining partial products of a single column are directly passed to the next stage. This process is repeated until the partial product array is compressed into two rows. (3) Final summation stage: A conventional multi-bit carry-forward adder or carry-lookahead adder can be used to add the compressed partial products of the two rows to obtain the final product. Wallace trees shorten the critical path delay by maximizing parallelism. Their operation speed is close to that of addition, but at the cost of increased hardware resource consumption, requiring more full adder and half adder units, resulting in increased chip area and dynamic power consumption. Therefore, they are widely used in digital signal processing, high-performance computing and cryptographic hardware acceleration fields with extremely high operation speed requirements, providing optimal multiplication performance in scenarios with sufficient area and power budget. The Dadda Tree described above is a partial product compression structure. As an optimized variant of the Wallace Tree, its core lies in achieving an optimal area-latency balance between latency and hardware resources through a more refined hierarchical control strategy. This architecture also begins with the partial product generation stage, but unlike the Wallace Tree, which maximizes the compression ratio level by level, the Dadda Tree employs a latency-optimal compression criterion. A predefined Dadda sequence (e.g., 2, 3, 4, 6, 9, 13…) specifies the maximum number of partial product rows allowed after each level of compression, ensuring that the total path latency from input to output is minimized rather than achieving local optima at each level. During compression, the Dadda Tree only uses full or half adders on columns exceeding the sequence threshold, prioritizing the compression of columns with the largest number of partial products, progressively reducing the array to two rows, and finally using a regular adder to calculate the product. This strategy allows Dadda trees to reduce the number of full adders and half adders while maintaining speeds close to Wallace trees, thereby reducing chip area and dynamic power consumption. Furthermore, it offers stronger compression regularity, better column-to-column balance, and is more friendly to placement and routing, facilitating compact integration and reducing routing congestion. Therefore, it is widely used in scenarios requiring a balance between performance and cost, such as general-purpose processors, digital signal processors, and communication baseband chips. The second approach is for area-constrained scenarios that require simultaneous support for unsigned and signed multipliers. This typically employs a high-bit extension strategy, extending each of the two N-bit operands by one bit to N+1 bits. The extended high-bit bit indicates whether the multiplier is signed or unsigned, for example, described as: wire[2N+1:0] mul_mix=$signed({is_signed&srca[N-1],srca[N-1:0]})*$signed({is_signed&srcb[N-1],srcb[N-1:0]}). The original independent unsigned N-bit multiplier and signed N-bit multiplier are replaced by an N+1-bit unified multiplier.Although this approach reduces hardware area through resource reuse, it still has two fundamental drawbacks: First, the added 1 bit increases the size of the partial product array of the multiplier, introducing a non-negligible additional area overhead; second, when only pure unsigned or pure signed operations are required, the added bit is redundant, resulting in wasted hardware resources and power consumption redundancy. The third approach is custom multiplier design for high-performance or special constraint scenarios. Designers can manually build the partial product generation array based on the Baugh-Wooley algorithm, using full adders, half adders, and special compression units from the foundry's standard cell library to construct a compression tree structure layer by layer, and repeatedly adjust the adder stages and cell types in conjunction with timing constraints. While this solution can approximate the theoretically optimal PPA (Power, Performance, Area) under specific processes, its drawbacks are more pronounced: First, the manual instantiation process is cumbersome and highly dependent on engineer experience, requiring multiple iterations and trial and error to address the latency and area characteristics of different foundry cell libraries, resulting in a design cycle of several weeks. Second, in the bottom-up synthesis process, the custom multiplier netlist at the bottom layer needs to be embedded in the top-level design for incremental synthesis. Changes in the timing boundaries of the top layer can easily lead to the deterioration of the carefully tuned multiplier timing, resulting in performance falling short of expectations. Third, when switching process nodes or changing timing constraints, the entire customization process must be repeated, resulting in extremely high process portability costs and severely restricting the reusability and agility of the design. More importantly, the Baugh-Wooley algorithm itself is only applicable to scenarios where both operands are signed numbers. For mixed signed multiplication (multiplying a signed number with an unsigned number), additional modifications to the partial product generation and compensation logic are required, further increasing the complexity and error risk of manual customization.

[0021] In view of this, embodiments of this application provide a multiplier generation method. This method delivers unsigned multiplication cores to the synthesizer at the behavior level through a hierarchical description strategy, enabling the synthesizer to automatically map the optimal multiplier hard core according to the timing and area constraints of the target process library. This reduces the reliance on repeated manual instantiation and iterative optimization for specific semiconductor foundries in traditional processes, which is beneficial to improving process adaptation efficiency and design convergence speed. On the other hand, by locking the sign bit correction logic through structure-preserving description and prohibiting the synthesizer from performing logic reorganization, the same multiplier hardware resources can realize multiple computation forms without expanding the original operand bit width. This avoids the area redundancy caused by high-bit expansion schemes and achieves a balance between performance and power consumption through the automatic optimization characteristics of the synthesizer, effectively solving the constraints of area, efficiency and process adaptability of hybrid sign multipliers.

[0022] Please see Figure 1This application provides a multiplier generation method, including: Step S110: acquiring a first symbol configuration signal and a second symbol configuration signal; wherein the first symbol configuration signal and the second symbol configuration signal are used to indicate whether the first operand and the second operand are signed numbers, respectively. The symbol configuration signal refers to a 1-bit digital logic signal generated by the upper-level control logic or instruction decoding unit. In register transfer level description, it can be defined as a Boolean value, used to statically or dynamically indicate whether the corresponding operand is a signed number before the multiplication operation starts or during the operation cycle. The first symbol configuration signal can be coupled to the sign bit input port of the first operand. When the signal is set to a logic high level, it indicates that the first operand is represented as a signed number in two's complement form, with its most significant bit serving as the sign bit; when it is set to a logic low level, it indicates that the first operand is represented as a standard binary unsigned number, with all bits being numerical bits. Similarly, the second symbol configuration signal can be coupled to the second operand using the same semantics. The sign configuration signal not only drives the generation of sign correction logic as a mode selection parameter during logic synthesis, but also directly participates in generating mode differentiation identifiers and the most significant bit of the compensated addend during circuit operation. This allows for time-division multiplexing of three operation modes—unsigned vs. unsigned, signed vs. signed, and signed vs. unsigned—without modifying the register-transfer level description code structure, enabling a single multiplier hardware architecture to dynamically adapt to multi-data-format operations. It is understandable that the aforementioned sign configuration signal differs from the most significant bit of the operand in both physical attributes and functional roles. The sign configuration signal belongs to the control signal domain and is a static or quasi-static logic quantity independent of the operand data path. Its level remains unchanged within a single multiplication cycle or multiple consecutive cycles. It is directly generated by the upper-level control logic or instruction decoding unit, without needing to be derived from the operand values ​​themselves, and is used to parameterize the sign semantic rules of the current operation in the register-transfer level description. The most significant bit of an operand belongs to the data signal field and is a bit in the two's complement representation of the operand that dynamically changes with the data being operated on. Its level is determined in real time by the actual data stream. In a hybrid sign multiplier, the logical interpretation weight of this bit is modulated by the level of the sign configuration signal: when the sign configuration signal is logic high, this bit functions as the sign bit, and its level determines the sign of the operand. Generally, a high level for the most significant bit of the operand represents a negative operand, and a low level represents a positive operand. When the sign configuration signal is logic low, the most significant bit of the operand is a normal numerical bit, contributing only to the magnitude of the value and not possessing any sign semantics. The generation of the aforementioned sign configuration signal can be dynamically identified at runtime based on the data type context of the operand, or it can be predefined statically before the operand reaches the arithmetic unit.When using dynamic identification, the symbol configuration signal is generated at the data path level by the operand preprocessing logic. It is independently determined by parsing the operational semantics indicated by the current instruction decoding result: if the instruction opcode corresponds to a signed multiplication operation, the corresponding symbol configuration signal is set to valid; if it corresponds to an unsigned multiplication operation, it is set to invalid. This determination logic is completely independent of the actual numerical level of the operand; its level state is directly driven by the instruction type or data stream markers (such as metadata bits accompanying the data), rather than deduced from the operand numerical bits. This mechanism allows the multiplier to adaptively process mixed signed and unsigned operands in the data stream on the same hardware architecture without software intervention for mode switching. When using static predefined identification, the symbol configuration signal is written by the upper-level control logic (such as the instruction decoding unit, configuration register file, or processor mode register) before the operation starts or during the initialization phase. The value of the symbol configuration signal remains unchanged within a single multiplication cycle or multiple consecutive cycles, regardless of the operand values ​​arriving subsequently. This method is suitable for scenarios where the data format can be determined at compile time. By eliminating runtime identification logic, critical path latency and dynamic power consumption can be further reduced. Both mechanisms are implemented through parameterizable conditional assignment in the register transfer level description, which enables the multiplier circuit to have both runtime flexibility and static configuration efficiency, thereby supporting a wider range of application scenarios and power-performance trade-off strategies without adding additional mode selection hardware.

[0023] Optionally, the register transfer level description described above is configured to, under the dynamic control of the first and second symbol configuration signals, enable the multiplier circuit to perform unsigned multiplication, signed multiplication, and mixed signed and unsigned multiplication operations in different clock cycles. The first and second symbol configuration signals are independently updated in each clock cycle through parameterizable conditional assignment logic. Their level states directly drive the enabling and disabling of the symbol correction data generation path in the second arithmetic unit. This allows the same multiplier architecture to dynamically activate the partial product correction and compensation logic under the corresponding symbol mode based on the control signal level, without modifying the register transfer level code topology, introducing redundant mode selection multiplexers, or expanding the original operand bit width. This dynamic control mechanism avoids the area overhead and power redundancy caused by designing independent multipliers for each symbol combination, improving hardware resource reuse. Furthermore, because the symbol configuration signal is decoupled from the behavioral description of the core unsigned multiplication core, the synthesizer can perform process-related deep optimization of the core unsigned multiplication, thereby achieving a dynamic balance between area, timing, and power consumption. Furthermore, the flexible switching of runtime symbol modes enables the multiplier circuit to adaptively match the format requirements of application-layer algorithms based on data flow characteristics, enhancing the design's process independence and market adaptability. The synthesizer described above is a core EDA tool in the digital integrated circuit design automation process, converting register-transfer level descriptions into gate-level netlists. Its function is to achieve process-dependent mapping and optimization from behavioral abstraction to physical implementation. The synthesizer typically takes RTL code written in a hardware description language (Verilog, VHDL, or SystemVerilog) as input, converting it into a process-independent general logic representation (usually Boolean equations or technology-independent graph structures) through syntax parsing and semantic analysis. Then, based on static timing analysis, algebraic transformations, and Boolean algebra optimization algorithms, under the conditions of timing constraints, area constraints, and power consumption constraints, it performs global optimization operations on the general logic netlist, such as logic reorganization, constant propagation, redundancy elimination, logic rewriting, and state coding optimization, to minimize circuit complexity and meet design goals. Finally, the optimized netlist is bound to specific physical cells (including standard cells, memory macrocells, and hard multipliers) in the target foundry process library (such as TSMC, Samsung, or Intel processes) through the process mapping engine, and process-related optimizations such as cell size adjustment, buffer insertion, fan-out optimization, clock gating inference, and multi-threshold voltage cell allocation are performed to generate a gate-level netlist composed of logic gates, flip-flops, and interconnects.The above scheme, through dynamic control of the first and second symbol configuration signals, enables the same multiplier circuit to independently configure symbol operating modes in different clock cycles. This achieves time-division multiplexing of three operation scenarios: unsigned vs. unsigned, signed vs. signed, and signed vs. unsigned. This eliminates the need to design independent hardware multipliers for each symbol combination, reducing chip area overhead and improving hardware resource reuse efficiency. Furthermore, this dynamic control mechanism allows the switching of the multiplier circuit's symbol operation mode to be entirely driven by signal levels, without requiring modification of the register transfer level description code structure or a resynthesis process. When application layer algorithm requirements change, only the timing stimulus of the symbol configuration signal needs to be updated to adapt to the new operation mode combination. This enhances the process independence and application flexibility of the multiplier circuit without increasing design iteration costs.

[0024] Optionally, the first width and the second width mentioned above are positive integers that are configured independently; the first width and the second width are configured to be equal or unequal. The first width mentioned above... With the second bit width It can be configured with independent positive integer parameters, enabling the register transfer level description to have parameterized bit width adaptation capability, thereby supporting fixed-length mode. ) and unequal length pattern ( The switching between two computational scenarios. The independent bit width configuration mechanism, at the hardware implementation level, can be manifested as follows: the bit extension width in the sign-corrected data generation path, the mask range for bitwise AND operations, and the vector length for XOR correction are all dynamically bound to the actual bit width parameters of the operands on the other side, while the bit width of the compensation addend term can be determined based on... Automatic adjustment ensures the alignment accuracy of the sign bit and the significant value bits in scenarios with unequal bit lengths. When the first and second bit widths are configured to be equal, the sign correction logic degenerates into a symmetrical structure, and the generation of the two sign correction data uses the same expansion and operation rules. When they are configured to be unequal, the bit width parameters of the two operands can be resolved independently, automatically adapting to the high-bit padding strategy of the short operand and the sign expansion range of the long operand, without requiring manual intervention from the designer in the boundary handling of the partial product array. The bit widths of the first and second bit widths are decoupled, allowing the sign configuration signal to focus solely on sign type determination. The parameterized script or synthesizer automatically generates the corresponding hardware structure during the logic synthesis stage based on the numerical relationship between n1 and n2. This allows a single RTL description to cover various unequal-length multiplication requirements without modifying the core sign correction algorithm, improving the versatility and process independence of the multiplier IP core, and shortening the design iteration cycle for different application bit width requirements. The above solution, by configuring the first and second bit widths as independent positive integer parameters, enables the register transfer level description to have parameterized design capabilities. This eliminates the need to rewrite RTL code for different bit width combinations, supporting mixed-signed multiplication operations with operands of equal or unequal lengths. This improves the versatility and reusability of the multiplier IP core and avoids the fragmentation of design resources and soaring maintenance costs caused by customizing circuits for each type of bit width combination in traditional processes. Furthermore, the independent bit width configuration mechanism allows the logic synthesis process to automatically adapt to partial product compression and adder tree optimization under different bit width ratios based on a unified sign correction logic framework. When the bit width requirements of the target application change, only parameter values ​​need to be adjusted and process constraints re-entered to generate the corresponding gate-level netlist, without requiring redesign of the underlying circuit structure. This significantly shortens the design convergence cycle of the multiplier circuit and reduces the complexity of process porting and product iteration.

[0025] Step S120: Generate a register-transfer-level description of the multiplier circuit; wherein the register-transfer-level description includes a first part description and a second part description; the first part description is configured to access the low-order data of the first operand. Bit and the low of the second operand A behavioral description of the bitwise operation logic; the behavioral description allows the synthesizer to perform automatic optimization; the second part of the description is configured to describe the bitwise operation logic involving the first operand. The bit and the second operand's first The structure of the bitwise operation logic is preserved; the structure preservation description prevents the synthesizer from reorganizing the logic. The width of the first bit of the first operand. This is the second bit width of the second operand. The synthesizer described above can achieve structure-preserving description locking through operator type identification and pattern matching mechanisms in register-transfer level descriptions. When the description uses bitwise logic operators (such as bitwise AND &, bitwise XOR ^), bitwise concatenation operators ({}), and arithmetic addition operators, the synthesizer's parsing engine recognizes them as low-level, indivisible basic logic constructs, rather than optimizable high-level arithmetic expressions. These operators are mapped to basic nodes in a technology-independent graph (such as AND gates, XOR gates, and WIRE nodes) during synthesis. Because the connections between nodes are explicit and lack extractable algebraic patterns (such as the distributive law of multiplication and constant propagation), the synthesizer's Boolean algebra optimizer and library matcher cannot recognize their high-level semantics, thus failing to trigger logic reorganization, operator rearrangement, or equivalent transformations. Conversely, when the description uses the arithmetic multiplication operator (*), the synthesizer identifies it as an optimizable macrofunctional unit through pattern matching, and then applies high-performance mapping rules such as Wallace trees and Dadda trees, and can perform global reconstruction of the addition tree structure. The aforementioned structure preservation description can circumvent high-level operators, forcing the synthesizer to treat sign-correction logic as an indivisible sequence of atomic operations when constructing the technology-independent graph. Combined with synthesis constraints (such as the `set_dont_touch` instruction or operator type restrictions), this forces the synthesizer to retain the original logic path, even if simplification is possible at the Boolean algebra level, as the synthesizer's optimization protection mechanisms will prevent it. The aforementioned Register-Transfer Level (RTL) description is a modeling abstraction level in digital integrated circuit design, situated between the algorithmic behavior level and the gate-level netlist. It uses hardware description languages ​​(such as Verilog, VHDL, or SystemVerilog) to provide a periodically precise and explicit expression of data flow and logic operations between registers in the circuit. The core components of register-transfer level description mainly include: first, sequential logic defined by always or process blocks, explicitly specifying the rules for register state transitions under specific clock edges or reset conditions; second, combinational logic functions described by assign statements or combinational logic blocks, defining the memoryless mapping relationship from input to output; and third, a signal network declared by wire and reg (or signal and variable), characterizing the interconnection topology between and within modules. Unlike purely behavioral descriptions, register-transfer level descriptions require explicit definition of register boundaries and data path structures, enabling logic synthesis tools to identify structures that can be mapped to physical flip-flops and combinational logic units, and then perform gate-level mapping and optimization based on the cell delay, area, and power consumption models of the target technology library.Register-transfer level descriptions preserve the designer's precision in controlling circuit timing and parallelism, while allowing synthesizers to reorganize, simplify, and perform process-dependent optimizations of combinational logic while maintaining functional equivalence, thereby achieving automated conversion from abstract functionality to physical implementation. The register-transfer level descriptions in this embodiment can adopt a layered design paradigm, consisting of decoupled behavioral-level descriptions and structure-preserving descriptions. The behavioral-level description is configured to be low on the first operand. Bit and the low of the second operand The core multiplication operation uses arithmetic multiplication operators for behavioral-level abstraction. This description method represents a function-oriented mathematical expression without specifying a specific circuit topology. This allows the logic synthesizer to autonomously map to optimal multiplier hard core structures such as Wallace trees, Dadda trees, or carry-lookahead adder arrays based on the timing and area constraints of the target technology library. Furthermore, it performs deep reorganization and process-related optimization of the addition hierarchy, cell type, and line length, thereby maximizing the performance potential of the technology node. The structure-preserving description is configured to perform multiplication on the first operand... The bit and the second operand's first The sign bit operations are explicitly encoded at the structural level using bitwise logic operators and bit concatenation operators. This description represents hard-wired logic that cannot be synthesized and recombined. By prohibiting the use of arithmetic operators and avoiding high-level synthesis optimization instructions, the logic synthesizer is forced to maintain the original logic paths of sign bit extension, bitwise AND, bitwise XOR, and compensating addend concatenation without being absorbed, merged, or equivalently transformed. This ensures that the sign correction logic of the Baugh-Wooley algorithm maintains structural integrity consistent with the RTL code in the gate-level netlist, avoiding deviations in sign processing functionality and cross-process timing mismatches caused by over-optimization of the synthesizer. Ultimately, the generated multiplier circuit supports unsigned, signed, and mixed sign operations while achieving a balance between design efficiency and circuit performance. The aforementioned Baugh-Wooley algorithm is a hardware-efficient algorithm designed for signed number multiplication operations in binary two's complement representation. Its core idea lies in transforming the sign bit processing of signed numbers into a unified correction mechanism for unsigned number partial product arrays through algebraic transformations, thereby avoiding independent sign bit operation logic. This algorithm is based on the mathematical properties of two's complement numbers: for N-bit signed numbers A and B, their product can be expanded to the sum of the partial products of the numerical bits plus a correction term related to the sign bit, where the partial product of the sign bit needs to be inverted and then added by +2. N-1The compensation constant is used to maintain algebraic correctness. The specific operation process is divided into three stages: First, multiply each bit of the multiplier B (including the sign bit) with the multiplicand A to generate N partial products, where the partial product related to the sign bit is -A (achieved by inverting the last bit of A and adding 1), and an additional +1 correction term is added; second, after aligning all partial products in binary bits, sum them step by step through an adder array (usually using a Wallace tree or Dadda tree for compression); finally, add the partial products compressed to two rows using a regular adder to obtain the final product. The hardware advantage of this algorithm is that it does not require converting the two's complement to the original code, which simplifies the control logic, and the sign bit processing is only implemented by inverting the partial products and fixed compensation, resulting in small additional hardware overhead and easy integration into existing multiplier architectures. However, its limitation lies in the fact that the standard algorithm only supports scenarios where both operands are signed numbers. For mixed signed multiplication (multiplication of a signed number and an unsigned number), the partial product generation rules and compensation term weights need to be modified specifically, which increases the complexity of hardware implementation. Moreover, the manually customized sign correction logic is difficult to reuse during process switching and cannot be automatically optimized by the synthesizer, thus restricting design efficiency and process adaptability. The embodiment of this application, on the other hand, organically integrates the advantages of automatic optimization by the synthesizer and structure-preserving description through a hierarchical register transfer level description strategy. Without extending the highest bit of the operand to N+1 bits, the sign correction logic of the Baugh-Wooley algorithm is fully implemented. This allows the core partial product generation and accumulation operation of the N-1 bit multiplier to be completely automatically optimized by the synthesizer based on process factors. At the same time, it ensures that the accumulation process of the sign correction part and the core multiplication core is also uniformly optimized by the synthesizer.

[0026] The following example, using an 8-bit unsigned number multiplier, illustrates the principle behind the above scheme's division of register-transfer level description into decoupled behavioral and structure-preserving descriptions: Please refer to [link to relevant documentation]. Figure 2 For the low-value 7×7 region in the unsigned multiplication array (i.e., the core numerical partial product array formed by the cross multiplication of a6-a0 and b6-b0), the corresponding... Figure 2The diamond-shaped dashed area in the diagram is described at the behavioral level. Functional abstraction is performed using the arithmetic multiplication operator srca[6:0]*srcb[6:0]. This allows the synthesizer to autonomously map the core multiplication operation to a Wallace tree, Dadda tree, or dedicated multiplier hard core based on the timing and area constraints of the target technology library. Furthermore, it performs deep reorganization and process-related optimization of the adder tree topology, cell size, and carry chain structure to maximize performance and area efficiency. For the boundary regions in the array involving sign bit interactions, including the upper region formed by the intersection of a7 and b0-b6, the left region formed by the intersection of b7 and a0-a6, and the sign cross-product term b7a7 located in the upper left corner of the array, a structure-preserving description is adopted. Hard-wired logic for sign bit extension, bitwise AND, bitwise XOR, and compensating addend concatenation is explicitly constructed using bitwise logic operators and bitwise concatenation operators. The synthesizer is prohibited from performing any form of functional equivalence transformation or logical reorganization on these paths, ensuring strict structural consistency between the gate-level implementation of the sign correction logic and the register-transfer level code. This partitioning strategy allows the synthesizer to optimize the core multiplier without being constrained by the sign processing logic, while ensuring that the sign correction path is not disturbed by the synthesizer's aggressive optimization. Finally, the behavior-level optimized core product and the structure-preserved sign correction data are synchronously accumulated through the addition circuit. Without expanding the original operand bit width or adding mode selection hardware, a unified multiplier architecture that supports multi-sign mode reuse and is process-adaptive is generated.

[0027] Optionally, the second part of the description above is configured to: use bitwise logical operators, bit concatenation operators, and arithmetic addition operators to perform operations on the first operand. The bit and the second operand's first The structure of the bitwise operation logic is preserved. The second part of the description above can be configured to implement the operation logic using only bitwise logic operators, bit concatenation operators, and arithmetic addition operators. This aims to construct a non-synthesizable and recombinable sign correction logic path at the register transfer level, ensuring that the sign processing structure of the Baugh-Wooley algorithm maintains its integrity during gate-level mapping. Bitwise logic operators and bit concatenation operators are basic logic gate-level operations and cannot be recognized as high-level arithmetic expressions during synthesis. The synthesizer cannot perform global optimizations such as constant propagation, logic absorption, or operator rearrangement with other logic, thus forcibly preserving the original circuit topology involving sign bit extension, bitwise AND, and bitwise XOR involving compensation addend concatenation. This prevents the sign correction logic from being optimized into a simplified structure with functionally equivalent but degraded timing characteristics, and prevents multiplication result errors caused by sign cross term correction data misalignment or compensation constant failure due to excessive recombination by the synthesizer. Meanwhile, the retention of the arithmetic addition operator allows the sign-corrected data, sign-cross term correction data, and compensation addend term to be accumulated within the second arithmetic unit, forming the final product together with the core unsigned multiplication core of the first arithmetic unit. However, this addition operation is strictly limited to a small-scale accumulation range within the sign-corrected data, without touching the addition tree structure of the core multiplication operation. This allows the synthesizer to maintain the sign-corrected logic structure while still utilizing the hard adder core and carry chain optimization techniques from the technology library to improve local accumulation speed, thus achieving a balance between structural lock-in and performance optimization. Ultimately, the generated multiplier circuit satisfies the functional correctness requirements of mixed-sign arithmetic while fully utilizing the unit performance of the advanced technology library, achieving a balance between design efficiency and circuit performance. Furthermore, the description in the first part above can be configured to implement the arithmetic logic using the arithmetic multiplication operator, with the core purpose of maximizing the potential of the synthesizer for process-related optimization of the core multiplication operation. Arithmetic multiplication operators are recognized as high-level functional primitives in register-transfer level descriptions (RTDs). The synthesizer can parse them into mathematical semantics independent of specific circuit topologies. Based on the cell characteristics of the target technology library (such as full adder delay, half adder area, and dedicated multiplier hard core performance), it autonomously decides the optimal implementation architecture, including but not limited to Wallace trees, Dadda trees, carry-lookahead adder arrays, or pre-verified multiplier hard cores provided by the technology library. It also globally optimizes partial product compression levels, adder tree balance, and cell size, thereby achieving adaptive PPA performance of a single RTD across different technology nodes. In contrast, if an explicit structural description (such as manually instantiating adder arrays) is used, the synthesizer's optimization space is locked to a fixed topology, unable to be reconstructed according to the advanced features of the technology library. This results in underperformance at advanced processes and the inability to eliminate area redundancy at mature processes.Furthermore, the adoption of arithmetic multiplication operators eliminates the need for designers to concern themselves with bit-width-dependent partial product generation rules and carry chain design, reducing design complexity and error probability. Simultaneously, it shifts the complexity of process adaptation to the synthesis stage. When the design goal shifts from high-performance to low-power scenarios, only the synthesis constraint file needs adjustment, allowing the synthesizer to automatically complete the architecture transformation without modifying the RTL code. This improves design reusability and iteration efficiency, ultimately achieving a synergistic balance between process-driven optimization of core multiplication performance and preservation of the sign-correction logic structure. The aforementioned structure preservation description can be achieved through two technical paths: manual instantiation or automatic generation via script. In the manual instantiation method, design engineers explicitly instantiate each logic gate instance in the register-transfer level description based on the standard cell list of the target process library. By writing the port connection relationships of basic units such as AND, OR, XOR, and MUX line by line, the specific circuit structure and cell selection for sign bit extension, bitwise AND, bitwise XOR, and bit concatenation operations can be precisely controlled. This method enables fine-grained control of the sign-correction logic path, ensuring that the synthesizer cannot recognize high-level operators and reassemble them. The script-based automatic generation method reads the bit width parameters and sign configuration signal list through parameterized script programs (such as Perl, Python, or TCL). Based on a predefined sign correction logic template, it generates RTL code in batches, which includes a fixed number of bit copies, bitwise operations, and bit concatenation operations. This method maintains the structural integrity equivalent to manual instantiation while improving design efficiency and code consistency. When the bit width or sign mode requirements change, only the script parameters need to be modified to regenerate the entire RTL description. Moreover, the generated code also has structural preservation characteristics because it avoids arithmetic operators, making it impossible for the synthesizer to absorb or equivalently transform the sign correction path. Thus, it balances the structural locking requirements and engineering implementation efficiency in large-scale designs.The above scheme, by limiting the second part of the description to use bitwise logic operators, bit concatenation operators, and arithmetic addition operators, can construct a non-synthesizable and recombinable sign correction logic path at the register transfer level. This prevents the synthesizer from recognizing the accumulation of sign bit-related negation correction and compensation terms as an optimizable arithmetic expression, thereby forcibly maintaining the integrity of the correction structure of the Baugh-Wooley algorithm. This avoids timing deviations and functional errors in sign processing logic caused by over-optimization of the synthesizer in traditional processes, which is beneficial to improving the correctness and robustness of the hybrid sign multiplier implementation under different process libraries. On the other hand, the operator selection strategy in the above scheme is decoupled from the behavioral description of the core unsigned multiplier core, making the RTL encoding of the sign correction logic completely independent of the target process characteristics. When the process node is switched or the timing constraints are updated, there is no need to manually adjust the topology of the sign correction circuit. Only the constraints need to be re-entered, and the synthesizer can automatically complete the process mapping and optimization, thereby shortening the design iteration cycle from several weeks to several hours. This significantly reduces the process porting cost and design threshold of the hybrid sign multiplier, and achieves a balance between design efficiency and circuit performance.

[0028] Optionally, the second part of the description above is configured to perform: acquiring a mode distinction identifier, a first symbol correction enable signal, and a second symbol correction enable signal based on a first symbol configuration signal and a second symbol configuration signal; wherein the mode distinction identifier is obtained by an XOR operation of the first symbol configuration signal and the second symbol configuration signal; the first symbol correction enable signal is equal to the first symbol configuration signal, and the first symbol correction enable signal is used to independently control the correction path related to the sign bit of the first operand; the second symbol correction enable signal is equal to the second symbol configuration signal, and the second symbol correction enable signal is used to independently control the correction path related to the sign bit of the second operand; generating first symbol correction data in response to the first symbol correction enable signal being at an active level; wherein the first symbol correction data is used to represent the cross-multiplication of the sign bit of the first operand and the numerical bit of the second operand and dynamically inverting the corrected partial product; generating second symbol correction data in response to the second symbol correction enable signal being at an active level; wherein the second symbol correction data is used to represent the cross-multiplication of the sign bit of the second operand and the numerical bit of the first operand and dynamically inverting the corrected partial product. The multiplier circuit performs the following steps: First, it inverts and corrects the partial product. Then, it acquires the sign cross term correction data, where the sign cross term correction data represents the Boolean product of the sign phase AND of the first and second operands and dynamically inverts and corrects it according to the mode distinction identifier. Second, in response to a valid first sign correction enable signal, it generates a first compensation addend term, which compensates for the sign compensation introduced by the sign number in the first sign correction data. Third, in response to a valid second sign correction enable signal, it generates a second compensation addend term, which compensates for the sign compensation introduced by the sign number in the second sign correction data. Fourth, in response to a valid mode distinction identifier, it generates a third compensation addend term, which adjusts the sign compensation introduced by the sign number in the sign cross term correction data in mixed sign mode. Finally, it combines the first sign correction data, the second sign correction data, the sign cross term correction data, the first compensation addend term, the second compensation addend term, and the third compensation addend term with the output result described in the first part through addition to obtain the final product of the multiplier circuit. The aforementioned mode distinction flag is generated by a bitwise XOR operation between the first symbol configuration signal and the second symbol configuration signal. It is a Boolean flag signal used to indicate whether the sign configurations of the two operands are heterogeneous: when the flag is logic high, it indicates that the sign configurations of the first and second operands are different, meaning the multiplication operation operates in a mixed mode of multiplying signed and unsigned numbers; when the flag is logic low, it indicates that the sign configurations of the two operands are homogeneous, meaning both are signed numbers or both are unsigned numbers. The aforementioned first symbol correction enable signal is defined in the register transfer level description as a control signal logically equivalent to the first symbol configuration signal. Its level is directly driven by the determination result of the first operand's sign attribute by the upper-level control logic or instruction decoding unit.This enable signal independently controls the operation path related to the sign bit of the first operand in the multiplier: when set to logic high, it activates the sign correction data generation path coupled to the sign bit of the first operand, enabling cross-multiplication, inversion correction, and partial accumulation operations between the sign bit of the first operand and the value bits of the second operand; when set to logic low, it bypasses the correction path, and the most significant bit of the first operand is resolved to a normal value bit for unsigned multiplication. This independent control mechanism strictly binds the activation state of the sign correction logic to the real-time sign attribute of the first operand, thereby achieving precise sign bit selective processing in mixed sign operation scenarios. Similarly, the second sign correction enable signal is also defined in the register transfer level description as a 1-bit control signal logically equivalent to the second sign configuration signal, and its level directly reflects the sign attribute determination result of the second operand. This enable signal independently controls the correction path associated with the sign bit of the second operand. Its function is symmetrical to the first sign correction enable signal: when valid, it drives the correction logic of cross-multiplication between the sign bit of the second operand and the value bit of the first operand, generating the second sign-corrected data; when invalid, the most significant bit of the second operand degenerates into a value bit and participates in the operation according to the unsigned rule. By completely decoupling the second sign correction enable signal from the first sign correction enable signal in terms of control, the multiplier can support time-division multiplexing operations of four sign combinations (signed × signed, unsigned × unsigned, signed × unsigned, unsigned × signed), and the enable state of each sign correction path is independently modulated by the corresponding enable signal, without interference, ensuring that the hybrid sign multiplier achieves multi-mode adaptive operation with zero hardware resource redundancy. Figure 3Taking the illustrated scenario as an example: the pattern differentiation identifier rev2 is generated by a bitwise XOR operation between the first symbol configuration signal signed_srca and the second symbol configuration signal signed_srcb, and its logical expression is rev2 = signed_srca ^ signed_srcb. This identifier is a 1-bit Boolean value, which performs the dual functions of pattern recognition and weight modulation in the hybrid symbol multiplier: when the two operands have different symbol configurations (01 or 10), rev2 outputs a logic high level, indicating that it is operating in a hybrid mode of multiplying signed and unsigned numbers; when the symbol configurations are the same (00 or 11), rev2 outputs a logic low level, indicating a pure unsigned or pure signed operation mode. rev2 can directly participate in the construction of the third compensation addend term and modulate the symbol cross term correction data through a dynamic inversion mechanism to offset the extra negative weight of the partial product of sign bits multiplied by sign bits in the hybrid computation mode, preventing the overcompensation error generated by the traditional Baugh-Wooley algorithm in the hybrid computation mode. In the register-transfer level description, the first sign correction enable signal `reva` is defined as logically equivalent to `signed_srcca`. Its physical implementation is a direct connection or buffer, introducing no additional logical delay. `reva` acts as a signal source for an independent control domain, precisely driving the correction path related to the sign bit of the first operand: when `reva` is validly high, the cross-multiplication logic between the first operand sign bit `a7` and the second operand value bits `b0` to `b6` is activated. This generates the original partial product through bit expansion and bitwise AND operations, which is then XORed with the repeated concatenation vector of `reva` to achieve dynamic inversion correction, ultimately outputting the first sign-corrected data. When `reva` is low, this path is forcibly bypassed, and `a7` degenerates into the highest value bit of the unsigned number, no longer generating sign-related correction terms. This independent control mechanism ensures that changes in the sign attribute of the first operand do not affect the sign processing path of the second operand, supporting seamless switching between the four subset modes in mixed-sign arithmetic. Similarly, the second sign correction enable signal `revb` is logically equivalent to `signed_srcb`, forming a control architecture symmetrical to `reva`. The `revb` function independently controls the cross-multiplication correction path between the second operand sign bit (b7) and the first operand value bits (a0 to a6): When `revb` is active high, the cross-multiplication logic between the second sign bit (b7) and the first operand value bits (a0 to a6) is activated. The original partial product is generated through bit expansion and bitwise AND operations, and then XORed with the repeated concatenation vector of `revb` to achieve dynamic inversion correction, finally outputting the second sign-corrected data. When `revb` is low, this path is forcibly bypassed, and `b7` participates in the unsigned multiplication kernel operation as a normal value bit.The decoupling design of reva and revb is manifested at the hardware level as two parallel sign correction chains. Each chain is activated and disabled by an independent enable signal, ensuring that in the hybrid sign mode, only the sign bit of the sign operand triggers the correction logic, while the highest bit of the unsigned operand retains its numerical attribute, avoiding the area redundancy introduced by traditional high-bit extension schemes. The sign cross term correction data b7a7 is directly generated by bitwise AND operation between the first operand sign bit a7 and the second operand sign bit b7, and further dynamically inverted by bitwise XOR operation with the mode differentiation identifier rev2, finally outputting the corrected result representing the multiplication of sign bits. The weight of the sign cross term correction data in the compensation network is dynamically modulated by rev2: in the pure sign mode (rev2=0), the sign cross term correction data retains its original value; in the hybrid computation mode (rev2=1), the sign cross term correction data is inverted to offset the additional negative weight of the sign cross term in the hybrid scenario and maintain the sign consistency of the product. The first compensation addend is generated in response to the first sign correction enable signal `reva` being validly high. Its most significant bit is directly driven by `reva`, and it is used to compensate for the sign compensation introduced by the signed number in the first sign correction data. This compensation amount strictly cancels out the sign bit extension weight of the first operand. The second compensation addend is generated in response to the second sign correction enable signal `revb` being validly high. Its most significant bit is directly driven by `revb`, and it is used to compensate for the sign compensation introduced by the signed number in the second sign correction data. This compensation amount strictly cancels out the sign bit extension weight of the second operand. When both `reva` and `revb` are low, the first and second compensation addends automatically disappear, and the adder circuit only accumulates the core unsigned product and the sign cross term correction data. The third compensation addend is generated in response to the mode distinction identifier `rev2` being validly high. It consists of `rev2` as the most significant bit, the sign cross term correction data as the second most significant bit, and zero padding at the lower bits. This compensation term primarily corrects the weights of the sign cross term correction data in hybrid computation mode, eliminating additional biases introduced by single operand sign bit processing through a conditional negation mechanism. In pure mode (rev2=0), this term is zeroed, causing the computation method to degenerate into the standard Baugh-Wooley algorithm. Driven by the condition of rev2, the third compensation addend term achieves hardware integration of hybrid mode detection and correction, eliminating the need for an additional mode selection multiplexer or state machine. The overall combinational logic performs bit-aligned accumulation of six data streams—first sign correction data, second sign correction data, sign cross term correction data, first compensation addend term, second compensation addend term, and third compensation addend term—with the core unsigned product through an addition circuit. This accumulation process is uniformly optimized by the synthesizer, but the sign correction and compensation paths are forced to maintain structural integrity due to the use of bitwise logic operators and bit concatenation operators, prohibiting synthesis and reassembly.Each bit of the final product contains a weighted contribution from the core multiplication kernel, dual-path sign correction, and three-level compensation. Hardware resource reuse reaches its theoretical limit, and area overhead approaches that of a single unsigned multiplier. It also supports dynamic switching between four sign combinations. This scheme can be extended to mixed-sign multiplication scenarios with operands of unequal length, such as... Figure 4 As shown, when the first width With the second bit width For independently configured unequal-length parameters (e.g.) , The generation paths for the first and second sign-corrected data automatically adapt to the bit-width difference: the bit width of the first sign-corrected data is determined by... The decision is made by copying and expanding the sign bit a7 of the first operand to... Bit width, and the low-order bit width of the second operand The bit values ​​b2 to b0 are cross-multiplied to generate mul_a7bx[2:0]; the bit width of the second sign-corrected data is... The decision is made by copying and expanding the sign bit b3 of the second operand to... Bit width, and the low-order bit width of the first operand Bitwise multiplication of bits a6 to a0 generates mul_b3ax[6:0]. The sign cross term correction data is simplified to a single bit of a7 & b3. The bit width of the first compensation addend term is automatically bound to... Its weight is fixed at the first The first sign correction enable signal, reva, is used to compensate for sign compensation introduced by the sign in the first sign correction data; the weight of the second compensation addend term is located in the first position. The third compensation addend term, driven by the second sign correction enable signal revb, is used to compensate for sign compensation introduced by the sign participation in the second sign correction data; the weight of the third compensation addend term is located in the 1st position. The bit, driven by the mode-distinguishing identifier rev2, is used to adjust the weight contribution of the sign cross term correction data in mixed sign mode. For example... Figure 5 and Figure 6As shown, in the scenario of multiplying purely signed numbers, the first sign configuration signal `signed_srca` and the second sign configuration signal `signed_srcb` are simultaneously set to logic high. At this time, the mode distinction flag `rev2 = signed_srca ^ signed_srcb` is always equal to 0, and the system operates in homogeneous sign mode. Under this condition, there is no need to use separate first sign correction enable signals `reva` and `revb` for branch control. The top-level signed multiplication flag signal `signed_mul` can be directly mapped to a unified sign correction drive signal `revt`, i.e., `revt = signed_mul`. This single signal uniformly drives the correction path of the cross-multiplication of the first operand sign bit `a7` and the second operand value bits `b0` to `b6` (generating `mul_a7bx`), and the correction path of the cross-multiplication of the second operand sign bit `b7` and the first operand value bits `a0` to `a6` (generating `mul_b7ax`). In digital circuits and hardware description languages, signed_mul is usually defined as a 1-bit control signal, which is generated by the instruction decoding unit or high-level control logic before the operation starts based on the instruction opcode or the state of the operation mode register. Its effective level clearly indicates that the current multiplication operation is a multiplication of signed numbers. When rev2=0, the sign cross term correction data degenerates to the original value of the sign cross term correction data of the standard Baugh-Wooley algorithm, without the need for inversion correction. The first and second compensation addend terms are generated in response to revt=1, and their most significant bits are directly driven by revt to compensate for the sign bit extension weights of the first and second sign correction data, respectively. The third compensation addend term is automatically reset to zero when rev2=0. This control signal multiplexing strategy merges the enable ends of the two parallel sign correction chains into a single driving source, eliminating redundant enable signal generation logic in the pure signed mode. Without expanding the original operand bit width or adding an additional mode selection multiplexer, it simplifies the complexity of the RTL description. The synthesizer can recognize revt as a global constant driver, and then perform constant propagation optimization and logic simplification on the sign correction path, reducing the hardware implementation area and dynamic power consumption, while maintaining strict equivalence with the traditional Baugh-Wooley algorithm in terms of function and timing.

[0029] The above scheme constructs a three-layer conditional response control architecture by multiplexing the symbol configuration signal into a first symbol correction enable signal and a second symbol correction enable signal, and introducing a mode distinction identifier generated by XOR operation. This achieves precise decoupling and hierarchical compensation of the symbol correction path. This architecture ensures that the two symbol correction data generation paths (first symbol correction data, second symbol correction data) and the three compensation addend generation paths (first compensation addend, second compensation addend, third compensation addend) respond to independent enable conditions, ensuring that the corresponding logic is activated only when the corresponding operand is a signed number or when operating in a mixed-symbol mode. This decomposes the signed extension mechanism of the Baugh-Wooley algorithm into atomic operation units strictly bound to the operand sign attribute. This fine-grained condition-driven mechanism avoids the redundant mode selection multiplexer and fixed compensation overhead introduced in traditional schemes to cover all sign combinations, allowing hardware resource reuse to reach its theoretical limit. The optimization space of the core unsigned multiplication kernel is fully preserved. The synthesizer can perform deep mapping of the core product using Wallace trees, Dadda trees, or dedicated multiplier hard cores under the constraints of the target technology library, while strictly maintaining the RTL structural integrity of the sign correction and compensation logic, preventing... Timing mismatch and functional errors caused by logic reorganization; on the other hand, a hierarchical compensation strategy based on enable signals and mode distinction identifiers achieves precise cancellation of symbol bit extension deviation and dynamic modulation of cross-term weights in mixed-symbol mode at the algorithm level. Specifically, the first and second compensation addends respond to the effective level of their respective symbol correction enable signals, independently compensating for the negative weights introduced by the symbols in the corresponding symbol correction data, ensuring that the compensation amount strictly cancels out the contribution of the symbol bits; the third compensation addend responds to the effective level of the mode distinction identifier, specifically handling the additional weights of the symbol cross-term correction data in mixed-symbol mode. The overcompensation error of the purely signed algorithm in mixed scenarios is eliminated through a conditional negation mechanism. This compensation structure and the symbol correction data generation path are implemented in the register transfer level description using bitwise logic operators and bit concatenation operators, preventing the synthesizer from recognizing it as an optimizable arithmetic expression. This ensures that the circuit topology of the compensation logic is strictly consistent with the RTL code in the gate-level netlist. When the process node is migrated or the timing constraints are changed, only the synthesis constraint file needs to be adjusted, and the synthesizer can automatically complete the process mapping, thereby shortening the design iteration cycle and reducing the product development threshold and maintenance cost of the hybrid sign multiplier in multiple application fields.

[0030] Optionally, in response to the first symbol correction enable signal being at an active level, generating first symbol correction data includes: expanding the most significant bit of the first operand to... Bit width, obtain the first symbol extension signal; combine the first symbol extension signal with the low-order bit width of the second operand. Perform a bitwise AND operation on each bit to obtain the first intermediate result; then combine the first intermediate result with the first sign correction enable signal. The first sign-corrected data is obtained by performing a bitwise XOR operation on the repetitive spliced ​​signal. This scheme transforms the cross-multiplication process of the sign bit of the first operand and the value bit of the second operand into a structured logic mapping path by combining sign bit expansion and bitwise operations triggered in response to the effective level of the first sign-correction enable signal. This path uses bitwise AND operations to accurately generate the sign-value cross-partial product, and then performs a bitwise XOR operation with the repetitive spliced ​​vector of the first sign-correction enable signal to achieve dynamic inversion correction. This explicit structural description prevents the synthesizer from recognizing the sign expansion as an arithmetic shift or performing constant propagation optimization, forcing the preservation of the original circuit topology of bit-level copying and logic operations. This physically decouples the sign-correction data generation path from the core unsigned multiplier core during the synthesis stage, ensuring that the synthesizer only performs process-related deep optimizations on the latter, while maintaining the structural integrity of the sign-correction logic. This avoids timing deviations and functional errors caused by logic reconfiguration, improving the correctness and robustness of the hybrid sign multiplier implementation under different process libraries. Furthermore, the conditional response mechanism based on the enable signal implements the operation mode... Adaptive adaptation: When the first sign correction enable signal driving path is activated, the generated first sign correction data accurately represents the partial product of the cross multiplication of the sign bit and the numerical bits of the opposite operand, enabling the second arithmetic unit to independently generate sign correction data when the first operand is a signed number; when the enable signal is invalid, the sign correction path is automatically bypassed, and the most significant bit of the first operand degenerates into a normal numerical bit to participate in unsigned multiplication. This condition-driven design can switch between signed and unsigned modes by changing the signal level without modifying the register transfer stage topology, enabling the same hardware resource to support time-division multiplexing of multiple computing modes, eliminating redundant mode selection multiplexer overhead, reducing chip area and static power consumption, and enhancing the process independence and application flexibility of the multiplier circuit.

[0031] Optionally, in response to the second symbol correction enable signal being at an active level, second symbol correction data is generated, including: expanding the most significant bit of the second operand to... Bit width, obtain the second symbol extension signal; combine the second symbol extension signal with the low-order bit width of the first operand. Perform a bitwise AND operation on each bit to obtain the second intermediate result; then combine the second intermediate result with the second sign correction enable signal. The second sign correction data is obtained by performing a bitwise XOR operation on the repetitive concatenation signal. The above scheme transforms the cross-multiplication process of the sign bit of the second operand and the numerical bit of the first operand into a structured logic mapping path by combining sign bit expansion and bitwise operations triggered in response to the effective level of the second sign correction enable signal. This path uses bitwise AND operations to accurately generate the sign-numerical cross-partial product, and then performs a bitwise XOR operation with the repetitive concatenation vector of the second sign correction enable signal to achieve dynamic inversion correction. This explicit structural description prevents the synthesizer from recognizing the sign expansion as an arithmetic shift or performing constant propagation optimization, forcibly maintaining the original circuit topology of bit-level copying and logic operations. This physically decouples the second sign correction data generation path from the core unsigned multiplication core during the synthesis stage, ensuring that the synthesizer only performs process-related deep optimizations on the latter, while maintaining the structural integrity of the second sign correction logic. This avoids timing deviations and functional errors caused by logic reconfiguration, improving the correctness and robustness of the hybrid sign multiplier implementation under different process libraries. On the other hand, the conditional response mechanism based on the enable signal achieves adaptive adaptation of the operation mode. Independent configuration of bit width parameters: When the second sign correction enable signal drive path is activated, the generated second sign correction data accurately represents the partial product of the cross multiplication of the sign bit of the second operand and the numerical bits of the opposite operand, enabling the second arithmetic unit to independently generate sign correction data when the second operand is a signed number; when the enable signal is invalid, the sign correction path is automatically bypassed, and the most significant bit of the second operand degenerates into a normal numerical bit to participate in unsigned multiplication. This condition-driven design can switch between signed and unsigned modes by changing the signal level without modifying the register transfer stage description topology, enabling the same hardware resource to support time-division multiplexing of multiple computing modes, eliminating redundant mode selection multiplexer overhead, reducing chip area and static power consumption, and enhancing the process independence and application flexibility of the multiplier circuit.

[0032] When the second sign configuration signal is configured as a signed number, the sign correction data can be obtained through the following operation: First, perform a bit copy operation on the most significant bit of the first operand to generate a data with a width of [value missing]. The first sign-extended signal is used, and each bit of this signal is logically equivalent to the sign bit of the first operand; then the sign-extended signal is used in conjunction with the low-order bits of the second operand. The bitwise AND operation is performed to establish the bitwise product path between the sign bit and the value bits. The resulting first intermediate result accurately represents the masking effect of the sign bit on each value bit of the second operand. Finally, the first intermediate result is distinguished from the pattern identifier. The bit-repeated concatenation vector performs a bitwise XOR operation, dynamically controlling the inversion correction of the sign-related partial product using the level state of the second sign configuration signal to generate the first sign-corrected data. When the first sign configuration signal is configured as a signed number, the sign-corrected data can be obtained through the following operation: extending the most significant bit of the second operand to... The second sign extension signal, along with the low bit of the first operand. After performing a bitwise AND operation, the second sign correction data is obtained by XORing the repeated concatenated vector of the pattern distinction identifier. The aforementioned sign cross term correction data can be achieved by directly performing a bitwise AND operation on the most significant bits of the two operands, generating a 1-bit Boolean product term. The aforementioned compensation addend term can be obtained as follows: a logical OR operation is performed on the first sign configuration signal and the second sign configuration signal. If either signal indicates a signed number, the OR operation result is set to a logic high level. This result is used as the most significant bit, and the lower bits are padded with zeros and concatenated to form a fixed-width compensation vector.

[0033] Please see Figure 5The following example uses a multiplier for an 8-bit signed number a and a signed number b to illustrate the behavioral and structural descriptions. The register transfer level descriptions generated in this scenario are as follows: wire revt = signed_mul; wire mul_a7b7 = srca[7]&srcb[7]; wire [6:0]mul_a7bx = ( {7{srca[7]}}&srcb[6:0] ) ^ {7{revt}}; wire [6:0]mul_b7ax = ( {7{srcb[7]}}&srca[6:0] ) ^ {7{revt}}; wire [15:0]mul = srca[6:0] * srcb[6:0]+{revt, mul_a7b7, 14'h0} +{ mul_b7ax, 7'h0} +{ mul_a7bx, 7'h0} + {revt, 8'h0}. The behavioral description corresponds to the subexpression srca[6:0]*srcb[6:0] in the assignment statement wire[15:0]mul. This subexpression is a behavioral abstraction that uses the arithmetic multiplication operator "*" to perform unsigned multiplication of the lower 7 bits of the first operand (srca[6:0]) and the lower 7 bits of the second operand (srcb[6:0]), without specifying any specific circuit implementation. After this description is delivered to the synthesizer, the synthesizer can autonomously map it to a Wallace tree, Dadda tree, or other high-compression-ratio multiplier structure based on the timing and area constraints of the target technology library, and perform deep optimization of the addition hierarchy, carry chain topology, and cell drive strength, thereby maximizing the performance potential of the technology node and achieving area and speed optimization of the core multiplication operation. The structure preservation description corresponds to all sign bit processing logic in the code except for srca[6:0]*srcb[6:0], specifically including: (1) Sign bit extension and cross term generation: {7{srca[7]}} and {7{srcb[7]}} in the above RTL description copy the sign bit into a 7-bit wide vector through the bit concatenation operator, and then perform a bitwise AND operation (&srcb[6:0], &srca[6:0]) with the numerical bits of the operand on the other side to explicitly construct the partial product term of the sign-numerical cross multiplication. This encoding prevents the synthesizer from recognizing the sign extension as an arithmetic shift or constant propagation optimization, and forces the preservation of the bit-level copy structure. (2) Dynamic sign correction: ^{7{revt}} in the above RTL description uses the bitwise XOR operator to invert and correct the repeated concatenation vector of the above cross partial product and the global sign mode signal revt.This structure allows the behavior of the sign correction path to be directly controlled by the revt signal level. The synthesizer cannot absorb it as a fixed constant or merge it into other logic, thus ensuring that the negation logic of the Baugh-Wooley algorithm in the mixed sign scenario maintains the structural integrity of the gate-level netlist consistent with the RTL code. (3) Construction of compensation addend terms: The four-segment bit-concatenation structure of {revt,mul_a7b7,14'h0}, {mul_b7ax,7'h0}, {mul_a7bx,7'h0}, and {revt,8'h0} in the above RTL description is combined into a multi-channel addend by the concatenation operator, which combines the compensation constant revt, the sign cross term correction data mul_a7b7, and the two sign correction data mul_a7bx and mul_b7ax with a fixed bit width. This description prohibits the synthesizer from rearranging or merging the position of the compensation terms, and forces the topology of the adder tree input port to strictly correspond to the RTL code, avoiding misalignment of compensation values ​​or failure of sign correction due to reorganization.

[0034] Step S130: Call the synthesizer to perform logic synthesis on the register transfer level description to generate the gate-level netlist of the multiplier circuit.

[0035] The gate-level netlist described above is a graphical representation of circuit logic structure used in digital integrated circuit design. It details the connections between logic gates and their input-output relationships. In a gate-level netlist, logic gates (such as AND, OR, and NOT gates) are the basic building blocks of the circuit, while other logic elements such as multiplexers (MUX) and flip-flops are combined according to design requirements. A gate-level netlist typically consists of a series of logic equations or graphical symbols, where the symbols visually represent the inputs, outputs, and connections between logic gates. The output of each logic gate can be the input of one or more other logic gates, forming a complex logic network. The gate-level netlist not only describes the logical function of the circuit but also implicitly contains its timing characteristics. In the physical design phase of digital integrated circuits, the gate-level netlist is fundamental, guiding the placement and routing of circuits on the silicon chip and ensuring that logic gates are physically arranged in an optimal manner to meet performance requirements. Designers can use logic synthesis tools to convert high-level register-transfer level descriptions (RTLs) into gate-level netlists, and then use place-and-route tools to map the netlists onto the actual chip, ultimately manufacturing an integrated circuit that meets specific functionalities. Logic synthesis is a crucial step in the digital integrated circuit design flow, its purpose being to convert RTLs into gate-level netlists for subsequent physical implementation. During logic synthesis, the synthesizer tool accepts RTLs written in a hardware description language as input. These descriptions detail the behavior and structure of the digital circuit, including but not limited to arithmetic operations, logic operations, data flow control, and sequential logic. The synthesizer parses these high-level RTLs, mapping them to low-level logic gate-level structures compatible with specific technology libraries, such as AND gates, OR gates, NOT gates, and multiplexers, while considering timing constraints, area efficiency, and power consumption optimization. During logic synthesis, the synthesizer applies a series of algorithms to analyze and transform the RTLs, including but not limited to logic simplification, Boolean algebra optimization, equivalent logic extraction, cell matching, and place-and-route preprocessing. These algorithms aim to generate a gate-level netlist that is functionally equivalent but optimized in terms of performance, area, and power consumption.

[0036] Optionally, step S130 above may include: inputting the timing and area constraints of the target process library into the synthesizer, so that the synthesizer generates a gate-level netlist that satisfies the timing and area constraints. The target process library is a set of data and models used to guide logic synthesis and physical implementation during integrated circuit design. It details the characteristics of various logic gates and memory cells available at a specific semiconductor manufacturing process node. These characteristics include, but are not limited to, cell size, timing delay, power consumption characteristics, drive capability, and fan-out requirements. The target process library is typically provided by the foundry and delivered to the designer in standard formats such as .db files and .lib files. During the logic synthesis stage, the synthesizer can utilize the cell models and timing information in the target process library to map high-level register-transfer level descriptions to gate-level netlists, while simultaneously optimizing the circuit to meet design timing and area constraints. During the physical implementation stage, placement and routing tools also rely on the target process library to determine how to accurately place and interconnect these logic cells on the silicon wafer, ensuring the correctness and manufacturing feasibility of the circuit at the physical level. Therefore, the target process library is a key resource connecting design intent with manufacturing capabilities, ensuring that the design meets specific process requirements. The timing constraints described above define the maximum allowable delay for each logic path in the circuit, ensuring correct operation at a predetermined clock frequency and avoiding timing errors and data conflicts. Timing constraints are typically expressed as parameters such as clock cycle, setup time, and hold time. Synthesizers and place-and-route tools utilize these parameters to optimize circuit performance, such as by selecting faster cells or adjusting the logic structure to meet timing requirements. The area constraints, on the other hand, specify the maximum area the circuit occupies on the silicon wafer. Area constraints directly affect the chip's cost, power consumption, and thermal performance. Area constraints are usually measured by the number of cells or logic gates on the silicon wafer. Designers must minimize the circuit area while meeting functional requirements to achieve optimal cost-effectiveness and energy efficiency. During the logic synthesis and place-and-route stages, the synthesizer considers these constraints and uses various optimization strategies such as logic refactoring, cell selection, and placement optimization to balance the circuit's timing performance and area footprint, thereby generating a gate-level netlist and physical layout that meets performance requirements and is cost-effective.The above solution, by inputting the timing and area constraints of the target process library into the synthesizer, enables the synthesizer to perform process-related deep optimization of the behavioral multiplication operations described in the first part of the layered RTL description framework, while strictly maintaining the sign correction logic structure described in the second part from being reorganized. This allows for the automatic generation of a hybrid sign multiplier netlist that meets specific PPA metrics without expanding the original bit width, avoiding manual iteration and performance degradation caused by constraint mismatches in traditional processes. Furthermore, the constraint-driven synthesis process shifts the complexity of process adaptation from the RTL coding stage to the synthesis stage. When the design goal shifts from a high-performance scenario to a low-power scenario or migrates to different process nodes, there is no need to modify the RTL structure of the sign correction logic; only the constraint file needs to be adjusted for the synthesizer to automatically complete the process mapping and optimization, which helps to improve the development cycle of products in different market sectors.

[0037] Please see Figure 7 Based on the same inventive concept, this application also provides a multiplier 200, including: an adder circuit 210 and a first arithmetic unit 220 and a second arithmetic unit 230 obtained by logical synthesis of a register transfer level description generated by the multiplier generation method provided in this application. The register transfer level description includes a first part description and a second part description, wherein the first part description is configured to handle the lower bounds of the first operand. Bit and the low of the second operand The second part of the description is a behavioral-level description of the bitwise operation logic, configured to describe the bitwise operations involving the first operand. The bit and the second operand's first The structure of the bitwise operation logic is described, wherein: a first arithmetic unit 220 and a second arithmetic unit 230 are used to generate a partial product when multiplying the first operand and the second operand; an adder circuit 210, coupled to the first arithmetic unit 220 and the second arithmetic unit 230, is used to combine the outputs of the first arithmetic unit and the second arithmetic unit into the final product output through addition. It is understood that both the first arithmetic unit 220 and the second arithmetic unit 230 are generated by process mapping of the register-transfer level description using logic synthesis tools, but there is a fundamental difference in their source description levels: the first arithmetic unit 220 originates from the behavioral-level abstraction of the first part of the description, which uses arithmetic multiplication operators on the lower bounds of the first operand. Bit and the low of the second operand The second operation unit 230 is derived from the structure-preserving encoding described in the second part, which uses bitwise logical operators, bitwise concatenation operators, and arithmetic addition operators to perform deep reorganization and optimization of the addition hierarchy, cell size, and interconnection topology, thereby maximizing the performance and area efficiency of the core multiplication operation. The bit and the second operand's first The design employs explicit hard-wired connections to prevent the synthesizer from logically reorganizing the sign bit extension, bitwise AND, bitwise XOR, and compensation addend concatenation paths, ensuring strict structural consistency between the gate-level implementation of the sign correction logic and the RTL code. The adder circuit 210 is coupled to the output ports of the first arithmetic unit 220 and the second arithmetic unit 230, forming a physical connection of a multi-input adder tree. Its function is to perform addition operations to finally accumulate the core unsigned product generated by the first arithmetic unit 220, the sign correction data generated by the second arithmetic unit 230, the sign cross term correction data, and the compensation addend term, outputting a complete and accurate mixed-signed multiplication result. This hierarchical architecture decouples the core multiplication operation from the sign correction logic during the synthesis stage. The former undergoes fully automated process-dependent optimization by the synthesizer, while the latter remains structurally locked to ensure functional correctness. This allows the same hardware multiplier to support time-division multiplexing of unsigned, signed, and mixed-signed operation modes without expanding the original operand width or adding redundant mode selection hardware, which is beneficial for improving area efficiency, process portability flexibility, and design convergence speed. The first arithmetic unit 220 and the second arithmetic unit 230 of the multiplier 200 described above can dynamically activate the corresponding sign correction path and compensation logic in each clock cycle according to the real-time level states of the first and second sign configuration signals: when both signals are at logic low level, the sign correction logic of the second arithmetic unit is bypassed, and the circuit only performs multiplication of unsigned numbers; when both signals are at logic high level, both sign correction data and compensation addend terms are activated, and the circuit performs multiplication of signed numbers; when the two signal levels are different, only the sign correction path corresponding to the signed operand is effective, and the circuit performs mixed multiplication of signed and unsigned numbers. This mechanism divides the usage period of hardware resources in the time domain by controlling the level changes of the control signals, so that the same set of adder trees, partial product compression arrays and sign processing logic undertake data processing tasks of different operation modes in adjacent clock cycles, without designing independent multiplier hardware for each mode. Thus, without increasing the area overhead, the hardware utilization rate is increased to the theoretical maximum, reducing chip area, static power consumption and design complexity.

[0038] Please see Figure 8Based on the same inventive concept, this application also provides a multiplication system, including: an operand splitting unit, a first multiplier, a second multiplier, a third multiplier, a fourth multiplier, and a result combination unit. The second and third multipliers are multipliers as provided in this application embodiment. The operand splitting unit is configured to split an M-bit signed third operand into S-bit suboperands and T-bit suboperands, and to split an N-bit signed fourth operand into U-bit suboperands and V-bit suboperands; wherein S+T=M, U+V=N, and M, N, S, T, U, and V are all positive integers; the first multiplier, coupled to the operand splitting unit, is configured to perform signed-to-signed multiplication operations by multiplying the S-bit suboperands and the U-bit suboperands. The system comprises: a second multiplier, coupled to the operand splitting unit, configured to perform signed-to-unsigned multiplication of an S-bit suboperand and a V-bit suboperand; a third multiplier, coupled to the operand splitting unit, configured to perform unsigned-to-signed multiplication of an T-bit suboperand and a U-bit suboperand; a fourth multiplier, coupled to the operand splitting unit, configured to perform unsigned-to-unsigned multiplication of an T-bit suboperand and a V-bit suboperand; and a result combination unit, coupled to the first, second, third, and fourth multipliers, configured to perform shift and addition operations on the outputs of the first, second, third, and fourth multipliers to generate the result of the multiplication of the third and fourth operands. The above multiplication system aims to achieve efficient decomposition and reconstruction of large-bit-width signed-number multiplication through the collaborative work of multiple multipliers provided in this application. The core architecture of the multiplication system includes an operand splitting unit, four multipliers, and a result combination unit. The operand splitting unit receives an M-bit signed third operand and an N-bit signed fourth operand as input. Based on configurable bit width parameters, it splits the third operand into high-order S-bits and low-order T-bits (S+T=M), and simultaneously splits the fourth operand into high-order U-bits and low-order V-bits (U+V=N). Here, S, T, U, and V are all positive integers and can be set independently to adapt to the bit width allocation requirements of different application scenarios.The four sets of suboperands after splitting are fed into four multipliers: The first multiplier performs the multiplication of the S-bit suboperand and the U-bit suboperand. Since both suboperands originate from the high-order part of the original operands, their sign attribute is signed, so this multiplier is configured as a signed-to-signed operation mode; The fourth multiplier performs the multiplication of the T-bit suboperand and the V-bit suboperand. Both suboperands originate from the low-order part of the original operands, and their sign attribute is unsigned, so it is configured as an unsigned-to-unsigned operation mode; The second multiplier processes the cross-segment bit-width multiplication of the S-bit suboperand and the V-bit suboperand. In this case, the S-bit is a signed number, while the V-bit is an unsigned number, forming a mixed operation mode of signed and unsigned numbers; The third multiplier corresponds to the multiplication of the T-bit suboperand and the U-bit suboperand, constituting another mixed operation mode of unsigned and signed numbers. All four multipliers adopt the multiplier structure provided in this application embodiment, which can dynamically adjust the internal sign correction logic according to the sign configuration signal of the input suboperands. It can accurately implement the multiplication operation of the above four sign combinations on a single hardware architecture without expanding the suboperand bit width. The result combination unit aligns and accumulates the output results of the four multipliers through a shift network and a multi-level addition tree: according to the weight position of the suboperands in the original operands, the output results of the first and second multipliers are shifted left by V bits, and the output results of the third and fourth multipliers are shifted left by T bits. Then, the four intermediate results after shifting are added bit by bit to finally generate the complete multiplication result of the M-bit third operand and the N-bit fourth operand. This system decomposes large-bit-width multiplication into several small-bit-width multiplication subtasks and optimizes each sub-multiplier independently using the aforementioned hierarchical description strategy. This avoids the excessive overhead in area and power consumption of a single large-bit-width multiplier and makes full use of the reusability and process adaptability of hybrid symbol multipliers, thus achieving comprehensive optimization of large-bit-width multiplication operations in terms of area, performance and design efficiency.

[0039] Based on the same inventive concept, this application also provides a multiplication system, including: an operand splitting unit, a multiplier, a time-division multiplexing control unit, and a result combination unit, wherein: the operand splitting unit is configured to split an M-bit signed third operand into S-bit suboperands and T-bit suboperands, and to split an N-bit signed fourth operand into U-bit suboperands and V-bit suboperands; wherein S+T=M, U+V=N, and M, N, S, T, U, and V are all positive integers; the multiplier is the multiplier provided in this application embodiment; the time-division multiplexing control unit is connected to the operand splitting unit and the multiplication unit. The system is coupled to control the multiplier to perform one of the following operations in different clock cycles: signed-to-signed multiplication of an S-bit suboperand with a U-bit suboperand; signed-to-unsigned multiplication of an S-bit suboperand with a V-bit suboperand; unsigned-to-signed multiplication of a T-bit suboperand with a U-bit suboperand; and unsigned-to-unsigned multiplication of a T-bit suboperand with a V-bit suboperand. The result combination unit is configured to shift and add the four results of the multiplier to generate the result of the multiplication of the third and fourth operands. This multiplication system aims to achieve extreme hardware resource optimization for large-bit-width signed number multiplication through a time-division multiplexing architecture using a single multiplier instance. The core architecture of this system includes an operand splitting unit, a single multiplier, a time-division multiplexing control unit, and a result combination unit. The operand splitting unit receives an M-bit signed third operand and an N-bit signed fourth operand as input. Based on configurable bit width parameters, it splits the third operand into high-order S bits and low-order T bits (satisfying S+T=M), and simultaneously splits the fourth operand into high-order U bits and low-order V bits (satisfying U+V=N). Here, S, T, U, and V are all positive integers and can be independently set to adapt to the bit width allocation requirements of different application scenarios. Under the scheduling of the time-division multiplexing control unit, the four sets of split sub-operands are sequentially fed into a single multiplier. This multiplier, as provided in this embodiment, has its first bit width dynamically configured to max(S,T) and its second bit width dynamically configured to max(U,V), thereby enabling multiplication operations of unequal-length sub-operands through a sign extension mechanism without expanding the original sub-operand bit width.The time-division multiplexing control unit is coupled with the operand splitting unit and the multiplier. It is configured to control the multiplier to perform signed multiplication of S-bit suboperands and U-bit suboperands, signed multiplication of S-bit suboperands and V-bit suboperands, unsigned multiplication of T-bit suboperands and U-bit suboperands, and unsigned multiplication of T-bit suboperands and V-bit suboperands respectively in four consecutive or discontinuous clock cycles. In each operation cycle, the multiplier adaptively switches the sign operation mode by dynamically assigning a sign configuration signal, without the need to configure independent hardware for each sign combination. The result combination unit is configured to read four sets of partial products from the cache unit, left-shift the S×U result by (T+V) bits according to the weight position of the sub-operands in the original operands, left-shift the S×V result by T bits, left-shift the T×U result by V bits, and not left-shift the T×V result. The four shifted intermediate results are then accumulated bit-by-bit through a multi-level addition tree to generate the complete multiplication result of the M-bit third operand and the N-bit fourth operand. The time-division multiplexing architecture adopted by the above multiplication system reduces the hardware overhead of the multiplier by converting parallel hardware resources into time-division multiplexing, optimizing chip area, static power consumption, and routing resources. Simultaneously, through the collaborative design of the cache unit and the result combination unit, the computational throughput is ensured to be equivalent to that of a parallel architecture.

[0040] Reference Figure 9Electronic device 300 includes a processor 310, a memory 320, and a communication interface 330. These components are interconnected and communicate with each other via a communication bus 340 and / or other forms of connection mechanisms (not shown). The memory 320 includes one or more (only one is shown in the figure), which can be, but is not limited to, random access memory, read-only memory, programmable read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, etc. The processor 310 and other possible components can access the memory 320, reading and / or writing data therein. The processor 310 includes one or more (only one is shown in the figure), which can be an integrated circuit chip with signal processing capabilities. The processor 310 can be a general-purpose processor, including a central processing unit, microcontroller unit, network processor, or other conventional processor; it can also be a special-purpose processor, including a digital signal processor, application-specific integrated circuit, field-programmable gate array, or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component. The communication interface 330 includes one or more (only one is shown in the figure) and can be used to communicate directly or indirectly with other devices for data exchange. For example, the communication interface 330 can be an Ethernet interface; it can be a mobile communication network interface, such as an interface for 3G, 4G, or 5G networks; or it can be other types of interfaces with data transmission and reception functions. One or more computer program instructions can be stored in the memory 320, and the processor 310 can read and execute these computer program instructions to implement the multiplier generation method provided in this application embodiment and other desired functions.

[0041] This application also provides a computer-readable storage medium storing computer program instructions. These computer program instructions are read and executed by a processor to perform the multiplier generation method provided in this application. For example, the computer-readable storage medium can be implemented as follows: Figure 9 The memory 320 in the electronic device 300, or a separate storage product (such as a USB flash drive, portable hard drive, etc.).

[0042] This application also provides a computer program product including computer program instructions. These computer program instructions are read and executed by a processor to perform the multiplier generation method provided in this application. For example, these computer program instructions can be stored in... Figure 9 The memory 320 in the electronic device 300 is located inside the memory, or it is stored in a separate storage product (such as a USB flash drive, portable hard drive, etc.).

[0043] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for generating a multiplier, characterized in that, The method includes: Obtain a first symbol configuration signal and a second symbol configuration signal; wherein the first symbol configuration signal and the second symbol configuration signal are used to indicate whether the first operand and the second operand are signed numbers, respectively; A register-transfer level description of the multiplier circuit is generated; wherein the register-transfer level description includes a first part description and a second part description; the first part description is configured to provide a low-level description of the first operand. Bit and the low of the second operand A behavioral-level description of the bitwise operation logic; the behavioral-level description allows the synthesizer to perform automatic optimization; the second part of the description is configured to describe the bitwise operation logic involving the first operand. The bit and the second operand's first The structure of the bitwise operation logic is preserved in a description; this preserved description prevents the synthesizer from performing logic reconfiguration. The width of the first operand is the first bit width. This is the second bit width of the second operand; The synthesizer is invoked to perform logic synthesis on the register transfer level description to generate the gate-level netlist of the multiplier circuit.

2. The multiplier generation method according to claim 1, characterized in that, The second part of the description is configured to execute: Based on the first symbol configuration signal and the second symbol configuration signal, a mode distinction identifier, a first symbol correction enable signal, and a second symbol correction enable signal are obtained; wherein, the mode distinction identifier is obtained by XOR operation of the first symbol configuration signal and the second symbol configuration signal; the first symbol correction enable signal is equal to the first symbol configuration signal, and the first symbol correction enable signal is used to independently control the correction path related to the sign bit of the first operand; the second symbol correction enable signal is equal to the second symbol configuration signal, and the second symbol correction enable signal is used to independently control the correction path related to the sign bit of the second operand; In response to the first sign correction enable signal being at an active level, first sign correction data is generated; wherein, the first sign correction data is used to characterize the cross-multiplication of the sign bit of the first operand and the value bit of the second operand and the dynamically inverted and corrected partial product. In response to the second sign correction enable signal being active, second sign correction data is generated; wherein, the second sign correction data is used to characterize the cross-multiplication of the sign bit of the second operand and the value bit of the first operand and the dynamically inverted and corrected partial product. Obtain sign cross term correction data; wherein, the sign cross term correction data is used to characterize the Boolean product after dynamic inversion correction of the sign phase AND of the first operand and the second operand according to the mode distinction identifier; In response to the first symbol correction enable signal being at an active level, a first compensation addend term is generated; wherein, the first compensation addend term is used to compensate for the symbol compensation introduced by the participation of the number of signs in the first symbol correction data; In response to the second symbol correction enable signal being at an active level, a second compensation addend is generated; wherein the second compensation addend is used to compensate for the symbol compensation introduced by the participation of the number of signs in the second symbol correction data; In response to the mode distinction identifier being active, a third compensation addend is generated; wherein, the third compensation addend is used to adjust the sign cross term correction data in the mixed sign mode due to the sign compensation introduced by the number of signs involved; The first sign correction data, the second sign correction data, the sign cross term correction data, the first compensation addend term, the second compensation addend term, and the third compensation addend term are combined with the output result described in the first part through addition to obtain the final product of the multiplier circuit.

3. The multiplier generation method according to claim 2, characterized in that, The step of generating first symbol correction data in response to the first symbol correction enable signal being at an active level includes: Extend the most significant bit of the first operand to Bit width, obtain the first symbol extension signal; The first symbol-extended signal is combined with the low value of the second operand. Perform a bitwise AND operation on each bit to obtain the first intermediate result; Combine the first intermediate result with the first symbol correction enable signal. The bit-repeated spliced ​​signal is subjected to bit-by-bit XOR operation to obtain the first symbol correction data.

4. The multiplier generation method according to claim 2, characterized in that, The generation of second symbol correction data in response to the second symbol correction enable signal being at an active level includes: Extend the most significant bit of the second operand to Bit width, obtain the second symbol extension signal; The second symbol-extended signal is combined with the low value of the first operand. Perform a bitwise AND operation on the bits to obtain a second intermediate result; The second intermediate result is compared with the second symbol correction enable signal. The bit-repeated spliced ​​signal is subjected to bit-by-bit XOR operation to obtain the second symbol correction data.

5. The multiplier generation method according to any one of claims 1 to 4, characterized in that, The second part of the description is configured as follows: Using bitwise logical operators, bit concatenation operators, and arithmetic addition operators, the first operand is processed... The bit and the second operand's first The structure of the bitwise operation logic is described.

6. The multiplier generation method according to any one of claims 1 to 4, characterized in that, The register transfer level description is configured as follows: Under the dynamic control of the first symbol configuration signal and the second symbol configuration signal, the multiplier circuit performs unsigned multiplication with unsigned numbers, signed multiplication with signed numbers, and mixed multiplication with signed and unsigned numbers in different clock cycles.

7. The multiplier generation method according to any one of claims 1 to 4, characterized in that, The first bit width and the second bit width are positive integers that are configured independently; the first bit width and the second bit width are configured to be equal or unequal.

8. The multiplier generation method according to any one of claims 1 to 4, characterized in that, The call synthesizer performs logical synthesis on the register transfer level description, including: Input the timing and area constraints of the target process library into the synthesizer so that the synthesizer generates a gate-level netlist that satisfies the timing and area constraints.

9. A multiplier, characterized in that, include: The addition circuit and the first and second arithmetic units obtained by logical synthesis of the register transfer level description generated by the multiplier generation method according to any one of claims 1 to 8, wherein the register transfer level description includes a first part description and a second part description, the first part description being configured to access the low-order part of the first operand. Bit and the low of the second operand The second part of the description is configured to describe the behavior-level logic of the bit operation logic involving the first operand. The bit and the second operand's first The structure of the bitwise operation logic is preserved in the description, where: The first arithmetic unit and the second arithmetic unit are used to generate a partial product when the first operand and the second operand are multiplied. The addition circuit is coupled to the first arithmetic unit and the second arithmetic unit, and is used to combine the output of the first arithmetic unit and the output of the second arithmetic unit into a final product output through addition operation.

10. A multiplication operation system, characterized in that, include: The system comprises an operand splitting unit, a first multiplier, a second multiplier, a third multiplier, a fourth multiplier, and a result combination unit, wherein the second and third multipliers are multipliers as described in claim 9, wherein: The operand splitting unit is configured to split an M-bit signed third operand into an S-bit suboperand and a T-bit suboperand, and to split an N-bit signed fourth operand into a U-bit suboperand and a V-bit suboperand; wherein S+T=M, U+V=N, and M, N, S, T, U, and V are all positive integers; The first multiplier, coupled to the operand splitting unit, is configured to perform signed-to-signed multiplication by multiplying the S-bit suboperand with the U-bit operand; The second multiplier, coupled to the operand splitting unit, is configured to perform signed-to-unsigned multiplication by multiplying the S-bit suboperand with the V-bit operand; The third multiplier, coupled to the operand splitting unit, is configured to perform unsigned and signed multiplication operations by multiplying the T-bit suboperands by the U-bit operands; The fourth multiplier, coupled to the operand splitting unit, is configured to perform unsigned multiplication of the T-bit suboperand and the V-bit operand. The result combination unit, coupled to the first multiplier, the second multiplier, the third multiplier, and the fourth multiplier, is configured to perform shift and addition operations on the output results of the first multiplier, the second multiplier, the third multiplier, and the fourth multiplier to generate the multiplication result of the third operand and the fourth operand.

11. A multiplication operation system, characterized in that, It includes an operand splitting unit, a multiplier, a time-division multiplexing control unit, and a result combination unit, wherein: The operand splitting unit is configured to split an M-bit signed third operand into an S-bit suboperand and a T-bit suboperand, and to split an N-bit signed fourth operand into a U-bit suboperand and a V-bit suboperand; wherein S+T=M, U+V=N, and M, N, S, T, U, and V are all positive integers; The multiplier is the multiplier as described in claim 9; The time-division multiplexing control unit, coupled to the operand splitting unit and the multiplier, is configured to control the multiplier to perform one of the following operations in different clock cycles: The signed-to-signed multiplication operation is the multiplication of the S-bit operand with the U-bit operand. The signed-to-unsigned multiplication operation is the multiplication of the S-bit operand with the V-bit operand. The unsigned and signed multiplication operation of multiplying the T-bit operand and the U-bit operand; The unsigned number multiplication operation is the multiplication of the T-bit operand with the V-bit operand. The result combination unit is configured to perform shift and addition operations on the four operation results of the multiplier to generate the multiplication result of the third operand and the fourth operand.

12. An electronic device, characterized in that, include: A processor, a memory, and a communication bus, wherein the processor and the memory communicate with each other via the communication bus; The memory stores program instructions that can be executed by the processor, and the processor can execute the method as described in any one of claims 1 to 8 by calling the program instructions.

13. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed by a computer, cause the computer to perform the method as described in any one of claims 1 to 8.

14. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the method as described in any one of claims 1 to 8.

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