A sparse-dense matrix multiplication array with high multiplier utilization rate for a graph neural network based on an FPGA

Abstract

The application discloses a sparse-dense matrix multiplication array of a graph neural network high-multiplier utilization rate based on FPGA, which can split sparse-dense multiplication in combination operation in the graph neural network through a set of multiplication-addition array structure, can accumulate effective values from different nodes together in an undetermined quantity, and can obtain a required sparse-dense matrix multiplication result. The method has more than 95% multipliers in an effective operation in each cycle on average, does not need complex data preprocessing, has high utilization rate of node feature vectors, and has the advantages of less required multipliers and the like.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of machine learning, and more particularly, to a sparse-dense matrix multiplication array with high utilization of multipliers for graph neural networks based on FPGA. BACKGROUND

[0002] Deep learning represented by convolutional neural networks (CNN) has excellent performance in a wide range of application scenarios, such as object detection, video processing, speech recognition, etc., but it can only extract and analyze potential information from Euclidean data. However, in recent years, more and more applications model complex relationships between objects as graphs, a non-Euclidean data structure.

[0003] In a graph, nodes represent objects of an application, and edges represent relationships between the objects. In some application scenarios, a graph has more than a million nodes. The degree of a node, that is, the number of edges associated with a node, varies greatly in a graph, but generally follows a power-law distribution. Moreover, different graphs have different characteristics of each node, and this irregularity makes it difficult for convolution and other operations to extract target features.

[0004] Graph convolutional networks (GNN) can well handle this type of graph data and have achieved good results in chemical reactivity prediction, e-commerce, and many other application scenarios, but the data involved has highly unbalanced non-zero data distribution, strong sparsity, and large matrix size. These data characteristics require GNN models to support both dense and extremely sparse computing operations, adapt to the structure of specific GNN algorithm variables and graphs, and be scalable to very large graphs. This makes existing deep convolutional neural network (DCNN) acceleration structures not directly applicable to GNN.

[0005] The GNN inference of each layer mainly includes two stages: aggregation and combination. In the aggregation stage, each node will aggregate the feature vectors of its neighbors to update. Since the adjacency matrix between nodes is extremely sparse and the feature matrix is also not very dense, the calculation intensity involved is not high, but a large number of irregular memory accesses are involved. In the combination stage, the aggregated edges and nodes are converted through a combination function, and the weight matrix involved is dense, so it involves dense matrix multiplication calculation. When the aggregation function of the GNN is linear, the order between aggregation and combination can be switched, but the order of the layers needs to be preserved to avoid violating data dependencies. The existing GNN accelerators are mainly deployed on application-specific integrated chips (ASICs) and field-programmable gate arrays (FPGAs). Since the development cycle of ASIC is long, its flexibility cannot meet the different data characteristics in different application scenarios. However, the rich on-chip storage resources, general logic resources and computing resources of commercial high-end FPGAs can provide powerful parallel computing capabilities. This multi-instruction multi-data stream feature can better meet the needs of GNN accelerators than the single-instruction but multi-data stream of CPUs and the single-instruction multi-data stream of GPUs, and can parallelly process different processing stages. Moreover, FPGA has lower power consumption and flexible reconfigurability.

[0006] The existing sparse-dense matrix multiplication array design for the combination stage of GNN basically wants to reuse the weight and feature matrices at the same time, which results in complex data preprocessing and many invalid operations in the calculation process, making the effective utilization rate of the multiplier low, and less than 25% of the used multipliers can perform effective operations per cycle on average.

[0007] The prior art discloses a configurable sparse attention mechanism hardware accelerator, which comprises a sampling dense matrix multiplication operation module, a mask block packing module and a configurable sparse matrix multiplication operation module; the sampling dense matrix multiplication operation module adopts a hardware structure of a systolic array; the mask block packing module comprises a column number counter, a row activation unit counter and a buffer; the configurable sparse matrix multiplication operation module comprises a configurable operation unit PE, a register array and a divider, and the configurable operation unit is separated from the register array. The effective utilization rate of the multiplier is still low in this scheme. SUMMARY

[0008] The present application provides a sparse-dense matrix multiplication array based on FPGA for high utilization rate of GNN multipliers, which reduces the number of required multipliers and improves the overall utilization rate of multipliers.

[0009] To solve the above technical problems, the technical scheme of the present application is as follows:

[0010] A sparse-dense matrix multiplication array based on FPGA for high multiplier utilization of a graph neural network, which is used in an application scenario capable of combining and then aggregating, and comprises a preprocessing module, a feature cache module, a multiplication array and an addition array, wherein:

[0011] The input of the preprocessing module is a GNN model and a dataset that need to be processed, and the preprocessing module generates the required functional configuration parameters and feature matrix according to the GNN model and the dataset;

[0012] The input of the feature cache module is the functional configuration parameters, and the feature cache module provides a cache and sends the valid values of the feature matrix into the multiplication array in a certain order through the cache;

[0013] The multiplication array performs multiplication operations and sends the operation results to the addition array, and further comprises a memory for storing a weight matrix;

[0014] The addition array is controlled by the functional configuration parameters, and combines and integrates the operation results of the multiplication array, so that the parts from the same node can be added together, and finally the combined part results required in the subsequent aggregation stage are obtained.

[0015] Preferably, the preprocessing module generates the required functional configuration parameters according to the GNN model and the dataset and sends them into the feature cache module, and then slices and rearranges the feature matrix and the weight matrix according to the dataset and the functional configuration parameters, and sends the CSR-encoded feature matrix after slicing and rearrangement into the feature cache module.

[0016] Preferably, the slicing and rearrangement of the feature matrix is according to the number of valid values owned by each node, and the greedy algorithm is traversed according to the number of valid values from large to small, and the valid values of each node are evenly distributed into different groups as much as possible.

[0017] Preferably, the feature cache module comprises a feature cache controller, a feature matrix memory, a decoder and a buffer, wherein the feature cache controller receives the functional configuration parameters and controls the feature matrix memory according to the functional configuration parameters, the feature matrix memory receives the CSR-encoded feature matrix, and under the control of the feature cache controller, the feature matrix is transported to the decoder for decoding, and the decoded feature matrix data is entered into the buffer and waits to be transported to the multiplication array.

[0018] Preferably, the number of nodes that can be processed in each cycle is limited, and it is assumed that only n vertex numbers can be processed in each cycle, and the valid values of the vertex numbers exceeding the range of n are cached, and the F efftpThe effective value is inputted into the input buffer in priority, and if the effective value is insufficient efftp The input is requested again to input the feature matrix.

[0019] Preferably, the multiplication array comprises a plurality of multiplication units, each of which stores a corresponding weight matrix.

[0020] Preferably, the multiplication array comprises F efftp multipliers, wherein Weightsize represents the dimension of the weight matrix, and m represents the number of groups of the feature matrix slice rearrangement.

[0021] Preferably, the addition array is an addition array with a size of F efftp ×log2F efftp The final destination of each effective value is determined according to the vertex number of the effective value, and then the required combination result can be obtained.

[0022] Preferably, a group of Weightsize*32bit addition results are stored in each calculation unit in each addition array in each clock cycle, and the output result of three calculation units of the previous layer can be simultaneously accepted, and the output result comprises two parts: the vertex number and the addition result. And through the vertex numbers of the three inputs and the position information of the calculation unit in the addition array, the logical control flow of whether to use the three input addition results is obtained.

[0023] Preferably, when the number of nodes processed in each cycle is not limited and the feature vector is not preprocessed and sliced, the time for completing the combination of the whole graph in a single layer is:

[0024]

[0025] wherein Fea_eff_num represents the total number of effective values contained in the feature matrix, F efftp represents the number of effective values inputted from the feature matrix in each cycle, Clk combination represents the total number of clock cycles required for an effective feature value from inputting into the whole combination module to outputting, and clk_period represents the time required in each clock cycle.

[0026] Compared with the prior art, the beneficial effects of the technical scheme of the present application are:

[0027] (1) The present application makes full use of the sparsity of the feature matrix and the characteristic of less weight matrix data, reduces the utilization rate of weight data, increases the utilization rate of feature data, and makes the effective operation amount in each cycle as close as possible to the number of multipliers used. In the case of the same calculation amount, only a smaller number of multipliers is required compared with other schemes.

[0028] (2) The memory access of the present application has regularity, and each time adjacent F efftp characteristic effective values are read from the DRAM, which fully utilizes the bandwidth. This also makes the present application have generality on different data sets, without complex data preprocessing, only log2F efftp times of scheduling accumulation in the addition array are needed to obtain the required result. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 The figure is a schematic diagram of the sparse-dense matrix multiplication array structure of the present application.

[0030] Figure 2 The figure is a feature input cache flow chart.

[0031] Figure 3 The figure is a multiplication unit module diagram.

[0032] Figure 4 The figure is an addition unit module diagram.

[0033] Figure 5 The figure is an addition array schematic diagram. DETAILED DESCRIPTION

[0034] The drawings are only used for illustrative purposes and cannot be understood as limiting the present patent;

[0035] In order to better illustrate the present embodiment, some components in the drawings may be omitted, enlarged or reduced, and do not represent the actual product size;

[0036] For those skilled in the art, it is understandable that some well-known structures in the drawings and their descriptions may be omitted.

[0037] The technical solutions of the present application will be further described below in combination with the drawings and embodiments.

[0038] Embodiment 1

[0039] The present embodiment provides a sparse-dense matrix multiplication array with high utilization rate of FPGA-based graph neural network multipliers, as shown in Figure 1 The sparse-dense matrix multiplication array is used in an application scenario capable of combining first and aggregating later, and the sparse-dense matrix multiplication array includes a preprocessing module, a feature cache module, a multiplication array and an addition array, wherein:

[0040] The input of the preprocessing module is a GNN model and a data set that need to be processed, and the preprocessing module generates the required functional configuration parameters and feature matrix according to the GNN model and the data set;

[0041] The input of the feature cache module is the function configuration parameter, and the feature cache module provides a cache and sends the effective values of the feature matrix into the multiplication array in a certain order through the cache.

[0042] The multiplication array performs multiplication operation and sends the operation result into the addition array, and further includes a memory for storing the weight matrix.

[0043] The addition array is controlled by the function configuration parameter, and the operation results of the multiplication array are combined and integrated, so that the partial sums from the same node can be accumulated together, and finally the combined partial results required in the subsequent aggregation stage are obtained.

[0044] By using the characteristics of the sparsity of the feature matrix, the dimension of the feature vector being much smaller than the number of nodes, and the small data amount of the weight matrix in the GNN calculation process, a calculation unit array special for the combination stage of the GNN is designed. The effective values in the feature matrix are input into the multiplier in a certain order, and then the multiplication results are combined and integrated through an addition array, so that the partial sums from the same node can be accumulated together, and finally the combined partial results required in the subsequent aggregation stage are obtained.

[0045] Embodiment 2

[0046] This embodiment is based on embodiment 1 and further discloses the following content:

[0047] The preprocessing module generates the required function configuration parameter according to the GNN model and the data set and sends it into the feature cache module, and then slices and rearranges the feature matrix and the weight matrix according to the data set and the function configuration parameter. After the sliced and rearranged feature matrix is CSR encoded, it is sent into the feature cache module.

[0048] The slicing and rearranging of the feature matrix is according to the number of effective values owned by each node, from large to small, according to the greedy algorithm to traverse all nodes, and the effective values of each node are evenly distributed to different groups as much as possible.

[0049] The feature cache module includes a feature cache controller, a feature matrix memory, a decoder and a buffer, wherein the feature cache controller receives the function configuration parameter and controls the feature matrix memory according to the function configuration parameter, the feature matrix memory receives the CSR encoded feature matrix, and under the control of the feature cache controller, the feature matrix is sent to the decoder for decoding, and the decoded feature matrix data is entered into the buffer and waits to be sent to the multiplication array.

[0050] In order to save logic resources, the number of nodes that can be processed per cycle is limited, assuming that n vertices can be processed per cycle, the effective values of vertex numbers exceeding n are cached, and the F efftp effective values input per cycle are preferentially input into the cache, and if the required F efftp inputs are insufficient, the feature matrix is requested to be input again.

[0051] The multiplication array includes a plurality of multiplication units, and each multiplication unit stores a corresponding weight matrix.

[0052] Since each BRAM resource of the FPGA can be split into two 18bitx1024 dual-port BRAMs, the feature vector dimension can be directly used as the address of the BRAM for indexing to obtain the required weight of the effective value, and the two ports stored in each group can support the indexing of two feature effective values. That is, assuming that F efftp effective values are obtained from the feature matrix per cycle, only groups of BRAMs can meet the weight input requirement. Each group of BRAMs requires BRAMs. Here, Weightsize refers to the dimension of the weight, and Feasize refers to the dimension of the feature vector. At this time, the entire combined multiplication array only requires F efftp x Weightsize multipliers. By copying the weight matrix, when the feature effective values are read in order, each feature effective value has a corresponding weight for effective operation, and the number of repeated calculations is reduced. F efftp x Weightsize multiplication results are obtained per clock cycle, and the F efftp feature values obtained after preprocessing meet the requirement that the effective values of the same node are adjacent.

[0053] In order to save the number of BRAMs used, when the dimension of the feature vector exceeds 1024, the feature vector dimension is sliced and rearranged using preprocessing, so that the feature vector of each vertex number is as evenly distributed as possible in the groups.

[0054] The multiplication array includes F efftp x Weightsize x m multipliers, where Weightsize represents the dimension of the weight matrix, and m represents the number of groups of feature matrix slice rearrangement.

[0055] The addition array is an addition array with a size of F efftp x log2F efftp , and the final destination of each effective value is determined according to the vertex number of the effective value, so that the required combination result can be obtained.

[0056] Each calculation unit in each adder array stores a set of Weightsize*32bit adder results in each clock cycle, which can simultaneously accept the output results of three calculation units in the previous layer. The output results include two parts: vertex number and adder result. Through the vertex numbers of the three inputs and the position information of the calculation unit in the adder array, the logical control flow of whether to use the three input adder results is obtained.

[0057] When the number of nodes processed in each cycle is not limited and the feature vector is not preprocessed, the time for completing the single-layer combination of the whole graph is:

[0058]

[0059] Where Fea_eff_num represents the total number of effective values contained in the feature matrix, F efftp represents the number of effective values input from the feature matrix in each cycle, Clk combination represents the total number of clock cycles required for a feature effective value from input to output of the whole combination module, and clk_period represents the time required in each clock cycle.

[0060] Take the Cora dataset of the GCN model as an example: the feature matrix vector dimension is 1433, the node number is 2708, the effective value number is 49216, and the weight dimension is 16. Because the node number is small, its adjacency matrix and feature matrix can be completely stored on the FPGA, and there is no need to slice the node dimension, and each node has an average of 19 effective values. In order to the subsequent CSR decoding part, the number of effective values and the number of nodes input per cycle are both 2, according to the ratio of the number of effective values, the number of nodes and the dimension of the feature vector, 8 nodes and 64 effective values are input per cycle. Because 8 nodes are input per cycle, the indptr (representing the number of effective values before each node) cache size of the CSR encoding is log249216x8x2=256bit. Because the weight dimension is 16, 64 effective values are needed, 64 multiplication units are needed, each unit has 16 multipliers (DSP) and a half group of BRAM, the bit width of BRAM storage is 16*16=256, and the depth is 1433, that is, a group of BRAM needs 12 BRAM, a total of 16*64=1024 multipliers (DSP) and 12*(64 / 2)=384 BRAM. 64 effective values, in order to facilitate the cache operation, a feature cache that can store 64*2=128 effective values needs to be prepared, and the specific storage amount is 128*(16+log21433)=3456bit. Since 64 effective values are input, the size of the addition array is 64xlog264. The depth of the partial combination result cache is twice the input node number, that is, 8*2=16, and the specific storage amount is 16*(16*32)=8192bit. The feature vector dimension exceeds 1433, so the feature vector needs to be sliced into two parts less than 1024 from the perspective of saving BRAM. The method of slicing the feature dimension of the feature matrix is to traverse all nodes according to the greedy algorithm from large to small according to the number of effective values owned by each node, and to divide the effective values of each node into different groups as evenly as possible. This also leads to an increase in the node throughput required by the CSR input part, and some logic judgment is needed in the partial combination result part, and some channels in the addition array need to be gated and truncated, which also brings changes to the front cache: the depth of the BRAM is less than 1024, so a group of weight cache only needs 7.5 BRAM, a total of 240 BRAM, the effective value cache becomes 2*64*(16+log21024)=3328bit, and the node indptr cache becomes In summary, the following configuration parameters can be obtained from the GCN model and the Cora dataset: 8 nodes and 32+32 valid values can be input per cycle, the feature cache depth of both groups is 32*2=64, there are 64 multiplication units, a total of 64*16=1024 multipliers are needed, and the size of the addition array is 64xlog264.

[0061] The valid values and nodes indptr mentioned earlier are from the CSR encoding method of a sparse matrix. All valid values of an original sparse matrix can be represented by its column (col), row (row), and data (data). The CSR encoding method represents the row (row) by the number of valid values before each row, which is called indptr. The original col is represented by indices, and data remains unchanged. At this time, taking the Cora dataset as an example, the number of data and indices is 49216, which is the total number of valid values, so the bit width of the valid value cache is 16+log21433=27 bits. The original indptr is 2708+1=2709 nodes in total (the last 2709 indptr is needed to calculate the last one, that is, the number of valid values owned by the 2708th node), so the cache bit width is log249216=16 bits. The decoding of the CSR encoding focuses on converting indptr back to the original row. The specific method is to compare the number of valid values that have been output and the valid value that is being output by using a counter to obtain a set of comparison values, the specific number is 8*2=16, which is twice the number of input nodes per cycle, that is, the valid value can be associated with 16-1=15 nodes. Here, in order to save the number of logic stages, the indptr is not directly converted back to the original row value, but is converted into an 8-bit vertex number, the first 7 bits are represented in a way similar to one-hot code, and the 8th bit is used to represent whether it belongs to the first 8 nodes or the last 8 nodes. For example: encoding 1: 8’b0_000_0001; encoding 7: 8’b0_111_1111;

[0062] Encoding 9: 8’b1_000_0001; Encoding 15 (representing an index range beyond the CSR indptr): 8’b1_111_1111.

[0063] The valid values beyond the index range of the existing indptr of the CSR will be cached. Each input of valid values will preferentially select the cached values for input, and a batch of new valid values will also be obtained from the feature matrix. The excess valid values will also be put into the cache until the number of cached values is greater than the number of valid values that can be input per cycle. At this time, only valid values are obtained from the cache. The specific flow chart of the feature cache is as follows: Figure 2The cache scheme can make the valid values satisfy the feature that the same nodes are adjacent and the different nodes are sequentially sorted from small to large, which is the prerequisite of the addition array scheduling.

[0064] The input valid values each contain two parts of {data, indices}, and indices are used as col to obtain the weights required for multiplication as the address of weight BRAM. According to matrix multiplication, each feature matrix valid value needs to be multiplied by 16 weights corresponding to its col, and 16 32-bit multiplication results are obtained. Therefore, the weight BRAM takes out 16*16=256 bits of data each time to perform 16 16-bit*16-bit multiplications, and finally the multiplication array will output 64 16*32=512-bit data and 64 corresponding vertex numbers. For the valid value input exceeding the indptr index range, the vertex number will be 16, representing exceeding the index range, and the data will be 0. The multiplier will not perform operation when it sees the code 16, and directly output the code 16 and data=0. The specific module diagram is shown in Figure 3 .

[0065] The module diagram of each unit of the addition array is shown in Figure 4 . The main goal is to determine the target position of the final scheduling according to the vertex number, and add the partial combination results of the same vertex number. The principle is that the distance between the original position and the scheduling target is decomposed into log264 values in binary, and each period moves the corresponding distance. Since the input valid values satisfy the feature that the same nodes are adjacent and the different nodes are sequentially sorted from small to large, the different nodes will not interfere with each other. Assuming that the a-th valid input of the addition unit is the b-th layer in the log264 layers, the three inputs come from the three addition units of (a-2 b-1 ,b-1)(a,b-1)(a+2 b-1 ,b-1). According to the vertex numbers (target positions or whether it is code 16) of the three addition units and the current position, the required three identifiers are obtained, and the vertex number to be output and the corresponding addition operation are selected. For example, for Cora, that is, the feature dimension is sliced, after obtaining the corresponding 16 partial combination results in each group, the two groups also need to be added. Only when both sides have processed the same node at the same time, the node has been combined, and can be output to the aggregation module for the next operation.

[0066] as Figure 5As shown, an 8×log28 adder array is used as an example to illustrate the specific scheduling process of the adder array. In this diagram, blue, light green, dark green, and yellow represent vertex codes 0, 1, 2, and 3, respectively. Column 0 is the buffer just removed from the multiplication array, and we can directly obtain the vertex code matrix [0,0,1,1,1,2,3,3] and the position matrix [0,1,2,3,4,5,6,7] of column 0. Subtracting the vertex code matrix from the position matrix yields [0,1,1,2,3,3,3,4], and taking its 0th bit and sign bit in binary, we obtain the flag matrix [0,1,1,0,1,1,1,0]. Correspondingly... Figure 4 The flags are 1, 2, and 3. When the flag matrix of column 0 is 0, flag 1 is high, and column 1 will receive the value of column 0 with the same position matrix value. When the position matrix value is increased by 2... 0 When the flag matrix of column 0 at position 1 is 1, flag 2 is high. At this time, column 1 will receive the position matrix value plus 2. 0 The valid value of column 0. When the position matrix value is subtracted by 2 0 When the value of the flag matrix in column 0 of position 1 is negative, flag 3 is high, and column 1 will receive the position matrix value minus 2. 0 The value of column 0. When the index is out of range, the corresponding flag will be 0 directly. For example, for the addition unit in column 1, row 0, its flag 3 will definitely be 0. In summary, the flag matrix of input column 1 {flag1, flag2, flag3} is: [{1,1,0},{0,1,0},

[0067] {0,0,0},{1,1,0},{0,1,0},{0,1,0},{0,0,0},{1,0,0}]. The addition unit in column 1 sums all received values ​​and outputs the sum. Vertex numbers are output according to priority, with flag 1 (the middle vertex number) being the first choice, followed by the vertex numbers below / above. When all flags are 0, the output value is 0, and the vertex code is 16. Due to the adjacency of identical vertices, when flags 2 and 3 are both 1, flag 1 must be 1.

[0068] For column 2, the calculation of the input flags involves adding or subtracting 2 from all positions. 0 Change to add or subtract 2 1 The 0th bit of the binary representation is replaced with the 1st bit. During the calculation, if a vertex is encoded as 16, its associated flag will be set to 0. Therefore, the flag matrix for input column 2 ({flag1, flag2, flag3}) is: [{1,0,0},{1,1,0},{0,1,0},{0,1,0},{0,0,0},{0,0,0},{0,0,0},{1,0,0}]. This process continues, and finally, the target combination result can be obtained in column 3.

[0069] Example 3

[0070] This example provides the comparison of the acceleration performance of the multiplication array of Example 1 and Example 2 on multiple public data sets with other accelerators, as shown in Table 1:

[0071] Table 1

[0072]

[0073] The same or similar reference signs correspond to the same or similar components;

[0074] The terms describing the positional relationship in the drawings are only used for illustrative description, and should not be understood as a limitation on the patent;

[0075] Obviously, the above embodiments of the present application are only examples for clearly illustrating the present application, and are not intended to limit the implementation manner of the present application. Based on the above description, other different forms of changes or variations can be made by those skilled in the art. Here, it is not necessary and impossible to enumerate all the implementation manners. Any modification, equivalent replacement and improvement made within the spirit and principle of the present application should be included in the protection scope of the claims of the present application.

Claims

1. A sparse-dense matrix multiplication array for FPGA-based graph neural networks with high multiplier utilization, comprising: The sparse-dense matrix multiplication array is used in an application scenario capable of combination before aggregation, and comprises a preprocessing module, a feature cache module, a multiplication array and an addition array. The preprocessing module is configured to generate functional configuration parameters and a feature matrix according to the GNN model and the dataset. The feature cache module is configured to provide a cache and send effective values of the feature matrix into the multiplication array in a certain order through the cache. The multiplication array is configured to perform multiplication operations and send operation results to the addition array. The addition array is configured to be controlled by the functional configuration parameters, and is configured to combine and integrate the operation results of the multiplication array, so that parts from the same node can be added together, and finally a combined part result required in a subsequent aggregation stage is obtained. The feature cache module comprises a feature cache controller, a feature matrix memory, a decoder and a buffer.

2. The FPGA-based sparse-dense matrix multiplication array for high multiplier utilization of graph neural networks according to claim 1, wherein, The preprocessing module is configured to generate functional configuration parameters and a feature matrix according to the GNN model and the dataset.

3. The FPGA-based sparse-dense matrix multiplication array for high multiplier utilization of graph neural networks according to claim 2, wherein, The feature cache module is configured to provide a cache and send effective values of the feature matrix into the multiplication array in a certain order through the cache.

4. The FPGA-based sparse-dense matrix multiplication array for high multiplier utilization of graph neural networks of claim 3, wherein, Limit the number of nodes that can be processed per cycle, assuming that each cycle can only handle n vertex numbers, the effective value of the vertex number exceeding n is cached, and the F efftp effective value input in each cycle is preferentially input into the cache, and if the required F efftp input is insufficient, request the feature matrix input again.

5. The FPGA-based sparse-dense matrix multiplication array for high multiplier utilization of graph neural networks according to claim 4, wherein, The multiplication array is configured to perform multiplication operations and send operation results to the addition array.

6. The FPGA-based sparse-dense matrix multiplication array for high multiplier utilization of graph neural networks according to claim 5, wherein, The multiplication array includes F efftp × Weightsize × m multipliers, where Weightsize represents the dimension of the weight matrix, and m represents the number of groups of feature matrix slice rearrangement.

7. The FPGA-based sparse-dense matrix multiplication array for high multiplier utilization of graph neural networks according to claim 6, wherein, The addition array is F efftp x log2F efftp The final destination of each valid value is determined according to the vertex number of the valid value, and the required combination result is obtained.

8. The sparse-dense matrix multiplication array for high multiplier utilization of graph neural networks based on FPGA of claim 7, wherein, The addition array is configured to be controlled by the functional configuration parameters, and is configured to combine and integrate the operation results of the multiplication array, so that parts from the same node can be added together, and finally a combined part result required in a subsequent aggregation stage is obtained.

9. The FPGA-based sparse-dense matrix multiplication array for high multiplier utilization of graph neural networks of claim 8, wherein, The feature cache module comprises a feature cache controller, a feature matrix memory, a decoder and a buffer. The preprocessing module is configured to generate functional configuration parameters and a feature matrix according to the GNN model and the dataset. The feature cache module is configured to provide a cache and send effective values of the feature matrix into the multiplication array in a certain order through the cache. The multiplication array is configured to perform multiplication operations and send operation results to the addition array. The addition array is configured to be controlled by the functional configuration parameters, and is configured to combine and integrate the operation results of the multiplication array, so that parts from the same node can be added together, and finally a combined part result required in a subsequent aggregation stage is obtained. The feature cache module comprises a feature cache controller, a feature matrix memory, a decoder and a buffer. The preprocessing module is configured to generate functional configuration parameters and a feature matrix according to the GNN model and the dataset. The feature cache module is configured to provide a cache and send effective values of the feature matrix into the multiplication array in a certain order through the cache. The multiplication array is configured to perform multiplication operations and send operation results to the addition array. The addition array is configured to be controlled by the functional configuration parameters, and is configured to combine and integrate the operation results of the multiplication array, so that parts from the same node can be added together, and finally a combined part result required in a subsequent aggregation stage is obtained. The feature cache module comprises a feature cache controller, a feature matrix memory, a decoder and a buffer. The preprocessing module is configured to generate functional configuration parameters and a feature matrix according to the GNN model and the dataset. The feature cache module is configured to provide a cache and send effective values of the feature matrix into the multiplication array in a certain order through the cache. The multiplication array is configured to perform multiplication operations and send operation results to the addition array. The addition array is configured to be controlled by the functional configuration parameters, and is configured to combine and integrate the operation results of the multiplication array, so that parts from the same node can be added together, and finally a combined part result required in a subsequent aggregation stage is obtained. The feature cache module comprises a feature cache controller, a feature matrix memory, a decoder and a buffer. The preprocessing module is configured to generate functional configuration parameters and a feature matrix according to the GNN model and the dataset. The feature cache module is configured to provide a cache and send effective values of the feature matrix into the multiplication array in a certain order through the cache. The multiplication array is configured to perform multiplication operations and send operation results to the addition array. The addition array is configured to be controlled by the functional configuration parameters, and is configured to combine and integrate the operation results of the multiplication array, so that parts from the same node can be added together, and finally a combined part result required in a subsequent aggregation stage is obtained. The feature cache module comprises a feature cache controller, a feature matrix memory, a decoder and a buffer. The preprocessing module is configured to generate functional configuration parameters and a feature matrix according to the GNN model and the dataset. The feature cache module is configured to provide a cache and send effective values of the feature matrix into the multiplication array in a certain order through the cache. The multiplication array is configured to perform multiplication operations and send operation results to the addition array. The addition array is configured to be controlled by the functional configuration parameters, and is configured to combine and integrate the operation results of the multiplication array, so that parts from the same node can be added together, and finally a combined part result required in a subsequent aggregation stage is obtained. The feature cache module comprises a feature cache controller, a feature matrix memory, a decoder and a buffer. The preprocessing module is configured to generate functional configuration parameters and a feature matrix according to the GNN model and the dataset. The feature cache module is configured to provide a cache and send effective values of the feature matrix into the multiplication array in a certain order through the cache. The multiplication array is configured to perform multiplication operations and send operation results to the addition array. The addition array is configured to be controlled by the functional configuration parameters, and is configured to combine and integrate the operation results of the multiplication array, so that parts from the same node can be added together, and finally a combined part result required in a subsequent aggregation stage is obtained. The feature cache module comprises a feature cache controller, a feature matrix memory, a decoder and a buffer. The preprocessing module is configured to generate functional configuration parameters and a feature matrix according to the GNN model and the dataset. The feature cache module is configured to provide a cache and send effective values of the feature matrix into the multiplication array in a certain order through the cache. The multiplication array is configured to perform multiplication operations and send operation results to the addition array. The addition array is configured to be controlled by the functional configuration parameters, and is configured to combine and integrate the operation results of the multiplication array, so that parts from the same node can be added together, and finally a combined part result required in a subsequent aggregation stage is obtained. The feature cache module comprises a feature cache controller, a feature matrix memory, a decoder and a buffer. The preprocessing module is configured to generate functional configuration parameters and a feature matrix according to the GNN model and the dataset. The feature cache module is configured to provide a cache and send effective values of the feature matrix into the multiplication array in a certain order through the cache. The multiplication array is configured to perform multiplication operations and send operation results to the addition array. The addition array is configured to be controlled by the functional configuration parameters, and is configured to combine and integrate the operation results of the multiplication array, so that parts from the same node can be added together, and finally a combined part result required in a subsequent aggregation stage is obtained. The feature cache module comprises a feature cache controller, a feature matrix memory, a decoder and a buffer. The preprocessing module is configured to generate functional configuration parameters and a feature matrix according to the GNN model and the dataset. The feature cache module is configured to provide a cache and send effective values of the feature matrix into the multiplication array in a certain order through the cache. The multiplication array is configured to perform multiplication operations and send operation results to the addition array. The addition array is configured to be controlled by the functional configuration parameters, and is configured to combine and integrate the operation results of the multiplication array, so that parts from the same node can be added together, and finally a combined part result required in a subsequent aggregation stage is obtained. The feature cache module comprises a feature cache controller, a feature matrix memory, a decoder and a buffer. The preprocessing module is configured to generate functional configuration parameters and a feature matrix according to the GNN model and the dataset. The feature cache module is configured to provide a cache and send effective values of the feature matrix into the multiplication array in a certain order through the cache. The multiplication array is configured to perform multiplication operations and send operation results to the addition array. The addition array is configured to be controlled by the functional configuration parameters, and is configured to combine and integrate the operation results of the multiplication array, so that parts from the same node can be added together, and finally a combined part result required in a subsequent aggregation stage is obtained. The feature cache module comprises a feature cache controller, a feature matrix memory, a decoder and a buffer. The preprocessing module is configured to generate functional configuration parameters and a feature matrix according to the GNN model and the dataset. The feature cache module is configured to provide a cache and send effective values of the feature matrix into the multiplication array in a certain order through the cache. The multiplication array is configured to perform multiplication operations and send operation results to the addition array. The addition array is configured to be controlled by the functional configuration parameters, and is configured to combine and integrate the operation results of the multiplication array, so that parts from the same node can be added together, and finally a combined part result required in a subsequent aggregation stage is obtained. The feature cache module comprises a feature cache controller, a feature matrix memory, a decoder and a buffer. The preprocessing module is configured to generate functional configuration parameters and a feature matrix according to the GNN model and the dataset. The feature cache module is configured to provide a cache and send effective values of the feature matrix into the multiplication array in a certain order through the cache. The multiplication array is configured to perform multiplication operations and send operation results to the addition array. The where Fea_eff_num represents the total number of effective values contained in the feature matrix, F efftp represents the number of effective values input from the feature matrix per cycle, Clk combination represents the total number of clock cycles required for an effective value of a feature to be input into the entire combination module and output, clk_period represents the time required per clock cycle.

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