Peripheral module firmware burning circuit and method

Abstract

The present disclosure provides a peripheral module firmware burning circuit and method, which is applied to an electronic system comprising a master module and a peripheral module. In a burning mode, the peripheral module is powered by a burner. A bypass power supply for maintaining operation is provided to the master module via a peripheral power supply control circuit and in cooperation with a peripheral burning bypass circuit. The master module can still work and output a stable reset signal to the peripheral module in the case that the system input power supply is not powered. Thus, the peripheral module is prevented from entering a continuous reset or abnormal state due to unstable reset, and the stability and success rate of firmware burning are improved. Meanwhile, in a non-burning mode, the bypass passage is closed, the influence on normal power supply and system operation is reduced, and the complexity and risk of additional wiring or manual switching are reduced.

Description

Technical Field

[0001] This disclosure relates to the field of electronic hardware and embedded systems technology, and more specifically, to a peripheral module firmware burning circuit and method. Background Technology

[0002] In electronic systems that include main control modules (such as MCUs / SoCs) and peripheral modules (such as Bluetooth modules, WiFi modules, communication modules, or sensor modules), peripheral modules typically require firmware flashing during production line manufacturing, repair maintenance, or version upgrades. A common flashing method involves connecting the flashing signal and power supply to the peripheral module via a programmer interface, allowing the peripheral module to enter flashing mode and complete the program writing. Simultaneously, during the flashing process, peripheral modules often rely on the main control module to provide cooperating signals such as reset control, startup configuration, or communication handshakes to ensure that the peripheral module is in the correct flashing timing and operating state.

[0003] In practical applications, programming scenarios often involve situations where the system input power is not connected or is inconvenient to connect (e.g., offline upgrades using a programmer connected only to peripheral modules, multi-station programming on a production line, avoiding powering on the entire device during board-level repairs). The main control module may be in a power-off or undervoltage state, causing unstable reset levels at its GPIO control terminals. Furthermore, the internal structure of the pins may cause abnormal clamping or partial power-on phenomena, leaving peripheral modules in a continuous reset or abnormal startup state. This leads to programming failures, unstable programming processes, and decreased success rates. Summary of the Invention

[0004] This disclosure provides at least one peripheral module firmware burning circuit and method. By using a programmer to power the peripheral module in burning mode, a peripheral power supply control circuit and a peripheral burning bypass circuit provide a bypass power supply to the main control module to maintain operation. This allows the main control module to continue working and output a stable reset signal to the peripheral module even when the system input power is not supplied, thereby preventing the peripheral module from entering a continuous reset or abnormal state due to unstable reset, and improving the stability and success rate of firmware burning. At the same time, the bypass path is kept off in non-burning mode, reducing the impact on normal power supply and system operation, and reducing the complexity and risk of additional wiring or manual switching.

[0005] This disclosure provides a peripheral module firmware burning circuit, applied to an electronic system including a main control module and peripheral modules. The circuit includes:

[0006] The main control power supply circuit is connected to the system input power supply and is used to provide the main control operating power.

[0007] The peripheral power supply circuit is connected to the system input power supply and is used to provide power supply voltage to the peripheral devices.

[0008] A peripheral power supply control circuit is connected between the peripheral power supply circuit and the peripheral module, and is connected to the control terminal of the main control module. It is used to selectively supply power to the peripheral module under the control of the main control module in non-burning mode.

[0009] A programmer interface is connected to the peripheral module and is used to provide programming power supply voltage to the peripheral module by the programmer in programming mode.

[0010] The peripheral programming bypass circuit is connected between the peripheral power supply control circuit and the main control module. In the programming mode, it is configured to receive power from the programmer interface through the peripheral power supply control circuit and provide bypass power to the main control module to maintain operation, so that the main control module outputs a stable reset signal to the peripheral module in the programming mode.

[0011] In one optional implementation, the peripheral power supply control circuit includes a first switching device;

[0012] The source of the first switching device is connected to the peripheral power supply circuit;

[0013] The drain of the first switching device is connected to the peripheral module;

[0014] The gate of the first switching device is connected to the control terminal of the main control module. The gate receives the GPIO control signal output by the main control module to turn on or off the power supply path of the peripheral module according to the GPIO control signal.

[0015] In one optional embodiment, the peripheral power supply control circuit further includes a first resistor, a second resistor, a third resistor, a first capacitor, and a second capacitor;

[0016] One end of the first resistor is connected to the control terminal of the main control module, and the other end is connected to the gate of the first switching device;

[0017] The second resistor and the third resistor are connected in series between the source of the first switching device and ground, and the series node between the second resistor and the third resistor is connected between the first resistor and the gate of the first switching device.

[0018] The first capacitor is connected between the source and gate of the first switching device, and the second capacitor is connected between the drain of the first switching device and ground.

[0019] In one optional implementation, the peripheral programming bypass circuit includes a second switching device;

[0020] The drain of the second switching device is connected to the programmer interface through the peripheral power supply control circuit;

[0021] The source of the second switching device is connected to the main control module;

[0022] The gate of the second switching device is grounded, wherein the second switching device is configured to be in the off state in the non-programming mode.

[0023] In one optional implementation, the peripheral programming bypass circuit further includes a fourth resistor, a fifth resistor, a third capacitor, and a fourth capacitor;

[0024] The fourth resistor is connected in series with the fifth resistor and is disposed between the source of the second switching device and ground;

[0025] The series connection node between the fourth resistor and the fifth resistor is connected to the gate of the second switching device;

[0026] The third capacitor is connected between the source and gate of the second switching device, and the fourth capacitor is connected between the drain of the second switching device and ground.

[0027] In one optional implementation, in the programming mode, the programming power supply voltage provides the bypass power supply to the main control module via the parasitic diode of the second switching device.

[0028] In one optional implementation, in the programming mode, the programming power supply voltage forms a power supply path to the peripheral programming bypass circuit via the parasitic diode of the first switching device.

[0029] This disclosure also provides a method for flashing firmware on a peripheral module, applied to a firmware flashing circuit for a peripheral module as described in any of the above embodiments, the method comprising:

[0030] In non-programming mode, when the system input power supply is provided, the main control module is powered through the main control power supply circuit, and under the control of the GPIO control signal output by the main control module, the peripheral power supply control circuit supplies power to the peripheral module, so that the main control module outputs the reset signal to the peripheral module and interacts with the peripheral module for data.

[0031] In programming mode, when the system input power supply is not providing power and the programmer interface is connected to the peripheral module, the programmer interface provides the programming power supply voltage to the peripheral module, and provides bypass power supply to the main control module through the peripheral programming bypass circuit, so that the main control module keeps running and outputs the reset signal to the peripheral module;

[0032] Under the condition that the main control module continues to operate and the peripheral module receives a stable reset signal, firmware burning is performed on the peripheral module.

[0033] In one optional implementation, in the programming mode, a first bypass power supply path is formed by the parasitic diode of the first switching device in the peripheral power supply control circuit.

[0034] A second bypass power supply path is formed by programming the parasitic diode of the second switching device in the bypass circuit through the peripheral device.

[0035] The programmer interface supplies power to the main control module through the first bypass power supply path and the second bypass power supply path.

[0036] In one optional implementation, in the non-programming mode, the peripheral programming bypass circuit remains off and does not participate in power supply.

[0037] This disclosure provides a firmware burning circuit and method for peripheral modules, applicable to an electronic system including a main control module and peripheral modules. In burning mode, the power supply to the peripheral modules is provided by a programmer via a peripheral power supply control circuit and a peripheral burning bypass circuit, providing a bypass power supply to the main control module to maintain operation. This allows the main control module to continue operating and output a stable reset signal to the peripheral modules even when the system input power is unavailable. This prevents the peripheral modules from entering a continuous reset or abnormal state due to unstable resets, improving the stability and success rate of firmware burning. Simultaneously, in non-burning mode, the bypass path is kept off, reducing the impact on normal power supply and system operation, and lowering the complexity and risk of additional wiring or manual switching.

[0038] To make the above-mentioned objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0039] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the embodiments will be briefly described below. These drawings are incorporated in and constitute a part of this specification. They illustrate embodiments conforming to this disclosure and, together with the specification, serve to explain the technical solutions of this disclosure. It should be understood that the following drawings only show some embodiments of this disclosure and should not be considered as limiting the scope. Those skilled in the art can obtain other related drawings based on these drawings without creative effort.

[0040] Figure 1 A schematic diagram of a peripheral module firmware burning circuit provided in an embodiment of this disclosure is shown;

[0041] Figure 2 A schematic diagram of a peripheral power supply control circuit provided in an embodiment of this disclosure is shown;

[0042] Figure 3 A schematic diagram of a peripheral programming bypass circuit provided in an embodiment of this disclosure is shown;

[0043] Figure 4 A flowchart of a firmware burning method for a peripheral module provided in an embodiment of this disclosure is shown. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. The components of the embodiments of this disclosure described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this disclosure provided in the accompanying drawings is not intended to limit the scope of the claimed disclosure, but merely represents selected embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure.

[0045] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0046] In this document, the term "and / or" merely describes a relationship, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0047] Research has revealed that in practical applications, programming scenarios often involve situations where the system input power is not connected or is inconvenient to connect (e.g., offline upgrades using a programmer connected only to peripheral modules, multi-station programming on a production line, or avoiding powering on the entire device during board-level repairs). The main control module may be in a power-off or undervoltage state, causing unstable reset levels at its GPIO control terminals. Furthermore, the internal structure of the pins may lead to abnormal clamping or partial power-on phenomena, causing peripheral modules to remain in a continuous reset or abnormal startup state. This results in programming failures, unstable programming processes, and decreased success rates.

[0048] Based on the above research, this disclosure provides a peripheral module firmware burning circuit and method, applied to an electronic system including a main control module and peripheral modules. By using the programmer to supply power to the peripheral modules in burning mode, a peripheral power supply control circuit and a peripheral burning bypass circuit provide a bypass power supply to the main control module to maintain operation. This allows the main control module to continue working and output a stable reset signal to the peripheral modules even when the system input power is not supplied, thereby preventing the peripheral modules from entering a continuous reset or abnormal state due to unstable reset, and improving the stability and success rate of firmware burning. At the same time, the bypass path is kept off in non-burning mode, reducing the impact on normal power supply and system operation, and reducing the complexity and risk of additional wiring or manual switching.

[0049] To facilitate understanding of this embodiment, a detailed description of a peripheral module firmware programming circuit disclosed in this disclosure is provided first. This peripheral module firmware programming circuit is applied to an electronic system including a main control module and peripheral modules. The main control module may include an MCU main control chip or a SoC chip, and the peripheral modules may include Bluetooth modules, WiFi modules, communication modules, or sensing modules, etc. See also... Figure 1 The diagram shown is a schematic diagram of a peripheral module firmware burning circuit provided in an embodiment of this disclosure.

[0050] like Figure 1 As shown, the peripheral module firmware burning circuit includes a main control power supply circuit 101, a main control module 102, a peripheral module 103, a peripheral power supply control circuit 104, a peripheral power supply circuit 105, a programmer interface 106, and a peripheral burning bypass circuit 107.

[0051] Specifically, the main control power supply circuit 101 is connected to the system input power supply to provide the main control operating power; the peripheral power supply circuit 105 is connected to the system input power supply to provide the peripheral power supply voltage; the peripheral power supply control circuit 104 is connected between the peripheral power supply circuit 105 and the peripheral module 103, and is also connected to the control terminal of the main control module 102, and is used to selectively supply power to the peripheral module 103 under the control of the main control module 102 in non-burning mode; the programmer interface 106 is connected to the peripheral module 103, and is used to provide the burning power supply voltage to the peripheral module 103 by the programmer in burning mode; the peripheral burning bypass circuit 107 is connected between the peripheral power supply control circuit 104 and the main control module 102, and is configured in burning mode to receive the power supply from the programmer interface 106 through the peripheral power supply control circuit 104, and to provide the main control module 102 with a bypass power supply to maintain operation, so that the main control module 102 outputs a stable reset signal to the peripheral module 103 in burning mode.

[0052] In specific implementation, the main control power supply circuit 101 is connected to the system input power supply and is used to provide the main control working power to the main control module 102 when the system is powered on normally, so that the main control module 102 can be in a controllable operating state and execute the control logic of the peripheral module 103.

[0053] Here, the main control module 102 can be an MCU, SoC, or other control unit with general-purpose input / output ports. Its control terminal can output GPIO control signals and reset signals for power supply and reset, thereby providing the necessary timing coordination for the power-on, reset, and working status of the peripheral module 103.

[0054] In practice, the peripheral power supply circuit 105 is also connected to the system input power supply to generate or provide peripheral power supply voltage to meet the power supply requirements of the peripheral module 103 during normal operation.

[0055] Here, peripheral module 103 can be a Bluetooth module, WiFi module, or other peripheral function module that requires firmware upgrade / burning.

[0056] In the firmware burning stage, the peripheral module 103 not only needs a stable burning power supply voltage, but also often needs to receive a reset signal from the main control module 102 in order to enter the desired burning state or maintain a working state that conforms to the burning timing.

[0057] In a specific implementation, the peripheral power supply control circuit 104 is located between the peripheral power supply circuit 105 and the peripheral module 103, and is connected to the control terminal of the main control module 102. It is used to selectively supply power to the peripheral module 103 under the control of the main control module 102 in non-burning mode.

[0058] Specifically, the peripheral power supply control circuit 104 can turn on or off the power supply path of the peripheral module 103 according to the GPIO control signal output by the main control module 102, thereby realizing the controlled power-on, controlled power-off and coordinated cooperation with the main control logic of the peripheral module 103 during normal system operation.

[0059] It should be noted that the non-programming mode here can be understood as the system input power is connected and the whole machine is in normal operation or normal startup state. In this state, the power supply of peripheral module 103 is provided by the system power supply path and is controlled and managed by peripheral power supply control circuit 104.

[0060] In a specific implementation, the programmer interface 106 is connected to the peripheral module 103 and is used to provide programming power supply voltage to the peripheral module 103 by the programmer in programming mode.

[0061] Here, the burning mode can be understood as the working state of writing or upgrading the firmware of the peripheral module 103, such as production line burning, maintenance upgrade or repair reburning, etc.

[0062] In some application scenarios, the system input power supply may not be available or may be inconvenient to provide power. In such cases, the peripheral module 103 may only obtain the firmware burning power supply voltage through the programmer interface 106.

[0063] In specific implementation, in order to solve the technical problem that the main control module 102 may not work stably in the burning scenario when the system input power is not supplied, this embodiment sets up an external burning bypass circuit 107 and connects it between the external power supply control circuit 104 and the main control module 102, so that in the burning mode, it is configured to receive power from the programmer interface 106 through the external power supply control circuit 104 and provide bypass power to the main control module 102 to maintain operation.

[0064] Specifically, when the programmer interface 106 provides programming power supply voltage to the peripheral module 103, the peripheral programming bypass circuit 107 can use the programming power supply voltage to form a bypass power supply support for the main control module 102, so that the main control module 102 can continue to operate in programming mode or at least be in a state where it can stably output control signals.

[0065] After receiving the bypass power supply, the main control module 102 can output a stable reset signal to the peripheral module 103 in the burning mode. This is to avoid the peripheral module 103 from being unstable in its reset level, continuously resetting, or entering an abnormal state due to the main control module 102 losing power, being undervoltage, or having an uncertain control port level, thereby affecting the stability and success rate of the firmware burning process.

[0066] Preferably, the peripheral programming bypass circuit 107 does not participate in power supply or does not have a substantial impact on the main control power supply path in non-programming mode, so as to reduce interference with the normal power supply management strategy of the system and avoid introducing unnecessary reverse power supply risks.

[0067] It should be noted that the above description of each module and its connection relationship is intended to illustrate the functional division and working coordination mechanism of this embodiment, and does not limit its internal circuit structure or device implementation method; the specific circuit composition, device selection and parameter configuration of the peripheral power supply control circuit 104 and the peripheral programming bypass circuit 107 can be further elaborated in subsequent embodiments in conjunction with the accompanying drawings.

[0068] This disclosure provides a firmware burning circuit for peripheral modules, applied to an electronic system including a main control module and peripheral modules. In burning mode, the circuit utilizes a programmer to supply power to the peripheral modules. Through a peripheral power supply control circuit and a peripheral burning bypass circuit, a bypass power supply is provided to the main control module to maintain operation. This allows the main control module to continue operating and output a stable reset signal to the peripheral modules even when the system input power is unavailable. This prevents the peripheral modules from entering a continuous reset or abnormal state due to unstable resets, improving the stability and success rate of firmware burning. Simultaneously, in non-burning mode, the bypass path remains off, reducing the impact on normal power supply and system operation, and lowering the complexity and risk of additional wiring or manual switching.

[0069] See Figure 2 The diagram shown is a schematic of a peripheral power supply control circuit 104 provided in an embodiment of this disclosure.

[0070] like Figure 2 As shown, the peripheral power supply control circuit 104 includes a first switching device T1, a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, and a second capacitor C2.

[0071] Specifically, the source of the first switching device T1 is connected to the peripheral power supply circuit 105; the drain of the first switching device T1 is connected to the peripheral module 103; the gate of the first switching device T1 is connected to the control terminal of the main control module 102, and the gate receives the GPIO control signal output by the main control module 102 to turn on or off the power supply path of the peripheral module 103 according to the GPIO control signal. One end of the first resistor R1 is connected to the control terminal of the main control module 102, and the other end is connected to the gate of the first switching device T1; the second resistor R2 and the third resistor R3 are connected in series between the source of the first switching device T1 and ground, and the series node between the second resistor R2 and the third resistor R3 is connected between the first resistor R1 and the gate of the first switching device T1; the first capacitor C1 is connected between the source and the gate of the first switching device T1, and the second capacitor C2 is connected between the drain of the first switching device T1 and ground.

[0072] In a specific implementation, the first switching device T1 is used to form the power supply switching path of the peripheral module 103. Here, the source of the first switching device T1 is connected to the output terminal of the peripheral power supply circuit 105 to receive the peripheral power supply voltage converted or provided by the system input power supply; at the same time, the drain of the first switching device T1 is connected to the power supply terminal of the peripheral module 103, so as to provide the peripheral power supply voltage to the peripheral module 103 when the first switching device T1 is turned on, and to cut off the power supply path of the peripheral module 103 when the first switching device T1 is turned off.

[0073] It should be noted that this embodiment does not limit the specific device type of the first switching device T1. The appropriate switching device can be selected based on factors such as the peripheral power supply voltage level, load current capability, and power consumption requirements. Preferably, it can be a P-channel MOSFET.

[0074] In a specific implementation, the gate of the first switching device T1 is connected to the control terminal of the main control module 102, and the gate is configured to receive the GPIO control signal output by the main control module 102, so as to realize the on or off control of the first switching device T1 according to the GPIO control signal.

[0075] Here, the GPIO control signal can be output by the main control module 102 at different working stages to achieve control objectives such as controlled power-on, controlled power-off, or controlled reset of the peripheral module 103.

[0076] Preferably, by directly associating the control terminal of the first switching device T1 with the GPIO port of the main control module 102, the power supply status of the peripheral module 103 can be kept consistent with the software control strategy of the main control module 102, thereby facilitating the implementation of refined power management of the peripheral module 103 in non-programming mode.

[0077] In specific implementation, in order to achieve current limiting and level stabilization of the gate control of the first switching device T1, this embodiment sets a first resistor R1, and connects one end of the first resistor R1 to the control terminal of the main control module 102, and the other end to the gate of the first switching device T1.

[0078] Specifically, the first resistor R1 can be used to limit the transient current of the GPIO control signal charging and discharging to the gate, and suppress ringing or electromagnetic interference introduced by the signal edge too fast, thereby improving the stability of the switch control.

[0079] It should be noted that the setting of the first resistor R1 can also isolate the transient coupling between the main control module 102 and the gate of the switching device to a certain extent, making the GPIO port more stable and reliable when facing switching transients.

[0080] In a specific implementation, the second resistor R2 and the third resistor R3 are connected in series between the source of the first switching device T1 and ground, and the series node between the second resistor R2 and the third resistor R3 is connected between the first resistor R1 and the gate of the first switching device T1.

[0081] Here, through the above connection relationship, the second resistor R2 and the third resistor R3 can constrain or bias the gate reference potential, so that the first switching device T1 has a more controllable gate potential change path under different power supply and control states, thereby reducing the risk of false turn-on caused by peripheral power supply voltage fluctuations, interference coupling or floating nodes.

[0082] Specifically, the connection method between the series node and the gate side enables the gate to obtain a definite potential pull and discharge path through the resistor network when the gate changes during switching transients or when the output voltage of the external power supply circuit 105 changes, thereby enhancing the level determinism.

[0083] In specific implementation, to further optimize the switching transient process and improve the stability of the power supply node, this embodiment sets up a first capacitor C1 and a second capacitor C2. Specifically, the first capacitor C1 is connected between the source and gate of the first switching device T1, and is used to dynamically couple and buffer the gate potential change when the source potential changes, so as to suppress transient spikes, slow down the excessively rapid gate-source voltage change, and improve the smoothness of the switching process. Here, the first capacitor C1, together with the aforementioned resistor network, can form a certain time constant at the moment of switch on / off, thereby reducing the probability of false triggering and improving the anti-interference capability.

[0084] In a specific implementation, the second capacitor C2 is connected between the drain of the first switching device T1 and ground, and the drain side is also the power supply node of the peripheral module 103. Specifically, the second capacitor C2 can be used to decouple and filter the power supply node of the peripheral module 103, so as to provide transient current support and suppress voltage drop when the peripheral module 103 is powered on, while reducing the impact of power ripple generated during the operation of the peripheral module 103 on the power supply node.

[0085] It should be noted that the setting of the second capacitor C2 helps to improve the stability of the power supply voltage of the peripheral module 103, thereby improving the working reliability of the peripheral module 103 in non-burning mode, and providing a more stable power supply foundation for subsequent power supply switching and control coordination related to burning mode.

[0086] See Figure 3 The diagram shown is a schematic diagram of a peripheral programming bypass circuit provided in an embodiment of this disclosure.

[0087] like Figure 3 As shown, the peripheral programming bypass circuit 107 includes a second switching device T2, a fourth resistor R4, a fifth resistor R5, a third capacitor C3, and a fourth capacitor C4.

[0088] Specifically, the drain of the second switching device T2 is connected to the programmer interface 106 via the external power supply control circuit 104; the source of the second switching device T2 is connected to the main control module 102; and the gate of the second switching device T2 is grounded. The second switching device T2 is configured to be in the off state in non-programming mode. A fourth resistor R4 and a fifth resistor R5 are connected in series between the source of the second switching device T2 and ground; the series connection point between the fourth resistor R4 and the fifth resistor R5 is connected to the gate of the second switching device T2; a third capacitor C3 is connected between the source and gate of the second switching device T2, and a fourth capacitor C4 is connected between the drain of the second switching device T2 and ground.

[0089] Based on the aforementioned peripheral module firmware burning circuit, this embodiment further describes a preferred implementation of the peripheral burning bypass circuit 107. Specifically, the peripheral burning bypass circuit 107 includes a second switching device T2, a fourth resistor R4, a fifth resistor R5, a third capacitor C3, and a fourth capacitor C4. Through the cooperation of the above devices, in burning mode, a bypass power supply is provided to the main control module 102 to maintain operation, and in non-burning mode, the influence of the bypass power supply path on the normal power supply of the system is suppressed.

[0090] In specific implementation, the second switching device T2 is used as a key control unit to form a bypass power supply path. Here, the drain of the second switching device T2 is connected to the programmer interface 106 through the peripheral power supply control circuit 104, so that in programming mode, when the programmer interface 106 provides programming power supply voltage to the peripheral module 103, the programming power supply voltage can reach the drain side of the second switching device T2 through the peripheral power supply control circuit 104, providing input conditions for the subsequent formation of bypass power supply.

[0091] Specifically, the source of the second switching device T2 is connected to the power supply terminal of the main control module 102 so as to transfer bypass power to the main control module 102 when the bypass power supply conditions are met, thereby ensuring that the main control module 102 is in a state that can maintain operation or can stably output control signals.

[0092] It should be noted that the source connection to the main control module 102 here can be understood as the power supply network or main control working power node connected to the main control module 102, so as to ensure that the bypass power supply can actually play a role in the operation and maintenance of the main control module 102.

[0093] In the specific implementation, the gate of the second switching device T2 is grounded, so that its control terminal is at a fixed reference potential. Here, the second switching device T2 is configured to be in the off state in non-programming mode to avoid unexpected power supply backflow or bypass power supply effects during normal system power-on operation.

[0094] Preferably, by keeping the second switching device T2 off in non-programming mode, the main control power supply path can still be dominated by the main control power supply circuit 101, and the bypass path will not participate in power supply, thereby maintaining a clear boundary of the system power architecture and normal power management strategy.

[0095] In specific implementation, in order to enhance the potential certainty and anti-interference capability of the second switching device T2 under different power supply states, this embodiment sets the fourth resistor R4 and the fifth resistor R5 in series and places them between the source of the second switching device T2 and ground.

[0096] Specifically, the series resistor network can provide a discharge path and potential pull for the source side of the second switching device T2, making it less likely for the relevant nodes to become floating when power supply is switched, the programmer is plugged in or out, or the power supply of peripherals fluctuates, thereby reducing the risk of false triggering or abnormal conduction.

[0097] In the specific implementation, the series connection node between the fourth resistor R4 and the fifth resistor R5 is connected to the gate of the second switching device T2. Here, due to the combined effect of the gate grounding configuration and the connection relationship of the series node, the gate reference state of the second switching device T2 is more stable, which helps to maintain its turn-off characteristics in non-programming mode and meet the potential relationship requirements when the bypass power supply is established in programming mode.

[0098] It should be noted that the purpose of the above resistor network and gate connection method is to improve the stability and predictability of the bypass control terminal, and does not limit its specific resistance value range. The specific parameters can be adapted according to the main control operating voltage, drain-source voltage difference and device characteristics.

[0099] In a specific implementation, the third capacitor C3 is connected between the source and gate of the second switching device T2 to dynamically buffer the gate-source voltage change process when the source potential changes, thereby suppressing transient interference caused by programmer insertion / removal, load sudden change or power supply switching.

[0100] Specifically, the third capacitor C3 can form a time constant together with the aforementioned resistor network, making the bypass power supply establishment process smoother, reducing the impact of transient spikes on the power supply stability of the main control module 102, and thus improving the ability of the main control module 102 to continuously and stably output a reset signal in the programming mode.

[0101] In the specific implementation, the fourth capacitor C4 is connected between the drain of the second switching device T2 and ground, and the drain side forms a power input node with the programmer interface 106 through the external power supply control circuit 104. Here, the fourth capacitor C4 can be used to decouple and filter this input node to suppress the voltage fluctuations caused by the programmer power supply ripple, the connection line impedance, and the voltage spikes caused by switching transients, thereby providing a more stable input voltage basis for the bypass power supply path.

[0102] Preferably, the fourth capacitor C4 works in conjunction with the third capacitor C3 to simultaneously stabilize the bypass power supply process on both the input and output sides, thereby improving the reliability of the main control module 102 in maintaining operation during the programming mode.

[0103] Below, in Figures 1-3 Based on this, the working mechanism of the circuit is explained in detail.

[0104] In practical implementation, the programming mode refers to a working state where the system input power supply is not connected or does not provide effective power to the main control power supply circuit 101 and the peripheral power supply circuit 105, while the programmer is connected to the peripheral module 103 via the programmer interface 106 and outputs programming power supply voltage to the peripheral module 103. In this working state, the original normal power supply path of the system no longer exists, that is, the main control power supply circuit 101 cannot provide main control working power to the main control module 102 in the normal mode; if no additional power supply maintenance path is built at this time, the main control module 102 will be in a power-down, undervoltage, or half-power-on state, and its reset signal output to the peripheral module 103 will be difficult to maintain stability.

[0105] Here, in programming mode, the programmer interface 106 first provides programming power supply voltage to the power supply side of the peripheral module 103. Since the first switching device T1 is located between the peripheral power supply circuit 105 and the peripheral module 103, and the drain of the second switching device T2 is connected to the programmer interface 106 through the peripheral power supply control circuit 104, the programming power supply voltage provided by the programmer interface 106 is not limited to the peripheral module 103 itself, but can establish potential transfer conditions along the power supply nodes on the peripheral module 103 side to the peripheral power supply control circuit 104 side. In other words, after the programmer is connected, the relevant nodes on the peripheral module 103 side will first obtain the programming power supply voltage, further creating the conditions for establishing a bypass power supply link.

[0106] In specific implementation, since the first switching device T1 does not rely on the main control module 102 to actively drive it to conduct in the programming mode, the programming power supply voltage is not transmitted through the controlled conduction channel of T1, but rather the first power supply transmission path is formed by the parasitic diode of the first switching device T1 itself.

[0107] Specifically, after the programmer interface 106 provides the programming power supply voltage to the peripheral module 103, a corresponding potential difference is formed across the first switching device T1. When this potential difference satisfies the forward bias condition of the parasitic diode, the parasitic diode of the first switching device T1 conducts, thereby enabling the programming power supply voltage to cross the location of the first switching device T1 and continue to be transmitted in the direction of the peripheral programming bypass circuit 107. It should be noted that the role of the parasitic diode here is not to replace the normal controlled switch function, but to provide an initial power supply path for the programming voltage that can be established without the main controller being powered on first, in a specific programming mode.

[0108] In specific implementation, after the programming power supply voltage reaches the input side of the peripheral programming bypass circuit 107 via the parasitic diode of the first switching device T1, the second switching device T2 participates in forming the second power supply transmission path. Here, in terms of circuit structure, the drain of the second switching device T2 is connected to the programmer interface 106 through the peripheral power supply control circuit 104, its source is connected to the power supply terminal of the main control module 102, and its gate is grounded.

[0109] Here, since the second switching device T2 is configured to be off in non-programming mode, it does not participate in normal power supply through the controlled conduction channel. However, in programming mode, when its drain side receives the voltage from the programmer interface 106 through the first power supply transmission path, the parasitic diode of the second switching device T2 will be turned on due to the establishment of a corresponding forward bias relationship between the drain and source, so that the programming power supply voltage is further transmitted from the drain side to the source side and finally delivered to the power supply node of the main control module 102.

[0110] Specifically, from the perspective of circuit transmission, the programming power supply voltage output by the programmer interface 106 passes sequentially through the power supply node on the peripheral module 103 side, the parasitic diode of the first switching device T1, the input node of the peripheral programming bypass circuit 107, and the parasitic diode of the second switching device T2, and finally reaches the power supply terminal of the main control module 102, forming a bypass power supply link from the programmer interface 106 to the main control module 102.

[0111] Here, the aforementioned power supply link is distinguished from the normal main control power supply link driven by the system input power: the former is only established in the burning mode to maintain the most basic operation and signal output capability of the main control module 102; the latter is mainly powered by the main control power supply circuit 101 in the normal working mode.

[0112] In practice, since the bypass power supply link is established step by step through the parasitic diodes of two switching devices, although the voltage delivered to the power supply terminal of the main control module 102 will have a certain voltage drop compared to the original output voltage of the programmer interface 106, it can still provide the basic power required for the main control module 102 to maintain operation.

[0113] Here, maintaining operation does not necessarily require the main control module 102 to execute complete business logic in the programming mode, but at least ensures that the main control module 102 does not completely lose power, and that its output port related to the reset signal can maintain a certain level or a stable drive state. Preferably, under this bypass power supply condition, the main control module 102 can continuously output a valid reset signal to the peripheral module 103, thereby keeping the peripheral module 103 in a programmable and responsive working state throughout the programming process.

[0114] In practical implementation, the main control module 102 needs to obtain the bypass power supply in the programming mode because the reset signal of the peripheral module 103 is output by the main control module 102. If the system input power is turned off and the main control module 102 is not maintained by the bypass power supply, the corresponding GPIO port or reset output port of the main control module 102 may be in a high impedance state, an uncertain state, or an abnormal state affected by the internal ESD structure or clamping structure.

[0115] Here, under such abnormal conditions, the reset pin level of peripheral module 103 may be floating, jittering, incompletely pulled low, or continuously clamped, which may cause peripheral module 103 to be unable to stably exit the reset state or repeatedly enter the reset state, ultimately affecting the firmware burning timing.

[0116] In this way, after the main control module 102 is supplied with the voltage to maintain operation through the above-mentioned bypass power supply link, the output port level of the main control module 102 has a clear power supply support basis, and thus can output a stable reset signal to the peripheral module 103.

[0117] Among them, a stable reset signal can be understood as the signal level output by the main control module 102 to the reset terminal of the peripheral module 103 having a clear high and low logic state during the burning process, and will not change randomly due to power failure of the main control module itself, power supply jitter or port failure; at the same time, the reset signal can maintain the continuity and consistency of meeting the burning requirements in the time dimension.

[0118] This disclosure provides a firmware burning circuit for peripheral modules, applied to an electronic system including a main control module and peripheral modules. In burning mode, the circuit utilizes a programmer to supply power to the peripheral modules. Through a peripheral power supply control circuit and a peripheral burning bypass circuit, a bypass power supply is provided to the main control module to maintain operation. This allows the main control module to continue operating and output a stable reset signal to the peripheral modules even when the system input power is unavailable. This prevents the peripheral modules from entering a continuous reset or abnormal state due to unstable resets, improving the stability and success rate of firmware burning. Simultaneously, in non-burning mode, the bypass path remains off, reducing the impact on normal power supply and system operation, and lowering the complexity and risk of additional wiring or manual switching.

[0119] Next, a detailed description of a peripheral module firmware burning method disclosed in this disclosure embodiment will be provided. The peripheral module firmware burning method disclosed in this disclosure embodiment is applied to the above-mentioned... Figures 1-3 The peripheral module firmware burning circuit shown is described in the following document. Figure 4 The diagram shows a flowchart of a firmware flashing method for a peripheral module provided in this embodiment of the present disclosure. The method includes steps S101-S103, wherein:

[0120] S101. In non-programming mode, when the system input power supply is provided, the main control module is powered through the main control power supply circuit, and under the control of the GPIO control signal output by the main control module, the peripheral power supply control circuit supplies power to the peripheral module, so that the main control module outputs the reset signal to the peripheral module and interacts with the peripheral module.

[0121] S102. In the burning mode, when the system input power supply is not providing power and the programmer interface is connected to the peripheral module, the programmer interface provides the burning power supply voltage to the peripheral module, and provides bypass power supply to the main control module through the peripheral burning bypass circuit, so that the main control module continues to operate and outputs the reset signal to the peripheral module.

[0122] S103. Under the condition that the main control module continues to operate and the peripheral module obtains a stable reset signal, firmware burning is performed on the peripheral module.

[0123] In practical implementation, the method is first executed in non-programming mode. Here, when the system input power is on, the main control power supply circuit provides the main control module with the main control operating power, enabling the main control module to enter normal operation. At the same time, the main control module outputs a GPIO control signal, and under the control of the GPIO control signal, it provides the peripheral power supply voltage to the peripheral module through the peripheral power supply control circuit, thereby enabling the peripheral module to complete controlled power-on under normal system power-on conditions.

[0124] Specifically, after the peripheral module is powered on, the main control module outputs a reset signal to the peripheral module so that the peripheral module enters the expected initial state or working state, and further interacts with the peripheral module to realize operations such as peripheral function call, status monitoring or business data transmission.

[0125] In practical implementation, when firmware writing or upgrading of peripheral modules is required, the method enters the burning mode. Here, the typical scenario corresponding to the burning mode is when the system input power is not supplying power and the programmer interface is connected to the peripheral module.

[0126] Specifically, in this scenario, the programmer interface provides the programming power supply voltage to the peripheral module, enabling the peripheral module to obtain the power supply conditions required for firmware programming; at the same time, the peripheral programming bypass circuit provides bypass power to the main control module, so that the main control module can continue to operate when the system input power is not supplied, or at least keep its output port in a stable driving state.

[0127] It should be noted that the purpose of setting up bypass power supply is to avoid the main control module losing power or being undervoltage, which would cause its GPIO port output to be uncertain, thus causing abnormal phenomena such as jitter, drift or continuous reset of the peripheral module reset signal, thereby affecting the normal progress of the burning process.

[0128] In practical implementation, after the main control module receives bypass power and continues to operate, the main control module continues to output a reset signal to the peripheral module. Here, the reset signal is used to provide stable reset control and timing coordination for the peripheral module in the programming mode, enabling the peripheral module to enter a state that meets the programming requirements and maintain that state.

[0129] Preferably, the reset signal remains stable during the programming stage, which helps to avoid the peripheral module from frequently restarting or remaining in an abnormal state due to unstable reset level, thereby improving the programming success rate and consistency.

[0130] Furthermore, once the main control module remains operational and the peripheral module receives a stable reset signal, the firmware flashing operation is performed on the peripheral module. Specifically, firmware flashing may include writing the target firmware to the peripheral module, verifying the writing result, and performing reset / reboot processing after flashing. The firmware flashing process can be initiated and completed by the programmer through the programmer interface, while the main control module provides necessary reset control for the peripheral module.

[0131] It should be noted that this embodiment does not limit the specific burning protocol or burning process details. The firmware burning can be adapted and implemented according to the interface type and burning specifications of the peripheral module.

[0132] Thus, through the above steps, this embodiment can ensure that the main control module still has the ability to output a stable reset signal even when the system input power is not supplying power during the burning scenario. This provides a stable burning timing and operating environment for the peripheral module, reduces the risk of burning failure, and improves the reliability and repeatability of firmware burning.

[0133] Those skilled in the art will understand that, in the above-described method of the specific implementation, the order in which each step is written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0134] This disclosure provides a method for firmware burning of peripheral modules, applied to an electronic system including a main control module and peripheral modules. In burning mode, the method utilizes a programmer to supply power to the peripheral modules. Through a peripheral power supply control circuit and a peripheral burning bypass circuit, a bypass power supply is provided to the main control module to maintain operation. This allows the main control module to continue operating and output a stable reset signal to the peripheral modules even when the system input power is unavailable. This prevents the peripheral modules from entering a continuous reset or abnormal state due to unstable resets, thus improving the stability and success rate of firmware burning. Simultaneously, in non-burning mode, the bypass path is kept off, reducing the impact on normal power supply and system operation, and lowering the complexity and risk of additional wiring or manual switching.

[0135] Finally, it should be noted that the above-described embodiments are merely specific implementations of this disclosure, used to illustrate the technical solutions of this disclosure, and not to limit it. The protection scope of this disclosure is not limited thereto. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this disclosure. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure, and should all be covered within the protection scope of this disclosure. Therefore, the protection scope of this disclosure should be determined by the protection scope of the claims.

Claims

1. A peripheral module firmware programming circuit, applied in an electronic system comprising a main control module and peripheral modules, characterized in that, The circuit includes: The main control power supply circuit is connected to the system input power supply and is used to provide the main control operating power. The peripheral power supply circuit is connected to the system input power supply and is used to provide power supply voltage to the peripheral devices. A peripheral power supply control circuit is connected between the peripheral power supply circuit and the peripheral module, and is connected to the control terminal of the main control module. It is used to selectively supply power to the peripheral module under the control of the main control module in non-burning mode. A programmer interface is connected to the peripheral module and is used to provide programming power supply voltage to the peripheral module by the programmer in programming mode. The peripheral programming bypass circuit is connected between the peripheral power supply control circuit and the main control module. In the programming mode, it is configured to receive power from the programmer interface through the peripheral power supply control circuit and provide bypass power to the main control module to maintain operation, so that the main control module outputs a stable reset signal to the peripheral module in the programming mode.

2. The peripheral module firmware burning circuit according to claim 1, characterized in that, The peripheral power supply control circuit includes a first switching device; The source of the first switching device is connected to the peripheral power supply circuit; The drain of the first switching device is connected to the peripheral module; The gate of the first switching device is connected to the control terminal of the main control module. The gate receives the GPIO control signal output by the main control module to turn on or off the power supply path of the peripheral module according to the GPIO control signal.

3. The peripheral module firmware burning circuit according to claim 2, characterized in that, The peripheral power supply control circuit also includes a first resistor, a second resistor, a third resistor, a first capacitor, and a second capacitor; One end of the first resistor is connected to the control terminal of the main control module, and the other end is connected to the gate of the first switching device; The second resistor and the third resistor are connected in series between the source of the first switching device and ground, and the series node between the second resistor and the third resistor is connected between the first resistor and the gate of the first switching device. The first capacitor is connected between the source and gate of the first switching device, and the second capacitor is connected between the drain of the first switching device and ground.

4. The peripheral module firmware burning circuit according to claim 1, characterized in that, The peripheral programming bypass circuit includes a second switching device; The drain of the second switching device is connected to the programmer interface through the peripheral power supply control circuit; The source of the second switching device is connected to the main control module; The gate of the second switching device is grounded, wherein the second switching device is configured to be in the off state in the non-programming mode.

5. The peripheral module firmware burning circuit according to claim 4, characterized in that, The peripheral programming bypass circuit also includes a fourth resistor, a fifth resistor, a third capacitor, and a fourth capacitor; The fourth resistor is connected in series with the fifth resistor and is disposed between the source of the second switching device and ground; The series connection node between the fourth resistor and the fifth resistor is connected to the gate of the second switching device; The third capacitor is connected between the source and gate of the second switching device, and the fourth capacitor is connected between the drain of the second switching device and ground.

6. The peripheral module firmware burning circuit according to claim 4, characterized in that: In the programming mode, the programming power supply voltage provides the bypass power supply to the main control module through the parasitic diode of the second switching device.

7. The peripheral module firmware burning circuit according to claim 2, characterized in that: In the programming mode, the programming power supply voltage forms a power supply path to the peripheral programming bypass circuit via the parasitic diode of the first switching device.

8. A method for flashing firmware onto a peripheral module, characterized in that, The method, applied to the firmware burning circuit of any one of claims 1-7, comprises: In non-programming mode, when the system input power supply is provided, the main control module is powered through the main control power supply circuit, and under the control of the GPIO control signal output by the main control module, the peripheral power supply control circuit supplies power to the peripheral module, so that the main control module outputs the reset signal to the peripheral module and interacts with the peripheral module for data. In programming mode, when the system input power supply is not providing power and the programmer interface is connected to the peripheral module, the programmer interface provides the programming power supply voltage to the peripheral module, and provides bypass power supply to the main control module through the peripheral programming bypass circuit, so that the main control module keeps running and outputs the reset signal to the peripheral module; Under the condition that the main control module continues to operate and the peripheral module receives a stable reset signal, firmware burning is performed on the peripheral module.

9. The firmware burning method for peripheral modules according to claim 8, characterized in that: In the programming mode, a first bypass power supply path is formed by the parasitic diode of the first switching device in the peripheral power supply control circuit; A second bypass power supply path is formed by programming the parasitic diode of the second switching device in the bypass circuit through the peripheral device. The programmer interface supplies power to the main control module through the first bypass power supply path and the second bypass power supply path.

10. The method for burning firmware to a peripheral module according to claim 8, characterized in that: In the non-programming mode, the peripheral programming bypass circuit remains off and does not participate in power supply.

Images