Method and apparatus for comparing source data in processor

Abstract

The invention relates to a method and apparatus for comparing source data in a processor. A method (1600) for comparing first and second source data in a processor in response to a vector maximum instruction having an index includes specifying first and second source registers containing the first and second source data, a destination register storing comparison data, and an assertion register (1602). Each of the registers includes a plurality of lanes. The method includes executing the instructions by: for each lane of the first and second source registers, comparing a value in the lane of the first source register with a value in a corresponding lane of the second source register to identify a maximum value (1604); storing the maximum value in a corresponding lane of the destination register (1606); if the maximum value is from the first source register, identifying a corresponding lane of the assertion register (1608); and if the maximum value is from the second source register, canceling the corresponding lane of the assertion register (1610).

Description

[0001] Related application information of division

[0002] This application is a divisional application. The parent application of this divisional application is the invention patent application with the application date of May 19, 2020, the application number of 202010424516.4, and the invention name of “Method and apparatus for comparing source data in a processor”. TECHNICAL FIELD

[0003] The present application relates to comparing source data in a processor, and more particularly to a method and apparatus for comparing source data in a processor in response to a vector max or min instruction with index. BACKGROUND

[0004] Modern digital signal processors (DSPs) face multiple challenges. A DSP can frequently execute software that requires a sorting function to be performed. The sorting function can require identifying a minimum or maximum value in an array of values, and in some cases also identifying a position or index of the identified minimum or maximum value in the array. Multiple instructions can be required to identify the minimum or maximum value and its position, which increases instruction overhead due to the frequent and repetitive nature of the sorting function performed by the DSP. SUMMARY

[0005] According to at least one example of the present disclosure, a method for comparing first and second source data in a processor in response to a vector max or min instruction with index includes specifying first and second source registers containing the first and second source data, a destination register to store comparison data, and a predicate register. Each of the registers includes a plurality of lanes. The method includes executing the instruction by, for each lane in the first and second source registers, comparing a value in the lane of the first source register with a value in a corresponding lane of the second source register to identify a maximum or minimum value, storing the maximum or minimum value in the corresponding lane of the destination register, asserting the corresponding lane of the predicate register if the maximum or minimum value is from the first source register, and de-asserting the corresponding lane of the predicate register if the maximum or minimum value is from the second source register.

[0006] According to another example of the present disclosure, a data processor includes a first source register configured to contain first source data, a second source register configured to contain second source data, a destination register, and a predicate register. Each of the first and second source registers, the destination register, and the predicate register includes a plurality of lanes. In response to executing a single indexed vector max or min instruction, the data processor is configured to compare values in a lane of the first source register with values in a corresponding lane of the second source register to identify a maximum or minimum value; store the maximum or minimum value in a corresponding lane of the destination register; assert a corresponding lane of the predicate register due to the maximum or minimum value being from the first source register; and de-assert the corresponding lane of the predicate register due to the maximum or minimum value being from the second source register. BRIEF DESCRIPTION OF DRAWINGS

[0007] For a detailed description of various examples, reference will now be made to the accompanying drawings in which:

[0008] Figure 1 A dual scalar / vector datapath processor according to various examples is shown;

[0009] Figure 2 A dual scalar / vector datapath processor shown in FIG. Figure 1 Registers and functional units in a dual scalar / vector datapath processor shown in FIG. 1 and according to various examples;

[0010] Figure 3 An exemplary global scalar register file is shown;

[0011] Figure 4 An exemplary local scalar register file shared by arithmetic functional units is shown;

[0012] Figure 5 An exemplary local scalar register file shared by multiply functional units is shown;

[0013] Figure 6 An exemplary local scalar register file shared by load / store units is shown;

[0014] Figure 7 An exemplary global vector register file is shown;

[0015] Figure 8 An exemplary predicate register file is shown;

[0016] Figure 9 An exemplary local vector register file shared by arithmetic functional units is shown;

[0017] Figure 10 An exemplary local vector register file shared by multiply and related functional units is shown;

[0018] Figure 11 The pipeline stages of the central processing unit are shown for each instance;

[0019] Figure 12 Sixteen instructions are shown for retrieving a single packet based on each instance;

[0020] Figure 13 A set of exemplary registers related to instruction execution is shown for each instance, including first and second source registers, destination registers, and assertion registers;

[0021] Figures 14A-14D Numerical examples of instruction execution are shown for each instance;

[0022] Figure 15 The instruction encoding for each instance of the instruction is shown; and

[0023] Figure 16 A flowchart illustrating the method of executing instructions based on each instance is shown. Detailed Implementation

[0024] As explained above, DSPs typically execute software that requires sorting functions. While sorting functions are generally well understood, implementing them at the processor level (e.g., using assembly or compiler-level instructions) may require multiple instructions. For example, a sorting function might need to identify the minimum or maximum value in an array of values, as well as the position or index of that minimum or maximum value within the array. Because sorting functions performed by DSPs are typically frequent and repetitive, additional instruction overhead is undesirable.

[0025] To improve the performance of a DSP performing sorting functions, at least by reducing the instruction overhead required to perform those sorting functions, examples of this disclosure relate to indexed vector maximum / minimum instructions that compare first source data in a first source register with second source data in a second source register. The indexed vector maximum / minimum instructions are single-instruction multiple-data (SIMD) instructions that operate on data in corresponding channels of the first and second source registers. For example, the first and second source registers are 512-bit vector registers, and each channel is an 8-bit channel, such that 64 comparisons are performed in response to the execution of a single indexed vector maximum / minimum instruction.

[0026] Referring to the indexed vector max instruction, execution of the indexed vector max instruction compares data in corresponding lanes of the first and second source registers, identifies a maximum value for each pair of compared data (i.e., data from the first and second source registers in a single lane), and stores the maximum value in a destination register. In at least one instance, the destination register is the second source register. The indexed vector max instruction also asserts or de-asserts a corresponding lane of a predicate register for each lane based on the comparison results of the corresponding lanes of the first and second source registers. For example, if the identified maximum value is from the first source register, the corresponding lane in the predicate register is asserted; if the identified maximum value is from the second source register, the corresponding lane in the predicate register is de-asserted. The predicate register value is used, for example, in the next sort iteration to zero out "lost" entries (e.g., those for which the identified maximum value is from the second source register and thus the corresponding lane in the predicate register is de-asserted), so that the corresponding values in the first source register are no longer in the sort pool.

[0027] The operation of the indexed vector min instruction is similar, except that instead of identifying a maximum value for each pair of compared data, the indexed vector min instruction identifies a minimum value and stores the minimum value in a destination register. The indexed vector min instruction also asserts or de-asserts a corresponding lane of a predicate register for each lane based on the comparison results of the corresponding lanes of the first and second source registers. For example, if the identified minimum value is from the first source register, the corresponding lane in the predicate register is asserted; if the identified minimum value is from the second source register, the corresponding lane in the predicate register is de-asserted. Similar to above, the predicate register value is used, for example, in the next sort iteration to zero out "lost" entries (e.g., those for which the identified minimum value is from the second source register and thus the corresponding lane in the predicate register is de-asserted), so that the corresponding values in the first source register are no longer in the sort pool.

[0028] By implementing a single indexed vector max / min instruction that both identifies a maximum / minimum value for each pair of compared data (i.e., data from the first and second source registers in a single lane) and identifies the location or index of the identified maximum / minimum value by asserting or de-asserting a corresponding lane in a predicate register, the instruction overhead for performing a sort function is reduced, which improves the performance of a DSP in executing software that requires a sort function to be performed.

[0029] Figure 1A dual scalar / vector datapath processor according to various examples of the present disclosure is shown. The processor 100 includes a separate level one instruction cache (LI I) 121 and a level one data cache (LID) 123. The processor 100 includes a level two combined instruction / data cache (L2) 130 that holds both instructions and data. Figure 1 The connection (bus 142) between the level one instruction cache 121 and the level two combined instruction / data cache 130 is shown. Figure 1 The connection (bus 145) between the level one data cache 123 and the level two combined instruction / data cache 130 is shown. In one example, the processor 100 level two combined instruction / data cache 130 stores both instructions to back up the level one instruction cache 121 and data to back up the level one data cache 123. In this example, the level two combined instruction / data cache 130 is further connected to higher level caches and / or main memory in a manner known in the art and not shown in the Figure 1 In this example, the central processing unit core 110, the level one instruction cache 121, the level one data cache 123, and the level two combined instruction / data cache 130 are formed on a single integrated circuit. The signal integrated circuit optionally includes other circuitry.

[0030] The central processing unit core 110 fetches instructions from the level one instruction cache 121 under the control of an instruction fetch unit 111. The instruction fetch unit 111 determines the next few instructions to be executed and invokes a set of fetch packet sizes for these instructions. The nature and size of the fetch packet is explained in further detail below. As is known in the art, on a cache hit, the instructions are fetched directly from the level one instruction cache 121 if these instructions are stored in the level one instruction cache 121. On a cache miss (the specified instruction fetch packet is not stored in the level one instruction cache 121), the instructions are looked up in the level two combined cache 130. In this example, the size of a cache line in the level one instruction cache 121 is equal to the size of a fetch packet. The memory location of these instructions is either a hit or a miss in the level two combined cache 130. A hit is serviced from the level two combined cache 130. A miss is serviced from a higher level cache (not shown) or from main memory (not shown). As is known in the art, the requested instructions can be provided to both the level one instruction cache 121 and the central processing unit core 110 simultaneously to speed up usage.

[0031] In one example, the central processing unit core 110 includes a plurality of functional units to perform instruction specified data processing tasks. An instruction dispatch unit 112 determines the target functional unit for each fetched instruction. In this example, the central processing unit 110 functions as a very long instruction word (VLIW) processor capable of operating on multiple instructions in corresponding functional units simultaneously. Preferably, a compiler organizes the instructions in an execution packet that are executed together. The instruction dispatch unit 112 directs each instruction to its target functional unit. The functional unit assigned to an instruction is completely specified by the compiler generated instruction. The hardware of the central processing unit core 110 has no role in this functional unit assignment. In this example, the instruction dispatch unit 112 can operate on multiple instructions in parallel. The number of these parallel instructions is set by the size of the execution packet. This is explained in further detail below.

[0032] One role of the dispatch task of the instruction dispatch unit 112 is to determine whether the instruction is executed on a functional unit of the scalar data path side A 115 or the vector data path side B 116. An instruction bit, referred to as the s-bit, in each instruction determines which data path the instruction controls. This is explained in further detail below.

[0033] The instruction decode unit 113 decodes each instruction in the current execution packet. Decoding includes identifying the functional unit to perform the instruction, identifying the registers from the possible register files to use to provide data for the corresponding data processing operation, and identifying the register destination for the result of the corresponding data processing operation. As explained further below, an instruction can include a constant field in place of a register number operand field. The result of this decoding is signals to control the target functional unit to perform the data processing operation on the indicated data specified by the corresponding instruction.

[0034] The central processing unit core 110 includes a control register 114. The control register 114 stores information used to control the functional units in the scalar data path side A 115 and the vector data path side B 116. This information can be mode information or the like.

[0035] The decoded instructions from the instruction decode 113 and the information stored in the control register 114 are provided to the scalar data path side A 115 and the vector data path side B 116. Thus, the functional units within the scalar data path side A 115 and the vector data path side B 116 perform the instruction specified data processing operation on the instruction specified data and store the result in one or more instruction specified data registers. Each of the scalar data path side A 115 and the vector data path side B 116 includes a plurality of functional units that preferably operate in parallel. These are explained in further detail below in connection with Figure 2Further details are provided. There is a data path 117 between the scalar data path side A 115 and the vector data path side B 116 that allows data exchange.

[0036] The central processing unit core 110 contains additional non-instruction based modules. The emulation unit 118 allows the machine state of the central processing unit core 110 to be determined in response to instructions. This capability is typically used for algorithm development. The interrupt / exception unit 119 enables the central processing unit core 110 to respond to external asynchronous events (interrupts) and to attempts to perform improper operations (exceptions).

[0037] The central processing unit core 110 contains a stream engine 125. The stream engine 125 of the present illustrative embodiment provides two data streams from a predetermined address, typically cached in the level two combined cache 130, to register the vector data path B side 116 file. This provides controlled data movement from memory (as cached in the level two combined cache 130) directly to functional unit operand input. This is further detailed below.

[0038] Figure 1 An exemplary data width of the buses between the various parts is shown. The level one instruction cache 121 provides instructions to the instruction fetch unit 111 via bus 141. Bus 141 is preferably a 512 bit bus. Bus 141 is unidirectional from the level one instruction cache 121 to the central processing unit 110. The level two combined cache 130 provides instructions to the level one instruction cache 121 via bus 142. Bus 142 is preferably a 512 bit bus. Bus 142 is unidirectional from the level two combined cache 130 to the level one instruction cache 121.

[0039] The level one data cache 123 exchanges data with the register file in the scalar data path side A 115 via bus 143. Bus 143 is preferably a 64 bit bus. The level one data cache 123 exchanges data with the register file in the vector data path side B 116 via bus 144. Bus 144 is preferably a 512 bit bus. Buses 143 and 144 are shown as bidirectional to support central processing unit 110 data reads and data writes. The level one data cache 123 exchanges data with the level two combined cache 130 via bus 145. Bus 145 is preferably a 512 bit bus. Bus 145 is shown as bidirectional to support cache servicing for central processing unit 110 data reads and data writes.

[0040] As known in the art, CPU data requests are serviced directly from the level one data cache 123 on a cache hit (if the requested data is stored in the level one data cache 123). On a cache miss (the specified data is not stored in the level one data cache 123), the data is looked up in the level two combined cache 130. The memory location of the requested data is a hit or a miss in the level two combined cache 130. Hits are serviced from the level two combined cache 130. Misses are serviced from another level of cache (not shown) or from main memory (not shown). As known in the art, the requested instruction can be provided to the level one data cache 123 and the central processing unit core 110 simultaneously to speed up usage.

[0041] The level two combined cache 130 provides data of a first data stream to the stream engine 125 via a bus 146. The bus 146 is preferably a 512-bit bus. The stream engine 125 provides data of the present first data stream to the functional units of the vector data path side B 116 via a bus 147. The bus 147 is preferably a 512-bit bus. The level two combined cache 130 provides data of a second data stream to the stream engine 125 via a bus 148. The bus 148 is preferably a 512-bit bus. The stream engine 125 provides data of the present second data stream to the functional units of the vector data path side B 116 via a bus 149. The bus 149 is preferably a 512-bit bus. According to various examples of the present disclosure, the buses 146, 147, 148, and 149 are shown as unidirectional from the level two combined cache 130 to the stream engine 125 and to the vector data path side B 116.

[0042] On a cache hit (if the requested data is stored in the level two combined cache 130), the stream engine 125 data request is fetched directly from the level two combined cache 130. On a cache miss (the specified data is not stored in the level two combined cache 130), the data is looked up from another level of cache (not shown) or from main memory (not shown). In some instances, it is technically feasible for the level one data cache 123 to cache data that is not stored in the level two combined cache 130. If this operation is supported, then on a stream engine 125 data request that is a miss in the level two combined cache 130, the level two combined cache 130 should snoop the level one data cache 123 for the stream engine 125 request data. If the level one data cache 123 stores the data, then its snoop response will contain the data, which is then provided to service the stream engine 125 request. If the level one data cache 123 does not store the data, then its snoop response will indicate this, and the level two combined cache 130 must service the stream engine 125 request from another level of cache (not shown) or from main memory (not shown).

[0043] In one instance, both the level one data cache 123 and the level two combined cache 130 can be configured as selected amounts of cache or directly addressable memory in accordance with U.S. Patent No. 6,606,686 entitled "UNIFIED MEMORY SYSTEM ARCHITECTURE INCLUDING CACHE AND DIRECTLY ADDRESSABLE STATIC RANDOM ACCESS MEMORY."

[0044] Figure 2Further details of the functional units and register files within the scalar datapath side A 115 and the vector datapath side B 116 are shown. The scalar datapath side A 115 contains a global scalar register file 211, an LI / S1 local register file 212, an M1 / N1 local register file 213, and a D1 / D2 local register file 214. The scalar datapath side A 115 contains an LI unit 221, an S1 unit 222, an M1 unit 223, an N1 unit 224, a D1 unit 225, and a D2 unit 226. The vector datapath side B 116 contains a global vector register file 231, an L2 / S2 local register file 232, an M2 / N2 / C local register file 233, and a predicate register file 234. The vector datapath side B 116 contains an L2 unit 241, an S2 unit 242, an M2 unit 243, an N2 unit 244, a C unit 245, and a P unit 246. There are restrictions on which functional units can read or which register files can write. These are detailed below.

[0045] The scalar datapath side A 115 contains an LI unit 221. The LI unit 221 typically takes two 64-bit operands and produces a 64-bit result. The two operands are each called from an instruction specified register in the global scalar register file 211 or the LI / S1 local register file 212. The LI unit 221 preferably performs the following instruction selection operations: 64-bit addition / subtraction operations; 32-bit min / max operations; 8-bit single instruction multiple data (SIMD) instructions such as absolute value, sum of minima, and sum of maxima determination; loop min / max operations; and various move operations between register files. The result can be written into an instruction specified register in the global scalar register file 211, the LI / S1 local register file 212, the M1 / N1 local register file 213, or the D1 / D2 local register file 214.

[0046] The scalar datapath side A 115 contains an S1 unit 222. The S1 unit 222 typically takes two 64-bit operands and produces a 64-bit result. The two operands are each called from an instruction specified register in the global scalar register file 211 or the LI / S1 local register file 212. The S1 unit 222 preferably performs the same types of operations as the LI unit 221. There can optionally be slight differences between the data processing operations supported by the LI unit 221 and the S1 unit 222. The result can be written into an instruction specified register in the global scalar register file 211, the LI / S1 local register file 212, the M1 / N1 local register file 213, or the D1 / D2 local register file 214.

[0047] Scalar datapath side A 115 includes Ml units 223. Ml units 223 typically take two 64-bit operands and produce a 64-bit result. Both operands are each called from an instruction specified register in global scalar register file 211 or Ml / Nl local register file 213. Ml units 223 preferably perform the following instruction selection operations: 8-bit multiply operations; complex dot product operations; 32-bit bit count operations; complex conjugate multiply operations; and bitwise logical operations, shifts, additions, and subtractions. The result can be written into an instruction specified register in global scalar register file 211, Ll / Sl local register file 212, Ml / Nl local register file 213, or Dl / D2 local register file 214.

[0048] Scalar datapath side A 115 includes Nl units 224. Nl units 224 typically take two 64-bit operands and produce a 64-bit result. Both operands are each called from an instruction specified register in global scalar register file 211 or Ml / Nl local register file 213. Nl units 224 preferably perform the same types of operations as Ml units 223. There can be certain double operations that employ both Ml units 223 and Nl units 224 (referred to as double issue instructions). The result can be written into an instruction specified register in global scalar register file 211, Ll / Sl local register file 212, Ml / Nl local register file 213, or Dl / D2 local register file 214.

[0049] Scalar datapath side A 115 includes Dl units 225 and D2 units 226. Dl units 225 and D2 units 226 each typically take two 64-bit operands and each produce a 64-bit result. Dl units 225 and D2 units 226 typically perform address calculations and corresponding load and store operations. Dl units 225 are used for 64-bit scalar loads and stores. D2 units 226 are used for 512-bit vector loads and stores. Dl units 225 and D2 units 226 preferably also perform: swapping, packing, and unpacking of load and store data; 64-bit SIMD arithmetic operations; and 64-bit bitwise logical operations. Dl / D2 local register file 214 typically stores base and offset addresses used in corresponding load and store address calculations. Both operands are each called from an instruction specified register in global scalar register file 211 or Dl / D2 local register file 214. The result can be written into an instruction specified register in global scalar register file 211, Ll / Sl local register file 212, Ml / Nl local register file 213, or Dl / D2 local register file 214.

[0050] Vector datapath side B 116 contains L2 unit 241. L2 unit 241 typically takes two 512-bit operands and produces a 512-bit result. The two operands are each called from an instruction specified register in global vector register file 231, L2 / S2 local register file 232, or predicate register file 234. L2 unit 241 preferably performs similar instructions as Ll unit 221, only on the wider 512-bit data. The result can be written to an instruction specified register in global vector register file 231, L2 / S2 local register file 232, M2 / N2 / C local register file 233, or predicate register file 234.

[0051] Vector datapath side B 116 contains S2 unit 242. S2 unit 242 typically takes two 512-bit operands and produces a 512-bit result. The two operands are each called from an instruction specified register in global vector register file 231, L2 / S2 local register file 232, or predicate register file 234. S2 unit 242 preferably performs similar instructions as S 1 unit 222. The result can be written to an instruction specified register in global vector register file 231, L2 / S2 local register file 232, M2 / N2 / C local register file 233, or predicate register file 234.

[0052] Vector datapath side B 116 contains M2 unit 243. M2 unit 243 typically takes two 512-bit operands and produces a 512-bit result. The two operands are each called from an instruction specified register in global vector register file 231 or M2 / N2 / C local register file 233. M2 unit 243 preferably performs similar instructions as Ml unit 223, only on the wider 512-bit data. The result can be written to an instruction specified register in global vector register file 231, L2 / S2 local register file 232, or M2 / N2 / C local register file 233.

[0053] Vector datapath side B 116 contains N2 unit 244. N2 unit 244 typically takes two 512-bit operands and produces a 512-bit result. The two operands are each called from an instruction specified register in global vector register file 231 or M2 / N2 / C local register file 233. N2 unit 244 preferably performs the same type of operations as M2 unit 243. There can be certain double operations that employ both M2 unit 243 and N2 unit 244 (referred to as double issue instructions). The result can be written to an instruction specified register in global vector register file 231, L2 / S2 local register file 232, or M2 / N2 / C local register file 233.

[0054] Vector datapath side B 116 contains C unit 245. C unit 245 typically accepts two 512-bit operands and produces a 512-bit result. Both operands are each called from instruction specified registers in either global vector register file 231 or M2 / N2 / C local register file 233. C unit 245 preferably performs: "rake" and "search" instructions; up to 512 2-bit PN * 8-bit multiply I / Q complex multiplications per clock cycle; 8-bit and 16-bit sum of absolute difference (SAD) computations up to 512 SADs per clock cycle; horizontal addition and horizontal min / max instructions; and vector permute instructions. C unit 245 also contains 4 vector control registers (CUCR0 through CUCR3) used to control certain operations of C unit 245 instructions. In certain C unit 245 operations, control registers CUCR0 through CUCR3 are used as operands. Control registers CUCR0 through CUCR3 are preferably used to control the general permute instruction (VPERM); and as masks for the SIMD multiple DOT product operation (DOTPM) and the SIMD multiple sum of absolute difference (SAD) operation. Control register CUCR0 is preferably used to store the polynomial for the Galois Field multiply operation (GFMPY). Control register CUCR1 is preferably used to store the Galois Field polynomial generator function.

[0055] Vector datapath side B 116 contains P units 246. P units 246 perform basic logical operations on registers of local predicate register file 234. P units 246 can read and write predicate register file 234 directly. These operations include single register unary operations. For example: NEG (negate), which inverts each bit of a single register; BITCNT (bit count), which returns a count of the number of bits in a single register having a predetermined numeric state (1 or 0); RMBD (rightmost bit detect), which returns the number of bit positions from the least significant bit position (rightmost) to the first bit position having a predetermined numeric state (1 or 0); DECIMATE, which selects every Nth (1, 2, 4, etc.) bit for output; and EXPAND, which duplicates each bit N times (2, 4, etc.) as instructed by the command. These operations include two register binary operations, for example: AND, a bitwise AND of the data of two registers; NAND, a bitwise AND of the data of two registers followed by a NOT; OR, a bitwise OR of the data of two registers; NOR, a bitwise OR operation of the data of two registers followed by a NOT; and XOR, an exclusive OR of the data of two registers. These operations include moving data from a predicate register of predicate register file 234 to another specified predicate register or to a specified data register in global vector register file 231. Typical intended uses of P units 246 include manipulating SIMD vector comparison results for controlling further SIMD vector operations. BITCNT instructions can be used to count the number of 1s in a predicate register to determine the number of valid data elements from a predicate register.

[0056] Figure 3 Global scalar register file 211 is shown. There are 16 independent 64-bit wide scalar registers, named A0 through A15. Each register of global scalar register file 211 can be read or written as 64-bit scalar data. All scalar datapath side A 115 functional units (LI unit 221, SI unit 222, Ml unit 223, Nl unit 224, Dl unit 225, and D2 unit 226) can read or write global scalar register file 211. Global scalar register file 211 can be read as 32-bit or 64-bit, and can only be written as 64-bit. Instruction execution determines the read data size. Vector datapath side B 116 functional units (L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, C unit 245, and P unit 246) can read from global scalar register file 211 via crossbar 117 under the limitations to be detailed below.

[0057] Figure 4The D1 / D2 local register file 214 is shown. There are 16 independent 64-bit wide scalar registers, named D0 through D16. Each register of the D1 / D2 local register file 214 can be read or written as 64-bit scalar data. All of the scalar data path side A 115 functional units (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, and D2 unit 226) can write to the global scalar register file 211. Only the D1 unit 225 and D2 unit 226 can read from the D1 / D2 local scalar register file 214. The data expected to be stored in the D1 / D2 local scalar register file 214 will contain the base address and offset address used in the address computation.

[0058] Figure 5 The L1 / S1 local register file 212 is shown. Figure 5 The example shown in FIG. 2 has 8 independent 64-bit wide scalar registers, named AL0 through AL7. The preferred instruction encoding (see Figure 15 ) allows the L1 / S1 local register file 212 to contain up to 16 registers. Figure 5 The example of FIG. 2 only implements 8 registers to reduce circuit size and complexity. Each register of the L1 / S1 local register file 212 can be read or written as 64-bit scalar data. All of the scalar data path side A 115 functional units (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, and D2 unit 226) can write to the L1 / S1 local scalar register file 212. Only the L1 unit 221 and S1 unit 222 can read from the L1 / S1 local scalar register file 212.

[0059] Figure 6 The M1 / N1 local register file 213 is shown. Figure 6 The example shown in FIG. 2 has 8 independent 64-bit wide scalar registers, named AL0 through AL7. The preferred instruction encoding (see Figure 15 ) allows the M1 / N1 local register file 213 to contain up to 16 registers. Figure 6 The example of FIG. 2 only implements 8 registers to reduce circuit size and complexity. Each register of the M1 / N1 local register file 213 can be read or written as 64-bit scalar data. All of the scalar data path side A 115 functional units (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, and D2 unit 226) can write to the M1 / N1 local scalar register file 213. Only the M1 unit 223 and N1 unit 224 can read from the M1 / N1 local scalar register file 213.

[0060] Figure 7 A global vector register file 231 is shown. There are 16 independent 512-bit wide vector registers. Each register of the global vector register file 231 can be read or written as 64-bit scalar data, named B0 through B15. Each register of the global vector register file 231 can be read or written as 512-bit vector data, named VB0 through VB15. The instruction type determines the data size. All vector data path side B 116 functional units (L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, C unit 245, and P unit 246) can read or write the global scalar register file 231. Scalar data path side A 115 functional units (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, and D2 unit 226) can read from the global vector register file 231 via the cross path 117 under the restrictions that will be detailed below.

[0061] Figure 8 A P local register file 234 is shown. There are 8 independent 64-bit wide registers, named P0 through P7. Each register of the P local register file 234 can be read or written as 64-bit scalar data. Vector data path side B 116 functional units (L2 unit 241, S2 unit 242, C unit 244, and P unit 246) can write to the P local register file 234. Only L2 unit 241, S2 unit 242, and P unit 246 can read from the P local scalar register file 234. The usual intended use of the P local register file 234 includes: writing a one-bit SIMD vector comparison result from L2 unit 241, S2 unit 242, or C unit 244; manipulating the SIMD vector comparison result by P unit 246; and using the manipulated result to control a further SIMD vector operation.

[0062] Figure 9 An L2 / S2 local register file 232 is shown. Figure 9 The example shown in the middle has 8 independent 512-bit wide vector registers. The preferred instruction encoding (see Figure 15 ) allows the L2 / S2 local register file 232 to contain up to 16 registers. Figure 9The example shown in FIG. 2A has 8 independent 512-bit wide vector registers. The preferred instruction encoding (see FIG. 3) allows the L2 / S2 local vector register file 232 to contain up to 16 registers.

[0063] Figure 10 The M2 / N2 / C local register file 233 is shown in FIG. 2B. Figure 10 The example shown in FIG. 2B has 8 independent 512-bit wide vector registers. The preferred instruction encoding (see FIG. 3) allows the M2 / N2 / C local vector register file 233 to contain up to 16 registers. Figure 15 Figure 10 The example shown in FIG. 2A has 8 independent 512-bit wide vector registers. The preferred instruction encoding (see FIG. 3) allows the L2 / S2 local vector register file 232 to contain up to 16 registers.

[0064] One design choice is to provide a global register file accessible by all functional units on one side and a local register file accessible by only some functional units on one side. Some examples of the present disclosure only employ one type of register file corresponding to the disclosed global register file.

[0065] Referring back to FIG. 2A Figure 2 ​The cross-path 117 allows limited data exchange between the scalar data path side A 115 and the vector data path side B 116. During each operation cycle, one 64-bit data word can be fetched from the global scalar register file A 211 to be used as an operand by one or more functional units of the vector data path side B 116, and one 64-bit data word can be fetched from the global vector register file 231 to be used as an operand by one or more functional units of the scalar data path side A 115. Any scalar data path side 115 functional unit (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, and D2 unit 226) can read a 64-bit operand from the global vector register file 231. This 64-bit operand is the least significant bits of 512 bits of data in the register of the global vector register file 231 that is accessed. Multiple scalar data path side A 115 functional units can take the same 64-bit cross-path data as an operand during the same operation cycle. However, only one 64-bit operand is transferred from the vector data path side B 116 to the scalar data path side A 115 in any single operation cycle. Any vector data path side B 116 functional unit (L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, C unit 245, and P unit 246) can read a 64-bit operand from the global scalar register file 211. If the corresponding instruction is a scalar instruction, the cross-path operand data is treated as any other 64-bit operand. If the corresponding instruction is a vector instruction, the upper 448 bits of the operand are filled with zeros. Multiple vector data path side B 116 functional units can take the same 64-bit cross-path data as an operand during the same operation cycle. Only one 64-bit operand is transferred from the scalar data path side A 115 to the vector data path side B 116 in any single operation cycle.

[0066] In certain restricted cases, the stream engine 125 transfers data. The stream engine 125 controls two data streams. A stream consists of a sequence of elements of a particular type. A program that operates on a stream reads the data sequentially, operating on each element in turn. Each stream has the following basic properties. Stream data has a well-defined start and end time. Stream data has a fixed element size and type throughout the stream. Stream data has a fixed sequence of elements. Thus, a program cannot randomly seek within a stream. Stream data is read-only in the active state. A program cannot write to a stream while it is being read. Once a stream is opened, the stream engine 125: computes the address; fetches the defined data type from the level two unified cache (this can require cache servicing from higher levels of memory); performs data type manipulations, such as zero extension, sign extension, data element reordering / swapping (e.g., matrix transpose); and passes the data directly to the program data register file within the CPU 110. Thus, the stream engine 125 is useful for real-time digital filtering operations on well-behaved data. The stream engine 125 frees these memory fetch tasks from the corresponding CPU, enabling other processing functions.

[0067] The stream engine 125 provides the following benefits. The stream engine 125 allows multi-dimensional memory access. The stream engine 125 increases the available bandwidth of the functional units. Since the stream buffer bypasses the level one data cache 123, the stream engine 125 minimizes the number of cache miss stalls. The stream engine 125 reduces the number of scalar operations required to maintain a loop. The stream engine 125 manages address pointers. The stream engine 125 handles address generation, freeing the address generation instruction slot and the Dl unit 225 and D2 unit 226 for other computations.

[0068] The CPU 110 operates on an instruction pipeline. Instructions are fetched in fixed-length instruction packets, described further below. All instructions require the same number of pipeline stages for fetch and decode, but different numbers of execution stages.

[0069] Figure 11 The following pipeline stages are shown: program fetch stage 1110, dispatch and decode stage 1120, and execution stage 1130. The program fetch stage 1110 contains three stages for all instructions. The dispatch and decode stage 1120 contains three stages for all instructions. The execution stage 1130 contains one to four stages, depending on the instruction.

[0070] The fetch stage 1110 comprises a program address generation stage 1111 (PG), a program access stage 1112 (PA) and a program receive stage 1113 (PR). During the program address generation stage 1111 (PG), a program address is generated in the CPU and a read request is sent to the memory controller of the level one instruction cache Ll I. During the program access stage 1112 (PA), the level one instruction cache Ll I processes the request, accesses the data in its memory and sends a fetch packet to the CPU boundary. During the program receive stage 1113 (PR), the CPU receives the fetch packet.

[0071] The instructions are always fetched in groups of sixteen 32-bit wide slots, constituting a fetch packet. Figure 12 Sixteen instructions 1201 to 1216 of a single fetch packet are shown. The fetch packet is aligned on a 512-bit (16-word) boundary. One example employs a fixed 32-bit instruction length. Fixed length instructions have advantages for a number of reasons. Fixed length instructions enable easy decoder alignment. Correctly aligned instruction fetches enable multiple instructions to be loaded into parallel instruction decoders. This correctly aligned instruction fetch can be achieved by a predetermined instruction alignment when stored in a memory coupled to the fixed instruction packet fetch (the fetch packet is aligned on a 512-bit boundary). Aligned instruction fetches allow the parallel decoders to operate on fetch bits of instruction size. Variable length instructions require an initial step of locating each instruction boundary before they can be decoded. Fixed length instruction sets typically allow more regular placement of instruction fields. This simplifies the construction of each decoder, which is an advantage for a wide issue VLIW central processor.

[0072] Execution of individual instructions is partially controlled by the p-bit in each instruction. This p-bit is preferably bit 0 of a 32-bit wide slot. The p-bit determines whether the instruction is executed in parallel with the next instruction. Instructions are scanned from low to high address. If the p-bit of an instruction is 1, then the next subsequent instruction (of higher memory address) is executed in parallel (in the same cycle) with the instruction. If the p-bit of an instruction is 0, then the next subsequent instruction is executed in the cycle after the instruction.

[0073] The CPU 110 and level one instruction cache Ll I 121 pipelines are separate from each other. Fetch packet returns from the level one instruction cache Ll I can take different amounts of clock cycles, depending on the external environment, such as whether there is a hit in the level one instruction cache 121 or a hit in the level two combination cache 130. Therefore, the program access stage 1112 (PA) can take several clock cycles, rather than 1 clock cycle as in the other stages.

[0074] The instructions executed in parallel constitute an execution packet. In one example, an execution packet can contain up to sixteen instructions. No two instructions in an execution packet can use the same functional unit. A slot is one of the following five types: 1) a self-contained instruction executed on one of the functional units (LI unit 221, SI unit 222, Ml unit 223, Nl unit 224, DI unit 225, D2 unit 226, L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, C unit 245, and P unit 246) of CPU 110; 2) a no-unit instruction, such as a NOP (no operation) instruction or a multi-NOP instruction; 3) a branch instruction; 4) a constant field extension; and 5) a condition code extension. Some of these slot types are explained further below.

[0075] Dispatch and decode stage 1120 includes instruction dispatch to appropriate execution unit stage 1121 (DS), instruction pre-decode stage 1122 (DC1), and instruction decode, operand read stage 1123 (DC2). During instruction dispatch to appropriate execution unit stage 1121 (DS), the fetch packet is divided into execution packets and assigned to the appropriate functional units. During instruction pre-decode stage 1122 (DC1), the source registers, destination registers, and related paths are decoded to execute the instructions in the functional units. During instruction decode, operand read stage 1123 (DC2), more detailed unit decoding is completed and operands are read from the register file.

[0076] Execution stage 1130 includes execution stages 1131-1135 (El-E5). Different types of instructions require different numbers of these stages to complete their execution. These stages of the pipeline play an important role in understanding the state of the device at the boundaries of CPU cycles.

[0077] During execution 1 stage 1131 (El), the condition of the instruction is evaluated and the operands are operated on. As shown in Figure 11 El, execution 1 stage 1131 can receive operands from one of stream buffer 1141 and a register file, shown schematically as 1142. For load and store instructions, address generation is performed and address modification is written to the register file. For branch instructions, the branch fetch packet of the PG stage is affected. As shown in Figure 11 El, load and store instructions access memory, shown schematically here as memory 1151. For single-cycle instructions, the result is written to the destination register file. This assumes that any condition of the instruction is evaluated to true. If the condition is evaluated to false, the instruction does not write any result or have any pipelined operations after execution 1 stage 1131.

[0078] During execution phase 2 1132 (E2), the load instruction sends the address to memory. The store instruction sends the address and data to memory. If saturation occurs, the single-cycle instruction whose result is saturated sets the SAT bit in the control status register (CSR). For the 2-cycle instruction, the result is written to the destination register file.

[0079] During execution phase 3 1133 (E3), the data memory access is made. If saturation occurs, any multiply instruction whose result is saturated sets the SAT bit in the control status register (CSR). For the 3-cycle instruction, the result is written to the destination register file.

[0080] During execution phase 4 1134 (E4), the load instruction brings the data into the CPU boundary. For the 4-cycle instruction, the result is written to the destination register file.

[0081] During execution phase 5 1135 (E5), the load instruction writes the data to the register. This is shown schematically in Figure 11 FIG. 11C with the input from memory 1151 to execution phase 5 1135.

[0082] In some cases, a processor 100 (e.g., a DSP) can be called upon to execute software that requires a sorting function to be performed. As explained above, implementing a sorting function at the processor level (e.g., using assembly or compiler-level instructions) requires multiple instructions to identify the maximum / minimum value and its index or position in the array of values. Since sorting functions performed by a DSP are often frequent and repetitive, it is undesirable to add instruction overhead.

[0083] Figure 13 One example of a register 1300 used in executing a vector maximum / minimum instruction with index is shown. The register 1300 includes a first source register 1302, a second source register 1304, and a destination register 1306. As will be explained further below, in some examples, the second source register 1304 is used as the destination register 1306. The register 1300 also includes a predicate register 1308. In this example, the first and second source registers 1302, 1304 and the destination register 1306 are 512-bit vector registers, such as those contained in the global vector register file 231 explained above. In this example, the predicate register 1308 is a 64-bit predicate register contained in the predicate register file 234, also explained above. In other examples, the first and second source registers 1302, 1304, the destination register 1306, and the predicate register 1308 can have different sizes; the scope of the present disclosure is not limited to one particular register size or one particular set of register sizes.

[0084] In this example, each of the first source register 1302, the second source register 1304, the destination register 1306, and the predicate register 1308 is divided into 64 equal-sized lanes, labeled lanes 0 through 63. Thus, the first and second source registers 1302, 1304 and the destination register 1306 are 8-bit lanes (labeled bytes 0 through 63, respectively), while the lanes of the predicate register 1308 are single-bit lanes (labeled P0 through P63, respectively). Data in similarly-numbered lanes in different registers are said to be in "corresponding" lanes. For example, byte 0 of the first source register 1302, byte 0 of the second source register 1304, byte 0 of the destination register 1306, and bit P0 of the predicate register 1308 are all in corresponding lanes, i.e., in lane 0.

[0085] The indexed vector max instruction contains fields specifying the first source register 1302, the second source register 1304, and the destination register 1306 (e.g., in the global vector register file 231). The indexed vector max instruction also contains a field specifying the predicate register 1308 (e.g., in the predicate register file 234). In response to executing the indexed vector max instruction, the DSP 100 compares each pair of values in the respective lanes of the first and second source registers 1302, 1304. For example, byte 0 of the first source register 1302 is compared with byte 0 of the second source register 1304, byte 1 of the first source register 1302 is compared with byte 1 of the second source register 1304, and so on. As a result of the comparisons of the values in the corresponding lanes of the first and second source registers 1302, 1304, the DSP 100 identifies the maximum value of each pair of compared values and stores the maximum value in the corresponding lane of the destination register 1306. For example, the maximum value of the lane 0 values in the first and second source registers 1302, 1304 is stored in lane 0 of the destination register 1306. In the example in which the second source register 1304 is used as the destination register 1306, the data in lane 0 of the second source register 1304 can be overwritten with the maximum value identified in the comparison.

[0086] Additionally, in response to executing the indexed vector maximum instruction, the DSP 100 asserts or de-asserts the corresponding lane of the predicate register 1308. For purposes of the following discussion, "assert" means setting the predicate register 1308 bit value to'1'and "de-assert" means setting the predicate register 1308 bit value to '0'. However, it should be understood that the scope of the present disclosure is not limited to certain values associated with the assertion or de-assertion of a field in the predicate register 1308. In one example, because the comparison indicates that the maximum value is from or contained in the first source register 1302, the DSP 100 asserts the corresponding lane of the predicate register 1308. In this example, because the comparison indicates that the maximum value is from or contained in the second source register 1302, the DSP 100 de-asserts the corresponding lane of the predicate register 1308. In the case where the values in the corresponding lanes of the first and second source registers 1302, 1304 are equal, whether to assert or de-assert the corresponding lane of the predicate register 1308 can be considered a design choice. That is, in some examples, an equal value in the lanes of the first and second source registers 1302, 1304 can result in asserting the corresponding lane of the predicate register 1308; in other examples, an equal value in the lanes of the first and second source registers 1302, 1304 can result in de-asserting the corresponding lane of the predicate register 1308.

[0087] The indexed vector minimum instruction also contains fields specifying the first source register 1302, the second source register 1304, and the destination register 1306 (e.g., in the global vector register file 231). The indexed vector minimum instruction also contains a field specifying the predicate register 1308 (e.g., in the predicate register file 234). In response to executing the indexed vector minimum instruction, the DSP 100 compares each pair of values in the lanes of the first and second source registers 1302, 1304. For example, byte 0 of the first source register 1302 is compared with byte 0 of the second source register 1304, byte 1 of the first source register 1302 is compared with byte 1 of the second source register 1304, and so on. As a result of the comparison of the values in the corresponding lanes of the first and second source registers 1302, 1304, the DSP 100 identifies the minimum value for each pair of compared values and stores the minimum value in the corresponding lane of the destination register 1306. For example, the minimum value of the lane 0 values in the first and second source registers 1302, 1304 is stored in lane 0 of the destination register 1306. In the example where the second source register 1304 is used as the destination register 1306, the data in lane 0 of the second source register 1304 can be overwritten with the minimum value identified in the comparison.

[0088] Additionally, in response to executing the indexed vector minimum instruction, the DSP 100 asserts or de-asserts the corresponding lane of the predicate register 1308. In one example, because the comparison indicates that the minimum value is from or contained in the first source register 1302, the DSP 100 asserts the corresponding lane of the predicate register 1308. In this example, because the comparison indicates that the minimum value is from or contained in the second source register 1302, the DSP 100 de-asserts the corresponding lane of the predicate register 1308. As above, in the case where the values in the corresponding lanes of the first and second source registers 1302, 1304 are equal, whether to assert or de-assert the corresponding lane of the predicate register 1308 can be considered a design choice. That is, in some examples, equal values in the lanes of the first and second source registers 1302, 1304 can result in asserting the corresponding lane of the predicate register 1308; in other examples, equal values in the lanes of the first and second source registers 1302, 1304 can result in de-asserting the corresponding lane of the predicate register 1308.

[0089] Figures 14A-14D Various examples of the functionality of the indexed vector maximum / minimum instruction are shown. In particular, Figures 14A-14D The values contained in the first four lanes of the first and second source registers 1402, 1404 are shown. Figures 14A-14D The values stored in the corresponding first four lanes of the destination register 1406 and the predicate register 1408, resulting from execution of the indexed vector maximum / minimum instruction, are also shown, as explained further below. Although only four lanes are shown for each of the first and second source registers 1402, 1404, the destination register 1406, and the predicate register 1408, it should be understood that this is for ease of discussion, and that Figures 14A-14D Examples of the indexed vector maximum / minimum instruction can extend to the register sizes discussed above with respect to Figure 13 the indexed vector minimum instruction. Furthermore, as explained above with respect to Figure 13 the indexed vector minimum instruction, in some examples, the second source register 1404 is used as the destination register 1406, and thus, the previous values of the second source register 1404 are overwritten with the minimum or maximum value identified for each lane.

[0090] Figure 14AOne example of a vector max with index instruction is shown in which the data in the lanes of the first and second source registers 1402a, 1404a are treated as unsigned values. Thus, as explained above, the destination register 1406a contains the maximum of each pair of comparison values from the corresponding lanes of the first and second source registers 1402a, 1404a. In this example, the corresponding lane of the predicate register 1408a is asserted if the identified maximum came from the first source register 1402a, and is de-asserted if the identified maximum came from the second source register 1404a.

[0091] The exemplary first source register 1402a data are x01, x04, x80, x7F in lanes 3 through 0, respectively. The exemplary second source register 1404a data are x02, x03, x6F, x7F in lanes 3 through 0, respectively. As a result of executing the vector max with index instruction, in this example in which the data values are unsigned values, the destination register 1406a contains the maximum values, x02 in lane 3, x04 in lane 2, x80 in lane 1, and x7F in lane 0.

[0092] As the identified maximum value x02 in lane 3 came from the second source register 1404a, the corresponding lane of the predicate register 1408a is de-asserted. As the identified maximum value x04 in lane 2 came from the first source register 1402a, the corresponding lane of the predicate register 1408a is asserted. As the identified maximum value x80 in lane 1 came from the first source register 1402a, the corresponding lane of the predicate register 1408a is asserted. Finally, as the values in lane 0 are equal, in this example the corresponding lane of the predicate register 1408a is de-asserted.

[0093] Figure 14B One example of a vector max with index instruction is shown in which the data in the lanes of the first and second source registers 1402b, 1404b are treated as signed values. Thus, as explained above, the destination register 1406b contains the maximum of each pair of comparison values from the corresponding lanes of the first and second source registers 1402b, 1404b. In this example, the corresponding lane of the predicate register 1408b is asserted if the identified maximum came from the first source register 1402b, and is de-asserted if the identified maximum came from the second source register 1404b.

[0094] Exemplary first source register 1402b data are x01, x04, x80, x7F in lanes 3-0, respectively. Exemplary second source register 1404b data are x02, x03, x6F, x7F in lanes 3-0, respectively. As a vector max with index instruction is executed, in this instance where data values are signed values, destination register 1406b contains the maximum values, x02 in lane 3, x04 in lane 2, x6F in lane 1, and x7F in lane 0.

[0095] As the identified maximum value x02 in lane 3 comes from the second source register 1404b, the corresponding lane of predicate register 1408b is de-asserted. As the identified maximum value x04 in lane 2 comes from the first source register 1402b, the corresponding lane of predicate register 1408b is asserted. As the identified maximum value x6F in lane 1 comes from the second source register 1404b, the corresponding lane of predicate register 1408b is de-asserted. Finally, as the values in lane 0 are equal, in this instance, the corresponding lane of predicate register 1408b is de-asserted.

[0096] Figure 14C An example of a vector min with index instruction is shown, where data in lanes of first and second source registers 1402c, 1404c are treated as unsigned values. Thus, as explained above, destination register 1406c contains the minimum value from each pair of compared values from corresponding lanes of first and second source registers 1402c, 1404c. In this instance, if the identified minimum value comes from the first source register 1402c, the corresponding lane of predicate register 1408c is asserted, and if the identified minimum value comes from the second source register 1404c, it is de-asserted.

[0097] Exemplary first source register 1402c data are x01, x04, x80, x7F in lanes 3-0, respectively. Exemplary second source register 1404c data are x02, x03, x6F, x7F in lanes 3-0, respectively. As a vector min with index instruction is executed, in this instance where data values are unsigned values, destination register 1406c contains the minimum values, x01 in lane 3, x03 in lane 2, x6F in lane 1, and x7F in lane 0.

[0098] Since the identified minimum value x01 in lane 3 comes from the first source register 1402c, the corresponding lane of the predicate register 1408c is asserted. Since the identified minimum value x03 in lane 2 comes from the second source register 1404c, the corresponding lane of the predicate register 1408c is de-asserted. Since the identified minimum value x6F in lane 1 comes from the second source register 1404c, the corresponding lane of the predicate register 1408c is de-asserted. Finally, since the values in lane 0 are equal, the corresponding lane of the predicate register 1408b is de-asserted in this example.

[0099] Finally, Figure 14D An example of a vector minimum with index instruction is shown in which the data in the lanes of the first and second source registers 1402d, 1404d are treated as signed values. Thus, as explained above, the destination register 1406d contains the minimum value from each pair of compared values from the corresponding lanes of the first and second source registers 1402d, 1404d. In this example, the corresponding lane of the predicate register 1408d is asserted if the identified minimum value comes from the first source register 1402d, and de-asserted if the identified minimum value comes from the second source register 1404d.

[0100] The exemplary first source register 1402d data are x01, x04, x80, x7F in lanes 3 through 0, respectively. The exemplary second source register 1404d data are x02, x03, x6F, x7F in lanes 3 through 0, respectively. Since the vector minimum with index instruction is executed, in this example in which the data values are signed values, the destination register 1406d contains the minimum values, x01 in lane 3, x03 in lane 2, x80 in lane 1, and x7F in lane 0.

[0101] Since the identified minimum value x01 in lane 3 comes from the first source register 1402d, the corresponding lane of the predicate register 1408d is asserted. Since the identified minimum value x03 in lane 2 comes from the second source register 1404d, the corresponding lane of the predicate register 1408d is de-asserted. Since the identified minimum value x80 in lane 1 comes from the first source register 1402d, the corresponding lane of the predicate register 1408d is asserted. Finally, since the values in lane 0 are equal, the corresponding lane of the predicate register 1408b is de-asserted in this example.

[0102] Figure 15One example of an instruction encoding 1500 for a functional unit instruction used by examples of the present disclosure is shown. Other instruction encodings are possible and within the scope of the present disclosure. Each instruction consists of 32 bits and controls the operation of one of the individually controllable functional units (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, D2 unit 226, L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, C unit 245, and P unit 246). The bit fields are defined as follows.

[0103] The pdst field 1502 (bits 26 to 31) specifies the predicate register in the corresponding predicate register file 234 as the index or destination of the predicate portion of the instruction result.

[0104] The src2 / dst field 1504 (bits 20 to 25) specifies a second source register (e.g., second source register 1304) from the global vector register file 231 and, in this example, also specifies a destination register (e.g., destination register 1306) that will hold the comparison result or identified maximum / minimum value.

[0105] The src1 field 1506 (bits 14 to 19) specifies a first source register (e.g., first source register 1302) from the global vector register file 231.

[0106] The opcode field 1508 (bits 5 to 13) specifies the type of instruction (e.g., maximum or minimum) and indicates the appropriate instruction options (e.g., treat the data in the lanes of the source registers as signed or unsigned values). The unit field 1510 (bits 2 to 4) provides a specific indication of the functional unit used and the operation performed. Detailed explanation of the opcode is generally outside the scope of the present disclosure except for the instruction options detailed below.

[0107] The s bit 1512 (bit 1) indicates whether the scalar data path side A 115 or the vector data path side B 116. If s = 0, the scalar data path side A 115 is selected. This restricts the functional unit to Figure 2 the L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, and D2 unit 226 shown in FIG. 1 15 and the corresponding register files. Similarly, s = 1 selects the vector data path side B 116, restricting the functional unit to Figure 2 the L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, P unit 246, and the corresponding register files shown in FIG. 1 16.

[0108] The p-bit 1514 (bit 0) flags an execution packet. The p-bit determines if the instruction is executed in parallel with a subsequent instruction. The p-bit is scanned from the low address to the high address. If the p = 1 for the current instruction, the next instruction is executed in parallel with the current instruction. If the p = 0 for the current instruction, the next instruction is executed in the cycle after the current instruction. All instructions executed in parallel form an execution packet. An execution packet can contain up to twelve instructions. Each instruction in an execution packet must use a different functional unit.

[0109] Figure 16 A flowchart of a method 1600 according to an example of the present disclosure is shown. The method 1600 begins in block 1602 by specifying a first source register containing first source data, a second source register containing second source data, a destination register for storing comparison data, and a predicate register. The first and second source registers, the destination register, and the predicate register are specified in fields of an indexed vector max / min instruction, such as the src1 field 1506, the src2 field 1504, the dst field 1504, and the pdst field 1502, respectively, with respect to Figure 15 the above description). In some cases, the predicate register is a 64-bit predicate register contained in the predicate register file 234, as explained above. In other cases, the first and second source registers, the destination register, and the predicate register can have different sizes; the scope of the present disclosure is not limited to one particular register size or one particular set of register sizes.

[0110] The method 1600 continues in block 1604 by executing the indexed vector max / min instruction, in particular by comparing values in lanes of the first source register with values in corresponding lanes of the second source register to identify a maximum / minimum value. In one example, the source registers are 512-bit vector registers, and the lanes are 8-bit lanes, such that 64 comparisons are made when executing a single indexed vector max / min instruction, as explained above with respect to Figure 13 the above description). The 8-bit lanes can be interpreted as signed or unsigned values.

[0111] The method 1600 further continues in block 1606 by storing the maximum / minimum identified value in a corresponding lane of the destination register. In one example, the destination register can be the second source register, such that the second source register is overwritten with the identified maximum / minimum value.

[0112] The method 1600 continues in block 1608 with asserting the corresponding lane of the predicate register due to the maximum / minimum value being from the first source register. However, if the maximum / minimum value is from the second source register, the method 1600 continues in block 1610 with de-asserting the corresponding lane of the predicate register. In this example, "asserting" refers to setting the predicate register value to '1', while "de-asserting" refers to setting the predicate register bit value to '0'. However, it should be understood that the scope of the present disclosure is not limited to certain values related to the assertion or de-assertion of a field in a predicate register. In one example, the DSP 100 asserts the corresponding lane of the predicate register due to the comparison indicating that the maximum / minimum value is from or contained in the first source register. In this example, the DSP 100 de-asserts the corresponding lane of the predicate register due to the comparison indicating that the maximum / minimum value is from or contained in the second source register. In the case where the values in the corresponding lanes of the first and second source registers are equal, it can be considered a design choice whether to assert or de-assert the corresponding lane of the predicate register. That is, in some examples, an equal value in the lanes of the first and second source registers will result in asserting the corresponding lane of the predicate register; in other examples, an equal value in the lanes of the first and second source registers will result in de-asserting the corresponding lane of the predicate register.

[0113] In the foregoing discussion and in the claims, the terms "including" and "comprising" are used in an open-ended fashion, and thus should be interpreted to mean "including, but not limited to...." Also, the term "couple" or "couples" is intended to mean either an indirect or direct connection. Thus, if a first device couples to a second device, that connection can be through a direct connection or through an indirect connection via other devices and connections. Similarly, a device that is coupled between a first component or location and a second component or location can be an indirect connection, through one or more other devices and connections, or a direct connection, without interposition of another device. An element or feature that is "configured to" perform a task or function can be configured (e.g., programmed or designed) at a time of manufacture to perform the function and / or can be reconfigurable (or configurable) by a user after manufacture to

[0114] The above discussion is meant to illustrate and provide a general understanding of the principles of the present disclosure along with the various examples. Once a complete understanding of the disclosure is achieved, many changes in the details, materials, and arrangements of parts can be made by those skilled in the art without departing from the scope of the present disclosure. The following claims are intended to cover all such changes and modifications.

Claims

1. A processor comprising: A set of functional units; The first source register coupled to the set of functional units; A second source register coupled to the set of functional units; as well as The assertion register coupled to the set of functional units, wherein: Each of the first source register, the second source register, and the assertion register includes a set of channels; and The processor is configured to: Receive instructions, Based on the instructions, the functional units in the set of functional units are: Each channel in the first source register's set of channels is compared with the corresponding channel in the second source register's set of channels to determine the maximum value, and The assertion register stores an indication that a portion of the first source register stores a value greater than the corresponding portion of the second source register, and Based on the indication in the assertion register, operations are selectively performed on the portion of the first source register that stores a value greater than the corresponding portion of the second source register.

2. The processor of claim 1, further comprising a destination register including a set of channels, wherein the processor is configured to: based on the instructions, cause the functional unit to store a corresponding maximum value in each of the set of channels of the destination register.

3. The processor of claim 2, wherein the instructions include specifying a first field of the first source register, specifying a second field of the second source register, specifying a third field of the assertion register, and specifying a fourth field of the destination register.

4. The processor of claim 2, wherein the destination register and the second source register are identical.

5. The processor according to claim 1, wherein: The set of functional units includes multiple functional units, each of which is configured to: Each channel in the first source register's set of channels is compared with the corresponding channel in the second source register's set of channels to determine the maximum value. The assertion register stores the indication that the portion of the first source register stores a value greater than the corresponding portion of the second source register; and The instructions include fields specifying the functional units from the plurality of functional units.

6. The processor according to claim 1, wherein: The set of functional units is arranged in the scalar data path and the vector data path; and The instruction includes a field specifying whether to use the scalar data path or the vector data path to execute the instruction.

7. The processor of claim 1, wherein the comparison performed between each channel of the first source register and the corresponding channel of the second source register is a signed comparison.

8. The processor of claim 1, wherein the comparison of each channel of the first source register with the corresponding channel of the second source register is an unsigned comparison.

9. The processor of claim 1, wherein the instruction includes a field specifying whether the instruction is allowed to be executed in parallel with another instruction.

10. The processor of claim 1, wherein each of the first source register and the second source register has a width of 512 bits.

11. A processor comprising: A set of functional units; The first source register coupled to the set of functional units; A second source register coupled to the set of functional units; as well as The assertion register coupled to the set of functional units, wherein: Each of the first source register, the second source register, and the assertion register includes a set of channels; and The processor is configured to: Receive instructions, and Based on the instructions, the functional units in the set of functional units are: Each channel in the first source register's set of channels is compared with the corresponding channel in the second source register's set of channels to determine the minimum value, and The assertion register stores an indication that a portion of the first source register stores a value smaller than the corresponding portion of the second source register, and Based on the indication in the assertion register, operations are selectively performed on the portion of the first source register that stores a value smaller than the corresponding portion of the second source register.

12. The processor of claim 11, further comprising a destination register including a set of channels, wherein the processor is configured to: based on the instructions, cause the functional unit to store a corresponding minimum value in each of the set of channels of the destination register.

13. The processor of claim 12, wherein the instructions include specifying a first field of the first source register, specifying a second field of the second source register, specifying a third field of the assertion register, and specifying a fourth field of the destination register.

14. The processor of claim 12, wherein the destination register and the second source register are identical.

15. The processor according to claim 11, wherein: The set of functional units includes multiple functional units, each of which is configured to: Each channel in the first source register's set of channels is compared with the corresponding channel in the second source register's set of channels to determine the minimum value, and The assertion register stores the indication that the portion of the first source register stores a value smaller than the corresponding portion of the second source register; and The instruction specifies the functional unit from the plurality of functional units.

16. The processor of claim 11, wherein: The set of functional units is arranged in the scalar data path and the vector data path; and The instruction includes a field specifying whether to use the scalar data path or the vector data path to execute the instruction.

17. The processor of claim 11, wherein the comparison performed between each channel of the first source register and the corresponding channel of the second source register is a signed comparison.

18. The processor of claim 11, wherein the comparison of each channel of the first source register with the corresponding channel of the second source register is an unsigned comparison.

19. The processor of claim 11, wherein the instruction includes a field specifying whether the instruction is allowed to be executed in parallel with another instruction.

20. The processor of claim 11, wherein each of the first source register and the second source register has a width of 512 bits.

21. A circuit device comprising: A first register is configured to store a first vector comprising a first set of vector elements; The second register is configured to store a second vector including a second set of vector elements; Functional unit, which is coupled to the first register and the second register; An instruction fetch circuit is configured to receive a vector maximum value instruction specifying the first register and the second register, as well as a second instruction; as well as An instruction decoding circuit, coupled to the instruction acquisition circuit and the functional unit, and configured to cause the functional unit to: Based on the aforementioned vector maximum value instruction Each vector element in the first group of vector elements is compared with the corresponding vector element in the second group of vector elements to determine the corresponding vector element in the third group of vector elements, wherein the corresponding vector element in the third group of vector elements is the larger of the corresponding vector element in the first group of vector elements and the corresponding vector element in the second group of vector elements; For each vector element in the third group of vector elements, a corresponding indicator is stored in the assertion register, the indicator specifying whether the corresponding vector element in the third group of vector elements is associated with the first vector or with the second vector; as well as Store the third set of vector elements in the second register; as well as Based on the second instruction, The operation is performed on a subset of the third vector determined based on the indicator stored in the assertion register.

22. The circuit arrangement of claim 21, wherein the vector maximum value instruction includes specifying a first field of the first register and specifying a second field of the second register.

23. The circuit device according to claim 22, wherein: The circuit device further includes a set of functional units, the set of functional units including the functional units; and The vector maximum value instruction includes a third field specifying the function unit from the set of function units.

24. The circuit arrangement of claim 21, wherein the vector maximum value instruction specifies whether the first vector and the second vector contain signed or unsigned values.

25. The circuit arrangement according to claim 21, wherein: The circuit device includes scalar data paths and vector data paths; and The vector maximum value instruction specifies whether to use the scalar data path or the vector data path to execute the vector maximum value instruction.

26. The circuit arrangement according to claim 21, wherein: The instruction fetching circuit is configured to receive a vector minimum value instruction specifying the first register and the second register; and The instruction decoding circuit is configured to cause the functional unit to: Based on the vector minimum value instruction, each vector element in the first group of vector elements is compared with the corresponding vector element in the second group of vector elements to determine the corresponding vector element in the fourth group of vector elements, wherein the corresponding vector element in the fourth group of vector elements is the smaller of the corresponding vector element in the first group of vector elements and the corresponding vector element in the second group of vector elements.

27. The circuit of claim 26, wherein the vector minimum value instruction includes specifying a first field of the first register and specifying a second field of the second register.

28. A circuit device comprising: A first register is configured to store a first vector comprising a first set of vector elements; The second register is configured to store a second vector including a second set of vector elements; Functional unit, which is coupled to the first register and the second register; An instruction fetching circuit is configured to receive a vector minimum value instruction specifying the first register and the second register, as well as a second instruction; as well as An instruction decoding circuit, coupled to the instruction acquisition circuit and the functional unit, and configured to cause the functional unit to: Based on the aforementioned vector minimum value instruction Each vector element in the first group of vector elements is compared with the corresponding vector element in the second group of vector elements to determine the corresponding vector element in the third group of vector elements, wherein the corresponding vector element in the third group of vector elements is the smaller of the corresponding vector element in the first group of vector elements and the corresponding vector element in the second group of vector elements; For each vector element in the third group of vector elements, a corresponding indicator is stored in the assertion register, the indicator specifying whether the corresponding vector element in the third group of vector elements is associated with the first vector or with the second vector; as well as Store the third set of vector elements in the second register; as well as Based on the second instruction, the functional unit: The operation is performed on a subset of the third vector determined based on the indicator stored in the assertion register.

29. The circuit arrangement of claim 28, wherein the vector minimum instruction includes specifying a first field of the first register and specifying a second field of the second register.

30. The circuit device according to claim 29, wherein: The circuit device further includes a set of functional units, the set of functional units including the functional units; and The vector minimum value instruction includes a third field specifying the functional unit from the set of functional units.

31. The circuit arrangement of claim 28, wherein the vector minimum value instruction specifies whether the first vector and the second vector contain signed or unsigned values.

32. The circuit device according to claim 28, wherein: The circuit device includes scalar data paths and vector data paths; and The vector minimum instruction specifies whether to use the scalar data path or the vector data path to execute the vector minimum instruction.

33. The circuit device according to claim 28, wherein: The instruction fetching circuit is configured to receive an instruction specifying the maximum vector value of the first register and the second register; and The instruction decoding circuit is configured to cause the functional unit to: Based on the vector maximum value instruction, each vector element in the first group of vector elements is compared with the corresponding vector element in the second group of vector elements to determine the corresponding vector element in the fourth group of vector elements, wherein the corresponding vector element in the fourth group of vector elements is the larger of the corresponding vector element in the first group of vector elements and the corresponding vector element in the second group of vector elements.

34. The circuit arrangement of claim 33, wherein the vector maximum value instruction includes specifying a first field of the first register and specifying a second field of the second register.

35. A method comprising: Store the first vector, which includes the first set of vector elements, in the first register; The second vector, which includes the second set of vector elements, is stored in the second register; Receives a vector maximum value instruction specifying the first register and the second register; and Based on the aforementioned vector maximum value instruction, the processor's functional units are configured as follows: Each vector element in the first group of vector elements is compared with the corresponding vector element in the second group of vector elements to determine the corresponding vector element in the third group of vector elements, wherein the corresponding vector element in the third group of vector elements is the larger of the corresponding vector element in the first group of vector elements and the corresponding vector element in the second group of vector elements; For each vector element in the third group of vector elements, a corresponding indicator is stored in the assertion register, the indicator specifying whether the corresponding vector element in the third group of vector elements is associated with the first vector or the second vector; as well as Store the third set of vector elements in the second register; as well as The operation is performed on a subset of the third vector determined based on the indicator stored in the assertion register.

36. The method of claim 35, further comprising: Receives a vector minimum value instruction specifying the first register and the second register; as well as Based on the vector minimum value instruction, the functional units of the processor are configured to: Each vector element in the first group of vector elements is compared with the corresponding vector element in the second group of vector elements to determine the corresponding vector element in the fourth group of vector elements, wherein the corresponding vector element in the fourth group of vector elements is the smaller of the corresponding vector element in the first group of vector elements and the corresponding vector element in the second group of vector elements.

37. The method of claim 36, wherein the vector minimum instruction includes specifying a first field of the first register and specifying a second field of the second register.

38. A method comprising: Store the first vector, which includes the first set of vector elements, in the first register; The second vector, which includes the second set of vector elements, is stored in the second register; Receives a vector minimum value instruction specifying the first register and the second register; and Based on the aforementioned vector minimum value instruction, the processor's functional units are: Each vector element in the first group of vector elements is compared with the corresponding vector element in the second group of vector elements to determine the corresponding vector element in the third group of vector elements, wherein the corresponding vector element in the third group of vector elements is the smaller of the corresponding vector element in the first group of vector elements and the corresponding vector element in the second group of vector elements; For each vector element in the third group of vector elements, a corresponding indicator is stored in the assertion register, the indicator specifying whether the corresponding vector element in the third group of vector elements is associated with the first vector or the second vector; as well as Store the third set of vector elements in the second register; as well as The operation is performed on a subset of the third vector determined based on the indicator stored in the assertion register.

39. The method of claim 38, further comprising: Receives a vector maximum value instruction specifying the first register and the second register; as well as Based on the vector maximum value instruction, the functional units of the processor are configured as follows: Each vector element in the first group of vector elements is compared with the corresponding vector element in the second group of vector elements to determine the corresponding vector element in the fourth group of vector elements, wherein the corresponding vector element in the fourth group of vector elements is the larger of the corresponding vector element in the first group of vector elements and the corresponding vector element in the second group of vector elements.

40. The method of claim 39, wherein the vector maximum value instruction includes specifying a first field of the first register and specifying a second field of the second register.

41. An apparatus comprising: The first register is configured to store the first set of values; The second register is configured to store the second set of values; as well as Functional unit, which is configured as follows: Receive instructions specifying the first register and the second register; Based on the instructions, for each value in the first group of values ​​and the corresponding value in the second group of values... Compare the value in the first group of values ​​with the corresponding value in the second group of values; Based on the comparison, one of the values ​​in the first set of values ​​and the corresponding values ​​in the second set of values ​​is identified; as well as The value is stored in the assertion register to indicate whether the identified value comes from the first set of values ​​or from the second set of values; as well as Based on the value of the assertion register, operations associated with the first set of values ​​and the second set of values ​​are performed.

42. The apparatus of claim 41, wherein the instruction specifies a maximum sorting operation, and wherein the identified value is the larger of the value in the first set of values ​​and the corresponding value in the second set of values.

43. The apparatus of claim 41, wherein the instruction specifies a minimum sorting operation, and wherein the identified value is the smaller of the value in the first set of values ​​and the corresponding value in the second set of values.

44. The apparatus of claim 41, comprising: A group of functional units including the aforementioned functional unit, The instructions therein specify the functional unit.

45. The apparatus of claim 41, wherein the instruction specifies whether the first set of values ​​and the second set of values ​​are signed or unsigned values.

46. ​​The apparatus of claim 41, wherein the instruction specifies the assertion register.

47. The apparatus of claim 41, wherein the functional unit is further configured to: For each value in the first set of values ​​and the corresponding value in the second set of values, the identified value is stored in the second register.

48. The apparatus of claim 41, wherein the functional unit is further configured to: For each value in the first set of values ​​and the corresponding value in the second set of values, the identified value is stored in a third register that is different from the first register and the second register.

49. The apparatus of claim 41, wherein the first register includes a set of channels, each channel storing a corresponding value from the first set of values, and wherein the second register includes a set of channels, each channel storing a corresponding value from the second set of values.

50. The apparatus of claim 41, wherein the first register is a 512-bit register, wherein the second register is a 512-bit register, and wherein the assertion register is a 64-bit register.

51. The apparatus of claim 50, wherein each value in the first set of values ​​is an 8-bit value, each value in the second set of values ​​is an 8-bit value, and each value in the assertion register is a 1-bit value.

52. The apparatus of claim 41, wherein the operation is a sorting operation, and wherein, in order to perform the sorting operation, the functional unit is configured to exclude a value from the first group of values ​​or a value from the second group of values ​​from the sorting operation based on the value of the assertion register.

53. The apparatus of claim 41, wherein the functional unit is further configured to determine the number of specific values ​​present in the values ​​of the assertion register.

54. The apparatus of claim 41, wherein the functional unit is further configured to transfer the value in the assertion register to another register.

55. A system comprising: A memory configured to store instructions, the instructions including a first instruction, wherein the first instruction specifies a first register for storing a first set of values ​​and a second register for storing a second set of values; A processor configured to execute the instructions to: Based on the first instruction, for each value in the first set of values ​​and the corresponding value in the second set of values... Compare the value in the first group of values ​​with the corresponding value in the second group of values; Based on the comparison, one of the values ​​in the first set of values ​​and the corresponding values ​​in the second set of values ​​is identified; as well as The value is stored in the third register to indicate whether the identified value comes from the first set of values ​​or the second set of values; and Based on the value of the third register, operations associated with the first set of values ​​and the second set of values ​​are performed.

56. The system of claim 55, wherein the first instruction specifies a maximum sorting operation, and wherein the identified value is the larger of the value in the first set of values ​​and the corresponding value in the second set of values.

57. The system of claim 55, wherein the first instruction specifies a minimum sorting operation, and wherein the identified value is the smaller of the value in the first set of values ​​and the corresponding value in the second set of values.

58. The system of claim 55, wherein the processor is further configured to: For each value in the first set of values ​​and the corresponding value in the second set of values, the identified value is stored in a register.

59. The system of claim 55, wherein the operation is a sorting operation, and wherein, in order to perform the sorting operation, the processor is configured to: exclude a value from the first group of values ​​or a value from the second group of values ​​from the sorting operation based on the value of the third register.

60. The system of claim 55, wherein the processor is further configured to determine the number of specific values ​​present in the values ​​of the third register.

61. An apparatus comprising: The instruction decoding circuit is capable of: Receives instructions specifying the first register, second register, third register, and functional unit; The functional unit executes the instructions, wherein the execution of the instructions includes: Each value in the first set of values ​​stored in the first register is compared with the corresponding value in the second set of values ​​stored in the second register; Based on the comparison, one of the values ​​in the first set of values ​​and the corresponding values ​​in the second set of values ​​is identified; and The third register stores a value to indicate whether the identified value comes from the first set of values ​​or the second set of values; and The functional unit performs an operation associated with at least one of the first set of values ​​or the second set of values ​​based on the value stored in the third register.

62. The apparatus of claim 61, wherein the instruction further specifies a maximum sorting operation, and wherein the identified value is the larger of the value in the first set of values ​​and the corresponding value in the second set of values.

63. The apparatus of claim 61, wherein the instruction further specifies a minimum sorting operation, and wherein the identified value is the smaller of the value in the first set of values ​​and the corresponding value in the second set of values.

64. The apparatus of claim 61, wherein the instructions further specify whether the first set of values ​​and the second set of values ​​are signed or unsigned values.

65. The apparatus of claim 61, wherein the instructions further specify a data path associated with the bus.

66. The apparatus of claim 65, wherein the data path is a first data path associated with a first bus having a first width or a second data path associated with a second bus having a second width, and wherein the first width of the first bus is different from the second width of the second bus.

67. The apparatus of claim 66, wherein the first width is 64 bits and the second width is 512 bits.

68. The apparatus of claim 65, wherein the functional unit is capable of receiving data through a specified data path, rather than through a different data path.

69. The apparatus of claim 61, wherein the instruction further specifies a destination register, and the instruction decoding circuitry enables the functional unit to store the identified value in the destination register.

70. The apparatus of claim 61, wherein the first register includes a first set of channels, each of the first set of channels storing a corresponding value from the first set of values, and wherein the second register includes a second set of channels, each of the second set of channels storing a corresponding value from the second set of values.

71. The apparatus of claim 70, wherein each channel in the first group of channels stores an 8-bit value, each channel in the second group of channels stores an 8-bit value, and each value in the third register is a 1-bit value.

72. The apparatus of claim 61, wherein the first register is a 512-bit register, wherein the second register is a 512-bit register, and wherein the third register is a 64-bit register.

73. The apparatus of claim 61, wherein the operation is a sorting operation, and wherein performing the operation includes excluding a value from the first group of values ​​or a value from the second group of values ​​from the sorting operation based on the value stored in the third register.

74. The apparatus of claim 61, wherein the instruction decoding circuitry is further capable of enabling the functional unit to determine the number of specific values ​​present in the values ​​stored in the third register.

75. The apparatus of claim 61, wherein the instruction decoding circuit is further capable of enabling the functional unit to transfer the value stored in the third register to another register.

76. A method comprising: The instruction decoding circuit receives instructions specifying the first register, second register, third register, and functional unit. The instruction decoding circuit causes the functional unit to execute the instruction, wherein the execution of the instruction includes: Each value in the first set of values ​​stored in the first register is compared with the corresponding value in the second set of values ​​stored in the second register; Based on the comparison, one of the values ​​in the first set of values ​​and the corresponding values ​​in the second set of values ​​is identified; and The third register stores a value to indicate whether the identified value comes from the first set of values ​​or the second set of values; and The instruction decoding circuit enables the functional unit to perform an operation associated with at least one of the first set of values ​​or the second set of values, based on the value stored in the third register.

77. The method of claim 76, wherein the instructions further specify: Maximum sorting operation, wherein the identified value is the larger of the value in the first group of values ​​and the corresponding value in the second group of values; or The minimum sorting operation, wherein the identified value is the smaller of the value in the first group of values ​​and the corresponding value in the second group of values.

78. The method of claim 76, wherein the instructions further specify whether the first set of values ​​and the second set of values ​​are signed or unsigned values.

79. The method of claim 76, wherein the instructions further specify a data path associated with a bus of a specific width.

80. The method of claim 76, wherein the instruction specifies a destination register, and wherein the method includes storing the identified value in the destination register.

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