Instruction distribution method and device, chip and computer program product
By acquiring and controlling state input data, the problems of instruction blocking and resource waste in traditional vector processors are solved, achieving smooth instruction output and stability of downstream devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-26
- Publication Date
- 2026-04-10
AI Technical Summary
The instruction dispatch mechanism of traditional vector processors is prone to instruction blocking and resource waste, and cannot adapt to diverse computing workloads.
By acquiring status input data, including instruction input information, output information, the occupancy status of the full instruction queue, and the valid instruction information of the output queue, the status output data is determined, and instructions are stored in the output queue according to the output information, controlling instruction distribution to avoid blocking and waste.
It enables smooth instruction output in a short time, avoiding instruction blocking and resource waste, and improving the operational stability of downstream devices.
Smart Images
Figure CN121833049A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of processor technology, and in particular relates to an instruction dispatch method, apparatus, chip, and computer program product. Background Technology
[0002] The instruction dispatch controller is the core control unit in the instruction output stage of the processor. Its main function is to distribute decoded and ready instructions in parallel through the physical output port in each clock cycle.
[0003] Traditional vector processors typically employ a single-port or fixed-number, fixed-type instruction dispatch mechanism. While this design is simple in structure and clear in control logic, it is prone to instruction blocking and resource waste when faced with diverse computational loads.
[0004] Therefore, an instruction distribution scheme that can avoid instruction blocking and resource waste is needed. Summary of the Invention
[0005] In view of this, embodiments of this application provide an instruction distribution method, apparatus, chip, and computer program product to improve the dynamic load of instruction distribution and avoid instruction blocking and resource waste.
[0006] A first aspect of this application provides an instruction dispatch method applied to an instruction dispatch controller, the method comprising: Acquire status input data; the status input data includes: instruction input information, instruction output information, the occupancy status of a pre-built full instruction queue, and valid instruction information of a pre-built output queue; the full instruction queue is used to sequentially store the instructions corresponding to each received instruction input information; The status output data is determined based on the status input data; the status output data includes updated valid instruction information and control information for the output queue. Based on the instruction output information, the instructions stored in the output queue are output; Based on the control information, the instruction input information and / or a portion of the instructions in the full instruction queue are stored in the output queue.
[0007] In some implementations of the first aspect, the step of outputting the instructions stored in the output queue according to the instruction output information includes: Based on the instruction output information, determine the output quantity; The instructions in the output queue are output sequentially according to the stated output quantity.
[0008] In some implementations of the first aspect, the occupancy state is determined by the following steps: Determine the enqueue pointer and dequeue pointer in the full instruction queue; The output occupancy value is determined based on the difference between the dequeue pointer and the enqueue pointer; The occupancy status is determined based on the output occupancy value.
[0009] In some implementations of the first aspect, determining the occupancy status based on the output occupancy value includes: If the output occupancy value is within a first numerical range, then the occupancy state is determined to be an initial state; the initial state is used to indicate that the transmission of instructions from the full instruction queue to the output queue is prohibited. If the output occupancy value is a first specified value, then the occupancy state is determined to be a first state; the first state is used to indicate that the number of instructions transferred from the full instruction queue to the output queue does not exceed a first threshold. If the output occupancy value is a second specified value, then the occupancy state is determined to be a second state; the second state is used to indicate that the number of instructions transferred from the full instruction queue to the output queue does not exceed a second threshold. If the output occupancy value is within the second numerical range, then the occupancy state is determined to be the third state; the third state is used to indicate that the instructions in the full instruction queue are preferentially transmitted to the output queue. The first specified value is less than the second specified value, and the first specified value and the second specified value are located between the first value range and the second value range.
[0010] In some implementations of the first aspect, the control information comprises multiple control commands corresponding to the positions of each element in the output queue; The control commands include direct instruction transmission commands, instruction extraction commands, queue element movement commands, and commands to retain original values. Wherein, the direct instruction transmission command is used to characterize the instruction corresponding to the instruction input information that can be directly transmitted to the output queue; the instruction extraction command is used to characterize the instruction that crosses the instruction corresponding to the direct instruction transmission command in the full instruction queue and is transmitted to the output queue; the queue element move command is used to characterize the instruction displacement in the output queue; and the retain original value command is used to ensure that the instruction with the element position remains unchanged.
[0011] In some implementations of the first aspect, the instruction dispatch controller is provided with a first number of input terminals and a second number of output terminals; the first number is greater than the second number. The input terminal is connected to the instruction decoding module, and the output terminal is connected to the scheduling module; the instruction decoding module is used to send the decoded instruction to the input terminal, and the scheduling module is used to receive and schedule the instruction output by the output terminal.
[0012] In some implementations of the first aspect, the instruction dispatch controller is located in a vector processor of a RISC architecture.
[0013] A second aspect of this application discloses an instruction distribution apparatus applied to an instruction distribution controller, the apparatus comprising: A status input data acquisition module is used to acquire status input data; the status input data includes: instruction input information, instruction output information, the occupancy status of a pre-built full instruction queue, and valid instruction information of a pre-built output queue; the full instruction queue is used to sequentially store the instructions corresponding to each received instruction input information; A status output data generation module is used to determine status output data based on the status input data; the status output data includes updated valid instruction information and control information for the output queue. The instruction output module is used to output the instructions stored in the output queue according to the instruction output information; The output queue control module is used to store the instruction input information and / or a portion of the instructions in the full instruction queue into the output queue based on the control information.
[0014] A third aspect of this application provides a chip including a processor, a memory, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the chip implements the instruction dispatch method described in the first aspect above.
[0015] A fourth aspect of this application provides a computer program product including a computer program that, when run, causes the instruction dispatch method described in the first aspect above to be executed.
[0016] A fifth aspect of this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the instruction dispatch method described in the first aspect above.
[0017] Compared with the prior art, the embodiments of this application have the following beneficial effects: This application embodiment acquires status input data, which includes: instruction input information, instruction output information, the occupancy status of a pre-built full instruction queue, and valid instruction information of a pre-built output queue. The full instruction queue is used to sequentially store instructions corresponding to each received instruction input information. Status output data is determined based on the status input data. The status output data includes updated valid instruction information and control information for the output queue. Based on the instruction output information, the instructions stored in the output queue are output. Based on the control information, the instruction input information and / or a portion of the instructions in the full instruction queue are stored in the output queue. Compared to the prior art, this application embodiment adds the occupancy status of the full instruction queue as one of the considerations for instruction output by the instruction distribution controller, achieving more refined instruction output. In addition, compared to the prior art, this application embodiment adds an output queue. Since each output only extracts instructions from the output queue and outputs them, the number of instructions output each time can be kept within the second queue length of the output queue. By controlling the length of the second queue, the maximum number of instructions output in a single instruction dispatch control can be adjusted. This allows the instruction dispatch controller to output instructions in a number not exceeding the length of the second queue when it receives a large number of instructions that need to be output in a short period of time. This achieves smooth instruction output, avoids instruction blocking and resource waste, and improves the operational stability of downstream devices of the instruction dispatch controller. Attached Figure Description
[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 This is a schematic diagram of an instruction distribution method provided in an embodiment of this application; Figure 2 This is a schematic diagram of an instruction distribution controller architecture provided in an embodiment of this application; Figure 3 This is a schematic diagram of an occupancy status change provided in an embodiment of this application; Figure 4a This is a schematic diagram of the first part of the corresponding state input data and state output data provided in the embodiments of this application; Figure 4b This is a schematic diagram of the second part of the corresponding state input data and state output data provided in the embodiments of this application; Figure 4cThis is a schematic diagram of the third part of the corresponding state input data and state output data provided in the embodiments of this application; Figure 4d This is a schematic diagram of the fourth part of the corresponding state input data and state output data provided in the embodiments of this application; Figure 4e This is a schematic diagram of the fifth part of the corresponding state input data and state output data provided in the embodiments of this application; Figure 5 This is a schematic diagram illustrating an example of instruction distribution provided in an embodiment of this application; Figure 6 This is a schematic diagram illustrating another example of instruction distribution provided in the embodiments of this application; Figure 7 This is a schematic diagram of an instruction distribution device provided in an embodiment of this application; Figure 8 This is a schematic diagram of a chip provided in an embodiment of this application. Detailed Implementation
[0020] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.
[0021] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.
[0022] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.
[0023] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."
[0024] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0025] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.
[0026] In existing technologies, instruction dispatch controllers typically output received compiled instructions as quickly as possible. However, instruction dispatch controllers may receive instructions intermittently rather than continuously. If instructions are output as quickly as possible every time they are received, it can easily lead to a situation where a large number of instructions are output for a period of time, followed by a period of no instructions output, and then another period of large number of instructions output. This can easily cause instruction blocking during periods of large number of instruction outputs, and cause downstream devices of the instruction dispatch controller to switch between high load and idle states, which can easily lead to resource waste and fluctuations in the operating stability of downstream devices. The embodiments of this application set a fixed-length output queue in the instruction dispatch controller. When the instruction dispatch controller receives an instruction, it first transmits the instruction to the output queue, and then outputs the instructions in the output queue. This achieves smooth instruction output, which can avoid instruction blocking, avoid resource waste, and improve the operating stability of downstream devices.
[0027] The technical solution of this application will be described below through specific embodiments.
[0028] Reference Figure 1 The diagram illustrates an instruction distribution method provided in an embodiment of this application, applied to an instruction distribution controller. Specifically, this embodiment may include the following steps: Step 101: Obtain status input data. Reference Figure 2The diagram illustrates an instruction distribution controller architecture provided in this application embodiment. In this application embodiment, a state machine is provided, which receives state input data. The state input data includes: instruction input information (Push), instruction output information (Pop), the occupancy status of the pre-built full instruction queue (Fstat), and the valid instruction information (Vld) of the pre-built output queue. The full instruction queue is used to store the instructions corresponding to each received instruction input information in sequence.
[0029] The instruction input information includes the number of compiled, pending instruction inputs received by the instruction dispatch controller from external sources. The instruction output information includes the number of instruction outputs determined based on output requests received from external sources. The instruction dispatch controller pre-constructs a full instruction queue and an output queue. Both the full instruction queue and the output queue are First-Input First-Out (FIFO) queues. The full instruction queue stores all instructions received by the instruction dispatch controller, and the output queue stores a number of instructions that the instruction dispatch controller is about to output.
[0030] The full instruction queue has a first queue length, and the output queue has a second queue length. The full instruction queue includes element positions corresponding to the first queue length, and the output queue includes element positions corresponding to the second queue length. For example, if the first queue length is 40, the full instruction queue has 40 element positions, and can store a maximum of 40 instructions simultaneously; if the second queue length is 3, the output queue has 40 element positions, and can store a maximum of 3 instructions simultaneously.
[0031] Since the full instruction queue has a certain queue length, its occupancy status can be determined based on the number of instructions currently stored in it. Different occupancy statuses correspond to different numbers of cached instructions in the full instruction queue.
[0032] Valid instruction information is used to characterize the validity status of each element in the output queue, which can be either valid or invalid. Typically, each instruction in the output queue is output only once. If an instruction in the output queue has not been output, its validity status is valid; if the instruction has been output (output to an external instruction dispatch controller), its validity status is invalid.
[0033] Step 102: Determine the status output data based on the status input data.
[0034] As one example, a state machine can determine the state output data based on the currently received state input data according to preset rules. As another example, a state machine can pre-store mapping information, which includes state data and the corresponding state output data. That is, it can pre-determine the corresponding state output data for different state input data and construct and store the corresponding mapping information. The state machine then determines the state output data corresponding to the current state input data from the mapping information based on the currently received state input data and extracts that state output data.
[0035] The state output data includes updated valid instruction information (NxtVld) and control information for the output queue (RegCmd). In practice, instruction input and output information may change periodically. The state machine can determine the valid instruction information for the next change of instruction input and / or instruction output information based on the current state input data. That is, when the state input data is received, Vld = NxtVld can be obtained.
[0036] Since the occupancy status of the full instruction queue is considered as one of the status output data, the performance of the instruction dispatch controller's output instructions can be adjusted based on the occupancy status of the full instruction queue, providing a foundation for the fine-grained output of the instruction dispatch controller. For example, with the same instruction input information, instruction output information, and valid instruction information, different occupancy statuses can correspond to different status output data, thereby realizing instruction output control of the instruction dispatch controller based on occupancy status.
[0037] Step 103: Output the instructions stored in the output queue according to the instruction output information.
[0038] After determining the instruction output information, the instruction dispatch controller outputs the instructions stored in the output queue to the outside of the controller. Since the output queue is a first-in, first-out (FIFO) queue, instructions must be output in the order they appear in the queue.
[0039] Step 104: Based on the control information, store the instruction input information and / or a portion of the instructions in the full instruction queue into the output queue.
[0040] After the instructions stored in the output queue are output, new instructions can be stored in the output queue. Therefore, in response to certain control information, several instructions can be extracted from the instruction input information and / or from the full instruction queue, and the extracted instructions can be sent to the output queue.
[0041] In the specific implementation, the instruction dispatch control loop executes steps 101-104 repeatedly until all instructions in the full instruction queue have been output to the outside of the instruction dispatch control. It is understood that if the control information indicates that instruction input information and / or some instructions in the full instruction queue do not need to be stored in the output queue, then step 104 is not executed, and the process returns to step 101.
[0042] In this embodiment, state input data is acquired, including instruction input information, instruction output information, the occupancy status of a pre-built full instruction queue, and valid instruction information of a pre-built output queue. The full instruction queue is used to sequentially store the instructions contained in each received instruction input information. State output data is determined based on the state input data, including updated valid instruction information and control information for the output queue. Instructions stored in the output queue are output based on the instruction output information. Instructions input information and / or a portion of the instructions in the full instruction queue are stored in the output queue based on the control information. Compared to existing technologies, this embodiment adds the occupancy status of the full instruction queue as one of the considerations for instruction output by the instruction distribution controller, achieving more refined instruction output. Furthermore, compared to existing technologies, this embodiment adds an output queue. Since each output only extracts instructions from the output queue and outputs them, the number of instructions output each time can be kept within the second queue length of the output queue. By controlling the length of the second queue, the maximum number of instructions output in a single instruction dispatch control can be adjusted. This allows the instruction dispatch controller to output instructions in a number not exceeding the length of the second queue when it receives a large number of instructions that need to be output in a short period of time. This achieves smooth instruction output, avoids instruction blocking and resource waste, and improves the operational stability of downstream devices of the instruction dispatch controller.
[0043] In some implementations of this application, outputting instructions stored in the output queue according to instruction output information includes: determining the output quantity according to the instruction output information; and outputting the instructions in the output queue sequentially according to the output quantity.
[0044] Existing instruction dispatch controllers typically output instructions as quickly as possible upon receiving them, which can lead to significant fluctuations in the number of instructions received by downstream devices. This application's embodiment, however, determines the output quantity based on the instruction output information in the status input data. It is understood that the maximum output quantity cannot exceed the number of instructions that are valid. After determining the output quantity, instructions are output sequentially from the output queue according to the output quantity. For example, if the second queue length of the output queue is 3, meaning the output queue can buffer a maximum of 3 instructions to be output, then if there are 3 valid instructions, the maximum output quantity is 3 (3 instructions output). It is understood that the output quantity can also be 1 (1 instruction output) or 2 (2 instructions output). If there are 0 valid instructions, the output quantity can only be 0.
[0045] In some implementations of this application, the occupancy status is determined by the following steps: determining the enqueue pointer and dequeue pointer in the full instruction queue; determining the output occupancy value based on the difference between the dequeue pointer and the enqueue pointer; and determining the occupancy status based on the output occupancy value.
[0046] The occupancy status (Focc) of the full instruction queue can be calculated from the enqueue pointer (EnqPtr) and the dequeue pointer (DeqPtr). The enqueue pointer points to the element position of the next instruction to be written to the full instruction queue, and the dequeue pointer points to the element position of the next instruction to be read from the full instruction queue. The element position can be the instruction storage location in the instruction queue.
[0047] The specific calculation method is: Occupied state = Enqueue pointer - Dequeue pointer. Therefore, the occupied state is used to represent the number of instructions that have not been output in the full instruction queue.
[0048] In some implementations of the embodiments of this application, determining the occupancy status based on the output occupancy value includes: If the output occupancy value is within the first numerical range, then the occupancy state is determined to be the initial state; the initial state is used to indicate that the transmission of instructions from the full instruction queue to the output queue is prohibited. If the output occupancy value is a first specified value, then the occupancy state is determined to be the first state; the first state is used to indicate that the number of instructions transferred from the full instruction queue to the output queue does not exceed a first threshold. If the output occupancy value is the second specified value, then the occupancy status is determined to be the second status; the second status is used to indicate that the number of instructions transferred from the full instruction queue to the output queue does not exceed the second threshold. If the output occupancy value is within the second numerical range, then the occupancy state is determined to be the third state; the third state is used to indicate that the instructions in the full instruction queue are preferentially transferred to the output queue. The first specified value is less than the second specified value, and the first specified value and the second specified value are located between the range of the first value and the range of the second value.
[0049] When the occupied value is within the first numerical range, the occupied state is determined to be the initial state. This indicates that the full instruction queue contains relatively few instructions, and the initial state prohibits the transfer of instructions from the full instruction queue to the output queue. At this time, instructions corresponding to the instruction input information are preferentially stored in the output queue. That is, in the initial occupied state, the output priority of instructions corresponding to the instruction input information is higher than that of instructions stored in the full instruction queue.
[0050] If the output occupancy value is the first specified value, then the occupancy state is determined to be the first state. This indicates that the full instruction queue has stored a certain number of instructions. The first state represents that the number of instructions transferred from the full instruction queue to the output queue does not exceed a first threshold. That is, instructions not exceeding the first threshold are preferentially transferred from the full instruction queue to the output queue. If the output queue is not full, instructions corresponding to the input information are transferred to the output queue until the number of instructions to be output stored in the output queue is the same as the length of the second queue. In other words, in the first occupancy state, instructions at the first threshold stored in the full instruction queue have higher output priority than instructions corresponding to the input information. For example, if the length of the second queue of the output queue is 3, and assuming the output queue can store unoutputted instructions, instructions at the first threshold are preferentially extracted from the full instruction queue and stored in the output queue. After the instructions at the first threshold are stored in the output queue, if the output queue can still store unoutputted instructions, several instructions corresponding to the input information are stored in the output queue until the output queue can no longer store any more unoutputted instructions.
[0051] If the output occupancy value is the second specified value, then the occupancy state is determined to be the second state. This indicates that a larger number of instructions have been stored in the full instruction queue. The second state represents the fact that the number of instructions transferred from the full instruction queue to the output queue does not exceed a second threshold. That is, instructions not exceeding the second threshold are preferentially transferred from the full instruction queue to the output queue. If the output queue is not full, and the instruction corresponding to the input information is transferred to the output queue until the number of instructions to be output stored in the output queue is the same as the length of the second queue. In other words, in the second occupancy state, instructions at the second threshold stored in the full instruction queue have higher output priority than instructions corresponding to the input information.
[0052] If the output occupancy value is within the second numerical range, the occupancy state is determined to be the third state. This indicates that there are enough instructions in the full instruction queue. The third state is used to prioritize the transmission of instructions from the full instruction queue to the output queue, meaning that instructions from the full instruction queue need to be output as soon as possible, until the occupancy state switches to a state other than the third state. That is, when the occupancy state is in the third state, instructions from the full instruction queue are prioritized for transmission to the output queue, and the transmission of instructions corresponding to the instruction input information to the output queue is stopped, until the occupancy state changes to one of the initial state, the first state, or the second state.
[0053] Reference Figure 3 This diagram illustrates a change in occupancy status according to an embodiment of this application. For example, if Foc ≤ 3, the occupancy status is VDF_EMPTY (initial state); if Foc = 4, the occupancy status is VDF_EQ1 (first state); if Foc = 5, the occupancy status is VDF_EQ2 (second state); and if Foc ≥ 6, the occupancy status is VDF_GET3 (third state). The occupancy status can switch between the initial state, first state, second state, and third state. The occupancy status can be updated periodically or when any of the instruction input information, instruction output information, or valid instruction information changes. In this example, the second length of the output queue is 3. If the occupancy status is VDF_EMPTY, then if the output queue can store new instructions, only the instruction corresponding to the instruction input information is stored in the output queue; the full instruction queue only receives instructions and does not transmit instructions to the output queue. The first threshold is 1. When the occupancy state is VDF_EQ1, if the output queue can store new instructions, one instruction from the full instruction queue is preferentially transferred to the output queue. If, after transferring one instruction from the full instruction queue to the output queue, the output queue can still store new instructions, then the instructions corresponding to the instruction input information are stored in the output queue. The second threshold is 2. When the occupancy state is VDF_EQ2, if the output queue can store new instructions, two instructions from the full instruction queue are preferentially transferred to the output queue. If, after transferring two instructions from the full instruction queue to the output queue, the output queue can still store new instructions, then the instructions corresponding to the instruction input information are stored in the output queue. If the occupancy state is VDF_GET3, if the output queue can store new instructions, three instructions from the full instruction queue are preferentially transferred to the output queue, but the instructions corresponding to the instruction input information are not transferred to the output queue.
[0054] In some implementations of this application, the control information (RegCmd) comprises multiple control commands corresponding to the positions of each element in the output queue; Control commands include the direct instruction transfer command DECX, the instruction fetch command FY, the queue element move command REGZ, and the original value preservation command HOLD; Among them, the instruction direct transfer command DECX is used to represent the instruction that can be directly transferred to the output queue corresponding to the instruction input information; the instruction fetch command FY is used to represent the instruction that crosses the instruction corresponding to the instruction direct transfer command DECX in the full instruction queue and is transferred to the output queue; the queue element move command REGZ is used to represent the instruction displacement in the output queue; and the original value retention command HOLD is used to keep the instruction element position unchanged.
[0055] The DECX identifier can be used to identify instructions that can be directly transmitted to the output queue, corresponding to the input information. For example, if the second queue length of the output queue is 3, and the number of instructions that can be directly transmitted to the output queue is 3, these 3 instructions can be identified as DEC0, DEC1, and DEC2 respectively. The instruction fetch command FY can be used to identify instructions extracted from the full instruction queue that cross the DECX, because the full queue also stores instructions corresponding to the direct transmission command DECX, thus avoiding duplicate output instructions; therefore, instructions that cross the DECX are necessary. Continuing with the example of the second queue length of the output queue being 3, FY can be F00, F01, and F02. It can be understood that the number of X values and the number of Y values are equal to the second queue length (as above, if the second queue length is 3, then the value of X can be 0, 1, 2, etc., and Y is similar, which will not be elaborated further here). Since the output queue may not contain all instructions at once, when the number of instructions output in a single operation is less than the length of the second queue, the remaining instructions in the output queue need to be shifted. Z represents the displacement amount. For example, REG1 means that the instruction moves forward (to the exit of the second queue) by 1 position, and REG2 means that the instruction moves forward (to the exit of the second queue) by 2 positions. It can be understood that the value of Z is the length of the second queue - 1.
[0056] In practical applications, each element position in the second queue corresponds to one of the following: Direct Instruction Transfer (DECX), Instruction Fetch (FY), Queue Element Move (REGZ), or Preserve Original Value (HOLD). Continuing with the example of a second queue length of 3, the control information can be {F02, F01, F00}. This control information indicates that three instructions, each corresponding to the instruction in the Direct Instruction Transfer (DECX) command, are retrieved from the full instruction queue and stored in three element positions of the output queue.
[0057] In some implementations of the embodiments of this application, the instruction distribution controller is provided with a first number of input terminals and a second number of output terminals; the first number is greater than the second number; the input terminals are connected to the instruction decoding module, and the output terminals are connected to the scheduling module; the instruction decoding module is used to send decoded instructions to the input terminals, and the scheduling module is used to receive and schedule the instructions output by the output terminals.
[0058] The first quantity corresponds to the number of instruction inputs, and the second quantity corresponds to the number of instruction outputs. The first quantity is greater than the second quantity, meaning that the instruction distribution controller has more inputs than outputs, and thus the instruction distribution controller is a multi-port type instruction distribution controller.
[0059] The instruction input information corresponds to the instructions input from the instruction decoding module to the instruction distributor, and the instruction output information corresponds to the instructions output from the instruction distributor to the scheduling module. For example, the instruction distributor has 5 input terminals and 3 output terminals. Instruction input information of 0-5 indicates that the instruction distribution controller can receive the corresponding number of instructions to be output to the scheduling module from the instruction decoding module through the 5 input terminals. Instruction output information of 0-3 indicates that the instruction distribution controller can output the corresponding number of instructions to the scheduling module through the 3 output terminals, and the scheduling module performs scheduling based on the received instructions.
[0060] Given the first quantity of inputs, the second quantity of outputs, and the length of the second queue, the corresponding state input data and state output data can be determined.
[0061] Reference Figure 4a This diagram illustrates the first part of the corresponding state input data and state output data provided in an embodiment of this application. (Refer to...) Figure 4b This diagram illustrates the second part of the corresponding state input data and state output data provided in an embodiment of this application. (Refer to...) Figure 4c This diagram illustrates the third part of the corresponding state input data and state output data provided in an embodiment of this application. (Refer to...) Figure 4d This diagram illustrates the fourth part of the corresponding state input data and state output data provided in an embodiment of this application. (Refer to...) Figure 4e This diagram illustrates the fifth part of the mutually corresponding state input data and state output data provided in an embodiment of this application. For example, with a first quantity of 5, a second quantity of 3, and a second length of 3, mutually corresponding state input data and state output data can be obtained. This mutually corresponding state input data and state output data are generated by... Figure 4a , 4bIt consists of five parts as shown in 4c, 4d and 4e. In the Vld section, 3'b*** indicates the validity status of the instruction corresponding to each element position in the second queue, with 1 indicating validity and 0 indicating invalidity. In the Push section, 3'd* (or a specific value can be used to replace "3'd*") indicates the number of instructions received, for example, 3'd5 indicates that the number of instructions received is 5, that is, new instructions are received through 5 input terminals. In the Pop section, 2'd* (or a specific value can be used to replace "2'd*") indicates the number of instructions output, for example, 2'd2 indicates that the number of instructions output is 2, that is, instructions are output through 2 output terminals. In the NxtVld section, 3'b*** indicates the validity status of the instruction corresponding to each element position in the second queue in the next state input data. RegCmd indicates the control command corresponding to each element position, with each element position separated by a comma, for example: {DEC2, DEC1, DEC0} indicates that the control commands corresponding to the element positions from the tail to the head in the second output queue are "DEC2", "DEC1", and "DEC0".
[0062] In some implementations of the embodiments of this application, the instruction dispatch controller is located in a vector processor of a RISC architecture.
[0063] As an example, embodiments of this application can be applied to vector processors based on the RISC-V architecture.
[0064] The following two examples, combined with the shooting delay, further illustrate the embodiments of this application: Reference Figure 5 This diagram illustrates an example of instruction distribution provided in an embodiment of this application. To improve the parallel processing capability of the instruction distribution controller, timing is typically implemented between the full instruction queue and the decoding module, between the output queue and the scheduling module, and before the state machine determines NxtVld. However, timing causes a delay in the number of instructions in the full instruction queue. Figure 5 The diagram shows a comparison between the number of instructions in the full instruction queue and the actual number of instructions that need to be output in the full instruction queue during the instruction dispatch process, as well as the corresponding state output data under different state input data.
[0065] Reference Figure 6 The diagram illustrates another example of instruction distribution provided in this application. Figure 6 The process of storing and outputting instructions in the second queue is further illustrated. The "(*)" in each control command is used to indicate the corresponding instruction identifier. For example, DEC2(8e), DEC1(8d), and DEC0(8c) correspond to three instructions, which are identified by 8e, 8d, and 8c, respectively.
[0066] It should be noted that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.
[0067] Reference Figure 7 The diagram illustrates a schematic of an instruction distribution device provided in an embodiment of this application. Located in the instruction distribution controller, the device may specifically include a status input data acquisition module 701, a status output data generation module 702, an instruction output module 703, and an output queue control module 704, wherein: The status input data acquisition module 701 is used to acquire status input data; the status input data includes: instruction input information, instruction output information, the occupancy status of the pre-built full instruction queue, and the valid instruction information of the pre-built output queue; the full instruction queue is used to store the instructions corresponding to each received instruction input information in sequence; The status output data generation module 702 is used to determine the status output data based on the status input data; the status output data includes updated valid instruction information and control information of the output queue. The instruction output module 703 is used to output the instructions stored in the output queue according to the instruction output information; The output queue control module 704 is used to store instruction input information and / or a portion of the instructions in the full instruction queue into the output queue based on control information.
[0068] In some implementations of the embodiments of this application, the instruction output module 703 includes: The output quantity determination submodule is used to determine the output quantity based on the instruction output information; The instruction output submodule is used to output the instructions in the output queue sequentially according to the number of outputs.
[0069] In some implementations of this application, the occupancy status is determined by the following module: The pointer determination module is used to determine the enqueue and dequeue pointers in the full instruction queue; The output occupancy value determination module is used to determine the output occupancy value based on the difference between the dequeue pointer and the enqueue pointer. The occupancy status determination module is used to determine the occupancy status based on the output occupancy value.
[0070] In some implementations of the embodiments of this application, the occupancy status determination module is specifically used to include: If the output occupancy value is within the first numerical range, then the occupancy state is determined to be the initial state; the initial state is used to indicate that the transmission of instructions from the full instruction queue to the output queue is prohibited. If the output occupancy value is a first specified value, then the occupancy state is determined to be the first state; the first state is used to indicate that the number of instructions transferred from the full instruction queue to the output queue does not exceed a first threshold. If the output occupancy value is the second specified value, then the occupancy status is determined to be the second status; the second status is used to indicate that the number of instructions transferred from the full instruction queue to the output queue does not exceed the second threshold. If the output occupancy value is within the second numerical range, then the occupancy state is determined to be the third state; the third state is used to indicate that the instructions in the full instruction queue are preferentially transferred to the output queue. The first specified value is less than the second specified value, and the first specified value and the second specified value are located between the range of the first value and the range of the second value.
[0071] In some implementations of this application, the control information comprises multiple control commands corresponding to the positions of each element in the output queue; Control commands include direct instruction transmission commands, instruction retrieval commands, queue element movement commands, and commands that retain original values. Among them, the direct instruction transfer command is used to represent the instruction that can be directly transferred to the output queue corresponding to the instruction input information; the instruction fetch command is used to represent the instruction that crosses the instruction corresponding to the direct instruction transfer command in the full instruction queue and is transferred to the output queue; the queue element move command is used to represent the instruction displacement in the output queue; and the original value preserve command is used to keep the instruction element position unchanged.
[0072] In some implementations of the embodiments of this application, the instruction dispatch controller is provided with a first number of input terminals and a second number of output terminals; the first number is greater than the second number; The input terminal is connected to the instruction decoding module, and the output terminal is connected to the scheduling module. The instruction decoding module is used to send decoded instructions to the input terminal, and the scheduling module is used to receive and schedule the instructions output by the output terminal.
[0073] In some implementations of the embodiments of this application, the instruction dispatch controller is located in a vector processor of a RISC architecture.
[0074] This application provides an instruction distribution device, which can be used to implement the steps in the aforementioned method embodiments.
[0075] As the apparatus embodiments are basically similar to the method embodiments, they are described in a relatively simple manner. For relevant details, please refer to the description in the method embodiment section.
[0076] Reference Figure 8 The diagram illustrates a chip provided in an embodiment of this application. Figure 8As shown, the chip 800 in this embodiment includes a processor 810, a memory 820, and a computer program 821 stored in the memory 820 and executable on the processor 810. When the processor 810 executes the computer program 821, it implements the steps in the various embodiments of the instruction dispatch method described above, for example... Figure 1 Steps 101 to 104 are shown. Alternatively, when processor 810 executes computer program 821, it implements the functions of each module / unit in the above-described device embodiments, for example... Figure 7 The functions of modules 701 to 704 are shown.
[0077] For example, computer program 821 can be divided into one or more modules / units, one or more of which are stored in memory 820 and executed by processor 810 to complete this application. One or more modules / units can be a series of computer program instruction segments capable of performing specific functions, which can be used to describe the execution process of computer program 821 in chip 800. For example, computer program 821 can be divided into a status input data acquisition module, a status output data generation module, an instruction output module, and an output queue control module, with the specific functions of each module as follows: The status input data acquisition module is used to acquire status input data. The status input data includes: instruction input information, instruction output information, the occupancy status of the pre-built full instruction queue, and the valid instruction information of the pre-built output queue. The full instruction queue is used to store the instructions corresponding to each received instruction input information in sequence. The status output data generation module is used to determine the status output data based on the status input data; the status output data includes updated valid instruction information and control information for the output queue. The instruction output module is used to output the instructions stored in the output queue according to the instruction output information; The output queue control module is used to store instruction input information and / or a portion of the instructions in the full instruction queue into the output queue based on control information.
[0078] This application also discloses a computer-readable storage medium storing a computer program that, when executed by a processor, implements the instruction dispatch method as described in the foregoing embodiments.
[0079] This application also discloses a computer program product, including a computer program, which, when run, causes the instruction dispatch method as described in the foregoing embodiments to be executed.
[0080] The embodiments described above are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.
Claims
1. An instruction dispatch method, characterized in that, For an instruction dispatch controller, the method includes: Acquire status input data; the status input data includes: instruction input information, instruction output information, the occupancy status of a pre-built full instruction queue, and valid instruction information of a pre-built output queue; the full instruction queue is used to sequentially store the instructions corresponding to each received instruction input information; The status output data is determined based on the status input data; the status output data includes updated valid instruction information and control information for the output queue. Based on the instruction output information, the instructions stored in the output queue are output; Based on the control information, the instruction input information and / or a portion of the instructions in the full instruction queue are stored in the output queue.
2. The method according to claim 1, characterized in that, The step of outputting the instructions stored in the output queue according to the instruction output information includes: Based on the instruction output information, determine the output quantity; The instructions in the output queue are output sequentially according to the stated output quantity.
3. The method according to claim 1 or 2, characterized in that, The occupancy status is determined through the following steps: Determine the enqueue pointer and dequeue pointer in the full instruction queue; The output occupancy value is determined based on the difference between the dequeue pointer and the enqueue pointer; The occupancy status is determined based on the output occupancy value.
4. The method according to claim 3, characterized in that, Determining the occupancy status based on the output occupancy value includes: If the output occupancy value is within a first numerical range, then the occupancy state is determined to be an initial state; the initial state is used to indicate that the transmission of instructions from the full instruction queue to the output queue is prohibited. If the output occupancy value is a first specified value, then the occupancy state is determined to be a first state; the first state is used to indicate that the number of instructions transferred from the full instruction queue to the output queue does not exceed a first threshold. If the output occupancy value is a second specified value, then the occupancy state is determined to be a second state; the second state is used to indicate that the number of instructions transferred from the full instruction queue to the output queue does not exceed a second threshold. If the output occupancy value is within the second numerical range, then the occupancy state is determined to be the third state; the third state is used to indicate that the instructions in the full instruction queue are preferentially transmitted to the output queue. The first specified value is less than the second specified value, and the first specified value and the second specified value are located between the first value range and the second value range.
5. The method according to claim 4, characterized in that, The control information consists of multiple control commands corresponding to the positions of each element in the output queue. The control commands include direct instruction transmission commands, instruction extraction commands, queue element movement commands, and commands to retain original values. Wherein, the direct instruction transmission command is used to characterize the instruction corresponding to the instruction input information that can be directly transmitted to the output queue; the instruction extraction command is used to characterize the instruction that crosses the instruction corresponding to the direct instruction transmission command in the full instruction queue and is transmitted to the output queue; the queue element move command is used to characterize the instruction displacement in the output queue; and the retain original value command is used to ensure that the instruction with the element position remains unchanged.
6. The method according to claim 1, characterized in that, The instruction distribution controller is provided with a first number of input terminals and a second number of output terminals; the first number is greater than the second number. The input terminal is connected to the instruction decoding module, and the output terminal is connected to the scheduling module; the instruction decoding module is used to send the decoded instruction to the input terminal, and the scheduling module is used to receive and schedule the instruction output by the output terminal.
7. The method according to claim 1, characterized in that, The instruction dispatch controller is located in a vector processor of a RISC architecture.
8. An instruction distribution device, characterized in that, Applied to an instruction dispatch controller, the device includes: A status input data acquisition module is used to acquire status input data; the status input data includes: instruction input information, instruction output information, the occupancy status of a pre-built full instruction queue, and valid instruction information of a pre-built output queue; the full instruction queue is used to sequentially store the instructions corresponding to each received instruction input information; A status output data generation module is used to determine status output data based on the status input data; the status output data includes updated valid instruction information and control information for the output queue. The instruction output module is used to output the instructions stored in the output queue according to the instruction output information; The output queue control module is used to store the instruction input information and / or a portion of the instructions in the full instruction queue into the output queue based on the control information.
9. A chip, characterized in that, The chip includes a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the chip implements the method as described in any one of claims 1-7.
10. A computer program product, characterized in that, Includes a computer program, which, when run, causes the method as described in any one of claims 1-7 to be performed.