DAG task energy-saving scheduling method and device and storage medium

Abstract

The invention relates to the technical field of computer computing resource scheduling, and discloses a DAG task energy-saving scheduling method and device and a storage medium, through dynamic analysis of a DAG structure, utilization of elastic time recovery on a non-critical path and combination of DVFS adjustment frequency, the real-time deadline requirement is finally met, and meanwhile the power consumption of a system is greatly reduced. In combination with the mapping schematic from the task to the core, the most necessary hardware resources are preferentially used in the execution process of the strategy, and the idle cores are timely combined and closed, so that the scheduling characteristics of high efficiency and energy conservation are embodied; the problems that in an existing technical scheme, a non-critical path dynamic elastic space cannot be utilized at the same time, DVFS frequency adjustment and idle core combination cannot be combined to achieve real-time scheduling, and the energy consumption cannot be reduced while the SLA requirement is guaranteed are solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer computing resource scheduling, for example, to a DAG task energy-saving scheduling method, device and storage medium. BACKGROUND

[0002] In a cloud computing environment, scientific computing and parallel workflow tasks are usually modeled as a directed acyclic graph (DAG), where nodes represent sub-tasks and directed edges represent the dependency between tasks. Each DAG task usually has a strict deadline requirement, requiring all sub-tasks to be completed before the deadline. A common method is to estimate the total execution time of the task by critical path analysis, and the tasks on the critical path are the longest task path required to complete the entire DAG. In actual systems, to meet real-time requirements, the scheduler needs to ensure that the critical path tasks are executed first, and the non-critical path tasks can be adjusted using the additional slack time.

[0003] Modern cloud data centers widely use multi-core processor technology that supports dynamic voltage and frequency scaling (DVFS) to reduce energy consumption. DVFS uses the CMOS circuit power consumption formula to control power consumption by reducing processor voltage and frequency. Existing research has shown that combining DVFS with task scheduling can effectively reduce energy consumption while ensuring task deadlines. In addition, the processor merging technology has also been proposed for further energy saving: by concentrating tasks on fewer cores and shutting down the remaining idle cores, the system's static power consumption can be significantly reduced.

[0004] However, existing scheduling algorithms usually have the following shortcomings: - Many traditional methods focus on minimizing task completion time while meeting real-time requirements, but do not make full use of the flexibility (slack) of non-critical paths in DAGs; - Even if DVFS is introduced to reduce frequency, it often only adjusts according to a fixed strategy without dynamically allocating and recycling the idle time of tasks; - Support for processor merging technology is weak, usually only shutting down the cores after the task is completed, lacking an online merging strategy that coordinates with task scheduling.

[0005] In summary, existing technical solutions cannot simultaneously utilize the dynamic flexibility space of non-critical paths and combine DVFS frequency adjustment and processor merging to achieve real-time scheduling, nor can they reduce energy consumption while ensuring SLA (Service Level Agreement) requirements.

[0006] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present application. SUMMARY

[0007] The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. The summary is not an extensive overview of the embodiments nor is it intended to identify key / critical elements of the embodiments or to delineate the scope of the embodiments but to present some concepts of the embodiments in a simplified form as a prelude to the more detailed description that is presented later.

[0008] The DAG task energy-saving scheduling method, device and storage medium provided by the embodiments of the present disclosure can solve the problem that the prior art cannot simultaneously utilize the dynamic elasticity space of non-critical paths and combine DVFS frequency adjustment and idle core merging to realize real-time scheduling, while guaranteeing the SLA (Service Level Agreement) requirement and reducing energy consumption.

[0009] The embodiments of the present disclosure provide a DAG task energy-saving scheduling method, which is applied to a heterogeneous multi-core processor platform, and the method can include: receiving a DAG task with a deadline constraint, and performing topological sorting and critical path analysis to determine critical path tasks and non-critical path tasks; calculating and assigning dynamic elasticity time for the non-critical path tasks; According to the dynamic elasticity time assigned to the non-critical path tasks, the working frequency and voltage of the processor core where the non-critical path tasks are located are reduced in proportion; During task execution, the load state of each processor core is monitored, and when it is detected that multiple processor cores are in an idle or low load state, an idle core merging strategy is triggered, the tasks are migrated to the active cores for execution, and the power consumption of the remaining idle cores is turned off or reduced.

[0010] The embodiments of the present disclosure provide an electronic device, which includes at least one processor; and a memory in communication connection with the at least one processor; The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the above-mentioned DAG task energy-saving scheduling method.

[0011] The embodiments of the present disclosure provide a non-transitory computer-readable storage medium storing computer instructions for causing a computer to execute the above-mentioned DAG task energy-saving scheduling method.

[0012] The DAG task energy-saving scheduling method, device and storage medium provided by the embodiments of the present disclosure can achieve the following technical effects: The present disclosure realizes, by dynamically analyzing the DAG structure, recycling the flexible time on the non-critical path, and adjusting the frequency in combination with DVFS, the system power consumption is greatly reduced while meeting the real-time deadline requirement. In combination with the task-to-core mapping diagram, it can be seen that the most necessary hardware resources are used preferentially during the execution of the present strategy, and the idle cores are closed in time, which embodies the efficient and energy-saving scheduling characteristics, and solves the problem that the existing technical solutions cannot simultaneously utilize the dynamic flexible space of the non-critical path and realize real-time scheduling in combination with the DVFS frequency adjustment and idle core merging to reduce the energy consumption while guaranteeing the SLA (Service Level Agreement) requirement. Compared with the prior art, the present disclosure dynamically utilizes the flexible space of the non-critical path and reduces the frequency in combination with DVFS, and simultaneously implements idle core merging, thereby realizing more significant energy consumption reduction. Compared with the traditional scheduling mode using only EDF+DVFS, the present method fully recycles the scheduling idle, improves the processor utilization, and significantly reduces the energy consumption and SLA violation rate under the premise of meeting the DAG task deadline requirement.

[0013] The foregoing general description and the following description are merely exemplary and explanatory, and are not intended to limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0014] One or more embodiments are illustrated by way of example, in relation to the accompanying drawings, which are not intended to be limiting of the embodiments, and in which like numerals refer to like elements across the various figures, the drawings are not intended to be to scale, and in which: Figure 1 is a flow diagram of a DAG task energy-saving scheduling method provided by an embodiment of the present disclosure; Figure 2 is a system architecture diagram provided by an embodiment of the present disclosure; Figure 3 is a scheduling flow diagram provided by an embodiment of the present disclosure; Figure 4 is a structure diagram of a DAG task energy-saving scheduling device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0015] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure will be described in detail below in combination with the drawings, which are only used for reference and do not limit the embodiments of the present disclosure. In the following technical description, in order to facilitate explanation, a plurality of details are provided to provide a full understanding of the disclosed embodiments. However, one or more embodiments can still be implemented without these details. In other cases, in order to simplify the drawings, well-known structures and devices can be simplified.

[0016] The terms "first", "second", etc. in the embodiments of the present disclosure are used to distinguish similar objects, and do not necessarily mean a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so as to implement the embodiments of the present disclosure described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion.

[0017] Unless otherwise specified, the term "plurality" means two or more.

[0018] In the embodiments of the present disclosure, the character " / " represents an "or" relationship between the objects before and after it. For example, A / B represents: A or B.

[0019] The term "and / or" is a description of the association relationship between objects, which means that there can be three relationships. For example, A and / or B means: A or B, or, A and B, the three relationships.

[0020] The term "corresponding" can refer to an association or binding relationship. A and B correspond to each other means that there is an association or binding relationship between A and B.

[0021] To solve the above problems, the present disclosure provides a DAG task energy-saving scheduling method, device and storage medium.

[0022] The DAG task energy-saving scheduling method, device and storage medium provided by the embodiments of the present disclosure will be described below with reference to the accompanying drawings.

[0023] Figure 1 It is a flowchart of a DAG task energy-saving scheduling method provided by the embodiments of the present disclosure.

[0024] In combination Figure 1 As shown in the figure, the DAG task energy-saving scheduling method can be applied to a heterogeneous multi-core processor platform. The method can specifically include: S101, receiving a DAG task with a deadline constraint, and performing topological sorting and critical path analysis to determine critical path tasks and non-critical path tasks; S102, calculating and assigning dynamic elastic time for non-critical path tasks; S103, according to the dynamic elastic time assigned for the non-critical path tasks, proportionally reducing the working frequency and voltage of the processor core where the non-critical path tasks are located; S104, during the task execution process, monitoring the load state of each processor core, when detecting that multiple processor cores are in an idle or low load state, triggering an idle core merging strategy, migrating the tasks to some active cores for execution, and shutting down or reducing the power consumption of the remaining idle cores.

[0025] In some embodiments, the above-mentioned dynamic slack time is calculated and allocated for non-critical path tasks, including: calculating the earliest start time and the latest finish time for each non-critical path task; calculating the initial slack time for each non-critical path task based on the earliest start time and the latest finish time; allocating the total slack time on the non-critical path to each task on the path according to a predetermined strategy.

[0026] In some embodiments, the above-mentioned predetermined strategy is a uniform allocation strategy.

[0027] In some embodiments, after reducing the working frequency and voltage of the processor core where the task is located, the above-mentioned method further includes calculating a new frequency, satisfying the formula: New frequency = original frequency × (worst-case execution time of the task / (worst-case execution time of the task + allocated dynamic slack time)).

[0028] In some embodiments, in the task mapping stage, the critical path tasks are mapped to the processor cores running in the target high-frequency range for execution, and the non-critical path tasks allocated with dynamic slack time are mapped to the processor cores with reduced frequency for execution.

[0029] In some embodiments, the above-mentioned idle core merging strategy is triggered dynamically online, and the triggering condition is that multiple processor cores are continuously idle or have a load lower than a preset threshold within a target time period.

[0030] In some embodiments, when reducing the working frequency of the processor core, the above-mentioned method synchronously reduces the working voltage of the processor core through dynamic voltage and frequency adjustment technology.

[0031] In some embodiments, the processor cores in the above-mentioned heterogeneous multi-core processor platform support multi-level dynamic voltage and frequency adjustment.

[0032] Figure 2 is a system architecture schematic diagram provided by an embodiment of the present disclosure, Figure 3 is a scheduling flow schematic diagram provided by an embodiment of the present disclosure, in combination with Figure 2 and Figure 3 , the DAG task energy-saving scheduling method in Figure 1 is further described.

[0033] In Figure 2 , the relationship between the task management module, the scheduler, the DVFS controller, and the heterogeneous multi-core processor is shown. The scheduler coordinates the task management module and the DVFS controller to complete resource allocation and frequency regulation according to the DAG input.

[0034] In Figure 3In the middle, it is illustrated that the DAG task input is sequentially analyzed by the critical path, the elastic space is calculated and allocated, the DVFS frequency is adjusted, and the idle core is combined, and the like. The flowchart directly shows the whole process from the task analysis to the frequency regulation and core combination.

[0035] The present application is directed to a DAG task graph with deadline constraints in a heterogeneous multi-core data center, and proposes a scheduling mechanism based on critical path dynamic elastic space recycling combined with DVFS dynamic voltage frequency adjustment, and combines the "idle core merging" strategy, so as to reduce the energy consumption to the greatest extent without violating the real-time constraint. The core structure and main process include: Critical path elastic recycling: the scheduler first performs topological sorting and critical path analysis on the input DAG task graph, calculates the earliest start time and the latest completion time of each task, and obtains the dynamic elasticity (slack) time of each non-critical path task. Based on the remaining time of each path, the available elastic space is allocated to the tasks on the non-critical path, and the executable time is extended.

[0036] Joint DVFS adjustment: for the non-critical path tasks that have been allocated elastic space, the present application reduces the working frequency of the processor in proportion to fill the idle time without affecting the task completion time. Specifically, if a non-critical path task has a certain proportion of slack, the processor frequency is reduced in proportion (voltage is reduced synchronously), so that the task execution time is extended accordingly but still completed within the deadline. This frequency adjustment not only utilizes the idle time, but also realizes energy optimization by reducing the voltage.

[0037] Idle core merging: during the task running process, the scheduler monitors the load state of each core. When multiple processor cores are in idle or low load state, the present application will perform the idle core merging strategy: migrate the tasks on some cores to other active cores for execution, and close or put the idle cores into low power mode to avoid the waste of static power consumption of idle cores. The merging strategy can be triggered online according to the load condition to realize dynamic core number adjustment.

[0038] Comparison with prior art: the present application dynamically utilizes the elastic space of non-critical path and combines DVFS to reduce the frequency, and simultaneously implements idle core merging, which realizes more significant energy consumption reduction. Compared with the traditional scheduling method using EDF+DVFS, the present method fully recycles the scheduling idle, improves the processor utilization, and significantly reduces the energy consumption and SLA violation rate under the premise of meeting the deadline of DAG task.

[0039] Overall, the scheduling strategy proposed in the present application includes: DAG task management module (responsible for task graph receiving and analysis), scheduling decision module (performing critical path analysis, Slack allocation and DVFS setting) and DVFS controller module (actually performing frequency adjustment and idle core management). The above modules work together to realize efficient and energy-saving DAG real-time scheduling.

[0040] The present application will be further described below in combination with the drawings and specific embodiments. It is assumed that there are several heterogeneous multi-core processors in the system, each processor core supports multi-level DVFS, and receives multiple DAG tasks with deadlines. The implementation steps of the scheduler are as follows: 1) Task receiving and analysis: After the scheduler receives a new DAG task, it first performs topological sorting on the task graph, calculates the earliest start time (EST) and the latest finish time (LFT) of each task. According to the dependency relationship between tasks, the longest path is found as the critical path, and the tasks on this path determine the latest finish time of the entire DAG. The Slack time of non-critical path tasks is the additional available time that the task can delay execution.

[0041] 2) Elastic space calculation and allocation: Calculate the total Slack available for each non-critical path, and allocate it to each task on the path according to a predetermined strategy (such as uniform allocation). In this way, each non-critical task can obtain additional execution time. For example, if a task execution time is $T$, the Slack is $S$, then the running frequency can be reduced by $\frac{S}{T+S}$ proportion, so that the execution time becomes $T+S$. This operation ensures that the task is completed before the deadline, and the idle gap is filled.

[0042] 3) DVFS frequency adjustment: According to the Slack of each task after allocation, calculate the corresponding frequency adjustment proportion. The scheduler instructs the DVFS controller to reduce the running frequency of each target processor core to a new level (voltage is reduced synchronously), and the specific proportion can be determined according to the execution time of the task after expansion. For example, if a task obtains a 20% Slack, the corresponding processor frequency is reduced to 80%. At this time, the task execution time is lengthened but just fills the Slack, thereby reducing energy consumption without violating the deadline.

[0043] 4) Task mapping and execution: After adjusting the frequency, the critical path tasks and non-critical path tasks are mapped to specific processor cores according to the EDF or weight algorithm. Generally, critical path tasks are assigned to high-frequency cores for execution to ensure the time limit; non-critical path tasks are assigned to reduced-frequency cores for execution. When the task is executed on the respective core, it runs at the new frequency.

[0044] 5) Idle core consolidation and management: During the execution of the schedule, the scheduler continuously monitors the load of each core. If multiple cores are found to be in a continuous idle or low load state, the core consolidation mechanism can be triggered. For example, when two or more cores are detected to have no tasks assigned for a period of time, the scheduler can migrate a small number of running tasks to other active cores and shut down these idle cores or enter low power mode. After consolidation, the system can set the frequency of the remaining cores to the lowest voltage to further reduce idle energy consumption.

[0045] Implementation example: Assume a DAG containing 3 parallel workflow chains, of which the first is the critical path and the remaining two are non-critical paths. After analysis by the scheduler, tasks for non-critical paths are assigned Slack and the frequency of the corresponding processors is reduced. During execution, if two processor cores are idle at the same time, the subsequent tasks at that time are consolidated onto a single processor core, and the other idle core is shut down. Thus, during the entire execution of the DAG, idle time and hardware resources are fully utilized to minimize energy consumption.

[0046] The pseudo code example of the algorithm of the present application is given below: For each arriving DAG task G: Calculate the critical path CP = longest_path(G) / / Get the longest path For each task Ti in G: if Ti is not on CP: Calculate Ti's Slack = Ti.LFT - Ti.EST - Ti.WCET For each non-critical path P: Distribute the Slack of tasks on P according to the strategy For each task Ti in G: If Ti is on a non-critical path and has obtained Slack: New frequency = original frequency × (Ti.WCET / (Ti.WCET + Ti.assigned Slack)) Instruct the DVFS controller to reduce the frequency of the core where Ti is located to the new frequency Monitor the processor load simultaneously: If multiple cores are idle for a long time: Migrate tasks on lightly loaded cores to other cores, And shut down the idle cores or set them to low power mode Execute all tasks at the adjusted frequency The scheduling method in the present disclosure dynamically analyzes the DAG structure through the above steps, recycles the flexible time on the non-critical path, and adjusts the frequency in combination with DVFS, and finally realizes the reduction of the power consumption of the system while meeting the real-time deadline requirement. In combination with the mapping of the task to the core, it can be seen that the present strategy preferentially uses the most necessary hardware resources during execution, and timely closes the idle core, which embodies the scheduling characteristics of high efficiency and energy saving, and solves the problem that the existing technical solutions cannot simultaneously utilize the dynamic flexible space of the non-critical path and realize real-time scheduling in combination with the DVFS frequency adjustment and idle core merging, and reduce the energy consumption while guaranteeing the SLA (Service Level Agreement) requirement.

[0047] In combination Figure 4 As shown in the accompanying drawings, the present disclosure further provides a DAG task energy-saving scheduling device 400, which comprises a processor 404 and a memory 401. Optionally, the system can further comprise a communication interface 402 and a bus 403. The processor 404, the communication interface 402 and the memory 401 can complete mutual communication through the bus 403. The communication interface 402 can be used for information transmission. The processor 404 can invoke the logical instructions in the memory 401 to execute the DAG task energy-saving scheduling method of the above-mentioned embodiments.

[0048] In addition, the logical instructions in the above-mentioned memory 401 can be realized in the form of a software functional unit and sold or used as an independent product, which can be stored in a computer readable storage medium.

[0049] The memory 401 as a kind of computer readable storage medium can be used to store software programs, computer executable programs, such as the program instructions / modules corresponding to the method in the embodiments of the present disclosure. The processor 404 executes the program instructions / modules stored in the memory 401, thereby executing function application and data processing, i.e. realizing the DAG task energy-saving scheduling method in the above-mentioned embodiments.

[0050] The memory 401 can include a program storage area and a data storage area, wherein the program storage area can store an operating system, at least one application required by a function; the data storage area can store data created according to the use of the terminal device, etc. In addition, the memory 401 can include a high-speed random access memory, and can also include a non-volatile memory.

[0051] The present disclosure provides a computer readable storage medium, which stores computer executable instructions, and the computer executable instructions are set as the DAG task energy-saving scheduling method.

[0052] The computer readable storage medium described above can be a transitory computer readable storage medium or a non-transitory computer readable storage medium.

[0053] The technical solutions of the embodiments of the present disclosure can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes one or more instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method of the embodiments of the present disclosure. The aforementioned storage medium can be a non-transitory storage medium, including a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes, or can be a transitory storage medium.

[0054] The above description and drawings sufficiently illustrate the embodiments of the present disclosure to enable one skilled in the art to practice them. Other embodiments can include structural, logical, electrical, process, and other changes. The embodiments represent only a few of the possible variations. Individual components and functions are optional unless explicitly required, and the order of operations can be changed. Parts and features of some embodiments can be included in or replace parts and features of other embodiments. As used in the description of the embodiments, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Similarly, as used in this application, the term "and / or" refers to any and all possible combinations of one or more associated listed items. In addition, when used in this application, the term "comprise" and its variants "comprises" and / or comprises" and the like mean the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Without more limitations, the element defined by the phrase "comprising a" does not exclude the presence of additional identical elements in the process, method, or device that includes the element. In this document, each embodiment focuses on the differences from other embodiments, and the same or similar parts between various embodiments can be referred to each other. For the method, product, etc. disclosed by the embodiments, if it corresponds to the method part disclosed by the embodiments, the relevant part can be referred to the description of the method part.

[0055] Those skilled in the art can understand that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software manner can depend on specific application and design constraints of the technical solutions. Those skilled in the art can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of the present disclosure. Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be repeated here.

[0056] In the embodiments disclosed herein, the disclosed methods, products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the above-described device embodiments are merely illustrative, for example, the division of units can be merely a logical function division, and actual implementation can have another division manner, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed units can be indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms. The units described as separate components can or can not be physically separated, and the components displayed as units can or can not be physical units, that is, they can be located in one place, or can be distributed on multiple network units. Part or all of the units can be selected according to actual needs to implement the embodiments. In addition, the functional units in the embodiments of the present disclosure can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit.

[0057] The computer program instructions can also be loaded onto a computer or other programmable apparatus to cause a series of operations to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus implement the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0058] The various embodiments of the systems and techniques described above can be implemented in digital electronic circuitry, integrated circuitry, a field programmable gate array (FPGA), a custom integrated circuit (ASIC), a special-purpose standard product (ASSP), a system-on-a-chip system (SOC), a loadable programmable logic device (CPLD), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include implementation in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0059] Program code for carrying out methods of the present disclosure can be written in any combination of one or more programming languages. This program code can be provided to a processor or controller of a general or special purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the program code, when executed by the processor or controller, implements the functions / acts specified in the flowchart and / or block diagram block or blocks. The program code can be executed entirely on a machine, partially on a machine, partially on a machine as a stand-alone software package, partially on a machine and partially on a remote machine or entirely on a remote machine or server.

[0060] In the context of this disclosure, a machine-readable medium can be a tangible medium that contains or stores a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include but is not limited to an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of the machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0061] To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.

[0062] The systems and techniques described here can be implemented in a computing system that includes a back end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front end component (e.g., a user computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0063] The computer system can include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server can arise by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0064] It should be understood that the various forms of flow shown above can be used to reorder, add, or delete steps. For example, the steps described in the present disclosure can be performed in parallel, in series, or in a different order, as long as the desired results of the technical solutions of the present disclosure can be achieved, which are not limited herein.

[0065] The above detailed description does not constitute a limitation on the protection scope of the present disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A DAG task energy-saving scheduling method, characterized in that, The method is applied to a heterogeneous multi-core processor platform, and the method comprises: receiving a DAG task with a deadline constraint, and performing topological sorting and critical path analysis to determine critical path tasks and non-critical path tasks; calculating and allocating dynamic elastic time for the non-critical path tasks; proportionally reducing the working frequency and voltage of the processor core where the non-critical path tasks are located according to the dynamic elastic time allocated to the non-critical path tasks; monitoring the load state of each processor core during task execution, and triggering an idle core merging strategy when it is detected that multiple processor cores are in an idle or low load state, migrating tasks to be executed on a part of active cores, and shutting down or reducing the power consumption of the remaining idle cores.

2. The method of claim 1, wherein, The method further comprises: calculating the earliest start time and the latest completion time of each non-critical path task; calculating the initial elastic time of each non-critical path task based on the earliest start time and the latest completion time; allocating the total elastic time on the non-critical path to each task on the path according to a predetermined strategy.

3. The method of claim 2, wherein, The predetermined strategy is a uniform allocation strategy.

4. The method of claim 1, wherein, After proportionally reducing the working frequency and voltage of the processor core where the non-critical path tasks are located, the method further comprises calculating a new frequency that satisfies the formula: New frequency = original frequency × (worst-case execution time of the task / (worst-case execution time of the task + allocated dynamic elastic time)).

5. The method of claim 1, wherein, In the task mapping stage, the critical path tasks are mapped to the processor cores running in the target high-frequency interval for execution, and the non-critical path tasks allocated with dynamic elastic time are mapped to the processor cores with reduced frequency for execution.

6. The method of claim 1, wherein, The idle core merging strategy is triggered dynamically online, and the triggering condition is that multiple processor cores are continuously in an idle or low load state below a preset threshold within a target time period.

7. The method of claim 1, wherein, When reducing the working frequency of the processor core, the method synchronously reduces the working voltage of the processor core through a dynamic voltage and frequency adjustment technology.

8. The method of claim 1, wherein, The processor cores in the heterogeneous multi-core processor platform support multi-level dynamic voltage and frequency adjustment.

9. An electronic device, comprising: comprise: at least one processor; and a memory connected in communication with the at least one processor; The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-8.

10. A non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable the computer to perform the method of any one of claims 1-8.

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