Storage device configured to write data based on write energy and operating method thereof

Abstract

A storage device is provided. The memory device includes a nonvolatile memory device including a memory cell array having a user area and a power-off protection (PLP) area; and a memory controller configured to write the first PLP data into a first memory cell connected to the first word line of the PLP region and write the second PLP data into a second memory cell connected to the second word line of the PLP region based on the detection of the sudden power failure. The first write energy of the first memory cell is less than the second write energy of the second memory cell.

Description

Cross-reference to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0136104, filed on October 7, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to a storage device, and more specifically, to a storage device that efficiently stores data in response to a sudden power outage. Background Technology

[0003] Semiconductor memories are divided into volatile memory devices and non-volatile memory devices. Volatile memory devices lose the data stored in them when power is turned off, such as static random access memory (SRAM) or dynamic RAM (DRAM). Non-volatile memory devices can retain the data stored in them when power is turned off, such as flash memory, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), or ferroelectric RAM (FRAM).

[0004] Storage devices such as solid-state drives (SSDs) may include non-volatile storage devices (such as flash memory) for semi-permanently storing data, and may also include volatile storage devices (such as DRAM) for temporarily storing data read from or to be written to the non-volatile storage devices. Furthermore, supercapacitors present in the SSD can serve as a power source to store power-loss protected (PLP) data being processed in the DRAM when the SSD is powered off.

[0005] However, with the increasing volume of data that needs to be urgently stored in SSDs in the event of a sudden power outage, methods for efficiently utilizing the limited power of supercapacitors are becoming increasingly important, given the growing demand for high-capacity storage devices such as SSDs. Summary of the Invention

[0006] One or more embodiments provide a method for efficiently writing power-loss protection (PLP) data being processed based on write energy in the event of a sudden power outage.

[0007] One or more embodiments provide a method for efficiently writing user data based on write energy.

[0008] According to one aspect of an embodiment, a storage device includes: a non-volatile storage device including a memory cell array having a user region and a PLP region; and a storage controller configured to, based on the detection of a sudden power failure, write first PLP data into a first memory cell of the PLP region connected to a first word line, and write second PLP data into a second memory cell of the PLP region connected to a second word line. The first write energy of the first memory cell is less than the second write energy of the second memory cell.

[0009] According to another aspect of the embodiments, a storage device includes: a non-volatile storage device including a memory cell array, the memory cell array including a user area and a PLP area; a storage controller configured to, based on the detection of a sudden power failure, write first PLP data to a first memory cell in the PLP area connected to a first word line, write virtual data to a second memory cell in the PLP area connected to a second word line, and write second PLP data to a third memory cell in the PLP area connected to a third word line, the third word line being adjacent to the second word line and having a second write energy. The second word line is adjacent to each of the first and third word lines. The first write energy of the first memory cell is less than the second write energy of the second memory cell.

[0010] According to another aspect of the embodiments, a storage device includes: a non-volatile storage device including a memory cell array comprising a plurality of cell strings extending in a direction perpendicular to a substrate, wherein each of the plurality of cell strings includes at least one string select transistor, a plurality of memory cells connected in series, and at least one ground select transistor; and a storage controller configured to write first user data to a first memory cell among the plurality of memory cells, and to write second user data to a second memory cell among the plurality of memory cells. A first write energy to the first memory cell is less than a second write energy to the second memory cell. Attached Figure Description

[0011] The above and other objects and features will become more apparent from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 This is a block diagram of a storage system according to an embodiment.

[0013] Figure 2 The configuration of the storage controller according to an embodiment is shown.

[0014] Figure 3 This is a block diagram illustrating a non-volatile storage device according to an embodiment.

[0015] Figure 4 An example of a storage block according to an embodiment is shown.

[0016] Figure 5 This is a cross-sectional view showing an example of a cell string of a storage block according to an embodiment.

[0017] Figure 6 This is a flowchart illustrating an operation method of a storage device according to an embodiment.

[0018] Figure 7 This is a conceptual block diagram illustrating low-power writing of a storage device according to an embodiment.

[0019] Figure 8 This is a diagram illustrating the threshold voltage distribution of the memory cells in the power-loss protection (PLP) region according to an embodiment.

[0020] Figure 9 This is a diagram used to describe the programming operations of the storage cells for the PLP region according to an embodiment.

[0021] Figure 10 The conceptual illustration shows programming operations performed on a specific memory cell of a PLP region according to an embodiment.

[0022] Figure 11 The conceptual illustration shows programming operations performed on a specific memory cell of a PLP region according to an embodiment.

[0023] Figure 12 This is a diagram illustrating the programming characteristics according to the size of the channel aperture, based on an embodiment.

[0024] Figure 13 This is a diagram illustrating the programming characteristics based on the shape of the channel hole according to an embodiment.

[0025] Figure 14 This is a flowchart illustrating an operation method of a storage device according to an embodiment.

[0026] Figure 15 An example of PLP writing according to an embodiment is shown.

[0027] Figure 16 This is a flowchart illustrating an operation method of a storage device according to an embodiment.

[0028] Figure 17 An example of PLP writing according to an embodiment is shown.

[0029] Figure 18 This is a flowchart illustrating an operation method of a storage device according to an embodiment.

[0030] Figure 19 An example of PLP writing according to an embodiment is shown.

[0031] Figure 20This is a flowchart illustrating an operation method of a storage device according to an embodiment.

[0032] Figure 21 An example of PLP writing according to an embodiment is shown.

[0033] Figure 22 Another example of PLP writing according to an embodiment is shown.

[0034] Figure 23 This is a flowchart illustrating an operation method of a storage device according to an embodiment.

[0035] Figure 24 This is a diagram showing the threshold voltage distribution of memory cells in a normal region according to an embodiment.

[0036] Figure 25 This is a diagram used to describe programming operations for storage cells in the normal area according to an embodiment.

[0037] Figure 26 The conceptual illustration shows programming operations performed on a specific memory cell in a normal region according to an embodiment.

[0038] Figure 27 The conceptual illustration shows programming operations performed on a specific memory cell in a normal region according to an embodiment.

[0039] Figure 28 This is a flowchart illustrating an operation method of a storage device according to an embodiment.

[0040] Figure 29 This is a cross-sectional view of a storage device according to an embodiment. Detailed Implementation

[0041] The embodiments will now be described in detail with reference to the accompanying drawings. Throughout this specification, similar components are indicated by similar reference numerals, and repeated descriptions thereof are omitted. It will be understood that when an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it may be directly on, directly connected to, or coupled to that other element or layer, or there may be intermediate elements or layers present. Conversely, when an element is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intermediate elements or layers present. The embodiments described herein are exemplary embodiments, and therefore, this disclosure is not limited thereto, and may be implemented in various other forms. Each exemplary embodiment provided in the following description does not exclude association with one or more features of another example or another example embodiment, whether also provided or not herein but consistent with this disclosure.

[0042] In the detailed description, the components described by reference to terms such as “unit,” “module,” “block,” “device,” etc., and the functional blocks shown in the accompanying drawings, will be implemented in hardware. For example, the hardware may include circuits, electronic circuits, processors, computers, integrated circuits, integrated circuit cores, pressure sensors, inertial sensors, microelectromechanical systems (MEMS), passive components, or combinations thereof.

[0043] Figure 1 This is a block diagram of a storage system according to an embodiment.

[0044] refer to Figure 1 The storage system 10 may include a host device 100 and a storage device 1000. In embodiments, the storage system 10 may be implemented using a computing system configured to process various types of information, such as a personal computer (PC), a laptop computer, a desktop computer, a server, a workstation, a tablet PC, a smartphone, a digital camera, and a black box.

[0045] Host device 100 can store data in storage device 1000, or can read data stored in storage device 1000. For example, host device 100 can send a write command and write data to storage device 1000 to store data in storage device 1000. Alternatively, in order to read data stored in storage device 1000, host device 100 can send a read command to storage device 1000 and receive data from storage device 1000.

[0046] Storage device 1000 may include storage controller 1100 and non-volatile storage device 1200. Storage device 1000 can operate according to requests from host device 100. Storage controller 1100 can operate in response to commands received from host device 100. For example, storage controller 1100 can receive write commands and write data from host device 100, and in response to the received write command, store the write data in non-volatile storage device 1200. Storage controller 1100 can receive read commands from host device 100, and in response to the received read commands, read data stored in non-volatile storage device 1200. Storage controller 1100 can send the read data to host device 100.

[0047] The storage controller 1100 can control the low-energy write manager 1170. The low-energy write manager 1170 can manage the non-volatile storage device 1200, enabling programming operations to be performed on storage cells with low write energy. In embodiments, the low-energy write manager 1170 can be understood as a component of the storage controller 1100, or as a component including instructions (e.g., firmware) loaded into and driven by the storage controller 1100's internal or external memory.

[0048] In this embodiment, the low-energy write manager 1170 can allow the storage device 1000 to operate in a low-energy write mode. For example, when a sudden power outage (SPO) occurs, the low-energy write mode can be activated, and the low-energy write manager 1170 can control the non-volatile storage device 1200 such that the power-loss protected (PLP) data being processed by the storage controller 1100 is stored in the storage cells of the PLP region 1210a that have (i.e., correspond to) low write energy. The sudden power outage can correspond to an unexpected power failure during the operation of the storage device 1000.

[0049] In an embodiment, during a normal write operation, the low-energy write manager 1170 can control the non-volatile storage device 1200 such that the write data requested by the host device 100 is stored in a storage cell with (i.e., corresponding to) low write energy in the storage cell of the normal region 1210b.

[0050] In an embodiment, the non-volatile storage device 1200 may include a NAND flash memory device. For example, the PLP region 1210a may be implemented using a single-level cell (SLC) storing 1 bit, and the normal region 1210b may be implemented using at least one of a multi-level cell (MLC) storing 2 bits, a three-level cell (TLC) storing 3 bits, a four-level cell (QLC) storing 4 bits, or a cell storing 5 bits or more.

[0051] Figure 2 It shows Figure 1 The configuration of the storage controller is used as an example.

[0052] The storage controller 1100 includes at least one processor 1110, an internal buffer 1120, an error checking and correction (ECC) engine 1130, a host interface circuit 1140, a buffer controller 1150, and a memory interface (I / F) circuit 1160.

[0053] Processor 1110 controls all operations of memory controller 1100. Processor 1110 can drive various operating systems, firmware, software, etc., required to control non-volatile memory device 1200. For example, processor 1110 can drive a flash translation layer for managing a mapping table that defines the non-volatile memory device 1200 and a reference... Figure 1 Describes the relationship between the logical and physical addresses of the low-energy write manager 1170.

[0054] Processor 1110 may store requests received from host device 100 in internal buffer 1120. Processor 1110 may generate addresses and commands for controlling non-volatile storage device 1200 based on the received requests. Processor 1110 may store various data for managing storage device 1000 in internal buffer 1120. For example, internal buffer 1120 may include static random access memory (SRAM) and / or dynamic random access memory (DRAM).

[0055] ECC engine 1130 can generate error correction codes (ECCs) for write data to be stored in non-volatile storage device 1200, and can perform error correction encoding by using the ECCs. ECC engine 1130 can perform error correction decoding on read data read from non-volatile storage device 1200 by using the ECCs.

[0056] The host interface circuit 1140 can communicate with the host device 100 using a bus with a bus format corresponding to various communication protocols. For example, the bus format can correspond to one or more of various interface protocols, such as Universal Serial Bus (USB), Small Computer System Interface (SCSI), Peripheral Component Rapid Interconnect (PCIe), Mobile PCIe (M-PCIe), Advanced Technology Attachment (ATA), Parallel ATA (PATA), Serial ATA (SATA), Serial Attached SCSI (SAS), Integrated Drive Electronics (IDE), Enhanced IDE (EIDE), Non-Volatile Fast Memory (NVMe), and Universal Flash Memory (UFS).

[0057] Buffer controller 1150 can provide an interface connection between storage controller 1100 and buffers (e.g., random access memory (RAM)). Buffer controller 1150 can access the buffer upon request from processor 1110 or any other intellectual property (IP). For example, the IP may include circuitry for performing specific functions and may have designs that include trade secrets. For example, under the control of processor 1110, buffer controller 1150 may temporarily record write data to be stored in non-volatile memory device 1200 and / or read data read from non-volatile memory device 1200 in the buffer.

[0058] The memory interface circuit 1160 can communicate with the non-volatile memory device 1200. For example, the memory interface circuit 1160 can access the non-volatile memory device 1200 through various signal lines. The memory interface circuit 1160 can communicate with the non-volatile memory device 1200 based on protocols defined according to standards or by the manufacturer.

[0059] Figure 3This is a block diagram illustrating a non-volatile storage device 1200 according to an embodiment.

[0060] refer to Figure 3 The non-volatile storage device 1200 may include a storage cell array 1210, a row decoder 1220, a page buffer 1230, an input / output (I / O) circuit 1240, a buffer circuit 1250, and a control logic circuit 1260.

[0061] Memory cell array 1210 includes multiple memory blocks BLK1 to BLKz. Each memory block BLK1 to BLKz includes multiple memory cells. Each memory block BLK1 to BLKz can be connected to line decoder 1220 via at least one ground select line GSL, one word line WL, and at least one string select line SSL. Some word lines in the word line WL can be used as dummy word lines. Each memory block BLK1 to BLKz can be connected to page buffer 1230 via multiple bit lines BL. Multiple memory blocks BLK1 to BLKz can be jointly connected to multiple bit lines BL.

[0062] In this embodiment, each of the plurality of storage blocks BLK1 to BLKz can correspond to a unit of erase operation. Storage cells belonging to each storage block can be erased simultaneously. As another example, each of the storage blocks BLK1 to BLKz can be divided into multiple sub-blocks. Each of the multiple sub-blocks can correspond to a unit of erase operation.

[0063] In an embodiment, at least some of the multiple storage blocks BLK1 to BLKz (e.g., BLK1) may be storage blocks belonging to PLP region 1210a, and at least some of the multiple storage blocks BLK1 to BLKz may be storage blocks belonging to normal region 1210b.

[0064] The line decoder 1220 can be connected to the memory cell array 1210 via the ground select line GSL, the word line WL, and the serial select line SSL. The line decoder 1220 operates under the control of the control logic circuit 1260.

[0065] The row decoder 1220 can decode the row address RA received from the buffer circuit 1250 and can control the voltage applied to the serial select line SSL, word line WL and ground select line GSL based on the decoded row address.

[0066] Page buffer 1230 can be connected to memory cell array 1210 via multiple bit lines BL. Page buffer 1230 can be connected to input / output circuit 1240 via multiple data lines DL. Page buffer 1230 operates under the control of control logic circuit 1260.

[0067] During a write operation, page buffer 1230 can store data to be written to the memory cell. Page buffer 1230 can apply voltages to multiple bit lines BL based on the stored data. During a read operation or a verification read operation (performed during a write or erase operation), page buffer 1230 can sense the voltage of the bit lines BL and store the sensed result.

[0068] Input / output circuit 1240 can be connected to page buffer 1230 via multiple data lines DL. Input / output circuit 1240 can receive column address CA from buffer circuit 1250. Input / output circuit 1240 can output data read from page buffer 1230 to buffer circuit 1250 according to column address CA. Input / output circuit 1240 can transfer data received from buffer circuit 1250 to page buffer 1230 according to column address CA.

[0069] Buffer circuit 1250 can be controlled from memory controller 1100 (reference) Figure 1 The buffer circuit 1250 receives the command CMD and the address ADDR. The buffer circuit 1250 operates under the control of the control logic circuit 1260. The buffer circuit 1250 can transmit the command CMD to the control logic circuit 1260. The buffer circuit 1250 can transmit the row address RA of the address ADDR to the row decoder 1220, and can transmit the column address CA of the address ADDR to the input / output circuit 1240. The buffer circuit 1250 can exchange data "DATA" with the input / output circuit 1240.

[0070] The control logic circuit 1260 can be controlled from the memory controller 1100 (reference). Figure 1 The control logic circuit 1260 receives the control signal CTRL. The control logic circuit 1260 can enable the buffer circuit 1250 to route the command CMD, the address ADDR, and the data "DATA".

[0071] The control logic circuit 1260 can decode the command CMD received from the buffer circuit 1250, and can control the non-volatile storage device 1200 according to the decoded command.

[0072] Figure 4 An example of storage block BLK1 according to an embodiment is shown.

[0073] refer to Figure 4 Multiple cell strings (CS) can be arranged in rows and columns on the substrate SUB along a first direction, a second direction, and a third direction. Multiple cell strings (CS) can be collectively connected to a common source line (CSL) formed on (or within) the substrate SUB. Figure 4 In order to better understand the structure of the memory block BLK1, the location of the substrate SUB is described as an example.

[0074] The cell strings in each row can be connected to the ground select line GSL, and can also be connected to the corresponding upper select lines from the first upper select line SSLu1 to the fourth upper select line SSLu4, and the corresponding lower select lines from the first lower select line SSLl1 to the fourth lower select line SSLl4. The cell strings in each column can be connected to the corresponding bit lines from the first bit line BL1 to the fourth bit line BL4. To avoid overly complex drawing, the cell strings connected to the second and third select lines SSL2l, SSL2u, SSL3l, and SSL3u are displayed in a blurred manner.

[0075] Each cell string may include: at least one ground select transistor GST connected to the ground select line GSL; a first dummy memory cell DMC1 connected to the first dummy word line DWL1; first memory cells MC1 to tenth memory cells MC10 connected to the first word line WL1 to the cross line WL10 respectively; a second dummy memory cell DMC2 connected to the second dummy word line DWL2; and an upper string select transistor SSTu and a lower string select transistor SST1 connected to the corresponding upper string select line and lower string select line respectively.

[0076] In each cell string CS, the ground selection transistor GST, the first dummy memory cell DMC1, the first memory cells MC1 to the tenth memory cells MC10, the second dummy memory cell DMC2, the upper string selection transistor SSTu, and the lower string selection transistor SST1 can be connected in series and can be stacked sequentially along a third direction perpendicular to the substrate SUB.

[0077] The memory block BLK1 is configured as a three-dimensional (3D) memory array. The 3D memory array is monolithically formed in one or more physical layers of an array of memory cells MCs, each MC having active regions disposed on a silicon substrate and circuitry associated with the operation of those memory cells MCs. The circuitry associated with the operation of the memory cells MCs may be located above or within the substrate. The term "monolithic" indicates that each layer of the 3D array is deposited directly on top of the layer of each layer below it in the 3D memory array.

[0078] As an example, a 3D memory array includes vertical cell strings (or NAND strings) that are vertically oriented such that at least one memory cell is positioned above another. At least one memory cell may include a charge trapping layer. Each cell string also includes at least one selection transistor disposed on the memory cell MC. The at least one selection transistor may have the same structure as the memory cell MC and may be formed consistent with the memory cell MC.

[0079] Figure 5 It shows Figure 4A cross-sectional view of example cell strings CS of memory block BLK1, which correspond to the second bit line BL2 and the third bit line BL3. (Reference) Figure 4 and Figure 5 It is provided with a common source pole region (CSR) that extends along a first direction and is spaced apart from each other along a second direction.

[0080] The common source regions (CSRs) can be interconnected to form a common source line (CSL). In this embodiment, the substrate 101 may include a P-type semiconductor material. The common source regions (CSRs) may include an N-type semiconductor material. For example, a conductive material may be disposed on the common source regions (CSRs) to improve the conductivity of the common source line (CSL).

[0081] Pillars PL can be provided between the common source regions CSR, perpendicular to the substrate 101 in a third direction. Each pillar PL may include an internal material 114, a channel layer 115, and a first insulating layer 116.

[0082] The internal material 114 may include an insulating material or an air gap. The channel layer 115 may include a P-type semiconductor material or an intrinsic semiconductor material. The first insulating layer 116 may include one or more insulating layers (e.g., different insulating layers), such as a silicon oxide layer, a silicon nitride layer, and an aluminum oxide layer.

[0083] The insulating layer 112 and conductive materials CM1 to CM15 may be alternately stacked on the substrate 101 along a third direction perpendicular to the substrate 101 and may surround the pillar PL. In an embodiment, the insulating layer 112 may include silicon oxide or silicon nitride.

[0084] The second insulating layer 117 may be located between the pillar PL and the conductive materials CM1 to CM15, and between the conductive materials CM1 to CM15 and the insulating layer 112. In each pillar PL, the first insulating layer 116 and the second insulating layer 117 can form an information storage layer when they are coupled adjacent to each other. For example, the first insulating layer 116 and the second insulating layer 117 may comprise oxide-nitride-oxide (ONO) or oxide-nitride-aluminum (ONA). The first insulating layer 116 and the second insulating layer 117 may form a tunneling insulating layer, a charge trapping layer, and a barrier insulating layer.

[0085] Bit line contact 118 may be disposed on post PL. In an embodiment, bit line contact 118 may comprise an N-type semiconductor material (e.g., silicon). Bit lines BL2 and BL3, extending in a second direction and spaced apart from each other in a first direction, are disposed on bit line contact 118. Bit lines BL2 and BL3 may be connected to bit line contact 118.

[0086] The pillar PL, together with the first insulating layer 116 and the second insulating layer 117 and the conductive materials CM1 to CM15, forms a cell string CS. Each pillar PL, together with the adjacent first insulating layer 116 and the second insulating layer 117 and the conductive materials CM1 to CM15, forms a cell string. The first conductive material CM1 may form a ground selection transistor GST together with the adjacent first insulating layer 116, the second insulating layer 117 and the channel layer 115. The first conductive material CM1 may extend along a first direction to form a ground selection line GSL.

[0087] The second conductive material CM2, together with the adjacent first insulating layer 116, second insulating layer 117, and channel layer 115, can form a first dummy memory cell DMC1. The second conductive material CM2 can extend along a first direction to form a first dummy word line DWL1.

[0088] The third conductive material CM3 to the twelfth conductive material CM12 can, together with the adjacent first insulating layer 116, second insulating layer 117 and channel layer 115, form the first memory cell MC1 to the tenth memory cell MC10. The third conductive material CM3 to the twelfth conductive material CM12 can extend along a first direction to form the first word line WL1 to the cross line WL10.

[0089] The thirteenth conductive material CM13, together with the adjacent first insulating layer 116, second insulating layer 117, and channel layer 115, can form a second dummy memory cell DMC2. The thirteenth conductive material CM13 can extend along a first direction to form a second dummy word line DWL2.

[0090] The fourteenth conductive material CM14 and the fifteenth conductive material CM15, together with the adjacent first insulating layer 116, second insulating layer 117, and channel layer 115, can form a lower string select transistor SST1 and an upper string select transistor SSTu. The fourteenth conductive material CM14 and the fifteenth conductive material CM15 can extend along a first direction to form a lower string select line and an upper string select line.

[0091] like Figure 5 As shown, each pillar PL may include a first portion adjacent to the substrate 101 and a second portion located on the first portion. Due to the manufacturing process of non-volatile memory devices (e.g., flash memory devices), in the first portion corresponding to the first conductive material CM1 to the seventh conductive material CM7, the width or cross-sectional area of ​​the pillar PL may decrease as the distance from the substrate 101 decreases, and may increase as the distance from the substrate 101 increases.

[0092] Similarly, in the second part corresponding to the eighth conductive material CM8 to the fifteenth conductive material CM15, the width or cross-sectional area of ​​the pillar PL can decrease as the distance from the substrate 101 decreases, and can increase as the distance from the substrate 101 increases.

[0093] Figure 6 This is a flowchart illustrating an operation method of a storage device 1000 according to an embodiment.

[0094] Let's refer to each other. Figure 1 , Figure 2 and Figure 6 In operation S110, the storage controller 1100 can detect sudden power failures. For example, a sudden power failure can be detected by monitoring power supply stability.

[0095] In the event of a sudden power outage, the storage controller 1100 can store the data being processed (i.e., PLP data) stored in the buffer or internal buffer 1120 in the PLP area 1210a; this is referred to as PLP writing or PLP programming. Specifically, PLP writing is for subsequent processing of data that has not yet been processed due to a sudden interruption of external power. In an embodiment, the power for PLP writing can be provided by a supercapacitor located within the storage device.

[0096] In operation S120, the storage controller 1100 can write PLP data to a first storage cell that has (i.e., corresponds to) a first write energy and is connected to a first word line. That is, the first write energy can indicate the energy required to program data into a storage cell (i.e., the first storage cell) connected to the first word line. However, in another embodiment, the first write energy can indicate the energy required to program multiple storage cells connected to a word line.

[0097] In operation S130, the storage controller 1100 may write PLP data to a second storage cell having (i.e., corresponding to) a second write energy and connected to a second word line. Similarly, the second write energy may indicate the energy required to program data into a storage cell (i.e., the second storage cell) connected to the second word line. However, in another embodiment, the second write energy may indicate the energy required to program multiple storage cells connected to a word line. In an embodiment, the second word line may be a word line not adjacent to the first word line. However, the embodiment is not limited to this. For example, the second word line may be a word line adjacent to the first word line. In an embodiment, the value of the second write energy may be greater than the value of the first write energy.

[0098] The first and second write energies mentioned above may not indicate the actual energy required to program the memory cell. That is, the memory manufacturer may set a specific reference value; in this case, when the energy required to program the memory cell is less than that reference value, the corresponding memory cell can be considered to have (i.e., correspond to) the first write energy. Conversely, when the energy required to program the memory cell is equal to or greater than that reference value, the corresponding memory cell can be considered to have (i.e., correspond to) the second write energy.

[0099] The write energy required to program each memory cell in PLP region 1210a can vary due to various factors, such as the location of the memory cell, its programming characteristics, and its manufacturing process. According to an embodiment, in the event of a sudden power outage, PLP writing can proceed sequentially from memory cells with lower write energy to those with higher write energy. Accordingly, the limited energy of the supercapacitor can be utilized efficiently, and the PLP writing time can be shortened. The factors determining the write energy values ​​and the PLP writing strategy according to the embodiment will be described in detail later.

[0100] Figure 7 This is a conceptual block diagram illustrating low-power writing of a storage device 1000 according to an embodiment.

[0101] When storage device 1000 is operational, storage controller 1100 can load word line tables stored in the meta region of non-volatile storage device 1200 into buffer 1300. In an embodiment, the meta region may indicate a region in the storage space of non-volatile storage device 1200 that is not allocated to users. As a contrasting concept, normal region 1210b may indicate an area where user data is stored. In an embodiment, PLP region 1210a may be part of the meta region. However, the embodiment is not limited thereto. For example, PLP region 1210a may be included in an over-provisioning (OP) region independent of the meta region and normal region 1210b.

[0102] In this embodiment, the word line table may include write energy information for the memory cells in the PLP region 1210a. Specifically, the word line table may include the logical address of the memory cell and information about whether normal write energy NE or low write energy LE is required to program the memory cell.

[0103] However, from the perspective of efficiently utilizing the limited energy stored in supercapacitors, managing the write energy of each of all memory cells using a table might be ideal. However, since managing write energy information about all memory cells is inefficient, managing write energy information on a word-line basis might be more efficient.

[0104] Furthermore, memory cells connected to the same word line typically have similar characteristics. For example, if any memory cell connected to a word line has low write power, then most memory cells connected to that word line are also likely to have low write power. Accordingly, such as Figure 7 As shown in the word line table, write energy (i.e., normal write energy (NE) information or low write energy (LE) information) can be managed in units of word lines, which is more efficient.

[0105] After the word line table is loaded into buffer 1300, storage controller 1100 can perform various processes on the data stored in buffer 1300. However, if a sudden power failure occurs before data processing is complete, at least a portion of the data being processed (i.e., the data stored in buffer 1300) may be PLP data, which should be stored in PLP area 1210a.

[0106] The storage controller 1100 can determine the logical address of the target word line for PLP writing by referring to the word line table loaded into the buffer 1300. The flash translation layer can translate the logical address of the target word line for PLP writing into a physical address. The storage controller 1100 can perform PLP writing on memory cells with word lines having (i.e., corresponding to) low write energy LE (e.g., WL12 to WL47 and WL60 to WL84) among the word lines connected to the first storage block BLK1.

[0107] In this embodiment, a normal write command or a separate command (e.g., a vendor-specific command) can be used to perform a PLP write. For example, when a sudden power outage occurs in low-energy write mode, the PLP write can be performed according to the write command or a separate command. However, the embodiment is not limited to this. For example, regardless of the operating mode, the PLP write operation described above can be performed as the default operation when a sudden power outage occurs.

[0108] As described above, the word line table can be loaded into buffer 1300 before a sudden power outage occurs. However, in another embodiment, when a sudden power outage occurs, the storage controller 1100 can read the word line table stored in the meta-region using energy stored in a supercapacitor to load it into buffer 1300. The storage controller 1100 can then perform a PLP write based on the read word line table.

[0109] According to the above method, since PLP writing is performed on memory cells with (i.e., corresponding to) low write energy, the limited energy of the supercapacitor can be utilized efficiently, and the PLP writing time can also be shortened.

[0110] After the sudden power outage ends (i.e., after power is restored to the storage device), the storage controller 1100 can read the PLP data present in the PLP area 1210a and store it in the buffer 1300. The storage controller 1100 can also complete the processing of the PLP data that was suspended due to the sudden power outage.

[0111] Figure 8 It shows Figure 7 A graph showing the threshold voltage distribution of memory cells in PLP region 1210a. Figure 8 In the distribution diagram, the horizontal axis represents the threshold voltage of the memory cell, and the vertical axis represents the number of memory cells.

[0112] refer to Figure 3 and Figure 8 The non-volatile storage device 1200 can program PLP data into the storage cells by controlling the threshold voltage of the storage cells in the storage block BLK1 of the PLP region 1210a. For example, the storage cells can be programmed to have either an erase state "E" or a programmable state "P".

[0113] The non-volatile storage device 1200 can verify the programming state of the memory cell based on a verification voltage Vvfy. For example, the non-volatile storage device 1200 can verify whether the memory cell corresponding to the programming state "P" is properly programmed by using the verification voltage Vvfy. The non-volatile storage device 1200 can read the data stored in the memory cell by sensing the programming state (i.e., the threshold voltage) of the memory cell.

[0114] Figure 9 It is used to describe Figure 7 A diagram showing the programming operations of the storage unit in PLP area 1210a. Figure 9 In the embodiments described, the programming operations may be associated with the programming characteristics (i.e., low write energy LE or normal write energy NE) of each word line during the testing phase of the non-volatile memory device 1200.

[0115] In an embodiment, the non-volatile storage device 1200 according to the embodiment can program the memory cells of the PLP region 1210a by sequentially executing multiple programming cycles based on incremental step pulse programming (ISPP).

[0116] refer to Figure 9The non-volatile memory device 1200 can perform programming operations through multiple programming cycles PL1 to PLk. Each of the multiple programming cycles PL1 to PLk may include a programming phase and a verification phase. The programming phase may include applying a programming voltage (e.g., each of Vpgm1 to Vpgmk) to a selected word line. The verification phase may include applying a verification voltage Vvfy to a selected word line.

[0117] In the first programming cycle PL1, a first programming voltage Vpgm1 can be applied to the memory cells connected to the selected word line that are to be programmed to the programming state "P", and a verification voltage Vvfy can be applied to verify whether these memory cells have been successfully programmed. Memory cells that have been successfully programmed (i.e., disabled cells) can be disabled for programming in the next programming cycle.

[0118] In the second programming cycle PL2, the second programming voltage Vpgm2 can be applied to the memory cells (instead of the disabled cells) in the remaining memory cells of the selected word line that are to be programmed to the programming state "P", and a verification voltage Vvfy can be applied to them to verify whether these memory cells have been successfully programmed.

[0119] By repeating programming loops PLk-1 and PLk similar to those described above, the programming of the selected memory unit can be completed.

[0120] Figure 10 The concept illustrates the PLP region 1210a (reference). Figure 7 Programming operations performed on specific memory units. Figure 11 The concept illustrates the PLP region 1210a (reference). Figure 7 Programming operations performed on specific memory units.

[0121] refer to Figure 10 First, assume that a programming operation is performed on the memory cell connected to the first word line WL1 in the memory cell of the cell string CS1 connected to the bit line BL1.

[0122] The memory cell can be programmed using the ISPP method, and the memory cell can be programmed within a programming cycle PL1. In this case, the electrical energy consumed in programming the memory cell can be represented by Equation 1 below. In Equation 1, iT1 can be the tunneling current flowing between the body and gate electrodes of the transistor connected to the first word line WL1, and i1 can be the current flowing between the drain and source electrodes of the transistor connected to the first word line WL1. However, it should be understood that, for accurate energy calculation, Equation 1 omits the current flowing between the drain and source electrodes of the transistor when the programming voltage is applied, because although the current is considered together, its magnitude is smaller than the tunneling current iT1.

[0123] [Equation 1]

[0124]

[0125] refer to Figure 11 Suppose a programming operation is performed on the memory cell connected to the sixteenth word line WL16 in the memory cell of the cell string CS1 connected to the bit line BL1.

[0126] The memory cell can be programmed using the ISPP method, and after three programming cycles PL1 to PL3, the memory cell is successfully programmed. In this case, the electrical energy consumed in programming the memory cell can be represented by Equation 2 below. In Equation 2, iT16 can be the tunneling current flowing between the body and gate electrodes of the transistor connected to the sixteenth-word line WL16, and i16 can be the current flowing between the drain and source electrodes of the transistor connected to the sixteenth-word line WL16. In Equation 2, the given description indicates that the tunneling current iT16 flowing in each programming cycle is the same; however, since the amplitudes of the programming voltages differ in each programming cycle, the amplitudes of the tunneling current iT16 in each programming cycle can also differ.

[0127] [Equation 2]

[0128]

[0129] Comparing Equations 1 and 2, it can be understood that the electrical energy required to program the memory cell connected to the first word line WL1 is less than the electrical energy required to program the memory cell connected to the sixteenth word line WL16.

[0130] Furthermore, since memory cells connected to the same word line mostly have the same programming characteristics, the programming characteristics (i.e., LE or NE) of memory cells connected to a specific word line can be determined by measuring the electrical energy required to program the memory cells connected to that word line. For example, it is possible to determine the programming characteristics of memory cells connected to a particular word line. Figure 10Each of the memory cells in the first word line WL1 has (i.e., corresponds to) low write energy LE, and can be determined to be connected to Figure 11 Each of the sixteenth word line WL16 memory cells has (i.e., corresponds to) the normal write energy NE.

[0131] In this embodiment, the level and application time of the programming voltage Vpgm and the level and application time of the verification voltage Vvfy can be obtained by controlling the voltage generator that generates the programming voltage and the verification voltage, and the tunneling currents iT1 and iT16 and the intensity of currents i1 and i16 can be obtained by separate measuring devices during the testing phase.

[0132] The above describes how to determine the programming characteristics of a memory cell based on the energy consumed during the execution of a programming loop. However, in other embodiments, any other factors may be alternatively or additionally considered.

[0133] In this embodiment, it is assumed that the energy required to program a memory cell connected to the first word line WL1 is equal to the energy required to program a memory cell connected to the sixteenth word line WL16. However, the intensity of the programming voltage applied in each programming cycle can be different from each other. In this case, a word line connected to a memory cell to which a low programming voltage is applied can be determined to have (i.e., corresponding to) a low write energy LE, and a word line connected to a memory cell to which a high programming voltage is applied can be determined to have (i.e., corresponding to) a normal write energy NE. It will be understood that, depending on the strategy, each of the two word lines can be determined to have (i.e., corresponding to) a low write energy LE.

[0134] In an embodiment, the programming characteristics of a memory cell can be determined by considering the number of programming cycles required to program the memory cell. For example, for Figure 10 Since only one programming cycle is executed, the memory cell connected to the first word line WL1 can be determined to have (i.e., corresponding to) low write energy LE. Conversely, for Figure 11 Since three programming cycles were executed, it can be determined that the memory cell connected to the sixteenth word line WL16 has (i.e., corresponding to) normal write energy NE.

[0135] In an embodiment, the programming characteristics of a memory cell can be determined by considering the level of the programming voltage Vpgm. For example, even if the number of programming cycles required to program a memory cell on the first word line WL1 is equal to the number of programming cycles required to program a memory cell on the sixteenth word line WL16, the programming voltage level may vary depending on the location of the memory cell. In this case, a memory cell connected to a word line with a low programming voltage in the same programming cycle can be determined to have (i.e., corresponding to) a low write energy LE, and a memory cell connected to a word line with a high programming voltage in the same programming cycle can be determined to have (i.e., corresponding to) a normal write energy NE. It will be understood that, depending on the strategy, each of the two word lines can be determined to have (i.e., corresponding to) a low write energy LE.

[0136] In this embodiment, due to factors such as the location of the memory cell, the characteristics of the memory cell, and the manufacturing process, a memory cell connected to a particular word line can be programmed successfully in just one programming cycle. During the testing of the non-volatile memory device 1200, the memory cell of a word line that is programmed successfully in just one programming cycle can be considered to have very high reliability, and no separate verification operation needs to be performed on the memory cell of that word line. That is, a memory cell that does not undergo a verification operation can be determined to have (i.e., corresponding to) low write energy LE.

[0137] In the embodiment, the tunneling currents iT1 and iT16 of the transistors in the cell string CS1 can be considered (reference). Figure 10 and Figure 11 The programming characteristics of a memory cell are determined by the strength of the currents i1 and i16. For example, when the number of programming cycles required to program a memory cell connected to the first word line WL1 is equal to the number of programming cycles required to program a memory cell connected to the sixteenth word line WL16, the strength of the tunneling current flowing through the transistors connected to word lines WL1 and WL16 respectively and / or the strength of the current flowing through the transistors can be additionally considered. When the strength of the tunneling current iT1 of a memory cell connected to the first word line WL1 is less than the strength of the tunneling current iT16 of a memory cell connected to the sixteenth word line WL16, the memory cell connected to the first word line WL1 can be determined to have (i.e., corresponding to) a low write energy LE, and the memory cell connected to the sixteenth word line WL16 can be determined to have (i.e., corresponding to) a normal write energy NE. It will be understood that, depending on the strategy, each of the two word lines can be determined to have (i.e., corresponding to) a low write energy LE.

[0138] As described above, as an example, some possible combinations of factors (e.g., programming voltage, voltage application time, tunneling current of the memory cell, number of programming cycles, and whether the verification voltage is skipped) used to determine the programming characteristics of a memory cell are presented. However, it should be understood that the above factors can be considered independently of each other, or the programming characteristics of a memory cell can be determined by different combinations of the above factors.

[0139] Figure 12 This is a diagram showing the programming characteristics based on the size of the channel aperture. Figure 12 It shows Figure 5 A simplified cross-sectional view is shown; in the embodiment, a cell string implementing a dual-stack structure and including 16 memory cells is illustrated. As shown, the dual-stack structure includes a first stack structure Stack1 (corresponding to the first part PL1) and a second stack structure Stack2 (corresponding to the second part PL2).

[0140] refer to Figure 12 Due to manufacturing process limitations of the memory device, the width or cross-sectional area of ​​the first portion PL1 can decrease as the distance from the substrate decreases, and can increase as the distance from the substrate increases. Similarly, the width or cross-sectional area of ​​the second portion PL2 can decrease as the distance from the substrate decreases, and can increase as the distance from the substrate increases.

[0141] Because the size of a memory cell increases with the width or cross-sectional area of ​​the pillars, additional energy may be required to program the cell. This can be due to factors such as increased programming voltage, longer programming time, and increased tunneling current. Conversely, because the size of a memory cell decreases with the width or cross-sectional area of ​​the pillars, less energy is required to program it. This can be due to factors such as decreased programming voltage, shorter programming time, and reduced tunneling current.

[0142] As described above, as the width or cross-sectional area of ​​the pillar decreases (i.e., as the distance from the substrate decreases), the PLP region 1210a (reference)... Figure 1 Programming the memory cells of PLP region 1210a (reference) requires lower write energy. Conversely, as the width or cross-sectional area of ​​the pillar increases (i.e., as the distance from the substrate increases), the write energy required for PLP region 1210a (reference) increases. Figure 1 Programming the storage cells can require high write power.

[0143] In an embodiment, a memory cell whose column width or cross-sectional area is smaller than a reference value can be determined to have (i.e., corresponding to) low write energy LE. Conversely, a memory cell whose column width or cross-sectional area is equal to or greater than a reference value can be determined to have (i.e., corresponding to) normal write energy NE.

[0144] Based on the above criteria, the first word line WL1 and the second word line WL2 of the first part of PL1, as well as the ninth word line WL9 and the cross line WL10 of the second part of PL2, can be identified as having (i.e., corresponding to) low write energy LE, and the remaining word lines can be identified as having (i.e., corresponding to) normal write energy NE. Of course, the number of word lines identified as having (i.e., corresponding to) low write energy LE can be changed according to the strategy.

[0145] Figure 13 This is a diagram illustrating the programming characteristics based on the shape of the channel hole. Figure 13 It shows Figure 5 A simplified cross-sectional view is shown; in the embodiment, a cell string implementing a dual-stack structure and including 16 memory cells is illustrated. As shown, the dual-stack structure includes a first stack structure Stack1 (corresponding to the first part PL1) and a second stack structure Stack2 (corresponding to the second part PL2).

[0146] refer to Figure 13 Due to limitations in the storage device manufacturing process, the shapes of the components of the pillar's cross-section (i.e., the internal material 114, the channel layer 115, and the first insulating layer 116) may not be perfectly circular. For example, the pillar's cross-section may be uneven or irregular, and in this respect, it may have rough edges. For instance, the components of the cross-section of the first portion PL1 of the pillar may be perfectly circular near the eighth letter line WL8.

[0147] However, near the sixteenth-word line WL16, the cross-section of the second portion PL2 of the post may not be perfectly circular and may exhibit heavy striations. In this case, during programming operations, a strong electric field can be applied to the memory cell connected to the sixteenth-word line WL16, and the energy required to program the memory cell connected to the sixteenth-word line WL16 can be less than that required for the eighth-word line WL8. Accordingly, even if the height occupied by the eighth-word line WL8 in the first portion PL1 of the post is equal to the height occupied by the sixteenth-word line WL16 in the second portion PL2 of the post, the memory cell connected to the eighth-word line WL8 can be determined to have (i.e., corresponding to) normal write energy NE; conversely, the memory cell connected to the sixteenth-word line WL16 can be determined to have (i.e., corresponding to) low write energy LE.

[0148] Figure 14 This is a flowchart illustrating an operation method of a storage device 1000 according to an embodiment.

[0149] Let's refer to each other. Figure 1 , Figure 2and Figure 14 In operation S210, the storage controller 1100 can detect a sudden power failure. When a sudden power failure occurs, the storage controller 1100 can store the data being processed (i.e., PLP data) (i.e., data stored in the buffer or internal buffer 1120) in the PLP area 1210a.

[0150] The low-energy write manager 1170 can check the size of the PLP data (S220) and can check the size of the memory cell with (i.e., corresponding to) low write energy LE (S230).

[0151] The low-energy write manager 1170 can determine whether the size of the PLP data is smaller than the size of the memory cell with (i.e., corresponding to) low write energy LE.

[0152] When the size of the PLP data is smaller than the size of the memory cell with low write energy LE (i.e., corresponding to low write energy LE), a PLP write can be performed on the memory cell with low write energy LE. In this case, since all PLP data is programmed into the memory cell with low write energy LE, the situation where PLP data is programmed into the memory cell with normal write energy NE does not occur.

[0153] Conversely, when the size of the PLP data is greater than or equal to the size of the memory cell with (i.e., corresponding to) low write energy LE (No in operation S240), in operation S260, the memory controller 1100 can write the PLP data into the memory cell with (i.e., corresponding to) low write energy LE. All available memory cells with (i.e., corresponding to) low write energy LE can be filled with PLP data.

[0154] In operation S270, the storage controller 1100 can write the remaining PLP data that has not yet been written into the storage cell having (i.e., corresponding to) normal write energy NE.

[0155] Figure 15 It is shown according to the reference Figure 14 An example of PLP writing using the described method.

[0156] refer to Figure 15 The PLP block storing PLP data may include word lines WL2, WL3, WL6, WL10, WL11 and WL14 with low write energy LE (i.e., corresponding to low write energy LE) and the remaining word lines with normal write energy NE (i.e., corresponding to normal write energy NE).

[0157] According to the reference Figure 14The described operating method allows the storage controller to detect sudden power outages and determine whether the size of the PLP data is greater than the size of a storage cell with (i.e., corresponding to) low write energy (LE).

[0158] The memory controller can perform PLP writes sequentially, starting with the lower word line numbers, to memory cells connected to word lines WL2, WL3, WL6, WL10, WL11, and WL14, which have (i.e., correspond to) low write energy LE. However, in another embodiment, the memory controller can perform PLP writes in reverse order, starting with the higher word line numbers.

[0159] When a PLP write to a word line with a low write energy LE is terminated, the memory controller can perform a PLP write to a word line with a normal write energy NE. An example of performing a PLP write to word lines WL1 and WL4 is shown.

[0160] Figure 16 This is a flowchart illustrating an operation method of a storage device 1000 according to an embodiment.

[0161] Figure 16 The operation method can be compared with Figure 14 The operation methods are roughly similar, and operations S310 to S340 are similar to... Figure 14 Operations S210 to S240 are the same. The description will follow. Figure 16 In and reference Figure 14 The operations described are different operations (i.e., the differences).

[0162] In operation S360, the storage controller 1100 can determine the target word line for normal write energy PLP writing. The reason is as follows: since the capacity of the storage cell with (i.e., corresponding to) low write energy LE is smaller than the size of the PLP data, it is necessary to reserve the size of the additional storage cell with (i.e., corresponding to) normal write energy NE in advance so that the PLP write can be completed in one go.

[0163] In operation S370, the memory controller can perform PLP writes on all memory cells with (i.e., corresponding to) low write energy LE and memory cells determined to be used for normal write energy PLP writes, based on word line numbers (or in reverse order).

[0164] Figure 17 It is shown according to the reference Figure 16 An example of PLP writing using the described method.

[0165] refer to Figure 17The PLP block storing PLP data may include word lines WL2, WL3, WL6, WL10, WL11 and WL14 with low write energy LE (i.e., corresponding to low write energy LE) and the remaining word lines with normal write energy NE (i.e., corresponding to normal write energy NE).

[0166] According to the reference Figure 16 The described operating method allows the storage controller to detect a sudden power outage and determine that the size of the PLP data is greater than the size of the storage cell with (i.e., corresponding to) low write energy LE.

[0167] The storage controller 1100 can determine word lines WL1 and WL4 for normal PLP writes. However, the embodiment is not limited to this. The storage controller 1100 can select any word line among word lines having (i.e., corresponding to) normal write energy NE.

[0168] The memory controller can sequentially perform PLP writes on word lines WL2, WL3, WL6, WL10, WL11 and WL14 with (i.e., corresponding to) low write energy LE, and on word lines WL1 and WL4 with (i.e., corresponding to) normal write energy NE. Figure 17 An embodiment is shown in which the memory controller performs PLP writes sequentially, starting from the low word line number. However, in another embodiment, the memory controller may perform PLP writes in reverse order, starting from the high word line number.

[0169] and Figure 15 In comparison, Figure 17 In this context, PLP writing is performed sequentially, starting from the low word line number (or in reverse order), which improves programming efficiency.

[0170] Figure 18 This is a flowchart illustrating an operation method of a storage device 1000 according to an embodiment.

[0171] The above description states that a PLP write operation is performed based on the condition that the memory cell (or word line) has either a low write energy (LE) or a normal write energy (NE). However, in Figure 18 The description given is: The range of low write energy is subdivided so that memory cells with (i.e., corresponding to) low write energy LE are divided into multiple groups.

[0172] Let's refer to each other. Figure 1 , Figure 2 and Figure 18In operation S410, the storage controller 1100 can detect a sudden power failure. When a sudden power failure occurs, the storage controller 1100 can store the data being processed (i.e., PLP data) (i.e., data stored in the buffer or internal buffer 1120) in the PLP area 1210a.

[0173] In operation S420, the storage controller 1100 can write PLP data to the storage cells connected to the first set of word lines. The storage cells connected to the first set of word lines can have a minimum range of write energy (hereinafter referred to as "first low write energy LE1").

[0174] In operation S430, the storage controller 1100 can write PLP data to storage cells connected to the second set of word lines. The storage cells connected to the second set of word lines can have a second low write energy range (hereinafter referred to as "second low write energy LE2"). The value of the first low write energy LE1 can always be less than the value of the second low write energy LE2.

[0175] Figure 19 It is shown according to the reference Figure 18 An example of PLP writing using the described method.

[0176] refer to Figure 19 The word lines of a PLP block can be divided into: word lines WL2, WL3 and WL10 with (i.e., corresponding to) the first low write energy LE1; word lines WL6 and WL11 with (i.e., corresponding to) the second low write energy LE2; word line WL14 with the third low write energy LE3; and word lines WL1, WL4, WL5, WL7, WL8, WL9, WL12, WL13, WL15 and WL16 with (i.e., corresponding to) the normal write energy NE.

[0177] According to the reference Figure 18 The described operating method allows the memory controller to detect a sudden power outage and perform PLP writes on word lines WL2, WL3, and WL10 that have (i.e., correspond to) a first low write energy LE1. The PLP write can be terminated when the size of the memory cell connected to word lines WL2, WL3, and WL10 that have (i.e., correspond to) the first low write energy LE1 is greater than or equal to the size of the PLP data.

[0178] However, when the size of the memory cell connected to word lines WL2, WL3, and WL10, which have (i.e., correspond to) the first low write energy LE1, is smaller than the size of the PLP data, the memory controller can perform PLP writes to word lines WL6 and WL11, which have (i.e., correspond to) the second low write energy LE2. The PLP write can be terminated when the size of the memory cell connected to word lines WL6 and WL11, which have (i.e., correspond to) the second low write energy LE2, is greater than or equal to the size of the remaining PLP data.

[0179] However, when the size of the memory cell connected to word lines WL6 and WL11, which have (i.e., correspond to) the second lowest write energy LE2, is smaller than the size of the remaining PLP data, the memory controller can perform a PLP write to word line WL14, which has the third lowest write energy LE3. The PLP write can be terminated when the size of the memory cell connected to word line WL14, which has the third lowest write energy LE3, is greater than or equal to the size of the remaining PLP data.

[0180] Conversely, when the size of the memory cell connected to word line WL14, which has the third low write energy LE3, is smaller than the size of the remaining PLP data, the memory controller is able to perform PLP writes on word lines WL1, WL4, WL5, WL7, WL8, WL9, WL12, WL13, WL15, and WL16, which have (i.e., corresponding to) the normal write energy NE.

[0181] exist Figure 19 In this embodiment, since PLP writes are performed sequentially from word lines having (i.e., corresponding to) the first low write energy LE1 to word lines having (i.e., corresponding to) the third low write energy LE3, PLP writes can be performed out of order (or in reverse order) according to the word line numbering. However, in another embodiment, it can be done by referring to... Figure 16 and Figure 17 The PLP writing method is applied to perform PLP writing according to the word line number (or in reverse order).

[0182] Figure 20 This is a flowchart illustrating an operation method of a storage device 1000 according to an embodiment.

[0183] Let's refer to each other. Figure 1 , Figure 2 and Figure 20 In operation S510, the storage controller 1100 can detect a sudden power failure. When a sudden power failure occurs, the storage controller 1100 can store the data being processed (i.e., PLP data) (i.e., data stored in the buffer or internal buffer 1120) in the PLP area 1210a.

[0184] In operation S520, the storage controller 1100 can write PLP data to a first storage cell having a first write power and connected to a first word line. Alternatively, the storage controller 1100 can write PLP data to a storage cell having (i.e., corresponding to) the first write power and connected to the first word line.

[0185] In operation S530, the storage controller 1100 can write virtual data to a second storage cell connected to a second word line adjacent to the first word line. In an embodiment, storage cells that do not have PLP data written to can be virtually programmed to prevent performance degradation of storage cells storing PLP data and to manage the lifespan of PLP blocks.

[0186] In operation S540, the storage controller 1100 can write PLP data to a third storage cell that has a second write power and is connected to a third word line. Alternatively, the storage controller 1100 can write PLP data to a storage cell that has (i.e., corresponds to) the second write power and is connected to a third word line. The third word line can be a word line adjacent to the second word line but not adjacent to the first word line.

[0187] exist Figure 20 The description given is as follows: the two word lines for writing PLP data are set in the following state: a word line for writing virtual data is located between these two word lines, but the embodiment is not limited to this. That is, in another embodiment, multiple word lines for writing virtual data can be set between the two word lines for writing PLP data.

[0188] Figure 21 It is shown according to the reference Figure 20 An example of PLP writing using the described method.

[0189] refer to Figure 21 The word lines of a PLP block can be divided into: word lines WL2, WL3, WL6, WL10, WL11 and WL14 with low write energy LE; and word lines WL1, WL4, WL5, WL7, WL8, WL9, WL12, WL13, WL15 and WL16 with normal write energy NE.

[0190] The storage controller can detect sudden power outages and can perform PLP writes and virtual writes in one direction (e.g., in the direction of word line numbering increase or decrease).

[0191] In this embodiment, the storage controller can perform virtual writes to the storage cells connected to the first word line WL1, and can perform PLP writes to the second word line WL2 and the third word line WL3. Next, the storage controller can alternately perform virtual writes and PLP writes, such as... Figure 21 As shown.

[0192] Figure 22 It is shown according to the reference Figure 20 Another embodiment of the described method for PLP writing.

[0193] refer to Figure 22 The word lines of a PLP block can be divided into: word lines WL2, WL3, WL6, WL10, WL11 and WL14 with low write energy LE; and word lines WL1, WL4, WL5, WL7, WL8, WL9, WL12, WL13, WL15 and WL16 with normal write energy NE.

[0194] The storage controller can detect sudden power outages and can perform PLP writes and virtual writes in one direction (e.g., along the direction of word line numbering increments or decrements). However, compared to... Figure 21 The difference lies in Figure 22 In this context, the size of the PLP data can be larger than the size of a memory cell with (i.e., corresponding to) low write energy LE. Accordingly, a portion of the PLP data can be written into a memory cell with (i.e., corresponding to) normal write energy NE.

[0195] In this embodiment, the storage controller can perform normal write energy PLP writes to the storage cells connected to the first word line WL1, and can perform low-energy PLP writes to the second word line WL2 and the third word line WL3. Furthermore, the storage controller can perform normal write energy PLP writes to the fourth word line WL4, and can perform virtual writes to the fifth word line WL5.

[0196] Next, the storage controller can alternate between low-energy PLP writes and virtual writes, such as... Figure 22 As shown.

[0197] Figure 23 This is a flowchart illustrating an operation method of a storage device 1000 according to an embodiment. Various methods for storing PLP data in a PLP block of a non-volatile storage device in the event of a sudden power failure have been described above. However, a scheme can be adopted to store user data without modification in which programming operations are preferentially performed on storage cells (or storage cells connected to word lines) with low write energy values ​​(i.e., corresponding to low write energy).

[0198] Let's refer to each other. Figure 1 , Figure 2 and Figure 23In operation S610, in low-energy write mode, the non-volatile storage device 1200 can receive write commands from the storage controller 1100. These write commands can be normal write commands or separate commands (e.g., vendor-specific commands) used to perform low-energy write operations.

[0199] In operation S620, the storage controller 1100 can write user data into at least one first storage cell having a first write power and connected to a first word line.

[0200] In operation S630, the storage controller 1100 can write user data to at least one second storage cell having a second write power and connected to a second word line. The energy required to program the first storage cell may be less than the energy required to program the second storage cell.

[0201] In this embodiment, the storage device 1000 may enter a low-energy write mode based on user settings or when given conditions are met. For example, the storage device 1000 may enter a low-energy write mode when the size of the data requested by the user is less than the size of a storage block (or less than the size of the programmable space of a block). The storage controller may write user data into storage cells of specific storage blocks that have (i.e., correspond to) low write energy (LE), and for data stability, to prevent storage cell degradation, and / or to manage the lifespan of the storage blocks, the storage controller may allow the storage blocks to remain in an open block state, no longer programming the free space, or may program virtual data into the free space.

[0202] Figure 24 It shows Figure 7 A graph showing the threshold voltage distribution of memory cells in the normal region 1210b. Figure 24 In the distribution diagram, the horizontal axis represents the threshold voltage of the memory cell, and the vertical axis represents the number of memory cells.

[0203] In this embodiment, for ease of description, it is assumed that each of the memory cells in the normal region 1210b is configured as a TLC (Tencent-Level Cell) storing three bits per cell. However, the embodiment is not limited to this. For example, each of the memory cells may be implemented as a single-level cell (SLC), a multi-level cell (MLC), or a quadruple-level cell (QLC).

[0204] refer to Figure 3 and Figure 24 The non-volatile storage device 1200 can store data in the storage cells of the storage block BLK by controlling the threshold voltage of the storage cells. For example, each of the storage cells can be programmed to have an erase state "E" and one of a plurality of programming states P1 to P7.

[0205] The non-volatile memory device 1200 can verify the state of the memory cells using multiple verification voltages Vvfy1 to Vvfy7. For example, the non-volatile memory device 1200 can verify whether the memory cell corresponding to the first programming state P1 is properly programmed using the first verification voltage Vvfy1. The non-volatile memory device 1200 can verify whether the memory cell corresponding to the second programming state P2 is properly programmed using the second verification voltage Vvfy2. Similarly, the non-volatile memory device 1200 can verify whether the memory cells corresponding to the third programming state P3 to the seventh programming state P7 are properly programmed using the third verification voltage Vvfy3 to the seventh verification voltage Vvfy7.

[0206] The non-volatile storage device 1200 can determine the data stored in the storage cell by sensing the programming state (i.e., threshold voltage) of the storage cell.

[0207] Figure 25 It is used to describe Figure 1 A diagram showing the programming operations of the memory cell in the normal region 1210b. Figure 25 The programming operations described in the embodiments can be associated with the programming characteristics (i.e., low write energy LE or normal write energy NE) of each word line during the testing phase of the non-volatile memory device 1200.

[0208] In an embodiment, the non-volatile storage device 1200 can program the memory cells of the normal region 1210b by sequentially executing multiple programming loops based on the ISPP method.

[0209] refer to Figure 25 The non-volatile memory device 1200 can perform programming operations through multiple programming cycles PL1 to PLk. Each of the multiple programming cycles PL1 to PLk may include a programming phase and a verification phase. The programming phase may include applying a programming voltage (e.g., each of Vpgm1 to Vpgmk) to a selected word line. The verification phase may include applying a set of verification voltages (e.g., verification voltages VF1 to VFk) to the selected word line. In an embodiment, the set of verification voltages for each verification phase may include a reference voltage. Figure 24 At least some of the multiple verification voltages Vvfy1 to Vvfy7 described.

[0210] Figure 26 The concept illustrates the normal region 1210b (reference). Figure 1 Programming operations performed on specific memory units. Figure 27 The concept illustrates the normal region 1210b (reference). Figure 1 Programming operations performed on specific memory units.

[0211] Reference Figure 26 and Figure 27 Describes a method for determining the programming characteristics of memory cells in normal regions, a method similar to the reference. Figure 10 and Figure 11 The methods of description are largely similar. Therefore, a brief description will be given below, or descriptions identical to those given above may be omitted.

[0212] In this embodiment, when a programming operation is performed based on the ISPP method, causing the memory cell to be programmed to the third programming state P3, the memory cell only operates in one programming cycle PL1 (see reference). Figure 26 In programming, the required electrical energy can be less than that of the storage unit during the execution of three programming cycles PL1 to PL3 (see reference). Figure 27 After programming, the required electrical energy is supplied. Accordingly, connected to... Figure 26 The memory cell of the first word line WL1 can be identified as having (i.e., corresponding to) low write energy LE, and connected to Figure 27 The sixteenth word line WL16 memory cell can be identified as having (i.e., corresponding to) normal write energy NE.

[0213] In this embodiment, the memory cell (reference) is programmed only in one programming cycle PL1. Figure 26 This can be identified as a memory cell that has (i.e., corresponds to) low write energy LE and has been programmed after a relatively large number of programming cycles PL1 to PL3 (see reference). Figure 27 It can be determined that it has (i.e., corresponding to) normal write energy NE.

[0214] Additionally / alternatively, in order to determine the programming characteristics of the memory cell, the level of the programming voltage Vpgm, whether the verification operation is skipped, the strength of the tunneling current of the memory cell, the duration of the programming voltage Vpgm, etc., can be considered independently or in combination. Furthermore, those skilled in the art can determine whether the memory cell in the normal region 1210b has low write energy LE or normal write energy NE based on the combination of the above factors.

[0215] Figure 28 This is a flowchart illustrating an operation method of a storage device 1000 according to an embodiment. Figure 28 and Figure 20 Similarly, PLP data and virtual data are written to the PLP area. Therefore, a brief description will be given.

[0216] Let's refer to each other. Figure 1 , Figure 2 and Figure 28In operation S710, in low-energy write mode, the non-volatile storage device 1200 can receive write commands from the storage controller 1100. These write commands can be normal write commands or vendor-specific commands used to perform low-energy write operations.

[0217] The storage controller 1100 can write user data to at least one first storage cell having a first write power and connected to a first word line (S720). The storage controller 1100 can write virtual data to a second storage cell connected to a second word line. The second word line may be a word line adjacent to the first word line. The storage controller 1100 can write user data to at least one third storage cell having a second write power and connected to a third word line (S740). The third word line may be a word line adjacent to the second word line but not adjacent to the first word line.

[0218] exist Figure 28 The description given is as follows: the two word lines for writing user data are set in the following state: a word line for writing virtual data is located between these two word lines, but the embodiments are not limited to this. That is, in another embodiment, multiple word lines for writing virtual data can be set between the two word lines for writing user data.

[0219] Furthermore, when the size of user data exceeds the size of the storage block, a method for performing low-energy writes can be similar to the reference. Figure 14 The described method is executed. Furthermore, the method for performing low-energy writes in word-line numbering order can be similar to the reference. Figure 16 The described method is executed. Furthermore, the method for subdividing the low write energy range, classifying memory cells with (i.e., corresponding to) low write energy LE, and performing low-energy writes can be similar to the method described in the reference. Figure 19 The described method is executed.

[0220] The above describes methods for writing PLP data to the PLP region based on write energy during a sudden power outage, and methods for writing user data to the normal region based on write energy. According to embodiments, the limited energy of the supercapacitor can be efficiently utilized during a sudden power outage, and the PLP write time can also be shortened. Furthermore, during normal write operations, the write energy can be reduced under certain conditions, and the write time can also be shortened (e.g., tPROG).

[0221] Figure 29 This is a diagram illustrating a storage device 500 according to some embodiments.

[0222] refer to Figure 29The memory device 500 may have a chip-to-chip (C2C) structure. At least one upper chip including a cell region and a lower chip including a peripheral circuit region (PERI) can be fabricated separately, and then the at least one upper chip and the lower chip can be connected to each other by a bonding method to realize the C2C structure. For example, the bonding method may indicate a method of electrically or physically connecting a bonding metal pattern formed in the uppermost metal layer of the upper chip to a bonding metal pattern formed in the uppermost metal layer of the lower chip. For example, if the bonding metal pattern is formed of copper (Cu), the bonding method may be a Cu-Cu bonding method. Alternatively, the bonding metal pattern may be formed of aluminum (Al) or tungsten (W).

[0223] The storage device 500 may include at least one on-chip containing cell regions. For example, such as Figure 29 As shown, the storage device 500 may include two upper chips. However, the number of upper chips is not limited to this. In the case where the storage device 500 includes two upper chips, a first upper chip including a first cell region CELL1, a second upper chip including a second cell region CELL2, and a lower chip including a peripheral circuit region PERI can be manufactured separately. Then, the first upper chip, the second upper chip, and the lower chip can be connected to each other by a bonding method to manufacture the storage device 500. The first upper chip can be flipped and then connected to the lower chip by a bonding method, and the second upper chip can also be flipped and then connected to the first upper chip by a bonding method. In the following, the upper and lower portions of each of the first and second upper chips will be defined based on the fact that each of the first and second upper chips is flipped. In this respect, the upper portion of the lower chip may indicate an upper portion defined based on the +Z axis direction, and the upper portion of each of the first and second upper chips may indicate an upper portion defined based on the +Z axis direction. Figure 29 The upper part is defined by the -Z axis direction. However, the embodiments are not limited to this. In some embodiments, one of the first and second upper chips can be flipped and then connected to the corresponding chip by a bonding method.

[0224] Each of the peripheral circuit region PERI and the first cell region CELL1 and the second cell region CELL2 of the storage device 500 may include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0225] The peripheral circuit region (PERI) may include a first substrate 210 and a plurality of circuit elements 220a, 220b, and 220c formed on the first substrate 210. An interlayer insulating layer 215, including one or more insulating layers, may be disposed on the plurality of circuit elements 220a, 220b, and 220c, and a plurality of metal lines electrically connected to the plurality of circuit elements 220a, 220b, and 220c may be disposed in the interlayer insulating layer 215. For example, the plurality of metal lines may include: first metal lines 230a, 230b, and 230c connected to the plurality of circuit elements 220a, 220b, and 220c; and second metal lines 240a, 240b, and 240c formed on the first metal lines 230a, 230b, and 230c. The plurality of metal lines may be formed of at least one of various conductive materials. For example, the first metal lines 230a, 230b and 230c can be formed of tungsten, which has a relatively high resistivity, and the second metal lines 240a, 240b and 240c can be formed of copper, which has a relatively low resistivity.

[0226] This embodiment shows and describes first metal lines 230a, 230b, and 230c and second metal lines 240a, 240b, and 240c. However, the embodiment is not limited thereto. In some embodiments, at least one or more additional metal lines may also be formed on the second metal lines 240a, 240b, and 240c. In this case, the second metal lines 240a, 240b, and 240c may be formed of aluminum, and at least some of the additional metal lines formed on the second metal lines 240a, 240b, and 240c may be formed of copper, which has a resistivity lower than that of aluminum in the second metal lines 240a, 240b, and 240c.

[0227] The interlayer insulating layer 215 may be disposed on the first substrate 210 and may include insulating materials such as silicon oxide and / or silicon nitride.

[0228] Each of the first cell region CELL1 and the second cell region CELL2 may include at least one memory block. The first cell region CELL1 may include a second substrate 310 and a common source line 320. Multiple word lines 330 (331 to 338) may be stacked on the second substrate 310 in a direction perpendicular to the top surface of the second substrate 310 (i.e., the Z-axis direction). Serial select lines and ground select lines may be disposed above and below the word lines 330, and multiple word lines 330 may be disposed between the serial select lines and the ground select lines. Similarly, the second cell region CELL2 may include a third substrate 410 and a common source line 420, and multiple word lines 430 (431 to 438) may be stacked on the third substrate 410 in a direction perpendicular to the top surface of the third substrate 410 (i.e., the Z-axis direction). Each of the second substrate 310 and the third substrate 410 may be formed of at least one of a variety of materials, and may be, for example, a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a substrate having a single-crystal epitaxial layer grown on a single-crystal silicon substrate. Multiple channel structures CH can be formed in each of the first unit region CELL1 and the second unit region CELL2.

[0229] In some embodiments, as shown in region "A1", a channel structure CH may be disposed in a bit line bonding region BLBA and may extend in a direction perpendicular to the top surface of the second substrate 310 to penetrate word line 330, string select line, and ground select line. The channel structure CH may include a data storage layer, a channel layer, and a filling insulating layer. The channel layer may be electrically connected to a first metal line 350c and a second metal line 360c in the bit line bonding region BLBA. For example, the second metal line 360c may be a bit line and may be connected to the channel structure CH via the first metal line 350c. The second metal line 360c may extend in a first direction (e.g., the Y-axis direction) parallel to the top surface of the second substrate 310.

[0230] In some embodiments, as shown in region "A2", the channel structure CH may include a lower channel LCH and an upper channel UCH connected to each other. For example, the channel structure CH may be formed by a process for forming the lower channel LCH and a process for forming the upper channel UCH. The lower channel LCH may extend in a direction perpendicular to the top surface of the second substrate 310 to penetrate the common source line 320 and the lower word lines 331 and 332. The lower channel LCH may include a data storage layer, a channel layer, and a fill insulating layer, and may be connected to the upper channel UCH. The upper channel UCH may penetrate the upper word lines 333 to 338. The upper channel UCH may include a data storage layer, a channel layer, and a fill insulating layer, and the channel layer of the upper channel UCH may be electrically connected to the first metal line 350c and the second metal line 360c. As the length of the channel increases, it may be difficult to form a channel with a substantially uniform width due to the characteristics of the manufacturing process. The storage device 500 according to this embodiment may include channels with improved width uniformity due to the lower channel LCH and upper channel UCH formed by sequentially executed processes.

[0231] In cases where the channel structure CH includes a lower channel LCH and an upper channel UCH as shown in region "A2", word lines located near the boundary between the lower channel LCH and the upper channel UCH can be dummy word lines. For example, word lines 332 and 333 adjacent to the boundary between the lower channel LCH and the upper channel UCH can be dummy word lines. In this case, data may not be stored in the memory cells connected to the dummy word lines. Alternatively, the number of pages corresponding to memory cells connected to dummy word lines can be less than the number of pages corresponding to memory cells connected to normal word lines. The voltage level applied to the dummy word lines can be different from the voltage level applied to the normal word lines, and thus the effect of uneven channel width between the lower channel LCH and the upper channel UCH on the operation of the memory device can be reduced.

[0232] In region "A2", the number of lower word lines 331 and 332 penetrated by the lower channel LCH is less than the number of upper word lines 333 to 338 penetrated by the upper channel UCH. However, the embodiments are not limited to this. In some embodiments, the number of lower word lines penetrated by the lower channel LCH may be equal to or greater than the number of upper word lines penetrated by the upper channel UCH. In addition, the structural features and connection relationships of the channel structure CH disposed in the second unit region CELL2 may be substantially the same as those of the channel structure CH disposed in the first unit region CELL1.

[0233] In the bit line bonding region BLBA, the first through electrode THV1 can be disposed in the first cell region CELL1, and the second through electrode THV2 can be disposed in the second cell region CELL2. For example... Figure 29As shown, the first through electrode THV1 can penetrate the common source line 320 and multiple word lines 330. In some embodiments, the first through electrode THV1 can also penetrate the second substrate 310. The first through electrode THV1 may include a conductive material. Alternatively, the first through electrode THV1 may include a conductive material surrounded by an insulating material. The second through electrode THV2 may have the same shape and structure as the first through electrode THV1.

[0234] In some embodiments, the first through electrode THV1 and the second through electrode THV2 can be electrically connected to each other via a first through metal pattern 372d and a second through metal pattern 472d. The first through metal pattern 372d can be formed at the bottom of a first upper chip including a first cell region CELL1, and the second through metal pattern 472d can be formed at the top of a second upper chip including a second cell region CELL2. The first through electrode THV1 can be electrically connected to a first metal line 350c and a second metal line 360c. A lower via 371d can be formed between the first through electrode THV1 and the first through metal pattern 372d, and an upper via 471d can be formed between the second through electrode THV2 and the second through metal pattern 472d. The first through metal pattern 372d and the second through metal pattern 472d can be connected to each other by a bonding method.

[0235] Additionally, in the bit line bonding area (BLBA), the upper metal pattern 252 can be formed in the uppermost metal layer of the peripheral circuit region (PERI), and an upper metal pattern 392 having the same shape as the upper metal pattern 252 can be formed in the uppermost metal layer of the first cell region (CELL1). The upper metal pattern 392 of the first cell region (CELL1) and the upper metal pattern 252 of the peripheral circuit region (PERI) can be electrically connected to each other by a bonding method. In the bit line bonding area (BLBA), the second metal line 360c can be electrically connected to the page buffer included in the peripheral circuit region (PERI). For example, some circuit elements 220c of the peripheral circuit region (PERI) can constitute a page buffer, and the second metal line 360c can be electrically connected to the circuit elements 220c constituting the page buffer through the upper bonding metal pattern 370c of the first cell region (CELL1) and the upper bonding metal pattern 270c of the peripheral circuit region (PERI).

[0236] Continue to refer to Figure 29In the word line bonding area (WLBA), the word line 330 of the first cell region CELL1 can extend in a second direction (e.g., the X-axis direction) parallel to the top surface of the second substrate 310 and can be connected to a plurality of cell contact plugs 340 (341 to 347). A first metal line 350b and a second metal line 360b can be sequentially connected to the cell contact plugs 340 connected to the word line 330. In the word line bonding area (WLBA), the cell contact plugs 340 can be connected to the peripheral circuit region PERI via an upper bonding metal pattern 370b of the first cell region CELL1 and an upper bonding metal pattern 270b of the peripheral circuit region PERI.

[0237] Cell contact plug 340 can be electrically connected to a line decoder included in the peripheral circuitry region (PERI). For example, some circuit elements 220b of the PERI can constitute a line decoder, and cell contact plug 340 can be electrically connected to the circuit elements 220b constituting the line decoder via the upper bonding metal pattern 370b of the first cell region (CELL1) and the upper bonding metal pattern 270b of the PERI. In some embodiments, the operating voltage of the circuit elements 220b constituting the line decoder can be different from the operating voltage of the circuit elements 220c constituting the page buffer. For example, the operating voltage of the circuit elements 220c constituting the page buffer can be greater than the operating voltage of the circuit elements 220b constituting the line decoder.

[0238] Similarly, in the word line bonding area WLBA, the word line 430 of the second cell region CELL2 can extend in a second direction (e.g., the X-axis direction) parallel to the top surface of the third substrate 410, and can be connected to a plurality of cell contact plugs 440 (441 to 447). The cell contact plugs 440 can be connected to the peripheral circuit region PERI via the upper metal pattern of the second cell region CELL2, the lower and upper metal patterns of the first cell region CELL1, and the cell contact plug 348.

[0239] In the word line bonding area WLBA, an upper bonding metal pattern 370b can be formed in the first cell area CELL1, and an upper bonding metal pattern 270b can be formed in the peripheral circuit area PERI. The upper bonding metal pattern 370b of the first cell area CELL1 and the upper bonding metal pattern 270b of the peripheral circuit area PERI can be electrically connected to each other by a bonding method. The upper bonding metal pattern 370b and the upper bonding metal pattern 270b can be formed of aluminum, copper, or tungsten.

[0240] In the external pad bonding area PA, a lower metal pattern 371e can be formed in the lower part of the first cell region CELL1, and an upper metal pattern 472a can be formed in the upper part of the second cell region CELL2. The lower metal pattern 371e of the first cell region CELL1 and the upper metal pattern 472a of the second cell region CELL2 can be connected to each other in the external pad bonding area PA by a bonding method. Similarly, the upper metal pattern 372a can be formed in the upper part of the first cell region CELL1, and the upper metal pattern 272a can be formed in the upper part of the peripheral circuit region PERI. The upper metal pattern 372a of the first cell region CELL1 and the upper metal pattern 272a of the peripheral circuit region PERI can be connected to each other by a bonding method.

[0241] Common source line contact plugs 380 and 480 can be disposed in the external pad bonding area PA. Common source line contact plugs 380 and 480 can be formed of conductive materials such as metals, metal compounds, and / or doped polysilicon. Common source line contact plug 380 of the first cell region CELL1 can be electrically connected to common source line 320, and common source line contact plug 480 of the second cell region CELL2 can be electrically connected to common source line 420. First metal line 350a and second metal line 360a can be sequentially stacked on common source line contact plug 380 of the first cell region CELL1, and first metal line 450a and second metal line 460a can be sequentially stacked on common source line contact plug 480 of the second cell region CELL2.

[0242] Input / output pads 205, 405, and 406 can be set in the external pad bonding area PA. (See reference) Figure 29 The lower insulating layer 201 may cover the bottom surface of the first substrate 210, and the first input / output pad 205 may be formed on the lower insulating layer 201. The first input / output pad 205 may be connected to at least one of a plurality of circuit elements 220a disposed in the peripheral circuit region PERI via the first input / output contact plug 203, and may be separated from the first substrate 210 by the lower insulating layer 201. In addition, a side insulating layer may be disposed between the first input / output contact plug 203 and the first substrate 210 to electrically isolate the first input / output contact plug 203 from the first substrate 210.

[0243] An upper insulating layer 401 covering the top surface of the third substrate 410 may be formed on the third substrate 410. A second input / output pad 405 and / or a third input / output pad 406 may be disposed on the upper insulating layer 401. The second input / output pad 405 may be connected to at least one of a plurality of circuit elements 220a disposed in the peripheral circuit region PERI via second input / output contact plugs 403 and 303, and the third input / output pad 406 may be connected to at least one of a plurality of circuit elements 220a disposed in the peripheral circuit region PERI via third input / output contact plugs 404 and 304.

[0244] In some embodiments, the third substrate 410 may not be disposed in the region where the input / output contact plugs are provided. For example, as shown in region "B", the third input / output contact plug 404 may be separated from the third substrate 410 in a direction parallel to the top surface of the third substrate 410 and may penetrate the interlayer insulating layer 415 of the second cell region CELL2 to connect to the third input / output pad 406. In this case, the third input / output contact plug 404 may be formed by at least one of various processes.

[0245] In some embodiments, as shown in region "B1", the third input / output contact plug 404 may extend in a third direction (e.g., the Z-axis direction), and the diameter of the third input / output contact plug 404 may gradually increase toward the upper insulating layer 401. In this respect, the diameter of the channel structure CH described in region "A1" may gradually decrease toward the upper insulating layer 401, but the diameter of the third input / output contact plug 404 may gradually increase toward the upper insulating layer 401. For example, the third input / output contact plug 404 may be formed after the second cell region CELL2 and the first cell region CELL1 are joined together by a bonding method.

[0246] In some embodiments, as shown in region "B2", the third input / output contact plug 404 may extend in a third direction (e.g., the Z-axis direction), and the diameter of the third input / output contact plug 404 may gradually decrease towards the upper insulating layer 401. In this respect, similar to the channel structure CH, the diameter of the third input / output contact plug 404 may gradually decrease towards the upper insulating layer 401. For example, the third input / output contact plug 404 may be formed together with the cell contact plug 440 before the second cell region CELL2 and the first cell region CELL1 are engaged with each other.

[0247] In some embodiments, the input / output contact plugs may overlap with the third substrate 410. For example, as shown in region "C", the second input / output contact plug 403 may penetrate the interlayer insulating layer 415 of the second cell region CELL2 in a third direction (e.g., the Z-axis direction) and be electrically connected to the second input / output pad 405 through the third substrate 410. In this case, the connection structure of the second input / output contact plug 403 and the second input / output pad 405 can be implemented by various methods.

[0248] In some embodiments, as shown in region "C1", the opening 408 may be formed to penetrate the third substrate 410, and the second input / output contact plug 403 may be directly connected to the second input / output pad 405 through the opening 408 formed in the third substrate 410. In this case, as shown in region "C1", the diameter of the second input / output contact plug 403 may gradually increase toward the second input / output pad 405. However, the embodiments are not limited thereto, and in some embodiments, the diameter of the second input / output contact plug 403 may gradually decrease toward the second input / output pad 405.

[0249] In some embodiments, as shown in region "C2", an opening 408 penetrating the third substrate 410 may be formed, and a contact portion 407 may be formed in the opening 408. One end of the contact portion 407 may be connected to the second input / output pad 405, and the other end of the contact portion 407 may be connected to the second input / output contact plug 403. Therefore, the second input / output contact plug 403 can be electrically connected to the second input / output pad 405 through the contact portion 407 in the opening 408. In this case, as shown in region "C2", the diameter of the contact portion 407 may gradually increase toward the second input / output pad 405, and the diameter of the second input / output contact plug 403 may gradually decrease toward the second input / output pad 405. For example, the second input / output contact plug 403 may be formed together with the cell contact plug 440 before the second cell region CELL2 and the first cell region CELL1 are joined together, and the contact portion 407 may be formed after the second cell region CELL2 and the first cell region CELL1 are joined together.

[0250] In some embodiments shown in region "C3", the blocking portion 409 may also be formed on the bottom end of the opening 408 of the third substrate 410, compared to region "C2". The blocking portion 409 may be a metal line formed in the same layer as the common source line 420. Alternatively, the blocking portion 409 may be a metal line formed in the same layer as at least one word line 430. The second input / output contact plug 403 may be electrically connected to the second input / output pad 405 via the contact portion 407 and the blocking portion 409.

[0251] Similar to the second input / output contact plug 403 and the third input / output contact plug 404 in the second cell region CELL2, the diameter of each of the second input / output contact plug 303 and the third input / output contact plug 304 in the first cell region CELL1 can gradually decrease or gradually increase towards the lower metal pattern 371e.

[0252] In some embodiments, slot 411 may be formed in the third substrate 410. For example, slot 411 may be formed at a specific location in the outer pad bonding region PA. For example, as shown in region "D", when viewed in a plan view, slot 411 may be located between the second input / output pad 405 and the cell contact plug 440. Alternatively, when viewed in a plan view, the second input / output pad 405 may be located between slot 411 and cell contact plug 440.

[0253] In some embodiments, as shown in region 'D1', slit 411 may be formed to penetrate the third substrate 410. For example, slit 411 may be used to prevent microcracks from forming in the third substrate 410 when the opening 408 is formed. However, embodiments are not limited thereto, and in some embodiments, slit 411 may be formed to a depth of approximately 60% to approximately 70% of the thickness of the third substrate 410.

[0254] In some embodiments, as shown in region "D2", conductive material 412 may be formed in slit 411. For example, conductive material 412 may be used to discharge leakage current generated when circuit elements in the external pad bonding region PA are driven to the outside. In this case, conductive material 412 may be connected to an external ground wire.

[0255] In some embodiments, as shown in region "D3", insulating material 413 may be formed in slit 411. For example, insulating material 413 may be used to electrically isolate the second input / output pads 405 and the second input / output contact plugs 403 disposed in the external pad bonding region PA from the word line bonding region WLBA. Because insulating material 413 is formed in slit 411, the voltage supplied through the second input / output pads 405 can be prevented from affecting the metal layer disposed on the third substrate 410 in the word line bonding region WLBA.

[0256] In some embodiments, the first input / output pads to the third input / output pads 205, 405, and 406 may be selectively formed. For example, the storage device 500 may be implemented as including only the first input / output pad 205 disposed on the first substrate 210; only the second input / output pad 405 disposed on the third substrate 410; or only the third input / output pad 406 disposed on the upper insulating layer 401.

[0257] In some embodiments, at least one of the second substrate 310 of the first cell region CELL1 or the third substrate 410 of the second cell region CELL2 can be used as a sacrificial substrate and can be completely or partially removed before or after the bonding process. Additional layers can be stacked after substrate removal. For example, the second substrate 310 of the first cell region CELL1 can be removed before or after the bonding process of the peripheral circuit region PER1 and the first cell region CELL1, and then an insulating layer or a conductive layer for connection can be formed covering the top surface of the common source line 320. Similarly, the third substrate 410 of the second cell region CELL2 can be removed before or after the bonding process of the first cell region CELL1 and the second cell region CELL2, and then an upper insulating layer 401 or a conductive layer for connection can be formed covering the top surface of the common source line 420.

[0258] According to an embodiment, in the event of a sudden power outage, PLP data being processed can be written efficiently based on the write energy.

[0259] According to the embodiments, user data can be written efficiently based on write energy.

[0260] Although various aspects of the embodiments have been described, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of this disclosure as set forth in the appended claims.

Claims

1. A storage device, comprising: a non-volatile memory device including an array of storage cells, the array of storage cells including a user area and a power loss protection (PLP) area; and a storage controller configured to, based on detecting a sudden power loss, write first PLP data into a first storage cell of the PLP area connected with a first word line, and write second PLP data into a second storage cell of the PLP area connected with a second word line, wherein a first write energy of the first storage cell is less than a second write energy of the second storage cell. the first write energy corresponds to a first program voltage for writing the first PLP data into the first storage cell, a first tunneling current for writing the first PLP data into the first storage cell, and a duration of applying the first program voltage to write the first PLP data into the first storage cell, and 2. The storage device of claim 1, wherein, wherein the second write energy corresponds to a second program voltage for writing the second PLP data into the second storage cell, a second tunneling current for writing the second PLP data into the second storage cell, and a duration of applying the second program voltage to write the second PLP data into the second storage cell. a first level of the first program voltage for writing the first PLP data into the first storage cell is lower than a second level of the second program voltage for writing the second PLP data into the second storage cell.

3. The storage device of claim 1, wherein, a number of first program loops performed for writing the first PLP data into the first storage cell is less than a number of second program loops performed for writing the second PLP data into the second storage cell.

4. The storage device of claim 1, wherein, a first duration of applying the first program voltage to write the first PLP data into the first storage cell is shorter than a second duration of applying the second program voltage to write the second PLP data into the second storage cell.

5. The storage device of claim 1, wherein, the storage controller is further configured to:

6. The storage device of claim 1, wherein, based on writing the first PLP data into the first storage cell, not apply a verify voltage to the first storage cell for verifying whether the first storage cell is programmed through; and based on writing the second PLP data into the second storage cell, apply the verify voltage to the second storage cell at least once for verifying whether the second storage cell is programmed through. a channel hole corresponding to the first storage cell is less than a channel hole corresponding to the second storage cell.

7. The storage device of claim 1, wherein, a third word line is disposed between the first word line connected with the first storage cell and the second word line connected with the second storage cell.

8. The storage device of claim 1, wherein, the storage controller is further configured to, after writing the first PLP data into the first storage cell and before writing the second PLP data into the second storage cell, write dummy data into a third storage cell connected with the third word line.

9. The storage device of claim 8, wherein, ​ 10. The storage device of claim 1, wherein, The storage controller is further configured to, after the sudden power loss termination, read the first PLP data and the second PLP data stored in the PLP area, and complete processing of the first PLP data and the second PLP data.

11. A storage device, comprising: a non-volatile storage device including an array of storage cells, the array of storage cells including a user area and a power loss protection (PLP) area; and a storage controller configured to, based on detecting a sudden power loss, write first PLP data to first storage cells of the PLP area connected to a first word line, write dummy data to second storage cells of the PLP area connected to a second word line, and write second PLP data to third storage cells of the PLP area connected to a third word line adjacent to the second word line and having a second write energy, wherein the second word line is adjacent to each of the first word line and the third word line, and wherein a first write energy of the first storage cells is less than the second write energy of the second storage cells.

12. The storage device of claim 11, wherein, the first write energy corresponds to a first program voltage for writing the first PLP data to the first storage cells, a first tunneling current for writing the first PLP data to the first storage cells, and a duration of applying the first program voltage to write the first PLP data to the first storage cells, and wherein the second write energy corresponds to a second program voltage for writing the second PLP data to the second storage cells, a second tunneling current for writing the second PLP data to the second storage cells, and a duration of applying the second program voltage to write the second PLP data to the second storage cells.

13. The storage device of claim 11, wherein, a first level of the first program voltage for writing the first PLP data to the first storage cells is lower than a second level of the second program voltage for writing the second PLP data to the second storage cells.

14. The storage device of claim 11, wherein, a number of first program cycles performed to write the first PLP data to the first storage cells is less than a number of second program cycles performed to write the second PLP data to the second storage cells.

15. The storage device of claim 11, wherein, a first duration of applying the first program voltage to write the first PLP data to the first storage cells is shorter than a second duration of applying the second program voltage to write the second PLP data to the second storage cells.

16. A storage device, comprising: a non-volatile storage device including an array of storage cells, the array of storage cells including a plurality of cell strings extending in a direction perpendicular to a substrate, wherein each of the plurality of cell strings includes at least one string select transistor, a plurality of storage cells connected in series, and at least one ground select transistor; and a storage controller configured to write first user data to first storage cells among the plurality of storage cells, and write second user data to second storage cells among the plurality of storage cells, wherein the first storage cells are connected to a first word line, the second storage cells are connected to a second word line adjacent to the first word line, and the second word line is adjacent to a third word line having a third write energy. The first write energy of the first memory cell is less than the second write energy of the second memory cell.

17. The storage device of claim 16, wherein, A third memory cell among the plurality of memory cells is disposed between the first memory cell and the second memory cell.

18. The storage device of claim 17, wherein, The memory controller is further configured to write dummy data to the third memory cell after the first user data is written to the first memory cell and before the second user data is written to the second memory cell.

19. The storage device of claim 16, wherein, A first level of a first program voltage used to write the first user data to the first memory cell is lower than a second level of a second program voltage used to write the second user data to the second memory cell.

20. The storage device of claim 16, wherein, A number of first program cycles performed to write the first user data to the first memory cell is less than a number of second program cycles performed to write the second user data to the second memory cell.

Images