Airborne AFDX (Avionics Full Duplex Switched Ethernet) data acquisition card and AFDX data acquisition method thereof

Abstract

The invention provides an airborne AFDX (avionics full duplex switched Ethernet) data acquisition card and an AFDX data acquisition method thereof, relates to the technical field of avionics, and solves the problems that an existing acquisition scheme is poor in vibration resistance, large in size and difficult to directly, stably and reliably work in a harsh airborne environment. The acquisition card comprises a field programmable gate array (FPGA) serving as a core processing unit; the configuration memory is used for storing a configuration file of the FPGA; the high-speed cache memory supports the FPGA to carry out real-time data processing; the at least one AFDX data acquisition interface is used for being connected with an external AFDX bus, comprises an isolation transformer and an Ethernet physical layer chip, and is used for transmitting and receiving AFDX bus data; and the MCB bus interface is led out from the interior of the FPGA and is used for carrying out configuration management and data interaction with the main controller. The highly integrated hardware design of the invention can better adapt to the installation requirements of narrow space and precise layout in an airborne equipment cabin.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of avionics technology, and is applied to the bus data acquisition process of an airborne data network, in particular to an airborne AFDX data acquisition card and an AFDX data acquisition method thereof. BACKGROUND

[0002] With the continuous evolution of avionics technology, the avionics full-duplex switched Ethernet (AFDX) has become the core network standard for internal data exchange of modern aircraft avionics systems due to its high-speed, high-reliability and deterministic real-time communication capabilities. This network carries the interactive information of key systems such as flight control, navigation and display, and the integrity and correctness of its data flow are directly related to flight safety and system performance evaluation. Therefore, during the research and development verification, system integration and flight test phases of avionics equipment, reliable acquisition and subsequent analysis of the data transmitted on the bus have become a crucial and routine technical requirement.

[0003] Under this background, special data acquisition equipment for avionics full-duplex switched Ethernet bus has emerged. Currently, the mainstream design scheme of such data acquisition cards generally relies on general industrial computer architecture, and its hardware form adopts a standardized board structure, which is connected and exchanges data with the host computer through a specific edge connector. This design route aims to utilize the mature industrial computing ecosystem to quickly realize data reception, caching and uploading functions.

[0004] However, this close reliance on general computing platforms has exposed significant limitations for such acquisition equipment when facing harsh airborne application environments: the mechanical structure, especially the electrical interface part connected to the host, has a risk of reduced connection reliability under continuous and intense mechanical vibration and impact conditions, which may cause intermittent interruption of data transmission, which is unacceptable for analysis tasks requiring continuous recording. The standardized board size is often large, making it difficult to adapt to the installation requirements of compact space and precise layout in the cabin of airborne equipment. The entire acquisition system usually includes an independent industrial computer and ancillary equipment, and its volume, weight and power consumption do not meet the general pursuit of miniaturization, lightweight and low power consumption of airborne equipment. These factors collectively make it difficult for existing data acquisition cards based on general architecture to be directly, stably and long-term deployed in real aircraft environments for data capture work.

[0005] While existing technical solutions can achieve the basic functions of full-duplex switched Ethernet data acquisition in avionics, their inherent design forms present an irreconcilable contradiction with the stringent requirements of airborne application scenarios regarding the physical robustness, environmental adaptability, space utilization, and system integration of the equipment. This restricts the ability to acquire network data in-situ, efficiently, and with high fidelity during flight testing. Therefore, the industry urgently needs a new hardware design approach that can fundamentally improve the mechanical and electrical characteristics of data acquisition cards, making their physical form and robustness better suited to the special constraints of the airborne environment, thereby providing more direct and reliable equipment support for acquiring flight test data. Summary of the Invention

[0006] The purpose of this invention is to address the problems of existing AFDX data acquisition cards, which rely on general-purpose industrial control computer architectures, resulting in poor vibration resistance, large size, and difficulty in stable and reliable operation in harsh airborne environments. Therefore, this invention proposes an airborne AFDX data acquisition card and its AFDX data acquisition method. The airborne AFDX data acquisition card of this invention uses an FPGA as the core processing unit, capable of parsing dual-redundant AFDX bus signals. Each channel has independent parsing functions, capable of filtering multiple port numbers and multiple virtual links, parsing various message types, and selectively acquiring all message words on the bus and timestamping them. The highly integrated hardware design of this invention better adapts to the installation requirements of confined space and precise layout within airborne equipment bays.

[0007] The present invention employs the following technical solutions to achieve its objective: An airborne AFDX data acquisition card, the acquisition card comprising: Field-Programmable Gate Array (FPGA) serves as the core processing unit; A configuration memory, connected to the FPGA, is used to store the FPGA's configuration file; A high-speed cache memory, connected to the FPGA, is used to support the FPGA in real-time data processing; At least one AFDX data acquisition interface is provided for connecting to an external AFDX bus. The AFDX data acquisition interface includes an isolation transformer and an Ethernet physical layer chip, and is coupled to the FPGA to realize the transmission and reception of AFDX bus data. The MCB bus interface, implemented internally by the FPGA, is used for configuration management and data interaction with the main controller.

[0008] Preferably, the internal logic unit of the FPGA includes an Ethernet IP core for sending and receiving data frames through the Ethernet physical layer chip; the configuration memory is a FLASH memory; and the cache memory is a static random access memory (SRAM).

[0009] Preferably, the AFDX data acquisition interface is a dual-channel structure, including a first AFDX data acquisition interface and a second AFDX data acquisition interface, which are used to independently connect to two AFDX buses, A and B, respectively; the FPGA is configured to perform independent protocol parsing and processing on the data received through the first AFDX data acquisition interface and the second AFDX data acquisition interface.

[0010] Furthermore, the internal logic units of the FPGA are configured to perform redundancy management functions, which include: Two independent receiving channels are set up, corresponding to the first AFDX data acquisition interface and the second AFDX data acquisition interface respectively; in each independent receiving channel, the integrity of the received AFDX data frames is checked; for the same data packets from the two independent receiving channels, a first-come-first-served strategy is adopted to select the valid data packet that passes the check first and remove redundant data packets.

[0011] Specifically, the internal logic unit of the FPGA includes: An input buffer is used to receive AFDX data frames from the Ethernet physical layer chip; The packet filtering module is used to filter and select parameters for received AFDX data frames according to configuration information. The channel caching module is used to cache the filtered data based on the determined acquisition channel number; The effective data extraction module is used to extract effective information from the cached data; An output buffer is used to temporarily store the valid information and output it through the MCB bus interface.

[0012] This invention also provides an AFDX data acquisition method based on the aforementioned airborne AFDX data acquisition card, the method comprising the following steps: AFDX bus data is received through at least one AFDX data acquisition interface, and the FPGA performs protocol parsing and format conversion on the received data. The FPGA performs redundancy management on the parsed data, including verifying the same data packets from different AFDX data acquisition interfaces and selecting valid data packets based on a first-come-first-served strategy to remove redundancy. The valid data after redundancy management is packaged and cached; the packaging and caching process includes: filtering the data according to the configuration information and caching the data in the cache memory according to the channel number; The FPGA extracts valid information from the cached data and temporarily stores the extracted valid information in the output buffer. The valid data temporarily stored in the output buffer is sent to the main controller through the MCB bus interface.

[0013] Preferably, AFDX bus data is received through at least one AFDX data acquisition interface, specifically by receiving data from two AFDX buses, A and B, through dual independent AFDX data acquisition interfaces. When the FPGA performs protocol parsing and format conversion on the received data, the data acquisition from each AFDX data acquisition interface is executed independently and in parallel within the FPGA.

[0014] Furthermore, the FPGA performs redundancy management on the parsed data, including: setting up independent data receiving channels and frame verification modules for the A and B AFDX buses within the FPGA; performing integrity verification on the AFDX data frames received by the corresponding channels through the frame verification modules of each channel; when data frames from different channels are identified as the same data packet, comparing their verification times, and selecting the data frame that passes the verification first as the valid data frame to enter the subsequent buffer, while discarding the redundant data frames of the other channel.

[0015] Specifically, the packet filtering in the packaging and caching process involves filtering data frames based on the configured virtual link identifier, port number, or message type information; and caching data according to channel number involves writing the filtered data into the corresponding channel cache area in the cache memory according to its acquisition channel number.

[0016] Specifically, before the FPGA performs protocol parsing and format conversion on the received data, a configuration step is also included: after the onboard AFDX data acquisition card is powered on, the FPGA loads the logic configuration file from the configuration memory; the FPGA receives configuration management information from the main controller through the MCB bus interface and completes the configuration of operating parameters, including filtering parameters and caching strategies.

[0017] In summary, due to the adoption of this technical solution, the beneficial effects of this invention are as follows: This invention significantly reduces the number and types of components on the board by using a highly integrated FPGA as a single core processing unit, supplemented by dedicated interface circuitry. This design allows for a substantial reduction in the physical size of the entire acquisition card, resulting in a more compact structure and lighter weight. This enables it to better adapt to the installation requirements of confined spaces and precise layouts within airborne equipment bays, achieving miniaturization and weight reduction of the equipment itself.

[0018] The airborne AFDX data acquisition card of this invention interacts with the internal bus of airborne equipment via a board-to-board connection. By incorporating existing, mature inter-board fixing methods, it enhances the connection stability and physical reliability of the card under continuous mechanical vibration compared to traditional gold-finger connectors.

[0019] This invention employs an independent dual-channel acquisition and intelligent redundancy management strategy implemented on FPGA. This ensures that when facing a dual-redundant AFDX bus, two data streams can be processed in parallel, and the optimal data is automatically selected. This mechanism not only improves compatibility with high-reliability bus architectures but also effectively avoids the risk of data loss due to a single channel failure, thereby comprehensively enhancing the integrity and reliability of the data acquisition process.

[0020] This invention achieves end-to-end hardware acceleration processing, from protocol parsing and filtering / caching to data output, through the configuration of the FPGA's internal logic. This approach avoids the latency and bottlenecks caused by frequent data movement between multiple hardware units in traditional solutions, significantly improving the real-time performance and throughput efficiency of data processing. The use of a high-speed cache memory smooths the data flow, ensuring stable operation even under sudden high loads.

[0021] This invention provides the data acquisition card with flexibility to meet different testing needs through configurable filtering, caching, and output mechanisms. Users can remotely configure the acquisition strategy through the main controller according to specific tasks, enabling the data acquisition card to adapt to the data acquisition requirements of various aircraft models or different testing phases, thus expanding its application scope and simplifying the configuration of ground support systems. Attached Figure Description

[0022] The present invention is described in detail with reference to the following figures, which include four figures as follows: Figure 1 This is a schematic diagram illustrating the application interconnection of the airborne AFDX data acquisition card of the present invention; Figure 2 This is a schematic diagram of the composition structure of the airborne AFDX data acquisition card of the present invention; Figure 3 This is a schematic block diagram of the AFDX receiver redundancy management function in this invention; Figure 4 This is a schematic diagram of the AFDX data processing flow in this invention. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0024] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0025] Example 1 This embodiment provides an airborne AFDX data acquisition card, which is suitable for airborne environments and used to acquire avionics full-duplex switched Ethernet AFDX data. Figure 1 As shown, the data acquisition card is integrated into a data acquisition chassis, forming part of a complete data acquisition system. In this system, the acquisition card connects externally to the aircraft's avionics via two independent AFDX bus interfaces, specifically named AFDX Bus A and AFDX Bus B, to receive dual-redundant AFDX network data streams. Internally, the acquisition card connects to the main controller, also located within the chassis, via an MCB bus. The main controller is responsible for the unified configuration, management, and control of the acquisition card, and receives the data processed by the acquisition card. The entire data acquisition chassis can upload the aggregated data to ground-based or airborne data analysis equipment for in-depth analysis via uplinks such as Ethernet. This application architecture allows the acquisition card to be tightly embedded as a dedicated, high-performance data acquisition front-end into the airborne test system.

[0026] like Figure 2 As shown, the airborne AFDX data acquisition card in this embodiment adopts a highly integrated hardware circuit design, with a Field-Programmable Gate Array (FPGA) chip at its core. This FPGA is the card's sole central processing unit, and all critical data processing, protocol parsing, and logic control tasks are performed by logic circuits programmed within it. The memory connected to the FPGA is mainly of two types: configuration memory and cache memory.

[0027] In this embodiment, a FLASH memory is used for configuration storage; this FLASH memory is used to store the FPGA's firmware program and hardware configuration file. When the acquisition card powers on, the FPGA automatically loads the logic configuration required for its operation from this FLASH memory to ensure correct functional initialization.

[0028] In this embodiment, the cache memory uses a static random access (SRAM) memory. This SRAM provides high-speed data buffer space for the FPGA to cope with the burstiness and high rate of the AFDX bus data stream, ensuring that data is not lost due to insufficient transmission during real-time processing, thus guaranteeing the stability and response speed of the processing.

[0029] In terms of interfaces, the acquisition card has two identical AFDX data acquisition interfaces, corresponding to AFDX buses A and B in the system interconnection, respectively. Each AFDX data acquisition interface consists of a physical layer isolation transformer and an Ethernet physical layer chip. The isolation transformer provides electrical isolation from the external AFDX bus, enhancing the system's anti-interference capability and security. The Ethernet physical layer chip is responsible for encoding, decoding, and driving physical layer signals. The signals from both interfaces are directly connected to the FPGA, and the reception of AFDX data frames is achieved through the Ethernet Media Access Controller IP core instantiated within it.

[0030] In addition, the data acquisition card features an MCB bus interface. This interface is not implemented by a separate physical chip, but rather through a logic interface programmed into the FPGA. It provides address, data, and control signal lines conforming to the MCB bus specification for high-speed and reliable data interaction and command transmission with the main controller. The data acquisition card also includes essential power management circuitry, clock generation and distribution circuitry, and reset circuitry. These modules provide a stable and reliable operating environment for the core components, ensuring stable operation of the entire board in complex airborne electrical environments.

[0031] In this embodiment, the data acquisition card operates based on logic functions implemented within the FPGA. These logic modules work together to complete the entire process from data reception to data output. This embodiment corresponds to two AFDX data acquisition interfaces, and the FPGA internally sets up two independent receiving and parsing channels. For example... Figure 3 As shown, each channel includes an interface module and an integrity verification module. When data enters the FPGA from the AFDX bus through the physical layer chip, the corresponding interface module immediately performs protocol parsing and format conversion to restore the standard AFDX frame structure. Subsequently, the integrity verification module verifies the data frame, such as checking whether the frame verification sequence is correct, to determine whether the frame data is valid. This design allows data from the A and B buses to be processed in parallel and independently, without interference.

[0032] As a preferred embodiment, an important component of the FPGA logic is the redundancy management function for a dual-redundant AFDX bus design. For example... Figure 3As shown, while processing data, the two channels also perform intelligent redundancy detection and rejection. The FPGA identifies whether data frames from buses A and B belong to the same data packet. When the integrity verification modules of both channels report receiving valid data packets identified as having the same sequence number or virtual link identifier, the redundancy management logic activates a "first-come, first-served" strategy. The FPGA compares the time points when these two valid data packets pass through their respective verification modules and marks only the first data packet that passes verification as valid, allowing it to enter the subsequent processing flow, while discarding the other data packet that arrives later as a redundant frame. This mechanism ensures that downstream processing units always receive the most timely and valid data from the dual buses, achieving both the security benefits of redundancy backup and avoiding resource waste and chaos caused by duplicate data processing.

[0033] After redundancy management, the data frames will enter the data packaging and caching stage. For example... Figure 4 As shown, the FPGA internally includes a packet filtering module. This module filters data frames based on configuration information downloaded from the main controller via the MCB bus. For example, the configuration information can specify a list of virtual link identifiers, a range of port numbers, or message types to be acquired. The acquisition card in this embodiment preferably supports filtering up to 512 independent virtual links and 1024 different port numbers, and can identify 1024 message types. Users can flexibly configure the acquisition of all data or only the data of interest according to their testing needs. Data frames that pass the filtering are assigned an acquisition channel number and sent to the channel buffer module for temporary storage. The channel buffer module allocates corresponding buffer space in SRAM; for example, it can provide a 1024-bit deep, 16-bit wide first-in-first-out buffer for up to eight logic channels, ensuring a smooth data flow and handling instantaneous data spikes.

[0034] Subsequently, the valid data extraction module reads data from the channel buffer and, according to the configured extraction rules, extracts valid message words from the original AFDX frame, filtering out invalid information such as protocol headers and padding, thereby improving the efficiency of data storage and transmission. The extracted valid data is sent to the output buffer; in this embodiment, the output buffer is also configured as a first-in-first-out queue with a depth of 512 bits and a width of 16 bits, used to temporarily store processed data waiting to be uploaded. Finally, the data output logic continuously sends the data in the output buffer to the main controller through the MCB bus interface in an efficient data block transmission mode. In the entire processing chain, the FPGA can also assign a high-precision timestamp to each successfully received AFDX data frame that enters the processing flow. In this embodiment, the timestamp resolution can reach 1µs, which provides a reliable basis for subsequent accurate timing analysis of the data.

[0035] The airborne AFDX data acquisition card in this embodiment uses an FPGA as its core hardware architecture, enabling independent reception of dual-channel AFDX data, intelligent redundancy elimination, flexible configuration filtering, and efficient buffered output. Its compact structure eliminates the traditional design that relies on the expansion slot of a general-purpose industrial control computer. It can be connected to the MCB bus on the backplane of the chassis via an onboard connector, making the card small in size and significantly more shock-resistant than cards using gold finger interfaces. It is very suitable for airborne applications with limited space and harsh environments.

[0036] Example 2 Based on Example 1, this example provides an AFDX data acquisition method using its airborne AFDX data acquisition card. This example will focus on introducing the complete process steps and internal collaborative working mechanism of data acquisition, processing and output using the acquisition card hardware in Example 1.

[0037] The execution subject of this embodiment is an airborne AFDX data acquisition card, and its hardware foundation and system connection relationship are as follows: Figure 1 As shown. Before starting the method, the acquisition card needs to be integrated into the data acquisition chassis and connected to the main controller via the MCB bus. At the same time, its two AFDX data acquisition interfaces (labeled as Interface A and Interface B respectively) have been correctly connected to the dual-redundant AFDX network of the avionics device under test, namely Bus A and Bus B.

[0038] The initial steps of the method are system power-on and configuration loading. After the acquisition card is powered on, its core processing unit FPGA automatically reads the firmware and hardware configuration file from the onboard configuration FLASH memory to complete the initialization of its own logic functions. Subsequently, the FPGA enters a standby state through the MCB bus interface, waiting for and receiving configuration management information from the main controller. The configuration management information determines the detailed rules for subsequent data processing, such as: the list of AFDX virtual link identifiers to be monitored and acquired, the port number filtering range, the message types to be parsed, and whether to acquire all message words on the bus, etc. In this embodiment, it is preferred to support independent configuration of up to 512 virtual links, 1024 port numbers, and 1024 message types. The FPGA's internal logic initializes and sets up various processing modules such as the packet filtering module and the channel buffer module according to these received configuration parameters, preparing for real-time data acquisition.

[0039] After configuration is complete, the method enters the data receiving and parsing phase. For example... Figure 2As shown, the data streams on the two AFDX buses enter the acquisition card through isolation transformers and Ethernet PHY chips. Inside the FPGA, two independent Ethernet MAC IP cores corresponding to interface A and interface B operate continuously, receiving serial data from their respective physical layer chips and assembling them into complete Ethernet / AFDX data frames. This process is parallel and independent, ensuring synchronous processing capability for dual-channel data input. For each received data frame, the FPGA's dedicated protocol parsing logic immediately processes it, including stripping the physical layer and link layer headers, parsing the frame content, virtual link ID, sequence number, destination port, and other key fields according to the AFDX protocol specification, and performing necessary format conversions to transform the network byte stream into an internal data format suitable for subsequent module processing. This parsing process establishes the foundation for the correct identification and classification of each data packet.

[0040] The next step is redundancy management and validity verification, the logical flow of which can also be found in [link to documentation]. Figure 3 The diagram illustrates this. After initial parsing, the data frame is immediately sent to the integrity verification module of its respective A or B channel. This verification module performs a deep check on the data frame, such as calculating and comparing the frame verification sequence to confirm that no errors occurred during transmission and determine whether it is a valid frame. Simultaneously, the redundancy management logic begins working, using the parsed virtual link ID and sequence number to determine in real time whether data frames from the two independent channels A and B belong to the same application data packet, i.e., redundantly transmitted identical data. When both channels receive the same data packet almost simultaneously and both pass the validity check, the system will initiate a "first-come, first-served" decision mechanism. This mechanism compares the time points when the two valid frames pass through their respective verification modules (the system timestamp accuracy is preferably 1µs), and only allows the data frame that passes verification first to enter the subsequent processing pipeline, while the other data frame arriving later is immediately discarded as a redundant frame. This strategy is implemented in hardware logic, enabling judgments at the microsecond level, fully utilizing the high reliability of the dual-redundancy network while avoiding the repeated processing of identical data, effectively saving buffer and transmission resources.

[0041] Valid data frames selected through redundancy management then enter the configuration-based intelligent filtering and caching stage, and the data processing flow is as follows: Figure 4As shown. At this point, the packet filtering module inside the FPGA operates, quickly comparing the virtual link ID, port number, message type, and other characteristics of the current data frame with the configuration table loaded from the main controller during the initialization phase. Based on the user's configuration intent, the filtering module decides whether to allow all data in the frame to pass, partially extract it, or discard it completely. For example, when configured to collect data from a few specific virtual links, frames not belonging to these virtual links will be filtered out; if configured to collect all messages, all frames will pass. Data that passes the filter is assigned a logical channel number, which can be categorized according to its source or type, and is then written to the corresponding channel buffer in SRAM.

[0042] In this embodiment, the channel buffer is organized in a first-in-first-out (FIFO) queue, with a depth of up to 1024 data units and a width of 16 bits. This smooths out fluctuations in the data stream and prevents data loss due to high-speed data bursts. During this process, the FPGA assigns a high-precision timestamp to each successfully received and buffered data frame. This timestamp records the arrival time of the frame at a resolution of 1µs, enabling subsequent precise timing analysis.

[0043] The method concludes with data extraction and uploading. When data accumulates to a certain amount in the channel buffer or meets specific triggering conditions, the effective data extraction module is activated. This module, based on its configuration, extracts the payload portion ("message words") of interest to the user from the buffered raw AFDX frame data. It may discard unnecessary information such as protocol headers and padding bytes, thus significantly compressing the amount of data that needs to be uploaded and improving overall transmission efficiency. The extracted clean and valid data is temporarily stored in a dedicated output buffer, which also uses a first-in-first-out queue with a depth of 512 data units.

[0044] Ultimately, the data output control logic within the FPGA transmits data in batches from the output buffer to the main controller within the data acquisition chassis via the MCB bus interface, using a high-bandwidth, low-latency block transmission method, either proactively or in response to requests from the main controller. After receiving the data, the main controller can further transmit the aggregated data from all acquisition cards to the backend analysis equipment via the chassis's uplink Ethernet interface.

[0045] This embodiment completes the entire process of physical layer signal reception, protocol parsing, redundancy deduplication, intelligent filtering, and efficient uploading. The entire process is pipelined within the FPGA hardware logic, enabling reliable, real-time, and flexible acquisition of AFDX network data in harsh airborne environments.

Claims

1. An airborne AFDX data acquisition card, characterized in that, The data acquisition card includes: Field-Programmable Gate Array (FPGA) serves as the core processing unit; A configuration memory, connected to the FPGA, is used to store the FPGA's configuration file; A high-speed cache memory, connected to the FPGA, is used to support the FPGA in real-time data processing; At least one AFDX data acquisition interface is provided for connecting to an external AFDX bus. The AFDX data acquisition interface includes an isolation transformer and an Ethernet physical layer chip, and is coupled to the FPGA to realize the transmission and reception of AFDX bus data. The MCB bus interface, implemented internally by the FPGA, is used for configuration management and data interaction with the main controller.

2. The airborne AFDX data acquisition card according to claim 1, characterized in that: The internal logic unit of the FPGA includes an Ethernet IP core for sending and receiving data frames through the Ethernet physical layer chip; the configuration memory is a FLASH memory; and the cache memory is a static random access memory (SRAM).

3. The airborne AFDX data acquisition card according to claim 1, characterized in that: The AFDX data acquisition interface is a dual-channel structure, including a first AFDX data acquisition interface and a second AFDX data acquisition interface, which are used to independently connect to two AFDX buses, A and B, respectively; the FPGA is configured to perform independent protocol parsing and processing on the data received through the first AFDX data acquisition interface and the second AFDX data acquisition interface.

4. The airborne AFDX data acquisition card according to claim 3, characterized in that, The internal logic units of the FPGA are configured to perform redundancy management functions, which include: Two independent receiving channels are set up, corresponding to the first AFDX data acquisition interface and the second AFDX data acquisition interface respectively; in each independent receiving channel, the integrity of the received AFDX data frames is checked; for the same data packets from the two independent receiving channels, a first-come-first-served strategy is adopted to select the valid data packet that passes the check first and remove redundant data packets.

5. The airborne AFDX data acquisition card according to claim 1, characterized in that, The internal logic unit of the FPGA includes: An input buffer is used to receive AFDX data frames from the Ethernet physical layer chip; The packet filtering module is used to filter and select parameters for received AFDX data frames according to configuration information. The channel caching module is used to cache the filtered data based on the determined acquisition channel number; The effective data extraction module is used to extract effective information from the cached data; An output buffer is used to temporarily store the valid information and output it through the MCB bus interface.

6. An AFDX data acquisition method using an airborne AFDX data acquisition card according to any one of claims 1-5, characterized in that, The method includes the following steps: AFDX bus data is received through at least one AFDX data acquisition interface, and the FPGA performs protocol parsing and format conversion on the received data. The FPGA performs redundancy management on the parsed data, including verifying the same data packets from different AFDX data acquisition interfaces and selecting valid data packets based on a first-come-first-served strategy to remove redundancy. The valid data after redundancy management is packaged and cached. The packaging and caching process includes: filtering data according to configuration information and caching the data in the cache memory according to the channel number; The FPGA extracts valid information from the cached data and temporarily stores the extracted valid information in the output buffer. The valid data temporarily stored in the output buffer is sent to the main controller through the MCB bus interface.

7. The AFDX data acquisition method according to claim 6, characterized in that, Receive AFDX bus data through at least one AFDX data acquisition interface, specifically: receive data from two AFDX buses, A and B, respectively, through two independent AFDX data acquisition interfaces. When the FPGA performs protocol parsing and format conversion on the received data, the data acquisition from each AFDX data acquisition interface is executed independently and in parallel within the FPGA.

8. The AFDX data acquisition method according to claim 7, characterized in that, The FPGA performs redundancy management on the parsed data, including: setting up independent data receiving channels and frame verification modules for the A and B AFDX buses within the FPGA; performing integrity verification on the AFDX data frames received by the corresponding channels through the frame verification modules of each channel; when data frames from different channels are identified as the same data packet, comparing their verification times, and selecting the data frame that passes the verification first as the valid data frame to enter the subsequent buffer, while discarding the redundant data frames of the other channel.

9. The AFDX data acquisition method according to claim 6, characterized in that, The packet filtering in the packaging and caching process specifically involves: filtering data frames based on the configured virtual link identifier, port number, or message type information; and caching data according to channel number specifically involves: writing the filtered data into the corresponding channel cache area in the cache memory according to its acquisition channel number.

10. The AFDX data acquisition method according to claim 6, characterized in that, Before the FPGA performs protocol parsing and format conversion on the received data, a configuration step is also included: after the onboard AFDX data acquisition card is powered on, the FPGA loads the logic configuration file from the configuration memory; The FPGA receives configuration management information from the main controller through the MCB bus interface and completes the configuration of operating parameters, including filtering parameters and caching strategies.

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