Memory training optimization method and device, controller and storage medium

Abstract

The invention provides a memory training optimization method and device, a controller and a storage medium, and the method comprises the steps: obtaining an initial sampling window of a target signal outputted by a memory physical interface based on automatic training when a memory chip is started for the first time; optimization training is executed on the initial sampling window, a target sampling window is obtained, and the width of the target sampling window is smaller than that of the initial sampling window; determining an optimal sampling point based on the target sampling window, and writing the optimal sampling point into a nonvolatile memory; and when the memory chip is subsequently started, reading the optimal sampling point from the nonvolatile memory, and writing the optimal sampling point into the memory physical interface. Therefore, the initial sampling window is narrowed and calibrated, an edge area with unstable signal sampling is eliminated, meanwhile, the optimal sampling point is directly read during subsequent starting, the automatic training process is skipped, and stability and efficiency are both considered.

Description

Technical Field

[0001] This application relates to the field of computer technology, and specifically to an optimization method, apparatus, controller, and storage medium for memory training. Background Technology

[0002] In computer systems, the controller and memory chips transmit signals through a physical memory interface. To ensure the accuracy of signal transmission, the physical memory interface can automatically train the timing relationship between the scanning clock and the signal during memory chip startup to determine the optimal sampling window and optimal sampling point. However, the sampling window output by the automatic training is not stable and may even result in read / write errors. Furthermore, the memory needs to be trained repeatedly every time it starts up, significantly increasing startup time. Summary of the Invention

[0003] This application provides an optimization method, apparatus, controller, and storage medium for memory training, aiming to optimize existing memory training, improve the stability of signal sampling, and reduce the startup time of memory chips.

[0004] In a first aspect, embodiments of this application provide an optimization method for in-memory training, comprising: Upon the initial startup of the memory chip, the initial sampling window of the memory physical interface is obtained based on the target signal output by automatic training. Optimization training is performed on the initial sampling window to obtain a target sampling window, the width of which is smaller than the width of the initial sampling window; The optimal sampling point is determined based on the target sampling window, and the optimal sampling point is written into non-volatile memory; During subsequent startup of the memory chip, the optimal sampling point is read from the non-volatile memory and written to the memory physical interface.

[0005] Secondly, embodiments of this application provide an optimization apparatus for memory training, comprising: The acquisition unit is used to acquire the initial sampling window of the memory physical interface based on the target signal output by automatic training when the memory chip is first started. A training unit is used to perform optimization training on the initial sampling window to obtain a target sampling window, wherein the width of the target sampling window is smaller than the width of the initial sampling window; The determining unit is used to determine the optimal sampling point based on the target sampling window and write the optimal sampling point into a non-volatile memory; The read / write unit is used to read the optimal sampling point from the non-volatile memory and write the optimal sampling point to the memory physical interface during subsequent startup of the memory chip.

[0006] Thirdly, embodiments of this application provide a controller including a processor, a memory, and one or more programs, the one or more programs being stored in the memory and configured to be executed by the processor, the programs including instructions for performing steps in the method as described in the first aspect of this application.

[0007] Fourthly, embodiments of this application provide a computer-readable storage medium having a computer program or instructions stored thereon, wherein the computer program or instructions, when executed by a processor, implement the steps of the method described in the first aspect of this application.

[0008] As can be seen in this embodiment, when the memory chip is first started, the controller obtains the initial sampling window of the target signal output by the memory physical interface based on automatic training. Then, it performs optimization training on the initial sampling window to obtain a smaller target sampling window. Based on the target sampling window, it determines the optimal sampling point and writes it to non-volatile memory. During subsequent startups of the memory chip, it directly reads the optimal sampling point from the non-volatile memory and writes it to the memory physical interface, skipping the automatic training process. In this way, by narrowing and calibrating the sampling window of the target signal output by the memory physical interface based on automatic training, unstable edge regions of signal sampling are eliminated. At the same time, the calibrated and optimized optimal sampling point is directly read during subsequent startups, skipping the automatic training process that must be executed on each startup. This improves the accuracy of signal sampling and shortens the system startup time. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a structural block diagram of a computer system provided in an embodiment of this application; Figure 2 This is a flowchart illustrating an optimization method for memory training provided in an embodiment of this application; Figure 3 This is a simplified illustration of an example of performing a first calibration operation on an initial sampling window, provided in an embodiment of this application. Figure 4 This is a simplified diagram illustrating another example of performing a first calibration operation on an initial sampling window, as provided in an embodiment of this application. Figure 5This is a simplified illustration of an example of performing a second calibration operation on a first sampling window, provided in an embodiment of this application. Figure 6 This is a structural block diagram of an optimization device for memory training provided in an embodiment of this application; Figure 7 This is a structural block diagram of another memory training optimization device provided in an embodiment of this application; Figure 8 This is a schematic diagram of the structure of a controller provided in an embodiment of this application. Detailed Implementation

[0011] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0012] The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0013] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0014] In computer systems, correct reading and writing of memory data depends on the stable sampling of memory interface signals within the effective sampling window. Memory interface signals refer to the signals transmitted between the controller and the memory chip through the physical memory interface, including data (DQ) signals, data mask (DM) signals, and data strobe (DQS) signals. Current technology determines the optimal sampling window for these signals by performing automatic training on the memory through the physical memory interface. However, in practical applications, this sampling window contains unstable edge regions, meaning the signal levels are unstable in these regions and are highly susceptible to interference, potentially leading to read / write errors. Furthermore, each memory startup requires repeated training, significantly increasing startup time. In production testing, this necessitates spending considerable time copying data, resulting in extremely high testing costs.

[0015] To address the aforementioned issues, embodiments of this application provide an optimization method, apparatus, controller, and storage medium for memory training.

[0016] Please see Figure 1 , Figure 1 This is a structural block diagram of a computer system provided in an embodiment of this application. For example... Figure 1 As shown, the computer system 10 includes a controller 11, a memory physical interface 12, a memory chip 13, and a non-volatile memory 14. The controller 11 is connected to both the memory physical interface 12 and the non-volatile memory 14, and the memory physical interface 12 is connected to the memory chip 13. Specifically, the computer system 10 is implemented as a PCB (Printed Circuit Board), serving as the support for various electronic components. The controller 11 includes logic circuits with logical computing capabilities, such as a microcontroller unit (MCU). The memory chip 13 is implemented, for example, as a Double Data Rate SDRAM (DDR). The memory physical interface 12 can specifically be a physical interface (PHY). The non-volatile memory 14 can specifically be implemented as an electrically erasable programmable read-only memory (EEPROM), flash memory, a solid-state drive (SSD), etc.

[0017] The following describes an optimization method for memory training provided by an embodiment of this application.

[0018] Please see Figure 2 , Figure 2This is a flowchart illustrating an optimization method for memory training provided in an embodiment of this application. Figure 2 As shown, the method includes: S201, during the first startup of the memory chip, acquires the initial sampling window of the target signal output by the memory physical interface based on automatic training.

[0019] In this embodiment, the storage structure of the non-volatile memory further includes a counter bit, which is initialized to 0 and used to characterize the number of times the memory chip has been booted. The counter bit increments by 1 after each successful boot. When the memory chip boots, the controller can determine the number of boots based on the counter bit. When the counter bit is detected to be 0, it is determined that the memory chip is booting for the first time. The target signal is a memory interface signal, including the DQ signal, DM signal, and DQS signal.

[0020] S202, perform optimization training on the initial sampling window to obtain the target sampling window.

[0021] The target sampling window is narrower than the initial sampling window. This means that the initial sampling window is narrowed and calibrated through optimized training to eliminate unstable edge regions of signal sampling and concentrate the margin in the central region. Even if timing offsets are caused by external factors, the sampling points can still be guaranteed to fall within the stable range, thus avoiding read and write errors.

[0022] S203, determine the optimal sampling point based on the target sampling window, and write the optimal sampling point into the non-volatile memory.

[0023] The optimal sampling point refers to the reference point in the target sampling window where the signal level is most stable and the degree of interference is minimal. This point is written into non-volatile memory for direct reading and use after subsequent startup, skipping the automatic training process.

[0024] S204, during the subsequent startup of the memory chip, the optimal sampling point is read from the non-volatile memory and written to the memory physical interface.

[0025] When the memory chip starts up, it reads the counter bit of the non-volatile memory. When the counter bit is not 0, it determines that the memory chip will start later. It directly reads the best sampling point from the non-volatile memory and writes it to the memory physical interface through bypass mode, skipping the automatic training process of the memory physical interface and shortening the startup time.

[0026] As can be seen, in this embodiment, when the memory chip is first started, the controller obtains the initial sampling window of the target signal output by the memory physical interface based on automatic training. Then, it performs optimization training on the initial sampling window to obtain a narrower target sampling window. Based on the target sampling window, it determines the optimal sampling point and writes it to non-volatile memory. During subsequent startups of the memory chip, the optimal sampling point is directly read from the non-volatile memory and written to the memory physical interface, skipping the automatic training process. Thus, by narrowing and calibrating the sampling window of the target signal output by the memory physical interface based on automatic training, unstable edge regions of signal sampling are eliminated. Simultaneously, the calibrated and optimized optimal sampling point is directly read during subsequent startups, skipping the automatic training process that must be executed on each startup. This improves the accuracy of signal sampling and shortens the system startup time.

[0027] In one possible example, the step of performing optimization training on the initial sampling window to obtain the target sampling window includes: performing a first calibration operation on the initial sampling window with a first preset step size to obtain a first reference left boundary and a first reference right boundary; wherein, the first calibration operation includes: adjusting the left boundary of the sampling window incrementally to the right, and performing read / write verification based on the adjusted left boundary until the read / write verification is successful, and determining the left boundary when the read / write verification is successful as the reference left boundary of the sampling window; and adjusting the right boundary of the sampling window incrementally to the left, and performing read / write verification based on the adjusted right boundary until the read / write verification is successful, and determining the right boundary when the read / write verification is successful as the reference right boundary of the sampling window; and determining the target sampling window based on the first reference left boundary and the first reference right boundary.

[0028] The first calibration operation is a narrowing calibration operation of the sampling window. Specifically, it involves adjusting the left boundary of the sampling window incrementally to the right and performing read / write verification based on the adjusted left boundary until the read / write verification is successful. This indicates that the sampling point corresponding to the adjusted left boundary is available, and the left boundary at the time of successful read / write verification is determined as the reference left boundary. Similarly, the right boundary of the sampling window is adjusted incrementally to the left and performing read / write verification based on the adjusted right boundary until the read / write verification is successful. This indicates that the sampling point corresponding to the adjusted right boundary is available, and the right boundary at the time of successful read / write verification is determined as the reference right boundary.

[0029] The single adjustment amount is the first preset step size, which is a timing adjustment unit set based on the conventional delay adjustment accuracy of the memory physical interface. It matches the efficiency requirements when narrowing and calibrating the initial sampling window, and determines the adjusted left and right boundaries more quickly.

[0030] Specifically, the read / write verification includes: generating sufficient random data, writing the random data to a specified storage address of the memory chip according to the adjusted sampling timing, reading the data from the same storage address after a preset delay, comparing the read data with the original random data bit by bit, and determining that the read / write verification of the current sampling timing is successful if the data comparison results of the consecutive preset number of read / write operations are completely consistent. If any data error occurs, the read / write verification is determined to be unsuccessful.

[0031] After the first calibration operation, the left and right boundaries of the initial sampling window are narrowed to the first reference left boundary and the first reference right boundary. The target sampling window is determined based on the first reference left boundary and the first reference right boundary, thereby eliminating the edge regions of the original sampling window where the signal sampling is unstable.

[0032] As can be seen, in this example, the controller performs a first calibration operation on the initial sampling window with a first preset step size, increasing the adjustment of the left boundary to the right and decreasing the adjustment of the right boundary to the left. The initial sampling window is narrowed and calibrated with successful read / write verification as the criterion, resulting in new left and right boundaries. The target sampling window is then determined, edge regions are eliminated, and the stability of signal sampling is improved.

[0033] In one possible example, determining the target sampling window based on the first reference left boundary and the first reference right boundary includes: determining the sampling window formed by the first reference left boundary and the first reference right boundary as a first sampling window; determining the first sampling window as a target sampling window when the width of the first sampling window is greater than or equal to a preset threshold; wherein the preset threshold is determined based on experimental data, the experimental data including the maximum left offset and the maximum right offset of sampling points under various working conditions, and the preset threshold is not less than the superposition value of the maximum left offset and the maximum right offset.

[0034] Different operating conditions can cause varying degrees of timing shifts in the sampling points of the target signal. For example, the resistance of PCB traces differs at different temperatures, leading to different signal propagation speeds and affecting the time it takes for the target signal to reach the controller. Simultaneously, the switching speed of transistors within the memory chip also varies with temperature, resulting in different degrees of timing shifts in the sampling points within the sampling window. Therefore, while narrowing and calibrating the initial sampling window, sufficient offset margin needs to be reserved to prevent the offset of sampling points under extreme operating conditions from exceeding the sampling window range, leading to read / write errors. Based on this, in this example, during the R&D phase, the maximum left and right offsets of sampling points under various operating conditions were statistically determined based on experimental data. A preset threshold, not less than the sum of these two values, was then established. Only when the width of the first sampling window, formed by the first reference left boundary and the first reference right boundary obtained after the first calibration operation, is greater than or equal to this preset threshold can the first sampling window be considered the target sampling window, thus providing sufficient space for the offset of sampling points under extreme operating conditions.

[0035] For example, such as Figure 3 As shown, the initial sampling window based on the target signal output by automatic training has a left boundary L0 of 10 and a right boundary R0 of 70, meaning the initial sampling window width is 60. A first preset step size of 8 is set, and a first calibration operation is performed. After the left boundary is adjusted to the right by two increments, read / write verification is successful, determining the new left boundary, i.e., the first reference left boundary L1, to be 26. After the right boundary is adjusted to the left by one increment, read / write verification is successful, determining the new right boundary, i.e., the first reference right boundary R1, to be 62. The resulting first sampling window width is 36. Assuming that experimental data verification shows the system's maximum left offset is 8 sampling points and the maximum right offset is 8 sampling points under various operating conditions, the preset threshold should be no less than 16. Assuming the preset threshold is 20, it can be determined that the window width of the first sampling window meets the fault tolerance requirements under extreme operating conditions, and this first sampling window is identified as the target sampling window.

[0036] As can be seen, in this example, the controller determines the sampling window formed by the first reference left boundary and the first reference right boundary as the first sampling window, and determines the width of the first sampling window based on the preset threshold determined by the experimental data. Only when the width of the first sampling window is greater than or equal to the preset threshold is it determined to be the target sampling window, thereby ensuring that the width of the target sampling window is sufficient to cover the sampling point offset range under various working conditions and improving the stability of signal sampling.

[0037] In one possible example, after determining the sampling window formed by the first reference left boundary and the first reference right boundary as the first sampling window, the method further includes: when the width of the first sampling window is less than the preset threshold, performing the first calibration operation on the initial sampling window with a second preset step size to obtain a second reference left boundary and a second reference right boundary, wherein the second preset step size is less than the first preset step size; determining the sampling window formed by the second reference left boundary and the second reference right boundary as the second sampling window; if the width of the second sampling window is greater than or equal to the preset threshold, then determining the second sampling window as the target sampling window; if the width of the second sampling window is less than the preset threshold, then outputting fault information.

[0038] In this example, when the width of the first sampling window is less than a preset threshold, the single adjustment amount is set to a smaller second preset step size, and the first calibration operation is re-performed on the initial sampling window to obtain the second reference left boundary and the second reference right boundary. The sampling window formed by these two boundaries is the second sampling window. The second preset step size is a timing adjustment unit set based on the minimum latency adjustment accuracy of the memory physical interface, matching the accuracy requirements of the secondary narrowing calibration of the initial sampling window, and more accurately determining the adjusted left and right boundaries. If the width of the second sampling window is greater than or equal to the preset threshold, then the second sampling window is determined to be the target sampling window; if the width of the second sampling window is still less than the preset threshold, it can be inferred that the system has an inherent hardware defect, such as substandard memory chip performance or damaged memory physical interface, and fault information is output to external devices to prompt maintenance personnel to perform subsequent hardware repairs and other processing.

[0039] For example, such as Figure 3 As shown, the initial sampling window has a left boundary L0 of 10 and a right boundary R0 of 70. The first preset step size is set to 8. The first calibration operation is performed, where the left boundary is adjusted three times to the right, and after successful read / write verification, the new left boundary, i.e., the first reference left boundary L1, is determined to be 34. The right boundary is adjusted two times to the left, and after successful read / write verification, the new right boundary, i.e., the first reference right boundary R1, is determined to be 54. The resulting first sampling window has a width of 20. Assuming that experimental data verification shows the system's maximum left offset is 12 sampling points and the maximum right offset is 10 sampling points under various operating conditions, the preset threshold should not be less than 22. If the preset threshold is 22, the window width of the first sampling window does not meet the fault tolerance requirements under extreme operating conditions. In this case, if... Figure 4As shown, the second preset step size is set to 5, and the first calibration operation is performed again on the initial sampling window. After the left boundary is adjusted to the right by 4 increments, the read and write verification is successful, and the new left boundary, namely the second reference left boundary L2, is determined to be 30. After the right boundary is adjusted to the left by 5 increments, the read and write verification is successful, and the new right boundary, namely the second reference right boundary R2, is determined to be 55. The width of the resulting second sampling window is 25, which is greater than the preset threshold of 22, and meets the fault tolerance requirements under extreme conditions. Therefore, the second sampling window is determined to be the target sampling window.

[0040] As can be seen in this example, when the width of the first sampling window is less than a preset threshold, the first calibration operation is re-performed on the initial sampling window with a smaller second preset step size to obtain the second reference left boundary and the second reference right boundary. The width of the resulting second sampling window is then determined based on the preset threshold. If the determination condition is met, the second sampling window is identified as the target sampling window; otherwise, a fault message is output to prompt maintenance personnel for inspection and subsequent processing. Thus, when the initial narrowing calibration does not meet the fault tolerance requirements, a more refined secondary calibration improves the accuracy of the sampling window calibration and enhances the stability of signal sampling.

[0041] In one possible example, after determining the sampling window formed by the first reference left boundary and the first reference right boundary as the first sampling window, the method further includes: when the width of the first sampling window is less than the preset threshold, performing a second calibration operation on the first sampling window with a second preset step size to obtain a third reference left boundary and a third reference right boundary, wherein the second preset step size is less than the first preset step size; wherein the second calibration operation includes: adjusting the left boundary of the sampling window to the left by decreasing it, and performing read / write verification based on the adjusted left boundary until the read / write verification fails, and determining the left boundary before the read / write verification failure as the reference left boundary of the sampling window; and adjusting the right boundary of the sampling window to the right by increasing it, and performing read / write verification based on the adjusted right boundary until the read / write verification fails, and determining the right boundary before the read / write verification failure as the reference right boundary of the sampling window; determining the sampling window formed by the third reference left boundary and the third reference right boundary as the third sampling window; if the width of the third sampling window is greater than or equal to the preset threshold, then determining the third sampling window as the target sampling window; if the width of the third sampling window is less than the preset threshold, then outputting fault information.

[0042] In this example, when the width of the first sampling window is less than a preset threshold, the single adjustment amount is set to a smaller second preset step size, and a second calibration operation is performed on the first sampling window to obtain a third reference left boundary and a third reference right boundary. The sampling window formed by these three boundaries is the third sampling window. The second calibration operation is a widening calibration operation of the sampling window. Specifically, it involves adjusting the left boundary of the sampling window to the left by decreasing the width, and performing read / write verification based on the adjusted left boundary until the read / write verification fails, indicating that the sampling point corresponding to the adjusted left boundary is unavailable. In this case, the previously adjusted left boundary is determined as the reference left boundary. Similarly, the right boundary of the sampling window is adjusted to the right by increasing the width, and read / write verification is performed based on the adjusted right boundary until the read / write verification fails, indicating that the sampling point corresponding to the adjusted right boundary is unavailable. In this case, the previously adjusted right boundary is determined as the reference right boundary.

[0043] After the second calibration operation, the first sampling window is widened into a third sampling window. If the width of the third sampling window is greater than or equal to a preset threshold, then the third sampling window is determined to be the target sampling window. If the width of the third sampling window is still less than the preset threshold, it can be inferred that there is an inherent defect at the hardware level in the system, and fault information is output to the external device to prompt the maintenance personnel to carry out subsequent processing such as hardware inspection.

[0044] For example, such as Figure 5 As shown, the left boundary (i.e., the first reference left boundary L1) of the first sampling window is 34, and the right boundary (i.e., the first reference right boundary R1) is 54, with a window width of 20. Assuming the preset threshold is 22, the window width of the first sampling window does not meet the fault tolerance requirements under extreme conditions. Setting the second preset step size to 5, a second calibration operation is performed on the first sampling window. The left boundary is adjusted to the left twice, resulting in a read / write verification failure (i.e., the third reference left boundary L3 is 29). The right boundary is adjusted to the right once, resulting in a read / write verification failure (i.e., the third reference right boundary R3 remains 54). The resulting third sampling window has a width of 25, which is greater than the preset threshold of 22, thus meeting the fault tolerance requirements under extreme conditions. Therefore, this third sampling window is determined as the target sampling window.

[0045] As can be seen in this example, when the width of the first sampling window is less than a preset threshold, a second calibration operation is performed on the first sampling window with a smaller second preset step size to obtain the third reference left boundary and the third reference right boundary. The width of the resulting third sampling window is then determined based on the preset threshold. If the determination condition is met, the third sampling window is identified as the target sampling window; otherwise, a fault message is output to prompt maintenance personnel for repair and subsequent processing. Thus, when the initial narrowing calibration does not meet the fault tolerance requirements, further widening calibration improves the accuracy of the sampling window calibration and enhances the stability of signal sampling.

[0046] In one possible example, determining the optimal sampling point based on the target sampling window includes: determining a center sampling point based on the target left and target right boundaries of the target sampling window; performing a state correction operation on the center sampling point to obtain the optimal sampling point; wherein the state correction operation includes: acquiring the state parameters of the memory chip, the state parameters including at least operating temperature, operating voltage, and cumulative runtime; calculating the total correction amount of the center sampling point based on a pre-stored mapping table, the mapping table including multiple state parameters and the sampling point correction amount corresponding to each state parameter, the sampling point correction amount being used to characterize the offset of the optimal sampling point relative to the center sampling point under the constraints of the state parameters; and determining the optimal sampling point based on the total correction amount and the center sampling point.

[0047] The center sampling point refers to the sampling point located at the center of the target sampling window, which has a balanced left and right timing margin. In actual operation, the state of the memory chip will cause the sampling point of the target signal to shift. Therefore, in this example, the center sampling point is corrected based on the state parameters of the memory chip to avoid the sampling point deviating from the stable range in actual operation.

[0048] Specifically, the state of the memory chip includes temperature state, voltage state, and aging degree. Temperature state is quantified by the operating temperature of the memory chip, voltage state by its operating voltage, and aging degree by its cumulative runtime. In this example, based on the real-time acquired state parameters, a pre-stored mapping table is consulted to obtain the sampling point correction amount corresponding to each state parameter. These corrections are accumulated to obtain the total correction amount. The central sampling point is then corrected based on this total correction amount to determine the optimal sampling point.

[0049] As can be seen in this example, the controller first determines the center sampling point of the target sampling window, then queries the pre-stored mapping table based on the acquired memory chip state parameters to calculate the total correction amount of the center sampling point. Based on the total correction amount, the center sampling point is corrected to obtain the target sampling point. In this way, the optimal sampling point can be adapted to the state of the memory chip, solving the problem of sampling point misalignment and failure under complex operating conditions, and further improving the stability and reliability of memory read and write.

[0050] In one possible example, the step of reading the optimal sampling point from the non-volatile memory and writing the optimal sampling point to the memory physical interface during a subsequent startup of the memory chip includes: if a preset condition is not met during a subsequent startup of the memory chip, then reading the optimal sampling point from the non-volatile memory and writing the optimal sampling point to the memory physical interface; if the preset condition is met during a subsequent startup of the memory chip, then re-performing the state correction operation on the central sampling point to obtain an updated optimal sampling point, and writing the updated optimal sampling point to the non-volatile memory and the memory physical interface respectively; wherein, the preset condition includes the number of startups of the memory chip reaching an integer multiple of a preset number, and / or, the cumulative runtime of the memory chip reaching an integer multiple of a preset duration.

[0051] During subsequent startups of the memory chip, the controller can access non-volatile memory to obtain the number of startups and the cumulative runtime of the memory chip, and then determine whether the preset conditions for dynamically updating the optimal sampling point are met. The conditions based on the number of startups and the conditions based on the cumulative runtime can be applied independently or in combination, and can be dynamically configured based on different application scenarios.

[0052] For example, assuming a preset number of times is 100, if during a subsequent startup of the memory chip, the startup count is detected to be a multiple of 100, then the state correction operation is re-executed on the central sampling point to update the optimal sampling point and configure it in real-time into the memory physical interface to support read and write operations. Similarly, assuming a preset duration of 1000 hours, if during a subsequent startup of the memory chip, the cumulative runtime is detected to be a multiple of 1000, then the state correction operation is re-executed on the central sampling point to update the optimal sampling point and configure it in real-time into the memory physical interface to support read and write operations. The specific values ​​of the preset number of times and preset duration can be flexibly adjusted based on the memory application scenario. For example, a larger threshold can be set for consumer computers, while a smaller threshold can be set for industrial control equipment and servers to adapt to high-frequency start-stop or long-term operation requirements.

[0053] As can be seen in this example, when the memory chip is subsequently started, the controller updates the decision based on the number of times the memory chip has been started and / or the cumulative runtime. The state correction is only re-executed when the preset conditions are met. When the preset conditions are not met, the controller directly writes the best sampling point and skips the automatic training process. This avoids the efficiency loss caused by repeated updates and ensures long-term stability through periodic updates.

[0054] Through the optimization method of memory training involved in the above embodiments, the test efficiency at the production test end can be improved and the test cost can be reduced. Specifically, during the test, the best sampling points are read from the non-volatile memory, and the whole is pulled leftward by a preset offset as a new sampling point and written into the memory physical interface, and a small amount of data read and write verification is performed. If there is no error code in the data comparison, it is determined that the left pull deviation test passes; and, the best sampling points are pulled rightward by the preset offset as a new sampling point and written into the memory physical interface, and a small amount of data read and write verification is performed. If there is no error code in the data comparison, it is determined that the right pull deviation test passes; if both the left and right pull deviation tests pass, it is determined that the test is qualified. Among them, the preset offset is determined based on the experimental data mentioned in the above embodiments, that is, based on the maximum left deviation amount and the maximum right deviation amount of the sampling points in multiple working conditions. For example, if the maximum left deviation amount and the maximum right deviation amount are both 5 under the extreme working condition, then the preset offset can be set to 8. That is, during the test, 8 sampling points are pulled leftward and 8 sampling points are pulled rightward respectively for read and write verification. If the read and write verification can pass under this extreme working condition, it can be inferred that the read and write verification can also pass under the normal working condition, and the test is determined to be qualified. Consistent with the above embodiments, please refer to Figure 6 , Figure 6 is a structural block diagram of an optimization device for memory training provided by an embodiment of the present application. The optimization device 60 for memory training includes: an acquisition unit 601, configured to obtain an initial sampling window of a target signal output based on automatic training by a memory physical interface when the memory chip is first started; a training unit 602, configured to perform optimization training on the initial sampling window to obtain a target sampling window, and the width of the target sampling window is smaller than the width of the initial sampling window; a determination unit 603, configured to determine the best sampling point based on the target sampling window and write the best sampling point into the non-volatile memory; a read and write unit 604, configured to read the best sampling point from the non-volatile memory and write the best sampling point into the memory physical interface when the memory chip is subsequently started.

[0055] In one possible example, regarding the optimization training performed on the initial sampling window to obtain the target sampling window, the training unit 602 is specifically configured to: perform a first calibration operation on the initial sampling window with a first preset step size to obtain a first reference left boundary and a first reference right boundary; wherein, the first calibration operation includes: adjusting the left boundary of the sampling window incrementally to the right, and performing read / write verification based on the adjusted left boundary until the read / write verification is successful, and determining the left boundary at the time of successful read / write verification as the reference left boundary of the sampling window; and adjusting the right boundary of the sampling window incrementally to the left, and performing read / write verification based on the adjusted right boundary until the read / write verification is successful, and determining the right boundary at the time of successful read / write verification as the reference right boundary of the sampling window; and determining the target sampling window based on the first reference left boundary and the first reference right boundary.

[0056] In one possible example, regarding the determination of the target sampling window based on the first reference left boundary and the first reference right boundary, the training unit 602 is specifically configured to: determine the sampling window formed by the first reference left boundary and the first reference right boundary as a first sampling window; when the width of the first sampling window is greater than or equal to a preset threshold, determine the first sampling window as a target sampling window; wherein the preset threshold is determined based on experimental data, the experimental data including the maximum left offset and the maximum right offset of sampling points in various working conditions, and the preset threshold is not less than the superposition value of the maximum left offset and the maximum right offset.

[0057] In one possible example, after determining the sampling window formed by the first reference left boundary and the first reference right boundary as the first sampling window, the memory training optimization device 60 is further configured to: when the width of the first sampling window is less than the preset threshold, perform the first calibration operation on the initial sampling window with a second preset step size to obtain a second reference left boundary and a second reference right boundary, wherein the second preset step size is less than the first preset step size; determine the sampling window formed by the second reference left boundary and the second reference right boundary as the second sampling window; if the width of the second sampling window is greater than or equal to the preset threshold, determine the second sampling window as the target sampling window; if the width of the second sampling window is less than the preset threshold, output fault information.

[0058] In one possible example, after determining the sampling window formed by the first reference left boundary and the first reference right boundary as the first sampling window, the memory training optimization device 60 is further configured to: when the width of the first sampling window is less than the preset threshold, perform a second calibration operation on the first sampling window with a second preset step size to obtain a third reference left boundary and a third reference right boundary, wherein the second preset step size is less than the first preset step size; wherein the second calibration operation includes: adjusting the left boundary of the sampling window to the left by decreasing it, and performing read / write verification based on the adjusted left boundary until the read / write verification fails, and then... The left boundary before the verification failure is determined as the reference left boundary of the sampling window; and the right boundary of the sampling window is adjusted to the right incrementally, and read / write verification is performed based on the adjusted right boundary until the read / write verification fails, and the right boundary before the read / write verification failure is determined as the reference right boundary of the sampling window; the sampling window formed by the third reference left boundary and the third reference right boundary is determined as the third sampling window; if the width of the third sampling window is greater than or equal to the preset threshold, the third sampling window is determined as the target sampling window; if the width of the third sampling window is less than the preset threshold, fault information is output.

[0059] In one possible example, regarding the determination of the optimal sampling point based on the target sampling window, the determining unit 603 is specifically configured to: determine a center sampling point based on the target left boundary and target right boundary of the target sampling window; perform a state correction operation on the center sampling point to obtain the optimal sampling point; wherein the state correction operation includes: acquiring the state parameters of the memory chip, the state parameters including at least operating temperature, operating voltage, and cumulative runtime; calculating the total correction amount of the center sampling point based on a pre-stored mapping table, the mapping table including multiple state parameters and the sampling point correction amount corresponding to each state parameter, the sampling point correction amount being used to characterize the offset of the optimal sampling point relative to the center sampling point under the constraints of the state parameters; and determining the optimal sampling point based on the total correction amount and the center sampling point.

[0060] In one possible example, regarding the subsequent startup of the memory chip, the optimal sampling point is read from the non-volatile memory and written to the memory physical interface. Specifically, the read / write unit 604 is configured to: if a preset condition is not met during subsequent startup of the memory chip, read the optimal sampling point from the non-volatile memory and write it to the memory physical interface; if the preset condition is met during subsequent startup of the memory chip, re-execute the state correction operation on the central sampling point to obtain an updated optimal sampling point, and write the updated optimal sampling point to both the non-volatile memory and the memory physical interface; wherein the preset condition includes the number of startups of the memory chip reaching an integer multiple of a preset number, and / or the cumulative runtime of the memory chip reaching an integer multiple of a preset duration.

[0061] When using integrated units, such as Figure 7 As shown, Figure 7 This is a structural block diagram of another memory training optimization device provided in the embodiments of this application. Figure 7 The memory training optimization apparatus 60 includes a processing module 62 and a communication module 61. The processing module 62 controls and manages the operations of the memory training optimization apparatus, for example, executing the steps of the acquisition unit 601, training unit 602, determination unit 603, and read / write unit 604, and / or other processes for performing the techniques described herein. The communication module 61 supports interaction between the memory training optimization apparatus and other devices. Figure 7 As shown, the memory training optimization device may further include a storage module 63, which is used to store the program code and data of the memory training optimization device.

[0062] All relevant content in each scenario involved in the above method embodiments can be referenced from the functional descriptions of the corresponding functional modules, and will not be repeated here. The above-mentioned memory training optimization device 60 can execute the above... Figure 2 The optimization method for memory training is shown.

[0063] Based on the description of the above method and device embodiments, please refer to... Figure 8 , Figure 8 This is a schematic diagram of the structure of a controller provided in an embodiment of this application. Figure 8 The controller shown includes a memory 801, a processor 802, a communication interface 803, and a bus 804. The memory 801, processor 802, and communication interface 803 are interconnected via the bus 804. Specifically, the controller may refer to controller 11 in the above embodiment.

[0064] The memory 801 can be a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM).

[0065] The memory 801 can store programs. When the program stored in the memory 801 is executed by the processor 802, the processor 802 and the communication interface 803 are used to execute the various steps of the memory training optimization method of the present application embodiment.

[0066] The processor 802 may be a general-purpose central processing unit (CPU), microprocessor, application specific integrated circuit (ASIC), graphics processing unit (GPU), or one or more integrated circuits, used to execute related programs to achieve the functions required by the unit in the controller of this application embodiment, or to execute the memory training optimization method of this application method embodiment.

[0067] The processor 802 can also be an integrated circuit chip with signal processing capabilities. During implementation, each step of the memory training optimization method of this application can be completed by the integrated logic circuits in the hardware of the processor 802 or by software instructions. The aforementioned processor 802 can also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The storage medium is located in memory 801. Processor 802 reads the information in memory 801 and, in conjunction with its hardware, performs the functions required by the units included in the controller of this application embodiment, or performs the memory training optimization method of this application method embodiment.

[0068] The communication interface 803 uses transceiver devices, such as, but not limited to, transceivers, to enable communication between the controller and other devices or communication networks. For example, data can be acquired through the communication interface 803.

[0069] Bus 804 may include a pathway for transmitting information between various components of the controller (e.g., memory 801, processor 802, communication interface 803).

[0070] It should be noted that, although Figure 8 The controller shown only illustrates the memory 801, processor 802, and communication interface 803. However, those skilled in the art should understand that in specific implementations, the controller may also include other devices necessary for normal operation. Furthermore, depending on specific needs, those skilled in the art should understand that the controller may also include hardware devices for implementing other additional functions. Moreover, those skilled in the art should understand that the controller may only include the devices necessary for implementing the embodiments of this application, and may not necessarily include... Figure 8 All the devices shown.

[0071] This application also provides a computer storage medium storing a computer program / instructions thereon, which, when executed by a processor, implements some or all of the steps of any of the methods described in the above method embodiments.

[0072] In the several embodiments provided in this application, it should be understood that the disclosed methods and apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for example, the division of units is merely a logical functional division, and there may be other division methods in actual implementation; for example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, or indirect coupling or communication connection between devices or units, and may be electrical, mechanical, or other forms.

[0073] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0074] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. This computer program product includes one or more computer instructions. When these computer program instructions are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in or transmitted through a computer-readable storage medium. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media.

[0075] The above description is merely a specific implementation of the embodiments of this application, but the protection scope of the embodiments of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the embodiments of this application should be covered within the protection scope of the embodiments of this application. Therefore, the protection scope of the embodiments of this application should be determined by the protection scope of the claims.

[0076] The device embodiments described above are merely illustrative. The units and modules described as separate components may or may not be physically separate. Furthermore, some or all of the units and modules can be selected to achieve the purpose of this embodiment, depending on actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0077] While this application discloses the above information, it is not limited thereto. Any person skilled in the art can easily conceive of variations or substitutions without departing from the spirit and scope of this application, and can make various alterations and modifications, including combinations of the different functions and implementation steps described above, as well as software and hardware implementation methods, all of which are within the protection scope of this application.

Claims

1. An optimization method for in-memory training, characterized in that, include: Upon the initial startup of the memory chip, the initial sampling window of the memory physical interface is obtained based on the target signal output by automatic training. Optimization training is performed on the initial sampling window to obtain a target sampling window, the width of which is smaller than the width of the initial sampling window; The optimal sampling point is determined based on the target sampling window, and the optimal sampling point is written into non-volatile memory; During subsequent startup of the memory chip, the optimal sampling point is read from the non-volatile memory and written to the memory physical interface.

2. The method according to claim 1, characterized in that, The step of performing optimization training on the initial sampling window to obtain the target sampling window includes: A first calibration operation is performed on the initial sampling window with a first preset step size to obtain a first reference left boundary and a first reference right boundary; wherein, the first calibration operation includes: adjusting the left boundary of the sampling window incrementally to the right, and performing read-write verification based on the adjusted left boundary until the read-write verification is successful, and determining the left boundary when the read-write verification is successful as the reference left boundary of the sampling window; and adjusting the right boundary of the sampling window incrementally to the left, and performing read-write verification based on the adjusted right boundary until the read-write verification is successful, and determining the right boundary when the read-write verification is successful as the reference right boundary of the sampling window; The target sampling window is determined based on the first reference left boundary and the first reference right boundary.

3. The method according to claim 2, characterized in that, Determining the target sampling window based on the first reference left boundary and the first reference right boundary includes: The sampling window formed by the first reference left boundary and the first reference right boundary is defined as the first sampling window; When the width of the first sampling window is greater than or equal to a preset threshold, the first sampling window is determined to be the target sampling window; The preset threshold is determined based on experimental data, which includes the maximum left offset and the maximum right offset of sampling points under various working conditions. The preset threshold is not less than the sum of the maximum left offset and the maximum right offset.

4. The method according to claim 3, characterized in that, After determining the sampling window formed by the first reference left boundary and the first reference right boundary as the first sampling window, the method further includes: When the width of the first sampling window is less than the preset threshold, the first calibration operation is performed on the initial sampling window with a second preset step size to obtain a second reference left boundary and a second reference right boundary, wherein the second preset step size is less than the first preset step size; The sampling window formed by the second reference left boundary and the second reference right boundary is defined as the second sampling window; If the width of the second sampling window is greater than or equal to the preset threshold, then the second sampling window is determined to be the target sampling window; If the width of the second sampling window is less than the preset threshold, then fault information is output.

5. The method according to claim 3, characterized in that, After determining the sampling window formed by the first reference left boundary and the first reference right boundary as the first sampling window, the method further includes: When the width of the first sampling window is less than the preset threshold, a second calibration operation is performed on the first sampling window with a second preset step size to obtain a third reference left boundary and a third reference right boundary. The second preset step size is less than the first preset step size. The second calibration operation includes: adjusting the left boundary of the sampling window to the left by decreasing the width, and performing read / write verification based on the adjusted left boundary until the read / write verification fails, and determining the left boundary before the read / write verification failure as the reference left boundary of the sampling window; and adjusting the right boundary of the sampling window to the right by increasing the width, and performing read / write verification based on the adjusted right boundary until the read / write verification fails, and determining the right boundary before the read / write verification failure as the reference right boundary of the sampling window. The sampling window formed by the third reference left boundary and the third reference right boundary is defined as the third sampling window; If the width of the third sampling window is greater than or equal to the preset threshold, then the third sampling window is determined to be the target sampling window; If the width of the third sampling window is less than the preset threshold, then fault information is output.

6. The method according to any one of claims 1-5, characterized in that, The step of determining the optimal sampling point based on the target sampling window includes: The center sampling point is determined based on the left and right boundaries of the target sampling window. Perform a state correction operation on the central sampling point to obtain the optimal sampling point; The state correction operation includes: acquiring the state parameters of the memory chip, the state parameters including at least operating temperature, operating voltage, and cumulative runtime; calculating the total correction amount of the center sampling point based on a pre-stored mapping table, the mapping table including multiple state parameters and the corresponding sampling point correction amount for each state parameter, the sampling point correction amount being used to characterize the offset of the optimal sampling point relative to the center sampling point under the constraints of the state parameters; and determining the optimal sampling point based on the total correction amount and the center sampling point.

7. The method according to claim 6, characterized in that, The step of reading the optimal sampling point from the non-volatile memory and writing the optimal sampling point to the memory physical interface during subsequent startup of the memory chip includes: If the preset conditions are not met during the subsequent startup of the memory chip, the optimal sampling point is read from the non-volatile memory and written to the memory physical interface. During the subsequent startup of the memory chip, if the preset conditions are met, the state correction operation is re-executed on the central sampling point to obtain the updated optimal sampling point, and the updated optimal sampling point is written to the non-volatile memory and the memory physical interface respectively. The preset conditions include the number of times the memory chip is started reaching an integer multiple of a preset number, and / or the cumulative runtime of the memory chip reaching an integer multiple of a preset duration.

8. An optimization device for memory training, characterized in that, include: The acquisition unit is used to acquire the initial sampling window of the memory physical interface based on the target signal output by automatic training when the memory chip is first started. A training unit is used to perform optimization training on the initial sampling window to obtain a target sampling window, wherein the width of the target sampling window is smaller than the width of the initial sampling window; The determining unit is used to determine the optimal sampling point based on the target sampling window and write the optimal sampling point into a non-volatile memory; The read / write unit is used to read the optimal sampling point from the non-volatile memory and write the optimal sampling point to the memory physical interface during subsequent startup of the memory chip.

9. A controller, characterized in that, It includes a processor, a memory, and one or more programs, said one or more programs being stored in the memory and configured to be executed by the processor, said programs including instructions for performing the steps in the method as claimed in any one of claims 1-7.

10. A computer-readable storage medium having a computer program / instructions stored thereon, characterized in that, When the computer program / instructions are executed by the processor, they implement the steps of the method according to any one of claims 1-7.

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