Chip test verification method and device and electronic equipment
By receiving and parsing parameter strings, constructing parameter sets, and configuring test instances, the problem of insufficient parameter configuration in chip testing and verification is solved, and flexible and efficient test case construction and enhanced reusability are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-19
- Publication Date
- 2026-04-10
AI Technical Summary
Existing technologies lack the flexibility and efficiency of parameter configuration in chip testing and verification, resulting in low efficiency in test case construction and maintenance, which severely restricts the reusability of test sequences.
Receive parameter strings, parse the value rules they contain, construct a parameter set, and configure test instances based on this set. Generate parameter sets of discrete and range values through preset format separators and splitting logic, and configure test instances to obtain verification results.
It improves the flexibility of parameter configuration and the efficiency of test case construction, enhances the reusability of test sequences, and avoids the tedious process of hard coding and repeating test cases.
Smart Images
Figure CN121835536A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of test verification, and in particular, to a chip test verification method, device and electronic equipment. BACKGROUND
[0002] In the front-end verification process of a chip, whether it is unit-level, module-level or system-level verification, in order to improve the reusability of test code and quickly build different test scenarios, verification engineers usually need to extract some common parameters and execute different test logics according to the parameter values passed in when the test instance is running.
[0003] In order to realize the above-mentioned parameterized configuration, the following two ways are usually adopted in the prior art. The first way is to directly pass parameters through a command line, and after the verification engineer executes the command of the simulation, the parameter name and its corresponding parameter value are appended, and the simulation environment can obtain these configurations after being started, and the test instance reads these values through a built-in function for use. The second way is to use a structured data file such as JSON (JavaScript Object Notation) or YAML (YAML Ain't Markup Language) to organize test cases, in which way, the related parameters and their configuration values are defined in the file, and then parsed by an automated script, and finally passed to the simulation environment through a command line or the like.
[0004] However, the above-mentioned prior art has deficiencies in flexibility and efficiency of parameter configuration. Specifically, whether through a command line or a configuration file, the design of the existing parameter configuration mechanism essentially associates a certain, single value or enumeration type with a parameter. This one-to-one mapping structure leads to the fact that when the verification task needs to associate a parameter with a set of values, such as an array, the existing mechanism cannot directly meet this requirement through a single configuration item. In order to realize the traversal test of a series of values, the verification engineer has to resort to workarounds, such as creating a large number of test cases with repetitive content, or hard-coding the series of values in the test instance code, both of which significantly reduce the efficiency of test case construction and maintenance, and seriously restrict the reusability of test sequences. SUMMARY
[0005] The present application provides a chip test verification method, device and electronic equipment to solve the deficiencies in flexibility and efficiency of parameter configuration in the prior art, which significantly reduces the efficiency of test case construction and maintenance, and seriously restricts the reusability of test sequences.
[0006] The present application provides a chip test verification method, comprising the following steps: Receive parameter string, which is obtained by encoding the value rules of all target parameters of the chip to be verified; The parameter string is parsed to obtain the target parameter values of all the target parameters to construct a parameter set; Configure at least one test instance based on the parameter set; Run the test instance and obtain the test verification results for all test instances.
[0007] According to a chip testing and verification method provided by the present invention, the step of parsing the parameter string to obtain the target parameter values of all the target parameters to construct a parameter set includes: Based on a preset format, the parameter string is parsed to obtain the target parameter values of all the target parameters to construct a parameter set.
[0008] According to a chip testing and verification method provided by the present invention, the preset format includes a first preset separator and a second preset separator; The step involves parsing the parameter string based on a preset format to obtain the target parameter values of all target parameters to construct a parameter set, including: Get the parameter value queue; The parameter string is divided based on the first preset delimiter to obtain multiple ordered substrings; Iterate through each of the ordered substrings in sequence; If the current substring does not include the second preset delimiter, the current substring is stored as the target parameter value in the parameter value queue; The parameter set is determined based on the parameter value queue after traversal is completed.
[0009] According to a chip testing and verification method provided by the present invention, the method further includes: If the current substring includes the second preset separator, then extract the start value string and end value string separated by the second preset separator from the current substring; Determine an intermediate value string; the intermediate value string is determined based on the start value string, the end value string, and a preset interval value; Based on the start value string, the end value string, and the intermediate value string, a target string is determined, and the target string is stored as the target parameter value in the parameter value queue.
[0010] According to a chip testing and verification method provided by the present invention, the received parameter string further includes, prior to: Parse the structured data file to extract the parameter string associated with the target parameter; Based on the target parameters and the parameter string, the command-line parameters are determined and sent to the simulation environment.
[0011] According to a chip testing and verification method provided by the present invention, the received parameter string includes: In the simulation environment, the parameter string is obtained based on command-line arguments.
[0012] According to a chip testing and verification method provided by the present invention, the step of running the test instance and obtaining the test verification results of all the test instances includes: During the execution of the test instance, each target parameter value in the parameter set is traversed; During the execution of the test instance, a first transaction-level data packet is created for each target parameter value in the parameter set; wherein the target parameter value is filled into a first preset field of the first transaction-level data packet; The padded first transaction-level data packet is sent as a test stimulus to the chip to be verified corresponding to the target parameter value; Obtain the response data of the chip to be verified in response to the test stimulus; Based on the response data and the expected data of the test stimulus, the test verification results of the target parameter value are obtained.
[0013] According to a chip testing and verification method provided by the present invention, the method further includes: Create a second transaction-level data packet; the parameter set is the set of values for the second preset field in the second transaction-level data packet; Based on the set of values, the second preset field is randomly assigned a value; The randomized second transaction-level data packet is sent as the test stimulus to the chip to be verified corresponding to the target parameter value; Obtain the response data of the chip to be verified in response to the test stimulus; Based on the response data and the expected data of the test stimulus, the test verification results of the target parameter value are obtained.
[0014] The present invention also provides a chip testing and verification apparatus, comprising the following units: A receiving unit is used to receive a parameter string, which is obtained by encoding the value rules of all target parameters of the chip to be verified; The parsing unit is used to parse the parameter string to obtain the target parameter values of all the target parameters to construct a parameter set; A configuration unit is used to configure at least one test instance based on the parameter set; The test verification unit is used to run the test instances and obtain the test verification results of all the test instances.
[0015] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the chip testing and verification method described above.
[0016] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the chip testing and verification method as described above.
[0017] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the chip testing and verification method described above.
[0018] The chip testing and verification method, apparatus, and electronic device provided by this invention receive parameter strings, which are encoded as value rules for all target parameters of the chip to be verified; parse the parameter strings to obtain the target parameter values of all target parameters to construct a parameter set; configure at least one test instance based on the parameter set; run the test instance and obtain the test verification results of all test instances. Thus, by receiving parameter strings containing value rules and parsing and expanding them, abstract value rules are restored to specific parameter sets, which are then configured for internal traversal execution in test instances. This allows complex parameter combinations or ranges to be expressed using concise parameter strings, avoiding the tedious process of hardcoding parameter values in verification code or repeatedly starting simulations for each parameter value. This significantly improves the flexibility of parameter configuration, the efficiency of test case construction, and enhances the reusability of test sequence templates. Attached Figure Description
[0019] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0020] Figure 1 This is one of the flowcharts of the chip testing and verification method provided by the present invention.
[0021] Figure 2 This is the second flowchart of the chip testing and verification method provided by the present invention.
[0022] Figure 3 This is a flowchart illustrating the process of parsing parameter strings provided by the present invention.
[0023] Figure 4 This is a schematic diagram of the chip testing and verification device provided by the present invention.
[0024] Figure 5 This is a schematic diagram of the structure of the electronic device provided by the present invention.
[0025] Figure label: 410: Receiving unit; 420: Parsing unit; 430: Configuration unit; 440: Test and verification unit; 510: Processor; 520: Communication interface; 530: Memory; 540: Communication bus. Detailed Implementation
[0026] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.
[0027] The terms "first," "second," etc., used in this invention are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention can be implemented in orders other than those illustrated or described herein, and that the objects distinguished by "first," "second," etc., are generally of the same class.
[0028] In related technologies, structured data files such as JSON or YAML are used to organize test cases and configure relevant parameters. For example, a test case like the one shown below can be built in a JSON file, where a test case named "test_a" is constructed, with parameter cfg_a configured to be 0 and parameter cfg_b configured as an enumeration type ENUM_B: { "test_a": { "cfg_a":"0", "cfg_b":"ENUM_B" }; }; By parsing the JSON file, the parameters cfg_a and cfg_b related to the simulation commands can be obtained. These parameters will ultimately be passed to the simulation tool as command-line arguments and retrieved and used in the test instance using built-in SystemVerilog functions.
[0029] However, existing technologies are insufficient in terms of the flexibility and efficiency of parameter configuration, which significantly reduces the efficiency of test case construction and maintenance, and severely restricts the reusability of test sequences.
[0030] To address the aforementioned issues, this invention provides a chip testing and verification method that can be applied to various levels of chip front-end verification, including but not limited to unit-level verification, block-level verification, and system-level verification. Figure 1 This is one of the flowcharts illustrating the chip testing and verification method provided by the present invention, such as... Figure 1 As shown, the method includes steps 110, 120 and 130.
[0031] Step 110, receive parameter string; the parameter string is obtained by encoding the value rules of all target parameters of the chip to be verified.
[0032] Specifically, firstly, it can receive parameter strings, which are obtained by encoding the value rules of all target parameters of the chip to be verified.
[0033] Here, a parameter string is a specific formatted text carrying logical information. Unlike ordinary strings in existing technologies that can only represent a single, definite value, a parameter string inherently contains parsable value rules. Verification engineers organize all target parameters of a series of chips to be tested according to a value rule agreed upon by both the encoding and decoding ends to obtain the parameter string.
[0034] Here, target parameters refer to variable objects that need to be configured or changed during chip verification, such as register addresses, burst lengths, and data packet sizes. Value rules refer to the definition information of how the target parameters should be valued. Value rules can include, but are not limited to, discrete values, range values, and step values; this embodiment of the invention does not specifically limit these. By encoding the value rules, a large amount of data can be expressed using extremely short strings, such as "1~100", greatly simplifying the complexity of parameter passing. Here, the received parameter string can be read by the simulator at startup via command-line parameters, or it can be read from a local or network configuration file, or it can be received from an external management script through inter-process communication mechanisms, etc. This embodiment of the invention does not specifically limit these.
[0035] Step 120: Based on a preset format, parse the parameter string to obtain the target parameter values of all the target parameters to construct a parameter set.
[0036] Specifically, after receiving the parameter string, the parameter string can be parsed to obtain the target parameter values of all target parameters in order to construct a parameter set.
[0037] It should be understood that parsing the parameter string is the reverse process of encoding the value rules of all target parameters to be verified. The parsing process can be executed by a processing module running in the verification environment. The processing module can scan the input parameter string, identify that it includes each individual target parameter value, and extract the target parameter values to construct the parameter set.
[0038] The target parameter value refers to the specific value actually used in each test after being expanded according to the value selection rules, such as the expanded addresses 0x10, 0x11, and 0x12. The parameter set is an ordered container that holds these target parameter values. The parameter set can be a dynamic array, queue, list, or other container type in a programming language; this embodiment of the invention does not specifically limit this.
[0039] In one specific embodiment, assuming the parameter string is "1~3", its encoding value rule is "consecutive integers from 1 to 3". The parsing step will expand this rule to obtain three specific target parameter values "1", "2", and "3", and store these three values in a queue to form a parameter set.
[0040] Step 130: Configure at least one test instance based on the parameter set.
[0041] Specifically, after constructing the parameter set, the parameter set is passed to the test instance in the verification environment to complete the configuration of the test instance.
[0042] Here, a test instance refers to an entity object used to execute specific test tasks within a verification environment. It is typically a component instance built upon a verification methodology. A test instance can be a sequence that generates stimuli, a test case that manages the test process, or a specific verification environment or proxy.
[0043] The process of configuring at least one test instance based on a parameter set can be achieved in several ways. For example, one can directly call the member function of the test instance to assign values. Through this step, the test instance will have complete parameter data to be traversed.
[0044] Step 140: Run the test instance and obtain the test verification results of all the test instances.
[0045] Specifically, the configured test instance is started and run. During the execution of the test instance, the test instance uses a set of parameters according to its internal logic and ultimately obtains the test verification results.
[0046] It should be understood that running a test instance typically involves the following process: After the test instance starts, it reads the parameter set stored internally and iterates through the parameter set. For each target parameter value in the set, the test instance generates corresponding test behavior, such as sending a read-write transaction.
[0047] Here, test verification results refer to the conclusions used to characterize whether the function of the chip under test meets expectations under the target parameter values. Test verification results typically include verification pass and verification failure, and may also include specific coverage data, error logs, etc. Since the test instance traverses all values in the parameter set, the final result obtained is a comprehensive test verification result covering all target parameter values.
[0048] The method provided in this invention receives a parameter string, which is obtained by encoding the value rules of all target parameters of the chip to be verified; parses the parameter string to obtain the target parameter values of all target parameters to construct a parameter set; configures at least one test instance based on the parameter set; runs the test instance, and obtains the test verification results of all test instances. Thus, by receiving, parsing, and expanding the parameter string containing value rules, the abstract value rules are restored to a specific parameter set, which is then configured for internal traversal execution in the test instance. This allows complex parameter combinations or ranges to be expressed using a concise parameter string, avoiding the tedious process of hardcoding parameter values in the verification code or repeatedly starting simulations for each parameter value. This significantly improves the flexibility of parameter configuration, the efficiency of test case construction, and enhances the reusability of test sequence templates.
[0049] Based on the above embodiments, step 120 includes: Step 1201: Based on a preset format, parse the parameter string to obtain the target parameter values of all the target parameters to construct a parameter set.
[0050] Specifically, the parsing process is not arbitrary character processing, but a reverse decoding process that strictly follows a preset format.
[0051] The preset format refers to a set of predefined syntax rules used to generate and subsequently parse parameter strings. The preset format can be any rule that can structure all target parameters. For example, the preset format may specify the use of specific characters as separators between target parameters, or the use of specific keywords to identify different types of target parameters, or a specific character arrangement to express a set of target parameters. This embodiment of the invention does not impose specific limitations on these aspects. The core of the preset format lies in determinism and parsability; it is sufficient to ensure that all target parameters can be unambiguously encoded into parameter strings according to the preset format, and that all original target parameters can be accurately parsed from the parameter strings.
[0052] Based on the above embodiments, the preset format includes a first preset separator and a second preset separator; Step 120 includes: Step 121, obtain the parameter value queue; Step 122: The parameter string is segmented based on the first preset delimiter to obtain multiple ordered substrings; Step 123: Iterate through each of the ordered substrings in sequence; Step 124: If the current substring does not include the second preset delimiter, store the current substring as the target parameter value in the parameter value queue; The parameter set is determined based on the parameter value queue after traversal is completed.
[0053] Specifically, the preset format includes a first preset separator and a second preset separator. The first preset separator is used to separate multiple different target parameters or target parameter expressions in the parameter string. For example, the first preset separator can be a comma or a semicolon, etc., and this embodiment of the invention does not specifically limit it.
[0054] Accordingly, firstly, a parameter value queue is obtained. This parameter value queue is an ordered data collection used to store each target parameter parsed from the parameter string in sequence. It should be understood that using this data structure helps maintain the original order of the target parameters. Furthermore, any ordered collection with similar functionality, such as a dynamic array or list, can also be used as a parameter value queue; this embodiment of the invention does not specifically limit this. Here, the second preset separator is used to represent a continuous range. The second preset separator is typically placed between the start and end values of the range. For example, this second preset separator can be a tilde (~) or a hyphen (-). By introducing the second preset separator, the expressive power of the parameter string is expanded, enabling it to represent not only multiple discrete parameter values but also one or more continuous parameter ranges.
[0055] Next, the parameter string is segmented based on the first preset delimiter, resulting in multiple ordered substrings. The parsing module can use the first preset delimiter as a basis to cut the entire parameter string into an ordered set of multiple substrings. For example, if the parameter string is "0x10, 0x20, 0x30" and the first preset delimiter is a comma, then after segmentation, an ordered set containing the three substrings "0x10", "0x20", and "0x30" will be obtained.
[0056] Accordingly, in this embodiment, each current substring in a plurality of ordered substrings is traversed in sequence. During the traversal, for each current substring, it is first determined whether it includes the second preset delimiter.
[0057] If the current substring does not contain the second preset delimiter, the parsing module determines that the current substring corresponds to a single discrete parameter value. In this case, the parsing module converts the type of the current substring and stores it as the target parameter value in the parameter value queue.
[0058] For example, suppose the parameter string is "10,20~30,40", with the first preset separator being a comma (,) and the second preset separator being a tilde (~). After splitting, we get a set of substrings ["10", "20~30", "40"]. When iterating to the current substring "10", since it does not contain the tilde (~), it is converted to the value 10 and stored in the parameter value queue. Similarly, when iterating to the current substring "40", it is also converted to the value 40 and stored.
[0059] Finally, the parameter set is determined based on the parameter value queue after the traversal is complete. In other words, when all substrings have been processed, the parameter value queue, including all target parameter values, constitutes the final parameter set.
[0060] The method provided in this invention includes a first preset separator and a second preset separator in the preset format. If the current substring does not include the second preset separator, the current substring is stored as a target parameter value in the parameter value queue. Thus, by encoding discrete values and range expressions together in the same parameter string, a single parameter configuration item can express not only a simple set of parameters but also heterogeneous sets of parameters including elements of different types, greatly enhancing the expressive power of the parameter string. Furthermore, this method avoids creating independent test cases or hard-coding for each target parameter value, allowing verification engineers to use parameter strings to describe more complex test intentions. This enables the configuration of test sequences based on the uniformly parsed parameter set, completing traversal testing. While improving the flexibility of parameterized configuration, it further enhances the expressive efficiency of parameter configuration and the versatility of the parameter string.
[0061] Based on the above embodiments, the method further includes: Step 210: If the current substring includes the second preset separator, then extract the start value string and end value string separated by the second preset separator from the current substring; Step 220: Determine the intermediate value string; the intermediate value string is determined based on the start value string, the end value string, and the preset interval value; Step 230: Based on the start value string, the end value string, and the intermediate value string, determine the target string and store the target string as the target parameter value in the parameter value queue.
[0062] Specifically, if the current substring includes a second preset delimiter, then the start value string and end value string separated by the second preset delimiter are extracted from the current substring. That is, when the parsing module determines that the current substring contains the second preset delimiter, it can further divide the current substring using the second preset delimiter as the boundary, thus obtaining two parts representing the upper and lower limits of the range, namely the start value string and the end value string. For example, for the current substring "20~30", after extraction, the start value string "20" and the end value string "30" are obtained.
[0063] Next, the intermediate value string is determined, based on the start value string, the end value string, and a preset interval value. The purpose of this step is to generate one or more representative intermediate values between the start and end values. The preset interval value can be a default value, such as 1, or a pre-configured value. For example, multiple equally spaced values can be generated within a range based on the preset interval value. For instance, for the current substring "20~30", if the preset interval value is 5, the intermediate value string can be determined to be "25"; and for the current substring "20~23", if the preset interval value is 1, the intermediate value strings can be determined to be "21, 22".
[0064] Then, based on the start value string, end value string, and intermediate value string, the target string can be determined and stored as the target parameter value in the parameter value queue. For example, for the current substring "20~30", if the preset interval value is 5, the final target string can be "20, 25, 30", and these three strings are then stored as target parameter values in the parameter value queue. As another example, for the current substring "20~23", if the preset interval value is 1, then based on the start value string "20", the end value string "23", and the intermediate value strings "21, 22", the target string is determined to be "20, 21, 22, 23".
[0065] The method provided in this invention introduces a second preset separator, enabling parameter strings to directly express a continuous range of parameters at the syntactic level. During parsing, the second preset separator acts as an explicit syntactic marker, driving the parsing module to execute predetermined range parsing logic, thereby unambiguously deriving the complete parameter set in form. This process accurately and reliably converts the functional intent of the second preset separator into discrete parameter values that can be directly used by test instances through preset format syntactic rules. This fundamentally avoids omissions, errors, or intent deviations that may result from manually enumerating ranges or hard-coding specific values, significantly improving the determinism, accuracy, and reliability of parameter configuration and test stimulus generation.
[0066] Based on the above embodiments, step 110 further includes the following prior steps: Step 111: Parse the structured data file to extract the parameter string associated with the target parameter; Step 112: Based on the target parameters and the parameter string, determine the command-line parameters and send the command-line parameters to the simulation environment.
[0067] Specifically, firstly, the structured data file is parsed to extract the parameter strings associated with the target parameter. In the verification process, for ease of management and maintenance, test case configurations are typically not written directly in the command line, but rather centrally defined in one or more structured data files. These structured data files can be in formats such as JSON or YAML; this embodiment of the invention does not impose specific limitations on this. In the structured data file, a key for a target parameter is associated with a value, and this value is the parameter string. By parsing the structured data file, this key-value relationship can be extracted.
[0068] Then, based on the target parameter and parameter string, the command-line parameters are determined and sent to the simulation environment. For example, if the target parameter is named addr_cfg and the parameter string is "10,20~30,40", the constructed command-line parameters could be +addr_cfg="10,20~30,40". Finally, when starting the simulator, the constructed command-line parameters are passed in as part of the startup command.
[0069] The method provided in this invention parses structured data files to extract parameter strings associated with target parameters, determines command-line parameters based on the target parameters and parameter strings, and sends the command-line parameters to the simulation environment. This method can be easily deployed in existing verification platforms and has good engineering practicality and compatibility.
[0070] Based on the above embodiments, step 110 includes: Step 110-1: In the simulation environment, obtain the parameter string based on command-line parameters.
[0071] Specifically, since the parameter strings have been passed to the simulation environment as command-line arguments, the simulation environment will load these command-line arguments when the simulation starts running and provide the corresponding mechanisms for the internal test code to access them.
[0072] In a SystemVerilog-based verification environment, test instances can retrieve command-line argument values by calling a system-level parameter query function or interface, such as VPI / DPI (Verilog Procedural Interface / Direct Programming Interface). The test instance uses the parameter name, such as `addr_cfg`, as the query index to accurately retrieve the complete parameter string associated with the command-line argument. The retrieved parameter string is typically stored in a string variable within the test instance for use in subsequent parsing steps.
[0073] Based on the above embodiments, step 140 includes: Step 141: During the execution of the test instance, a first transaction-level data packet is created for each target parameter value in the parameter set; wherein the target parameter value is filled into a first preset field of the first transaction-level data packet; Step 142: Send the padded first transaction-level data packet as a test stimulus to the chip to be verified corresponding to the target parameter value; Step 143: Obtain the response data of the chip to be verified in response to the test stimulus feedback; Step 144: Based on the response data and the expected data of the test stimulus, obtain the test verification result of the target parameter value.
[0074] Specifically, during the execution of the test instance, the test instance uses a loop structure to access each target parameter value in the parameter set in turn.
[0075] Next, a first transaction-level data packet is created for each target parameter value in the parameter set; the target parameter value is filled into a first preset field of the first transaction-level data packet. In the chip testing and verification method, the test stimulus is described by an abstract data object called a transaction-level data packet. A transaction-level data packet typically includes all the information required to perform a complete operation, such as address, read / write type, data, etc. In this step, for each target parameter value currently traversed, the test instance creates one or more first transaction-level data packets and fills the target parameter value into a predefined field in the first transaction-level data packet. For example, if the target parameter value is an address, it will be assigned to the address field of the transaction-level data packet. Other fields of the transaction-level data packet can retain default values or be randomized to increase the diversity of the test; this embodiment of the invention does not specifically limit this.
[0076] Finally, the padded first transaction-level data packet is sent as a test stimulus to the chip to be verified corresponding to the target parameter value. Here, the chip to be verified corresponding to the target parameter value refers to the specific hardware module function point controlled or affected by the target parameter value. After processing the input test stimulus, the chip to be verified generates an output signal. The monitor in the verification environment captures these output signals and assembles them into a response data packet, i.e., response data.
[0077] Finally, based on the response data and the expected data from the test stimulus, the test verification result of the target parameter value is obtained. The scoreboard or checker in the verification environment receives the response data and compares it with the expected data. The expected data is the theoretically correct result derived by the reference model based on the input test stimulus. By comparing whether the response data and the expected data of the test stimulus are consistent, it is determined whether the test for the target parameter value has passed, thus obtaining the test verification result.
[0078] Based on the above embodiments, the method further includes: Step 31: Create a second transaction-level data packet; the parameter set is the set of values for the second preset field in the second transaction-level data packet; Step 32: Based on the set of values, randomly assign values to the second preset field; Step 33: The randomized second transaction-level data packet is sent as the test stimulus to the chip to be verified corresponding to the target parameter value; Step 34: Obtain the response data of the chip to be verified in response to the test stimulus feedback; Step 35: Based on the response data and the expected data of the test stimulus, obtain the test verification result of the target parameter value.
[0079] Specifically, after obtaining the parameter set including all target parameter values by parsing the parameter string, the test instance can use the constrained randomization mechanism in the verification methodology to generate test stimuli without having to manually write loops to specify values one by one.
[0080] First, a second transaction-level data packet is created. In this packet, the parameter set is no longer directly read and assigned values; instead, it serves as a set of constraint values applied to a second preset field within the transaction-level data packet. In the intelligent verification language, constraint syntax can be used to specify that the value of this second preset field must fall within the range of the parameter set during randomization. Subsequently, the randomization function is called to process the second transaction-level data packet. During this process, the constraint solver automatically selects a target parameter value randomly from the parameter set and assigns it to the second preset field. It can also randomize other non-fixed fields in the second transaction-level data packet, thereby generating effective test stimuli with random characteristics. This approach can simulate more realistic, non-linear, random business scenarios.
[0081] Finally, the randomized second transaction-level data packet is sent as a test stimulus to the chip under test corresponding to the target parameter value. Based on the test stimulus, the test verification result is obtained. Here, the chip under test corresponding to the target parameter value refers to the specific hardware module function point controlled or affected by the target parameter value. After processing the input test stimulus, the chip under test generates an output signal. The monitor in the verification environment captures these output signals and assembles them into a response data packet, i.e., response data.
[0082] Finally, based on the response data and the expected data of the test stimulus, the test verification result of the target parameter value is obtained. The scoreboard or checker in the verification environment receives the response data and compares it with the expected data. The expected data is the theoretically correct result derived by the reference model based on the input test stimulus. Whether the target parameter value passes the test is determined by whether the comparison response data matches the expected data of the test stimulus, thus obtaining the test verification result. In this way, the verification personnel only need to pass a list, such as 1, 5, 10~20, to the command line, and the test instance can automatically test within the range defined by the list. This ensures that the test covers the points of interest while introducing randomness to trigger potential boundary condition errors. Finally, the test verification result of this random stimulus is obtained by judging the response of the chip under verification by the comparison module.
[0083] It should be noted that the chip testing and verification method provided in this invention has broad applicability and can be applied to any technical field based on the SystemVerilog language. Specifically, its implementation scenarios include, but are not limited to, the design and verification of graphics processing units (GPUs); the chip testing and verification method described in this invention can be applied to any scenario involving parameter passing and verification environment construction using the features of the SystemVerilog language.
[0084] The chip testing and verification method provided by this invention offers a general paradigm for command-line parameter processing. Users can customize the configuration format according to module characteristics and their own needs, and only need to adjust the parameter string processing logic accordingly to achieve flexible and scalable parameter configuration.
[0085] Based on any of the above embodiments Figure 2 This is the second flowchart illustrating the chip testing and verification method provided by this invention, as shown below. Figure 2As shown, firstly, a parameter string is defined, where different values are separated by commas and a range is indicated by a tilde. Based on this preset format, verification engineers configure parameters via JSON / YAML or command line to generate a parameter string containing multiple target parameter values. Subsequently, the simulator obtains the command-line parameters and their configuration, loading the parameter string into the simulation environment. In the simulation environment, the test instance uses a procedural interface function to obtain the values of the command-line parameters, i.e., the parameter string, and calls a custom processing function to parse the parameter string. After parsing the parameter string to obtain the parameter set, the test instance generates test stimuli based on the values of the parameter set. Finally, verification is completed by checking and comparing the responses to all test stimuli, thus achieving automated testing of a series of parameter values.
[0086] Based on any of the above embodiments Figure 3 This is a flowchart illustrating the parsing of parameter strings provided by the present invention, as shown below. Figure 3 As shown, this method first defines a function in the verification environment to process the parameter string, which encapsulates the subsequent parsing logic. When this function is called, its core process starts by traversing the parameter string, which can be understood as an ordered set of multiple substrings. During the traversal, for each current substring, a judgment step is first performed to determine whether it includes the second preset delimiter. If the judgment result is negative, it indicates that the substring represents a discrete value, and the process switches to the right branch, performing the operation of storing the current substring as the target parameter value into the parameter value queue. Conversely, if the judgment result is positive, it indicates that the substring represents a range expression, and the process switches to the left branch. First, it extracts the start value string and end value string separated by the second preset delimiter. Then, it determines the intermediate value string and stores the start value string, end value string, and intermediate value string as the target parameter value into the parameter value queue. After processing is completed in any branch, a loop control judgment step is entered, which determines whether it is the last string. If not, the process returns to the traversal step to process the next substring; if it is, it means that all substrings have been processed, the entire parsing process ends, and the final parameter set is determined based on the parameter value queue after traversal.
[0087] The chip testing and verification apparatus provided by the present invention is described below. The chip testing and verification apparatus described below can be referred to in correspondence with the chip testing and verification method described above.
[0088] Based on any of the above embodiments, the present invention provides a chip testing and verification device. Figure 4 This is a schematic diagram of the chip testing and verification device provided by the present invention, as shown below. Figure 4 As shown, the device includes: The receiving unit 410 is used to receive a parameter string, which is obtained by encoding the value rules of all target parameters of the chip to be verified; The parsing unit 420 is used to parse the parameter string to obtain the target parameter values of all the target parameters to construct a parameter set; Configuration unit 430 is used to configure at least one test instance based on the parameter set; The test verification unit 440 is used to run the test instances and obtain the test verification results of all the test instances.
[0089] The apparatus provided in this invention receives a parameter string, which is obtained by encoding the value rules of all target parameters of the chip to be verified; it parses the parameter string to obtain the target parameter values of all target parameters to construct a parameter set; it configures at least one test instance based on the parameter set; it runs the test instance and obtains the test verification results of all test instances. Thus, by receiving, parsing, and expanding the parameter string containing value rules, the abstract value rules are restored to a specific parameter set, which is then configured for internal traversal execution in the test instance. This allows complex parameter combinations or ranges to be expressed using a concise parameter string, avoiding the tedious process of hardcoding parameter values in the verification code or repeatedly starting simulations for each parameter value. This significantly improves the flexibility of parameter configuration, the efficiency of test case construction, and enhances the reusability of test sequence templates.
[0090] Based on any of the above embodiments, the parsing unit 420 specifically includes: The parsing subunit is used to parse the parameter string based on a preset format to obtain the target parameter values of all the target parameters in order to construct a parameter set.
[0091] Based on any of the above embodiments, the preset format includes a first preset separator and a second preset separator; The parsing subunit is specifically used for: Get the parameter value queue; The parameter string is divided based on the first preset delimiter to obtain multiple ordered substrings; Iterate through each of the ordered substrings in sequence; If the current substring does not include the second preset delimiter, the current substring is stored as the target parameter value in the parameter value queue; The parameter set is determined based on the parameter value queue after traversal is completed.
[0092] Based on any of the above embodiments, a target string determination unit is further included, wherein the target string determination unit is specifically used for: If the current substring includes the second preset separator, then extract the start value string and end value string separated by the second preset separator from the current substring; Determine an intermediate value string; the intermediate value string is determined based on the start value string, the end value string, and a preset interval value; Based on the start value string, the end value string, and the intermediate value string, a target string is determined, and the target string is stored as the target parameter value in the parameter value queue.
[0093] Based on any of the above embodiments, a sending unit is further included, wherein the sending unit is specifically used for: Parse the structured data file to extract the parameter string associated with the target parameter; Based on the target parameters and the parameter string, the command-line parameters are determined and sent to the simulation environment.
[0094] Based on any of the above embodiments, the receiving unit 410 is specifically used for: In the simulation environment, the parameter string is obtained based on command-line arguments.
[0095] Based on any of the above embodiments, the test verification unit 440 is specifically used for: During the execution of the test instance, each target parameter value in the parameter set is traversed; During the execution of the test instance, a first transaction-level data packet is created for each target parameter value in the parameter set; wherein the target parameter value is filled into a first preset field of the first transaction-level data packet; The padded first transaction-level data packet is sent as a test stimulus to the chip to be verified corresponding to the target parameter value; Obtain the response data of the chip to be verified in response to the test stimulus; Based on the response data and the expected data of the test stimulus, the test verification results of the target parameter value are obtained.
[0096] Based on any of the above embodiments, a second test verification unit is further included, the second test verification unit being specifically used for: Create a second transaction-level data packet; the parameter set is the set of values for the second preset field in the second transaction-level data packet; Based on the set of values, the second preset field is randomly assigned a value; The randomized second transaction-level data packet is sent as the test stimulus to the chip to be verified corresponding to the target parameter value; Obtain the response data of the chip to be verified in response to the test stimulus; Based on the response data and the expected data of the test stimulus, the test verification results of the target parameter value are obtained.
[0097] Figure 5 This is a schematic diagram of the structure of the electronic device provided by the present invention, such as... Figure 5 As shown, the electronic device may include a processor 510, a communications interface 520, a memory 530, and a communication bus 540, wherein the processor 510, communications interface 520, and memory 530 communicate with each other via the communication bus 540. The processor 510 can call logical instructions in the memory 530 to execute a chip testing and verification method. This method includes: receiving a parameter string, wherein the parameter string is obtained by encoding the value rules of all target parameters of the chip to be verified; parsing the parameter string to obtain the target parameter values of all the target parameters to construct a parameter set; configuring at least one test instance based on the parameter set; running the test instance, and obtaining the test verification results of all the test instances.
[0098] Furthermore, the logical instructions in the aforementioned memory 530 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0099] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the chip testing and verification method provided by the above methods. The method includes: receiving a parameter string, wherein the parameter string is obtained by encoding the value rules of all target parameters of the chip to be verified; parsing the parameter string to obtain the target parameter values of all the target parameters to construct a parameter set; configuring at least one test instance based on the parameter set; running the test instance and obtaining the test verification results of all the test instances.
[0100] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon. When executed by a processor, the computer program is implemented to perform the chip testing and verification methods provided by the above methods. The method includes: receiving a parameter string, wherein the parameter string is obtained by encoding the value rules of all target parameters of the chip to be verified; parsing the parameter string to obtain the target parameter values of all the target parameters to construct a parameter set; configuring at least one test instance based on the parameter set; running the test instance and obtaining the test verification results of all the test instances.
[0101] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.
[0102] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.
[0103] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A chip testing and verification method, characterized in that, include: Receive parameter string, which is obtained by encoding the value rules of all target parameters of the chip to be verified; The parameter string is parsed to obtain the target parameter values of all the target parameters to construct a parameter set; Configure at least one test instance based on the parameter set; Run the test instance and obtain the test verification results for all test instances.
2. The chip testing and verification method according to claim 1, characterized in that, The step of parsing the parameter string to obtain the target parameter values of all the target parameters to construct a parameter set includes: Based on a preset format, the parameter string is parsed to obtain the target parameter values of all the target parameters to construct a parameter set.
3. The chip testing and verification method according to claim 2, characterized in that, The preset format includes a first preset separator and a second preset separator; The step involves parsing the parameter string based on a preset format to obtain the target parameter values of all target parameters to construct a parameter set, including: Get the parameter value queue; The parameter string is divided based on the first preset delimiter to obtain multiple ordered substrings; Iterate through each of the ordered substrings in sequence; If the current substring does not include the second preset delimiter, the current substring is stored as the target parameter value in the parameter value queue; The parameter set is determined based on the parameter value queue after traversal is completed.
4. The chip testing and verification method according to claim 3, characterized in that, The method further includes: If the current substring includes the second preset separator, then extract the start value string and end value string separated by the second preset separator from the current substring; Determine an intermediate value string; the intermediate value string is determined based on the start value string, the end value string, and a preset interval value; Based on the start value string, the end value string, and the intermediate value string, a target string is determined, and the target string is stored as the target parameter value in the parameter value queue.
5. The chip testing and verification method according to any one of claims 1 to 4, characterized in that, The received parameter string also includes: Parse the structured data file to extract the parameter string associated with the target parameter; Based on the target parameters and the parameter string, the command-line parameters are determined and sent to the simulation environment.
6. The chip testing and verification method according to claim 5, characterized in that, The received parameter string includes: In the simulation environment, the parameter string is obtained based on command-line arguments.
7. The chip testing and verification method according to any one of claims 1 to 4, characterized in that, The process of running the test instance and obtaining the test verification results of all the test instances includes: During the execution of the test instance, a first transaction-level data packet is created for each target parameter value in the parameter set; wherein the target parameter value is filled into a first preset field of the first transaction-level data packet; The padded first transaction-level data packet is sent as a test stimulus to the chip to be verified corresponding to the target parameter value; Obtain the response data of the chip to be verified in response to the test stimulus; Based on the response data and the expected data of the test stimulus, the test verification results of the target parameter value are obtained.
8. The chip testing and verification method according to claim 7, characterized in that, The method further includes: Create a second transaction-level data packet; the parameter set is the set of values for the second preset field in the second transaction-level data packet; Based on the set of values, the second preset field is randomly assigned a value; The randomized second transaction-level data packet is sent as the test stimulus to the chip to be verified corresponding to the target parameter value; Obtain the response data of the chip to be verified in response to the test stimulus; Based on the response data and the expected data of the test stimulus, the test verification results of the target parameter value are obtained.
9. A chip testing and verification device, characterized in that, include: A receiving unit is used to receive a parameter string, which is obtained by encoding the value rules of all target parameters of the chip to be verified; The parsing unit is used to parse the parameter string to obtain the target parameter values of all the target parameters to construct a parameter set; A configuration unit is used to configure at least one test instance based on the parameter set; The test verification unit is used to run the test instances and obtain the test verification results of all the test instances.
10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the chip testing and verification method as described in any one of claims 1 to 8.