Method for evaluating single-particle radiation effect of layout-level SRAM chip

Abstract

The invention provides a layout-level SRAM (Static Random Access Memory) chip single-particle radiation effect evaluation method, and relates to the technical field of microelectronic and spatial effect simulation analysis, the method comprises the following steps: establishing an SRAM chip three-dimensional stack structure model and carrying out heavy ion energy deposition simulation to obtain electron-hole pair three-dimensional space distribution; the area of the SRAM unit is determined based on layout information of the SRAM unit, an off-state NMOS device charge collection model is established, and drain charge transfer coefficient distribution is obtained through simulation; establishing a 6T SRAM unit circuit model based on circuit topology, and performing simulation to determine a turnover critical charge quantity; and integrating the distribution and the critical charge quantity to construct a charge collection calculation model, and predicting the overturning cross section of the SRAM array in combination with the area of a unit layout. According to the invention, efficient and accurate evaluation of the radiation effect in the chip design stage is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of microelectronic and space effect simulation analysis, in particular to a layout-level SRAM chip single particle radiation effect evaluation method, system and device. BACKGROUND

[0002] Single event upset (SEU) is one of the most important space environment factors inducing spacecraft failures, and its micro mechanism is directly related to the ionization effect caused by high-energy charged particles in the sensitive area of the device. In a typical 6T SRAM memory cell, two cross-coupled CMOS inverters form the basic storage structure, and the current stored data is determined by the level coupling state as "0" or "1". Under normal working conditions, this structure has good electrical isolation characteristics, and the data is stable. However, when high-energy heavy ions penetrate the SRAM sensitive area, its energy is transferred to the sensitive area atoms through ionization, exciting a large number of transient electron-hole pairs. These carriers are rapidly separated under the action of the internal electric field, forming a transient current and causing fluctuations in the voltage of the corresponding inverter node. Once the fluctuation exceeds the logic threshold of the other inverter, the coupling flip process will be triggered, ultimately leading to a change in the stored data error.

[0003] In related technologies, the anti-radiation performance of SRAM is usually evaluated by experimental irradiation test or device-level physical simulation method. Among them, the experimental irradiation test needs to use heavy ions to irradiate the real chip on the accelerator, and the flip cross section is obtained by directly counting the number of error bits. Although the results of this method are direct and reliable, the cost is high, the period is long, and it is seriously dependent on the specific chip process and flow sample, and cannot be predicted and optimized in the design stage. Device-level physical simulation uses process computer-aided design (TCAD) tools to perform fine physical simulation on a single transistor or SRAM cell, which can study the micro mechanism and obtain critical charge parameters, but this method consumes a lot of computing resources, and it is usually difficult to directly and efficiently extend to the full-chip array level flip cross section calculation containing millions of cells. The existing methods have significant limitations in efficiency, cost or scalability, and it is difficult to provide simulation basis for radiation hardening in the chip design stage while considering accuracy and efficiency. SUMMARY

[0004] The problem solved by the present application is how to efficiently and accurately predict the single event upset cross section of the SRAM memory array under heavy ion radiation in the design stage.

[0005] To solve the above problems, the present application provides a layout-level SRAM chip single particle radiation effect evaluation method, system and device.

[0006] In a first aspect, a layout-level SRAM chip single particle radiation effect evaluation method of the present application comprises: A three-dimensional stacked structure model of the SRAM chip is established, and heavy ion energy deposition simulation is performed on the three-dimensional stacked structure model to obtain a three-dimensional spatial distribution of electron-hole pairs deposited by a heavy ion in a silicon device layer of the three-dimensional stacked structure model; Based on layout information of an SRAM cell of the SRAM chip, the layout area of the SRAM cell is determined, and a charge collection model of an off-state NMOS device in the SRAM cell is established; and the charge collection model is simulated to obtain a drain charge transfer coefficient distribution of the off-state NMOS device; Based on the circuit topology of the SRAM cell, a 6T SRAM cell circuit model is established; and flip threshold simulation is performed on the 6T SRAM cell circuit model to obtain a flip critical charge amount of the SRAM cell; By integrating the three-dimensional spatial distribution of electron-hole pairs, the drain charge transfer coefficient distribution, and the flip critical charge amount, a charge collection calculation model is constructed, and according to the charge collection calculation model and the layout area of the SRAM cell, a flip cross section of an SRAM array composed of the SRAM cell is predicted.

[0007] Optionally, the establishment of the three-dimensional stacked structure model of the SRAM chip comprises: Based on the manufacturing process data and layout information of the SRAM chip, a multi-layer stacked geometric model reflecting the actual material composition of the SRAM chip is constructed, wherein the multi-layer stacked geometric model sequentially comprises: a plurality of insulating dielectric layers, Cu wiring layers arranged between the insulating dielectric layers, a W metal contact layer, and a silicon device layer; The silicon device layer includes an active region structure of a FinFET device, a substrate, and a well region structure.

[0008] Optionally, the heavy ion energy deposition simulation on the three-dimensional stacked structure model to obtain a three-dimensional spatial distribution of electron-hole pairs deposited by a heavy ion in a silicon device layer of the three-dimensional stacked structure model comprises: The heavy ion is set to be vertically incident to the three-dimensional stacked structure model; The three-dimensional stacked structure model is divided into unit grids of a preset size in three-dimensional space; The process of the heavy ion penetrating the three-dimensional stacked structure model is simulated to obtain the deposition energy of the heavy ion in each unit grid; Based on the deposition energy, the deposition energy in each grid is converted into the corresponding number of electron-hole pairs according to the ionization energy required to generate a single electron-hole pair from the silicon material constituting the silicon device layer; generate three-dimensional spatial distribution data of the electron-hole pairs in the silicon device layer based on the number of the electron-hole pairs of all the grids.

[0009] Optionally, the layout information of the SRAM cell of the SRAM chip is used to determine the layout area of the SRAM cell, and a charge collection model of the off-state NMOS device in the SRAM cell is established, including: The layout area of the SRAM cell is determined according to the layout information, and the two-dimensional geometric profile and size of the off-state NMOS device are extracted based on the layout information; The two-dimensional geometric profile and the size are used as boundaries to establish a two-dimensional projection model of the NMOS device; The active region corresponding to the NMOS device in the two-dimensional projection model is divided into a plurality of grid cells, and the two-dimensional projection model divided into a plurality of grid cells is used as the charge collection model.

[0010] Optionally, the charge collection model is simulated to obtain the drain charge transfer coefficient distribution of the off-state NMOS device, including: For each grid cell in the charge collection model, a heavy ion with a set linear energy transfer value is incident to the center of each grid cell; The transient current pulse generated by the drain of the off-state NMOS device at each simulation is recorded, and the transient current pulse is integrated to obtain the corresponding single-event drain collected charge; Based on the linear energy transfer value of the heavy ion, the total deposited charge amount of the heavy ion in the grid cell is determined; According to the single-event drain collected charge and the total deposited charge amount of each grid cell, the drain charge transfer coefficient of each grid cell is obtained; Based on the drain charge transfer coefficients of all the grid cells, the drain charge transfer coefficient distribution is generated.

[0011] Optionally, the circuit topology of the SRAM cell is used to establish a 6T SRAM cell circuit model, including: Based on the circuit topology of the SRAM cell, all NMOS devices and all PMOS devices constituting the 6T SRAM cell and the interconnection relationship of the NMOS devices and the PMOS devices are determined; According to the NMOS devices, the PMOS devices and the interconnection relationship, the 6T SRAM cell circuit model is established, wherein the 6T SRAM cell circuit model contains the off-state NMOS device.

[0012] Optionally, the flip threshold simulation on the 6T SRAM cell circuit model to obtain the flip critical charge quantity of the SRAM cell comprises: In the 6T SRAM cell circuit model, a predetermined sensitive region of the off-state NMOS device is irradiated with gradually increasing linear energy transfer values; The logic state of the storage node of the SRAM cell in each radiation simulation process is monitored; When the logic state of the storage node is first monitored to flip, a transient current pulse generated by the drain of the off-state NMOS device in this radiation is obtained, and the transient current pulse is integrated, and the charge quantity obtained by integration is determined as the flip critical charge quantity of the SRAM cell.

[0013] Optionally, the flip cross section of the SRAM array composed of the SRAM cell is predicted according to the charge collection calculation model and the layout area of the SRAM cell, comprising: Based on the charge collection calculation model, for each scanning incident position of heavy ions on the SRAM cell layout, the actual collection charge quantity of the heavy ions at the drain of the off-state NMOS device is obtained; The actual collection charge quantity corresponding to each scanning incident position is compared with the flip critical charge quantity, and if the actual collection charge quantity exceeds the flip critical charge quantity, it is determined that a single event upset event occurs at the scanning incident position; The total number of single event upset events occurring in all scanning incident positions is counted; According to the total number of flip events and the total number of scanning incident positions, the flip probability of a single SRAM cell under the heavy ion radiation condition is obtained; Based on the flip probability of a single SRAM cell and the total number of bits in the unit area projection of the multi-layer SRAM array, the flip cross section of the SRAM array is obtained.

[0014] In a second aspect, an evaluation system for single event radiation effects of a layout-level SRAM chip is provided, comprising: A three-dimensional stacked modeling and energy deposition simulation unit is configured to establish a three-dimensional stacked structure model of the SRAM chip, and perform heavy ion energy deposition simulation on the three-dimensional stacked structure model to obtain a three-dimensional spatial distribution of electron-hole pairs deposited by heavy ions in the silicon device layer of the three-dimensional stacked structure model. The layout processing and charge collection simulation unit determines the layout area of the SRAM unit based on the layout information of the SRAM unit of the SRAM chip, establishes a charge collection model of an off-state NMOS device in the SRAM unit, and simulates the charge collection model to obtain a drain charge transfer coefficient distribution of the off-state NMOS device. The circuit modeling and flipping threshold simulation unit is used for establishing a 6T SRAM unit circuit model based on the circuit topology of the SRAM unit, and performing flipping threshold simulation on the 6T SRAM unit circuit model to obtain a flipping critical charge amount of the SRAM unit. The integrated prediction unit constructs a charge collection calculation model by integrating the electron-hole pair three-dimensional space distribution, the drain charge transfer coefficient distribution and the flipping critical charge amount, and predicts a flipping cross section of an SRAM array composed of the SRAM unit according to the charge collection calculation model and the layout area of the SRAM unit.

[0015] In a third aspect, a computer device of the present application comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the above-mentioned layout-level SRAM chip single-particle radiation effect evaluation method when executing the computer program.

[0016] The layout-level SRAM chip single-particle radiation effect evaluation method, system and device of the present application first obtain the charge deposition distribution rule of heavy ions in the process layer through a three-dimensional stacked structure model and energy deposition simulation; secondly, the charge collection efficiency (drain charge transfer coefficient distribution) of the off-state NMOS device is quantified through the charge collection model simulation of the off-state NMOS device; finally, the flipping critical charge amount is determined through the 6T SRAM unit circuit model, and the acquisition of the three key parameters is relatively independent and reusable. In the final evaluation stage, instead of re-performing time-consuming physical simulation, a charge collection calculation model integrating the above-mentioned parameters is constructed to quickly simulate the charge amount collected when heavy ions are incident at different positions, and compared with the critical charge, the flipping cross section of the entire array is then calculated. The present application pre-positions and solidifies the most time-consuming fine physical simulation as core parameters, so that the evaluation of any array size is converted into efficient numerical scanning and statistical calculation, thereby realizing rapid and quantitative prediction of the anti-radiation performance of the SRAM array in the chip design stage.

[0017] Meanwhile, compared with the traditional estimation method based on empirical formula or simplified model, the present application ensures that the evaluation result has a solid physical basis and high accuracy through the multi-level physical modeling from bottom to top. First, at the charge generation level, the three-dimensional stacked structure model based on the actual process of the chip can accurately reflect the different material layers (such as , Cu, W) to the heavy ion energy, so as to obtain the three-dimensional spatial distribution of the initial electron-hole pair in the silicon device layer more truly. Secondly, at the charge collection layer, the off-state NMOS device charge collection model established based on the real layout, the drain charge transfer coefficient distribution obtained by simulation can accurately depict the collection efficiency of the deposited charge by the internal electric field and the geometry of the device, rather than using a uniform collection coefficient. Finally, at the flip-flop determination level, the flip-flop critical charge amount determined by 6T SRAM cell circuit simulation directly reflects the real flip-flop threshold of the specific circuit structure under the instantaneous current impact. By integrating the three key parameters accurately obtained from different physical levels, the charge collection calculation model constructed can more truly simulate the complete chain effect of charge deposition-charge collection-circuit response, so as to make a more reliable and accurate prediction of the single event upset cross section of the SRAM array in the spatial radiation environment than the empirical method or the partially simplified simulation, and provide a high-confidence simulation basis for radiation hardening design. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 A flowchart of the layout-level SRAM chip single particle radiation effect evaluation method of the embodiment of the present application is shown in the figure. Figure 2 A three-dimensional stack SRAM material stack modeling diagram of the embodiment of the present application is shown in the figure. Figure 3 An NMOS, PMOS device modeling diagram in the SRAM cell of the embodiment of the present application is shown in the figure. Figure 4 A LET=0.003 pC / um device area conversion coefficient diagram of the embodiment of the present application is shown in the figure. Figure 5 A diagram of the off-state NMOS drain current generated by the incident particle when LET=0.0022 (pC / um) of the embodiment of the present application is shown in the figure. Figure 6 A 14nm FinFET SRAM cell layout diagram of the embodiment of the present application is shown in the figure. Figure 7 A numerical comparison diagram obtained by calculating the flip-flop cross section of the SRAM array of the 14nm FinFET SRAM cell layout of the embodiment of the present application is shown in the figure. Figure 8 A structure diagram of the layout-level SRAM chip single particle radiation effect evaluation system of the embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0019] In order to make the above objectives, characteristics and advantages of the present application more apparent, specific embodiments of the present application will be described in detail below with reference to the accompanying drawings. Although some embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms, and should not be interpreted as being limited to the embodiments set forth herein, but rather, these embodiments are provided so as to more thoroughly and completely understand the present application. It should be understood that the drawings and embodiments of the present application are merely for exemplary purposes, and are not intended to limit the scope of protection of the present application.

[0020] It should be understood that each of the steps recited in the method embodiments of the present application can be performed in different orders, and / or in parallel. In addition, the method embodiments can include additional steps and / or omit the steps shown. The scope of the present application is not limited in this respect.

[0021] The term "comprising" and variations thereof as used herein are open-ended, that is "including, but not limited to"; the term "based on" is "based, at least in part, on"; the term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments"; the term "optional" means "optional in at least some embodiments". Related definitions are given throughout the detailed description. It should be noted that the concepts mentioned in the present application are merely for distinguishing different devices, modules or units, and are not intended to limit the functions of the devices, modules or units.

[0022] It should be noted that the terms "one" and "a" and "multiple" are illustrative and not limiting, and those skilled in the art will understand that, unless the context clearly indicates otherwise, "one" or "a" should be understood as "one or more".

[0023] In conjunction Figure 1 As shown, the embodiment of the present application provides a layout-level SRAM chip single-particle radiation effect evaluation method, comprising: A three-dimensional stacked structure model of the SRAM chip is established, and heavy ion energy deposition simulation is performed on the three-dimensional stacked structure model to obtain a three-dimensional spatial distribution of electron-hole pairs deposited by heavy ions in the silicon device layer of the three-dimensional stacked structure model.

[0024] Specifically, according to the manufacturing process data and layout information of the chip, a multi-layer three-dimensional stacked structure model reflecting the actual material composition and geometric layout is constructed. For example, Figure 2As shown, the model abstracts the multi-layer material stack-up relationship of the chip. After the 3D structure modeling is completed, heavy ion energy deposition simulation is performed. During the simulation, for example, heavy ion vertical incidence can be set, the 3D model is discretized in space with a unit grid of a preset size, and by simulating the heavy ion penetration process, the deposition energy of the heavy ion in each grid is obtained. Subsequently, the deposition energy in the grid is converted into the corresponding number of electron-hole pairs according to the ionization energy required by the silicon material constituting the silicon device layer to generate electron-hole pairs. Finally, based on the conversion results of all grids, the 3D spatial distribution data of the electron-hole pairs deposited by the heavy ion in the silicon device layer are generated.

[0025] Based on the layout information of the SRAM cell of the SRAM chip, the layout area of the SRAM cell is determined, and a charge collection model of the off-state NMOS device in the SRAM cell is established; and the charge collection model is simulated to obtain the drain charge transfer coefficient distribution of the off-state NMOS device.

[0026] Specifically, the layout area of the SRAM cell is obtained, which is directly determined from the layout information of the SRAM cell. At the same time, based on the same layout information, a charge collection model is established to quantify the charge collection efficiency of the off-state NMOS device. Specifically, first, the two-dimensional geometric profile and size of the off-state NMOS device are extracted, and a two-dimensional projection model is established thereon, the structure of which is shown in, for example, Figure 3 Subsequently, the sensitive region of the device is meshed on the two-dimensional projection model. For each meshed grid unit, a heavy ion with a set linear energy transfer value (LET) is simulated to be incident at the center thereof, the transient current pulse induced at the drain of the device by each incidence is recorded, and the pulse is integrated to obtain the single-event drain collection charge corresponding to the grid unit. At the same time, based on the LET value of the incident heavy ion, the total charge deposited in the corresponding grid unit is obtained. By calculating the ratio of the collected charge to the total deposited charge of each grid unit, the drain charge transfer coefficient of each grid unit is obtained. The coefficients of all grid units constitute the drain charge transfer coefficient distribution of the off-state NMOS device, and the spatial variation thermodynamic map form is shown in, for example, Figure 4

[0027] Exemplarily, device models are constructed for the NMOS and PMOS in the SRAM cell, as shown in, for example, Figure 3 Then, the central region of the off-state NMOS of the SRAM cell storing data is struck with LET=0.0018 (pC / um) to LET=0.0025 (pC / um) at a step size of 0.0001 (pC / um), the LET value is gradually increased, and the coupled potential is flipped, Figure 5 is the drain pulse current of the off-state NMOS when the flip occurs. ​

[0028] Based on the circuit topology of the SRAM cell, a 6T SRAM cell circuit model is established; and a flip threshold simulation is performed on the 6T SRAM cell circuit model to obtain the flip critical charge amount of the SRAM cell.

[0029] Specifically, based on the circuit topology of the SRAM cell, all NMOS and PMOS devices constituting the 6T SRAM cell and their interconnection relationship are determined, and a 6T SRAM cell circuit model containing the off-state NMOS device is established accordingly. A predetermined sensitive region (such as the central region) of the off-state NMOS device is irradiated with a gradually increasing linear energy transfer value (LET), and the logic state of the SRAM cell storage node is monitored in each simulation. When the logic state is first monitored to flip, the transient current pulse generated at the drain of the off-state NMOS device by this time of irradiation is obtained, integrated, and the charge amount obtained by the integration is determined as the flip critical charge amount of the SRAM cell, wherein the pulse current waveform is as shown in the following figure. Figure 5

[0030] By integrating the three-dimensional spatial distribution of the electron-hole pairs, the drain charge transfer coefficient distribution, and the flip critical charge amount, a charge collection calculation model is constructed, and the flip cross section of the SRAM array composed of the SRAM cell is predicted according to the charge collection calculation model and the layout area of the SRAM cell.

[0031] Specifically, by integrating the three-dimensional spatial distribution of the electron-hole pairs, the drain charge transfer coefficient distribution, and the flip critical charge amount obtained in the above steps, a charge collection calculation model is constructed. Based on this model, the heavy ions under specific radiation conditions are evaluated, and for each scanning incident position of the heavy ions on the layout of the SRAM cell, the actual collection charge amount at the drain of the off-state NMOS device is calculated by the model. The actual collection charge amount is compared with the flip critical charge amount to determine whether a single event upset occurs at each position, the total number of flip events occurring in all scanning positions is counted, and the flip probability of a single SRAM cell under this radiation condition is calculated accordingly. Combined with the previously determined layout area of the SRAM cell, the flip cross section of the cell is calculated. Finally, based on the flip cross section of the cell and the total number of cells contained in the SRAM array, the flip cross section of the entire SRAM array is derived. As shown in the following figure, the layout of the array is calculated by the method of the embodiment for different heavy ions, and the flip cross section result as shown in the following figure is obtained, which verifies the effectiveness of the method. Figure 6 Figure 7

[0032] Optionally, the establishing of the three-dimensional stacked structure model of the SRAM chip comprises: ​​​Based on the manufacturing process data and layout information of the SRAM chip, a multi-layer stacked geometric model reflecting the actual material composition of the SRAM chip is constructed, wherein the multi-layer stacked geometric model sequentially includes: a plurality of layers insulating dielectric layers, Cu wiring layers arranged between the insulating dielectric layers, a W metal contact layer, and a silicon device layer; The silicon device layer includes an active region structure of a FinFET device, a substrate, and a well region structure.

[0033] Specifically, the construction of the three-dimensional stacked structure model is specifically based on the manufacturing process data and layout information of the SRAM chip to truly reflect the actual material composition. The model is a multi-layer stacked geometric model, which sequentially includes a plurality of layers insulating dielectric layers, Cu wiring layers arranged between the insulating dielectric layers, a W metal contact layer, and a silicon device layer; wherein the silicon device layer further includes an active region structure of a FinFET device, a substrate, and a corresponding well region structure, thereby geometrically completely describing the functional layers and physical levels of the chip. In a specific implementation, the three-dimensional stacked geometric model is divided into a unit grid of 2nm x 2nm x 2nm in space to facilitate the subsequent fine recording and calculation of energy deposition; at the same time, in this embodiment, the incident angles of heavy ions are all set to be perpendicular to the horizontal plane direction of the chip, which provides a clear boundary condition and calculation framework for energy deposition simulation.

[0034] In this optional embodiment, a three-dimensional stacked geometric model including a plurality of layers insulating dielectric layers, Cu wiring layers, W metal contact layers, and a silicon device layer integrated with FinFET active regions, substrates, and well region structures is constructed based on the actual manufacturing process data and layout information of the SRAM chip, and a 2nm fine grid division and a perpendicular incidence condition are used in simulation, establishing a high-fidelity physical structure representation method, improving the physical fidelity and spatial resolution of heavy ion energy deposition simulation, and more accurately reflecting the influence of different material interfaces and complex device structures on particle energy attenuation and charge generation distribution, thereby providing reliable and fine initial physical input for subsequent charge collection, flip determination, and array cross-section prediction, effectively overcoming the shortcomings of traditional simplified models in describing advanced process chip multi-layer heterogeneous structures, and laying the key foundation for the accuracy of the full-process evaluation results.

[0035] Optionally, the three-dimensional stacked structure model is simulated for heavy ion energy deposition to obtain a three-dimensional spatial distribution of electron-hole pairs deposited by heavy ions in the silicon device layer of the three-dimensional stacked structure model, including: The heavy ions are set to be vertically incident to the three-dimensional stacked structure model; The three-dimensional stacked structure model is divided into a unit grid of a preset size in three-dimensional space. simulate a process of the heavy ion penetrating the three-dimensional stacked structure model to obtain a deposition energy of the heavy ion in each unit grid; convert the deposition energy in each grid into a corresponding number of electron-hole pairs based on an ionization energy required for generating a single electron-hole pair from a silicon material constituting the silicon device layer; generate three-dimensional spatial distribution data of the electron-hole pairs in the silicon device layer based on the number of electron-hole pairs in all grids.

[0036] Specifically, first, an initial condition of simulation is set, i.e., the heavy ion is incident to the three-dimensional stacked structure model in a direction perpendicular to a horizontal plane of the chip, which simplifies the incident geometry, focuses on studying the common and important radiation scene of vertical incidence, and establishes a clear benchmark for subsequent analysis. In the simulation preparation stage, the three-dimensional stacked structure model that has been constructed is finely discretized in three-dimensional space, and specifically, a cube with a side length of 2 nm is used as a unit grid with a preset size to divide the entire model volume, so that the micro energy deposition characteristics of the heavy ion track can be captured with high resolution, and each grid after division is used as a basic unit for recording energy deposition.

[0037] Then, a physical process simulation is performed, a particle transport simulation tool based on the Monte Carlo method is used to simulate the whole process of the heavy ion penetrating the three-dimensional stacked structure model containing multiple layers of materials, and the energy value deposited by ionization loss in each 2 nm x 2 nm x 2 nm unit grid is calculated. The output of this step is a set of deposition energy data corresponding to each grid. Finally, data conversion and generation are performed, based on the grid deposition energy obtained above, and according to the average ionization energy of about 3.6 eV required for generating one electron-hole pair from the silicon material constituting the silicon device layer, the deposition energy value in each grid is divided by the ionization energy, so as to convert the number of electron-hole pairs deposited in the grid; the conversion results of all grids are accumulated and integrated, i.e., three-dimensional spatial distribution data of the electron-hole pairs deposited by the heavy ion in the silicon device layer are generated, which are indexed by grids and completely characterize the initial spatial form of charge generation, providing accurate input for subsequent charge collection calculation.

[0038] Optionally, in the embodiment, by setting the heavy ion vertical incidence condition to establish a reproducible benchmark radiation scenario, and using a 2nm fine grid to spatially disperse the three-dimensional stacked structure model, combining the Monte Carlo method to simulate the energy deposition of particles penetrating multi-layer materials, and then converting the deposited energy into the number of electron-hole pairs according to the characteristic ionization energy of silicon material, the high-resolution, physically accurate quantitative description of the charge generation process of heavy ions in the chip sensitive layer is realized. The three-dimensional spatial distribution data of electron-hole pairs provides a real and detailed initial charge distribution input for subsequent charge collection efficiency calculation and flip event judgment, significantly improving the physical credibility and prediction accuracy of the full-link simulation results.

[0039] Optionally, based on the layout information of the SRAM unit of the SRAM chip, the layout area of the SRAM unit is determined, and a charge collection model of the off-state NMOS device in the SRAM unit is established, comprising: determining the layout area of the SRAM unit according to the layout information, and extracting the two-dimensional geometric profile and size of the off-state NMOS device based on the layout information; establishing a two-dimensional projection model of the NMOS device by taking the two-dimensional geometric profile and the size as boundaries; dividing the active area corresponding to the NMOS device in the two-dimensional projection model into a plurality of grid cells; and taking the two-dimensional projection model divided into a plurality of grid cells as the charge collection model.

[0040] Specifically, from the layout design file (such as GDSII format) of the SRAM unit, the geometric data is read and parsed by using electronic design automation (EDA) tools, the total area of the closed region of all layer graphics on the plane is calculated, and the layout area of the SRAM unit is directly and accurately determined; at the same time, from the same layout information, the accurate two-dimensional geometric profile and key size of the specific off-state NMOS device are extracted by layer selection and graphic Boolean operation, including the shape and position information of its active area, gate, source-drain contact and other components, which provides a geometric basis for subsequent device-level modeling.

[0041] Then, taking the extracted two-dimensional geometric profile and key size of the off-state NMOS device as strict boundaries, a simplified two-dimensional plane model, i.e. a two-dimensional projection model of the NMOS device, is constructed in the simulation environment; this model ignores the three-dimensional depth details of the device, but accurately retains the physical boundaries and functional division on the top-down plane, which is used to simulate the lateral geometric effect of charge collection when heavy ions are incident at different positions on the device plane. The projection plane size can refer to the example of 44nm×150nm in the embodiment.

[0042] Then, the two-dimensional projection model established above is discretely processed in detail, and the corresponding active area, i.e., the main charge collection sensitive area, is divided into grid units with a preset size. Specific parameters can refer to the embodiments, for example, the length of the conversion coefficient grid is selected as 6-8 nm, which is close to the interval of the Gaussian distribution of the charge diffusion as the Gaussian distribution parameter of the charge diffusion, and the length of the conversion coefficient grid is set to 6-8 nm, which is close to the interval of the Gaussian distribution of the charge diffusion to 4 to ensure that the discretization accuracy can reasonably reflect the continuous physical process of charge collection. When dividing, the symmetry of the device structure can be used to optimize the scanning range, for example, the FinFET device is symmetric about the left and right fins, and only the key area needs to be divided.

[0043] Finally, the two-dimensional projection model after the above grid division is defined as a whole and used as the charge collection model. Each grid unit in the model corresponds to a spatial position that needs to be independently evaluated in subsequent simulation. The entire model is a numerical carrier for systemically simulating and evaluating the charge collection efficiency of the off-state NMOS device at different local positions, i.e., the drain charge transfer coefficient, and preparing for the next step of performing heavy ion scanning simulation and generating a transfer coefficient distribution map.

[0044] In the optional embodiment, the layout area of the SRAM cell is accurately determined directly from the layout information of the SRAM cell, and the real two-dimensional geometric profile and size of the off-state NMOS device are extracted synchronously, so that the design data is seamlessly converted into a simulation boundary, and a two-dimensional projection model based on strict physical boundaries is constructed. By implementing fine grid division based on charge diffusion physics in the active area of the model, a charge collection model that can systematically evaluate spatial position dependence is formed. Not only does it ensure that the acquisition of key geometric parameters such as layout area and the establishment of the simulation model are rooted in unique and accurate layout source data, eliminating errors caused by human simplification or estimation, but also it realizes quantitative characterization of the spatial difference of the internal charge collection efficiency of the device through the grid model, thereby providing a geometric and physical basis highly consistent with the actual chip design for subsequent accurate acquisition of the drain charge transfer coefficient distribution, significantly enhancing the credibility and predictability of the entire evaluation process.

[0045] Optionally, the simulation of the charge collection model to obtain the drain charge transfer coefficient distribution of the off-state NMOS device includes: for each grid unit in the charge collection model, simulating the incidence of a heavy ion with a set linear energy transfer value to the center of each grid unit; recording the transient current pulse generated by the drain of the off-state NMOS device at each simulation, and integrating the transient current pulse to obtain the corresponding single-event drain collected charge; determining a total deposited charge amount of the heavy ion within the grid cell based on the linear energy transfer value of the heavy ion; obtaining a drain charge transfer coefficient of each of the grid cells according to the single event drain collected charge and the total deposited charge amount of each of the grid cells; generating the drain charge transfer coefficient distribution based on the drain charge transfer coefficients of all of the grid cells.

[0046] Specifically, a systematic scanning simulation is performed on the established charge collection model. For each grid cell divided in the active region of the model, a heavy ion with a set linear energy transfer value, such as LET = 0.003 pC / um, is simulated to vertically incident on the geometric center position of the grid cell. In specific implementation, the scanning strategy can be optimized in combination with the symmetry of the device. For example, for a FinFET structure, only 3 columns of 20 strike points can be set in one half of the substrate, and 1 column of 20 strike points can be set in the center of the fin, to efficiently cover the sensitive area. Secondly, in each single particle incidence simulation, the transient current pulse waveform generated by the off-state NMOS device drain node is recorded by a device simulation tool. Then, the current pulse is numerically integrated in the time domain, and the integration result is the charge amount actually collected by the NMOS device drain for the single particle event at the specific position. This step quantifies the charge collection efficiency of a single position point. Next, according to the preset linear energy transfer value of the incident heavy ion and the track length of the particle in the material, the total charge amount deposited by the heavy ion in the silicon material corresponding to the grid cell is calculated. This calculation is based on the relationship between the ionization ability of the heavy ion and the material characteristics, and provides a denominator benchmark for evaluating the charge collection efficiency.

[0047] Finally, the single event drain collected charge corresponding to each grid cell is divided by the total deposited charge amount thereof, to obtain the drain charge transfer coefficient of the grid cell. After the calculation is completed by traversing all the grid cells, the transfer coefficient values of all the grid cells are integrated and visually expressed according to their spatial positions, to generate a two-dimensional distribution map completely characterizing the spatial variation of the charge collection efficiency of the off-state NMOS device in the entire active region. The data form can be a heat map, such as the conversion coefficient distribution shown in FIG. 2. Figure 4 The output result of this process is the conversion coefficient distribution shown in FIG. 2.

[0048] In this optional embodiment, by adopting a systematic grid scanning simulation strategy and combining the symmetry of the device structure to optimize the scanning area, such as scanning only half of the substrate area of the FinFET device and setting specific row and column impact points, the data acquisition efficiency of obtaining the charge collection efficiency distribution of the off-state NMOS device is significantly improved; by accurately recording the transient current pulse of the drain in each simulation and integrating it, the single-event drain collection charge of each grid position is quantitatively obtained, and the total deposited charge amount corresponding to each grid is calculated based on the preset linear energy transfer value, thereby reliably obtaining the drain charge transfer coefficient of each grid unit; finally, the coefficients of all grids are integrated to generate a two-dimensional distribution map, realizing fine and quantitative characterization of the spatial variation of the charge collection efficiency in the active region of the device. The distribution result provides key and accurate input data for the subsequent charge collection calculation model, effectively supporting the accuracy and reliability of the entire evaluation process.

[0049] Optionally, based on the circuit topology structure of the SRAM cell, a 6T SRAM cell circuit model is established, including: Based on the circuit topology structure of the SRAM cell, the interconnection relationship of all NMOS devices and all PMOS devices constituting the 6T SRAM cell and the NMOS devices and the PMOS devices is determined; According to the NMOS devices, the PMOS devices and the interconnection relationship, the 6T SRAM cell circuit model is established, wherein the 6T SRAM cell circuit model contains the off-state NMOS device.

[0050] Specifically, first, based on the circuit design data of the SRAM cell, such as the netlist or schematic diagram, the fixed circuit topology structure is parsed to determine all six transistor devices constituting a complete 6T SRAM memory cell, including four NMOS devices and two PMOS devices, and the interconnection relationship between these devices is accurately extracted, including the connection mode between the source, drain and gate of each transistor and the connection relationship with the power supply (VDD), ground (GND), bit line (BL, BLB) and word line (WL); then, according to the determined NMOS devices, PMOS devices and their detailed interconnection relationship, the 6T SRAM cell circuit model is constructed in the circuit simulation environment, which completely reproduces the core circuit structure of the SRAM cell as a cross-coupled inverter; when constructing the model, the specific NMOS device in the storage "0" or "1" state needs to be applied with the corresponding gate-source voltage condition according to the simulation purpose, so that it is in the off state, thereby ensuring that the 6T SRAM cell circuit model clearly contains the off-state NMOS device for subsequent simulation of the circuit response and flip threshold of the specific device under heavy ion radiation.

[0051] In this optional embodiment, by strictly following the real circuit topology of the SRAM cell, all NMOS and PMOS devices and their interconnection relationships are determined, and a precise 6T SRAM cell circuit model containing a specific off-state NMOS device is constructed accordingly, thus realizing the real modeling of the circuit response of the storage cell in the actual working state. This method can directly and accurately determine the critical charge amount for flip through subsequent circuit simulation, avoiding the errors caused by traditional empirical estimation or simplified models, thus ensuring the high precision and high reliability of the entire single event effect evaluation process at the circuit response level, and providing a solid circuit-level foundation for the final accurate prediction of the array flip cross section.

[0052] Optionally, the flip threshold simulation on the 6T SRAM cell circuit model to obtain the flip critical charge amount of the SRAM cell comprises: In the 6T SRAM cell circuit model, a predetermined sensitive region of the off-state NMOS device is irradiated with a gradually increasing linear energy transfer value; The logic state of the storage node of the SRAM cell in each radiation simulation process is monitored; When the logic state of the storage node is first monitored to flip, the transient current pulse generated by the drain of the off-state NMOS device in this radiation is obtained, and the transient current pulse is integrated, and the charge amount obtained by integration is determined as the flip critical charge amount of the SRAM cell.

[0053] Specifically, in the constructed circuit model, first, a small initial linear energy transfer value (LET) is set, and a predetermined sensitive region of the off-state NMOS device, such as the device center region, is selected as the radiation target point, then the LET value of the heavy ion used in the simulation is gradually increased by a pre-set fixed step, for example, 0.0001 pC / µm, and a series of radiation simulations are sequentially performed, and this process continues until a key change in the circuit state is observed.

[0054] In each simulation run, the logic level of the storage node in the SRAM cell that determines the data state, i.e., the common output node of the two cross-coupled inverters, or the coupling point, is continuously monitored; when the monitoring system first identifies that the logic state of the node has a stable and irreversible flip, for example, from high level to low level, which means that the stored data changes from "1" to "0", it is determined that the LET value corresponding to this simulation is the critical condition for triggering the flip, and the simulation process stops at this moment.

[0055] Immediately, the complete transient current pulse waveform induced by the specific radiation event triggering the flip at the drain of the off-state NMOS device is extracted and recorded, for example, Figure 5The drain pulse current is shown; by numerically integrating this current pulse over the time axis, the total charge contained in this pulse is accurately calculated; finally, the charge obtained by this integration is formally defined as the critical charge (Qcrit) required for the SRAM cell to occur single event upset, which is the core decision threshold for subsequent evaluation of whether a single event causes an error.

[0056] In this optional embodiment, by gradually increasing the linear energy transfer value (LET) and systematically scanning the sensitive region of the off-state NMOS device, combined with real-time monitoring of the logic state of the SRAM cell storage node, the critical radiation condition that first triggers data upset can be accurately captured, and by integrating the drain transient current pulse under this specific condition, the upset critical charge is directly and accurately determined. Not only does this avoid the errors caused by traditional empirical estimation or indirect derivation, but it also provides a real and reliable circuit-level upset decision threshold for the entire single event effect evaluation process.

[0057] Optionally, the upset cross section of the SRAM array composed of the SRAM cell according to the charge collection calculation model and the layout area of the SRAM cell comprises: Based on the charge collection calculation model, for each scanning incident position of heavy ions on the SRAM cell layout, the actual collection charge of the heavy ions at the drain of the off-state NMOS device is obtained; Compare the actual collection charge corresponding to each scanning incident position with the upset critical charge. If the actual collection charge exceeds the upset critical charge, it is determined that a single event upset occurs at this scanning incident position; Statistical total number of single event upsets occurring in all scanning incident positions; According to the total number of upset events and the total number of scanning incident positions, the upset probability of a single SRAM cell under the heavy ion radiation condition is obtained; Based on the upset probability of a single SRAM cell and the total number of bits in the unit area projection of the multi-layer SRAM array, the upset cross section of the SRAM array is obtained.

[0058] In the optional embodiment, a charge collection calculation model integrating the three-dimensional spatial distribution of electron-hole pairs and the distribution of charge transfer coefficients of the drain is used to calculate each preset scanning incident position of heavy ions of specific types and energies, such as O 90 MeV, Cl 160 MeV, etc., on the layout of the SRAM cell; for each position, the model quickly calculates the amount of charge actually collected by the drain of the off-state NMOS device in the incident event by combining the deposited charge distribution of the position and the charge transfer coefficient of the corresponding grid, which replaces the time-consuming sequential physical simulation and realizes efficient calculation. Secondly, the actual collected charge amount obtained by calculating each scanning incident position is compared with the flip critical charge amount of the SRAM cell determined in advance through circuit simulation; if the actual collected charge amount of a certain position exceeds the critical charge amount, it is determined that an effective single event upset event occurs at the position; by traversing and comparing all scanning positions, the identification of all possible upset events is completed.

[0059] Then, the total number of single event upset events determined to occur in all scanning incident positions is counted; this number reflects the sensitivity of the SRAM cell to upset under the specific heavy ion radiation.

[0060] Then, the ratio of the total number of upset events to the total number of preset scanning incident positions, i.e., the total number of samples, is calculated to obtain the upset probability of a single SRAM cell under the specific heavy ion radiation condition; the probability statistically represents the risk of errors occurring in the cell due to radiation. Finally, based on the calculated upset probability of a single SRAM cell and the total number of bits in the projection of the multi-layer SRAM array per unit area, the total upset cross section of the entire SRAM array under the corresponding radiation condition can be derived, thereby completing the quantitative evaluation from the characteristics of the cell to the performance of the array level, and the calculation result is shown in the following table as an example. Figure 7

[0061] In combination with the table shown in Figure 8 The embodiment of the present application provides a layout-level SRAM chip single event radiation effect evaluation system, which comprises: A three-dimensional stacked modeling and energy deposition simulation unit is configured to establish a three-dimensional stacked structure model of an SRAM chip, and perform heavy ion energy deposition simulation on the three-dimensional stacked structure model to obtain a three-dimensional spatial distribution of electron-hole pairs deposited by heavy ions in a silicon device layer of the three-dimensional stacked structure model. A layout processing and charge collection simulation unit is configured to determine the layout area of an SRAM cell of the SRAM chip based on layout information of the SRAM cell, and establish a charge collection model of an off-state NMOS device in the SRAM cell; and perform simulation on the charge collection model to obtain a distribution of charge transfer coefficients of the drain of the off-state NMOS device.​ circuit modeling and flipping threshold simulation unit, for establishing a 6T SRAM cell circuit model based on a circuit topology of the SRAM cell, and performing flipping threshold simulation on the 6T SRAM cell circuit model to obtain a flipping critical charge amount of the SRAM cell; integrated prediction unit, for constructing a charge collection calculation model by integrating the three-dimensional spatial distribution of the electron-hole pairs, the drain charge transfer coefficient distribution and the flipping critical charge amount, and predicting a flipping cross section of an SRAM array composed of the SRAM cells according to the charge collection calculation model and the layout area of the SRAM cell.

[0062] The evaluation system of the layout-level SRAM chip single-particle radiation effect of the present application has the same advantages as the evaluation method of the layout-level SRAM chip single-particle radiation effect of the present application compared with the prior art, which will not be repeated here.

[0063] The embodiment of the present application also provides a computer device, which comprises a memory, a processor and a computer program stored in the memory and executable on the processor, and the processor realizes the evaluation method of the layout-level SRAM chip single-particle radiation effect when executing the computer program.

[0064] The computer device of the present application has the same advantages as the evaluation method of the layout-level SRAM chip single-particle radiation effect compared with the prior art, which will not be repeated here.

[0065] The embodiment of the present application also provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to realize the evaluation method of the layout-level SRAM chip single-particle radiation effect.

[0066] The computer readable storage medium of the present application has the same advantages as the evaluation method of the layout-level SRAM chip single-particle radiation effect compared with the prior art, which will not be repeated here.

[0067] Although the present application is disclosed as above, the protection scope of the present application is not limited to this. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and these changes and modifications will fall within the protection scope of the present application.

Claims

1. A method for evaluating the single-event radiation effect of a layout-level SRAM chip, characterized in that, include: A three-dimensional stacked structure model of an SRAM chip was established, and heavy ion energy deposition simulation was performed on the three-dimensional stacked structure model to obtain the three-dimensional spatial distribution of electron-hole pairs deposited by heavy ions in the silicon device layer of the three-dimensional stacked structure model. Based on the layout information of the SRAM cells of the SRAM chip, the layout area of ​​the SRAM cells is determined, and a charge collection model of the off-state NMOS device in the SRAM cells is established; the charge collection model is simulated to obtain the drain charge transfer coefficient distribution of the off-state NMOS device. Based on the circuit topology of the SRAM cell, a 6T SRAM cell circuit model is established; and a flip threshold simulation is performed on the 6T SRAM cell circuit model to obtain the flip critical charge of the SRAM cell. By integrating the three-dimensional spatial distribution of electron-hole pairs, the distribution of drain charge transfer coefficients, and the critical charge for flipping, a charge collection calculation model is constructed, and the flipping cross section of the SRAM array composed of the SRAM cells is predicted based on the charge collection calculation model and the layout area of ​​the SRAM cells.

2. The method for evaluating the single-event radiation effect of a layout-level SRAM chip according to claim 1, characterized in that, The establishment of the three-dimensional stacked structure model of the SRAM chip includes: Based on the manufacturing process data and layout information of the SRAM chip, a multilayer stacked geometric model reflecting the actual material composition of the SRAM chip is constructed. The multilayer stacked geometric model sequentially includes: multiple layers... An insulating dielectric layer, a Cu wiring layer disposed between the insulating dielectric layers, a W metal contact layer, and a silicon device layer; The silicon device layer includes the active region structure, substrate, and well region structure of the FinFET device.

3. The method for evaluating the single-event radiation effect of a layout-level SRAM chip according to claim 2, characterized in that, The heavy-ion energy deposition simulation of the three-dimensional stacked structure model yields the three-dimensional spatial distribution of electron-hole pairs deposited by heavy ions in the silicon device layer of the three-dimensional stacked structure model, including: The heavy ions are assumed to be incident perpendicularly onto the three-dimensional stacked structure model; The three-dimensional stacked structure model is divided into three-dimensional spaces using a unit grid of a preset size; The process of heavy ions penetrating the three-dimensional stacked structure model was simulated to obtain the deposition energy of the heavy ions in each unit grid. Based on the deposition energy, and according to the ionization energy required to generate a single electron-hole pair from the silicon material constituting the silicon device layer, the deposition energy in each grid is converted into the corresponding number of electron-hole pairs. Based on the number of electron-hole pairs in all grids, three-dimensional spatial distribution data of the electron-hole pairs in the silicon device layer is generated.

4. The method for evaluating the single-event radiation effect of a layout-level SRAM chip according to claim 1, characterized in that, The process of determining the layout area of ​​the SRAM cell based on the layout information of the SRAM chip and establishing a charge collection model for the off-state NMOS device in the SRAM cell includes: The layout area of ​​the SRAM cell is determined based on the layout information, and the two-dimensional geometric contour and dimensions of the off-state NMOS device are extracted based on the layout information. Using the two-dimensional geometric contour and the dimensions as boundaries, a two-dimensional projection model of the NMOS device is established. The active region of the NMOS device in the two-dimensional projection model is divided into multiple grid cells; the two-dimensional projection model divided into multiple grid cells is used as the charge collection model.

5. The method for evaluating the single-event radiation effect of a layout-level SRAM chip according to claim 4, characterized in that, The simulation of the charge collection model to obtain the drain charge transfer coefficient distribution of the off-state NMOS device includes: For each grid cell in the charge collection model, heavy ions with a set linear energy transfer value are simulated to be incident on the center of each grid cell; Record the transient current pulse generated at the drain of the off-state NMOS device during each simulation, and integrate the transient current pulse to obtain the corresponding drain charge collected in a single event; Based on the linear energy transfer value of the heavy ions, the total charge deposited by the heavy ions within the grid cell is determined; The drain charge transfer coefficient of each grid cell is obtained based on the drain charge collected in a single event and the total deposited charge of each grid cell. The drain charge transfer coefficient distribution is generated based on the drain charge transfer coefficients of all the grid cells.

6. The method for evaluating the single-event radiation effect of a layout-level SRAM chip according to claim 1, characterized in that, The circuit topology based on the SRAM cell is used to establish a 6T SRAM cell circuit model, including: Based on the circuit topology of the SRAM cell, the interconnection relationships between all NMOS devices and all PMOS devices constituting the 6T SRAM cell, as well as between the NMOS devices and the PMOS devices, are determined. Based on the NMOS device, the PMOS device, and the interconnection relationship, a 6T SRAM cell circuit model is established, wherein the 6T SRAM cell circuit model includes the off-state NMOS device.

7. The method for evaluating the single-event radiation effect of a layout-level SRAM chip according to claim 6, characterized in that, The step of performing a flip-flop threshold simulation on the 6T SRAM cell circuit model to obtain the flip-flop critical charge of the SRAM cell includes: In the 6T SRAM cell circuit model, the radiation of a predetermined sensitive region of the off-state NMOS device is simulated with a gradually increasing linear energy transfer value; Monitor the logic state of the storage nodes of the SRAM cells during each radiation simulation; When the logic state of the memory node is first detected to be flipped, the transient current pulse generated by this radiation at the drain of the off-state NMOS device is acquired, and the transient current pulse is integrated. The amount of charge obtained by integration is determined as the flipping critical charge of the SRAM cell.

8. The method for evaluating the single-event emission effect of a layout-level SRAM chip according to claim 1, characterized in that, The step of predicting the flip-out cross section of the SRAM array composed of the SRAM cells based on the charge collection calculation model and the layout area of ​​the SRAM cells includes: Based on the charge collection calculation model, for each scan incident position of heavy ions on the SRAM cell layout, the actual collected charge of the heavy ions at the drain of the off-state NMOS device is obtained; The actual collected charge at each of the scanning incident positions is compared with the flip critical charge. If the actual collected charge exceeds the flip critical charge, a single-particle flip event is determined to have occurred at that scanning incident position. Count the total number of single-particle flip events that occurred at all of the stated scan incident positions; The flipping probability of a single SRAM cell under heavy ion radiation conditions is obtained based on the total number of flipping events and the total number of scanned incident positions. The flipping cross section of the SRAM array is obtained based on the flipping probability of a single SRAM cell and the total number of bits of the multilayer SRAM array projected per unit area.

9. A system for evaluating the single-event radiation effect of a layout-level SRAM chip, characterized in that, include: The three-dimensional stacking modeling and energy deposition simulation unit is used to establish a three-dimensional stacking structure model of SRAM chip and perform heavy ion energy deposition simulation on the three-dimensional stacking structure model to obtain the three-dimensional spatial distribution of electron-hole pairs deposited by heavy ions in the silicon device layer of the three-dimensional stacking structure model. The layout processing and charge collection simulation unit determines the layout area of ​​the SRAM cell based on the layout information of the SRAM cell of the SRAM chip, and establishes a charge collection model of the off-state NMOS device in the SRAM cell; and simulates the charge collection model to obtain the drain charge transfer coefficient distribution of the off-state NMOS device. The circuit modeling and flip-threshold simulation unit is used to establish a 6T SRAM cell circuit model based on the circuit topology of the SRAM cell; and to perform flip-threshold simulation on the 6T SRAM cell circuit model to obtain the flip-threshold critical charge of the SRAM cell. The integrated prediction unit constructs a charge collection calculation model by integrating the three-dimensional spatial distribution of electron-hole pairs, the drain charge transfer coefficient distribution, and the flip critical charge, and predicts the flip cross section of the SRAM array composed of the SRAM cells based on the charge collection calculation model and the layout area of ​​the SRAM cells.

10. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the method for evaluating the single-event radiation effect of a layout-level SRAM chip as described in any one of claims 1 to 8.

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