Integrated circuit layout planning method and device

Abstract

The invention provides a layout planning method and device for an integrated circuit, and the method comprises the steps: obtaining the current state information, the current state information comprises image information, graph information and sequence information, the image information comprises the image information of a mask, and the image information of the mask indicates the constraint of a deployment motion space of a current to-be-deployed module; the image information, the graph information and the sequence information serve as input of a strategy network model, the deployment action of the current to-be-deployed module is output, and the deployment action indicates the deployment position of the current to-be-deployed module on the bare chip and the aspect ratio of the current to-be-deployed module; and determining a layout planning result based on the deployment action of each to-be-deployed module output by the policy network model, the layout planning result indicating the deployment position of each to-be-deployed module on the bare chip and the aspect ratio of each to-be-deployed module. According to the layout planning method of the integrated circuit provided by the embodiment of the invention, complex constraint conditions can be processed, and the quality of layout planning is improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a layout planning method and apparatus for integrated circuits. Background Technology

[0002] Floorplanning, as an early step in integrated circuit physical design, significantly impacts the power, performance, and area (PPA) of integrated circuits. When the wafer size is fixed, floorplanning with higher area utilization and shorter trace lengths results in a more compact chip, capable of housing more circuit blocks and achieving better PPA. Floorplanning refers to the rational arrangement of modules with given interconnections within a given chip area, minimizing the bus length between modules. With the development of integrated circuit technology and increasing demands for chip performance, the number of modules that floorplanning needs to consider has grown rapidly, and the constraints have become more complex, such as module alignment, module-to-module adjacency, and module-to-port adjacency constraints.

[0003] However, most existing layout planning schemes cannot handle complex constraints, resulting in poor layout planning performance. Summary of the Invention

[0004] Embodiments of this application provide a layout planning method for integrated circuits, which can handle complex constraints and improve the quality of layout planning.

[0005] In a first aspect, this application provides a layout planning method for integrated circuits, including acquiring current state information, which includes image information, graph information, and sequence information. The image information includes the current layout image information and the masking image information. The current layout image information indicates the module distribution on several bare chips (dies), the masking image information indicates the constraints on the deployment action space of the current module to be deployed, the graph information indicates the connection relationship between multiple modules to be deployed, and the sequence information indicates the deployment order of multiple modules to be deployed. The image information, graph information, and sequence information are used as input to a policy network model to output the deployment action of the current module to be deployed. The deployment action indicates the deployment position of the current module to be deployed on the die and the aspect ratio of the current module to be deployed. Based on the deployment actions of each module to be deployed output by the policy network model, the layout planning result is determined. The layout planning result indicates the deployment position of each module to be deployed on the die and the aspect ratio of each module to be deployed.

[0006] This application represents constraints as masked images and uses these images as input to a policy network model. This allows the policy network model to consider the constraints on the output deployment actions during inference, establishing a mapping relationship between the current state with constraints and the module deployment actions. This enables the handling of complex constraints during layout planning, improving the quality of layout planning. For example, layout planning can achieve higher area utilization and shorter line lengths, making the chip more compact, capable of supporting more circuit modules, and having better PPA.

[0007] In one possible implementation, several dies include multiple dies, and the deployment action also indicates the die layer to be deployed, i.e., which die layer's module should be placed at the current time. The policy network model includes an encoder, a layer decision network, an aspect ratio decision network, and a position decision network. A specific implementation that takes image information, graph information, and sequence information as input to the policy network model and outputs the deployment action of the module to be deployed is as follows: taking image information and sequence information as input to the layer decision network, outputting the probability distribution of the die layer to which the module to be deployed is currently deployed; taking image information as input to the aspect ratio decision network, outputting the aspect ratio probability distribution of the module to be deployed is currently output; taking image information and graph information as input to the encoder, outputting the target encoding vector is currently output; taking the target encoding vector as input to the position decision network, outputting the deployment position probability distribution of the module to be deployed is currently output; and determining the deployment action of the module to be deployed based on the probability distribution of the die layer to which the module to be deployed is currently deployed, the aspect ratio probability distribution of the module to be deployed is currently output, and the deployment position probability distribution of the module to be deployed is currently output.

[0008] The integrated circuit layout planning method provided in this application is applicable to the layout planning of multi-layer dies, that is, it can be used for the layout planning of 3D chips. The deployment actions output by the policy network model include three parts: module location, module aspect ratio, and module layer (i.e., which layer of the die the module is deployed on). These three different action spaces together form a hybrid action space, which can directly select and control the module location, aspect ratio, and layer, enhancing flexibility. At the same time, the policy network model sets up corresponding decision networks for each action. For example, a layer decision network is set for predicting module layer actions, an aspect ratio decision network is set for predicting aspect ratio actions, and a location decision network is set for predicting location actions, thereby improving the accuracy of deployment action prediction.

[0009] In another possible implementation, the encoder includes an image sub-encoder and a graph sub-encoder; a specific implementation of using image information and graph information as input to the encoder and outputting a coded vector is as follows: using image information as input to the image sub-encoder and outputting a first coded vector; using graph information as input to the graph sub-encoder and outputting a second coded vector; and fusing the first encoder vector and the second coded vector to obtain the target coded vector.

[0010] By setting sub-encoders within the encoder to handle different modal inputs, feature encoding of inputs of different modalities can be achieved. For example, an image sub-encoder can be set within the encoder to handle image modal inputs, and an image sub-encoder can be set to handle image inputs.

[0011] Optionally, the image sub-encoder includes a convolutional neural network (CNN), the graph sub-encoder includes an attention-based graph neural network, the layer decision network includes a convolutional neural network and a transformer neural network, the aspect ratio decision network includes a convolutional neural network, and the position decision network includes a multilayer perceptron (MLP) network.

[0012] In another possible implementation, before determining the deployment action of the module to be deployed, based on the probability distribution of the bare chip layer to be deployed, the probability distribution of the aspect ratio of the module to be deployed, and the probability distribution of the deployment location of the module to be deployed, the following steps are taken: based on the image information of the mask, the probability distribution of the deployment location of the module to be deployed is corrected.

[0013] For example, the masking image can be a location masking image, indicating the constraints on the deployable locations of the module to be deployed on the die. For instance, the location masking image could represent all deployable locations of the module on the die using a green mask. The deployment location probability distribution output by the location decision network is corrected using the location masking image. For example, the probability of unmasked locations on the die in the deployment location probability distribution output by the location decision network is set to 0. This achieves explicit constraints on location actions, filters the location probability distribution output by the location decision network, and further improves the accuracy of the location decision network output.

[0014] In another possible implementation, the masking image information includes one or more of the following: a position masking image, an alignment masking image, a line length masking image, a module and module adjacency masking image, and a module and port adjacency masking image; wherein, the position masking image indicates the constraints on the deployable location of the currently deployed module on the die; the alignment masking image indicates the constraints on the alignment of the currently deployed module with its alignment peer module; the line length masking image indicates the constraints on the increased line length after the currently deployed module is deployed on the die; the module and module adjacency image indicates the constraints on the length of the common edge between the currently deployed module and its adjacent modules; and the module and port adjacency masking image indicates the constraints on the adjacency of the currently deployed module with its ports.

[0015] By using masked images that represent various constraint information, we can process a variety of complex constraints and ensure the quality of layout planning.

[0016] In another possible implementation, the image information is determined based on the current layout planning image, the graph information is determined based on the netlist circuit diagram, the sequence information is determined based on the sorting information and several attribute information of each module to be deployed, and the sorting information is determined based on the sorting of multiple modules to be deployed according to the target attribute information.

[0017] In another possible implementation, the policy network model is trained based on a reinforcement learning training architecture. Reinforcement learning training does not require a labeled training dataset, saving expensive labeling costs.

[0018] In another possible implementation, the reinforcement learning training architecture includes a policy network model to be trained and an evaluation model. The evaluation model is used to evaluate the reward of the deployment action output by the policy network model and adjust the weight parameters of the policy network model based on the reward. The evaluation model is trained on a training dataset, which includes multiple labeled training samples. The training samples are deployment actions, and the labels of the deployment actions are determined based on local advantage and global baseline. Local advantage indicates the reward value of the deployment action in the intermediate step, and global baseline indicates the reward value of the deployment action in the last step.

[0019] This application designs a new reward function that introduces local advantages to accelerate learning convergence and avoid the problem of sparse rewards. At the same time, it introduces a global reward (i.e., a global baseline) to stabilize training and avoid the degradation of asynchronous layer decision-making mechanisms and local optima.

[0020] In another possible implementation, local advantage is determined based on the difference between the optimization metric after the deployment action of the intermediate step and the optimization metric after the deployment action of the previous step, and the global baseline is used to correct the local advantage.

[0021] In another possible implementation, the evaluation model and the policy network model share the same encoder, increasing training efficiency.

[0022] Secondly, this application also provides an integrated circuit layout planning device, including an acquisition module, an inference module, and a planning module. The acquisition module acquires current state information, which includes image information, graph information, and sequence information. The image information includes image information of the current layout and image information of the mask. The image information of the current layout indicates the distribution of modules on several dies, the image information of the mask indicates constraints on the deployment action space of the modules to be deployed, the graph information indicates the connection relationship between multiple modules to be deployed, and the sequence information indicates the deployment order of the multiple modules to be deployed. The inference module takes the image information, graph information, and sequence information as input to a policy network model and outputs the deployment action of the modules to be deployed. The deployment action indicates the deployment position of the modules to be deployed on the die and the aspect ratio of the modules to be deployed. The planning module determines the layout planning result based on the deployment actions of each module to be deployed output by the policy network model. The layout planning result indicates the deployment position of each module to be deployed on the die and the aspect ratio of each module to be deployed.

[0023] In one possible implementation, several dies include multiple dies, and the deployment action also indicates the die layer to be deployed, i.e., which die layer to which the module should be placed. The policy network model includes an encoder, a layer decision network, an aspect ratio decision network, and a location decision network. The inference module is specifically used to: take image information and sequence information as input to the layer decision network and output the probability distribution of the die layer to which the module to be deployed should be; take image information as input to the aspect ratio decision network and output the aspect ratio probability distribution of the module to be deployed; take image information and graph information as input to the encoder and output the target encoding vector; take the target encoding vector as input to the location decision network and output the deployment location probability distribution of the module to be deployed; and determine the deployment action of the module to be deployed based on the probability distribution of the die layer to which the module to be deployed should be, the aspect ratio probability distribution of the module to be deployed, and the deployment location probability distribution of the module to be deployed.

[0024] In another possible implementation, the encoder includes an image sub-encoder and a graph sub-encoder; a specific implementation of using image information and graph information as input to the encoder and outputting a coded vector is as follows: using image information as input to the image sub-encoder and outputting a first coded vector; using graph information as input to the graph sub-encoder and outputting a second coded vector; and fusing the first encoder vector and the second coded vector to obtain the target coded vector.

[0025] Optionally, the image sub-encoder includes a convolutional neural network, the graph sub-encoder includes an attention-based graph neural network, the layer decision network includes a convolutional neural network and a transformer neural network, the aspect ratio decision network includes a convolutional neural network, and the position decision network includes a multilayer perceptron network.

[0026] In another possible implementation, the integrated circuit layout planning apparatus provided in this application further includes a correction module for correcting the probability distribution of the deployment location of the module to be deployed based on the image information of the mask.

[0027] In another possible implementation, the masking image information includes one or more of the following: a position masking image, an alignment masking image, a line length masking image, a module and module adjacency masking image, and a module and port adjacency masking image; wherein, the position masking image indicates the constraints on the deployable location of the currently deployed module on the die; the alignment masking image indicates the constraints on the alignment of the currently deployed module with its alignment peer module; the line length masking image indicates the constraints on the increased line length after the currently deployed module is deployed on the die; the module and module adjacency image indicates the constraints on the length of the common edge between the currently deployed module and its adjacent modules; and the module and port adjacency masking image indicates the constraints on the adjacency of the currently deployed module with its ports.

[0028] In another possible implementation, the image information is determined based on the current layout planning image, the graph information is determined based on the netlist circuit diagram, the sequence information is determined based on the sorting information and several attribute information of each module to be deployed, and the sorting information is determined based on the sorting of multiple modules to be deployed according to the target attribute information.

[0029] In another possible implementation, the policy network model is trained based on a reinforcement learning training architecture. Reinforcement learning training does not require a labeled training dataset, saving expensive labeling costs.

[0030] In another possible implementation, the reinforcement learning training architecture includes a policy network model to be trained and an evaluation model; the evaluation model is used to evaluate the reward of the deployment action output by the policy network model and adjust the weight parameters of the policy network model based on the reward; the evaluation model is trained on a training dataset, which includes multiple labeled training samples, which are deployment actions. The labels of the deployment actions are determined based on local advantage and global baseline. Local advantage indicates the reward value of the deployment action in the intermediate step, and global baseline indicates the reward value of the deployment action in the last step.

[0031] In another possible implementation, local advantage is determined based on the difference between the optimization metric after the deployment action of the intermediate step and the optimization metric after the deployment action of the previous step, and the global baseline is used to correct the local advantage.

[0032] In another possible implementation, the evaluation model and the policy network model share the same encoder, increasing training efficiency.

[0033] Thirdly, embodiments of this application provide a computing device, including a memory and a processor, wherein the memory stores instructions that, when executed by the processor, cause the method described in the first aspect or any possible implementation of the first aspect to be implemented.

[0034] Fourthly, embodiments of this application provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, causes the method described in the first aspect or any possible implementation thereof to be implemented.

[0035] Fifthly, embodiments of this application also provide a computer program or computer program product, which includes instructions that, when executed, cause a computer to perform the method described in the first aspect or any possible implementation thereof.

[0036] In a sixth aspect, embodiments of this application also provide a chip including at least one processor and a communication interface, the processor being configured to perform the method described in the first aspect or any possible implementation thereof. Attached Figure Description

[0037] Figure 1 A flowchart illustrating the chip design and manufacturing process is shown.

[0038] Figure 2 A schematic diagram of a system architecture is shown;

[0039] Figure 3 A schematic flowchart illustrating an integrated circuit layout planning method provided in an embodiment of this application;

[0040] Figure 4 This illustrates a schematic diagram of image information;

[0041] Figure 5 This diagram illustrates the process by which a policy network model processes input state data.

[0042] Figure 6 A schematic diagram of a reinforcement learning training architecture for a policy network model is shown.

[0043] Figure 7 This diagram illustrates the processing of input state data by another strategy network model.

[0044] Figure 8 A schematic diagram of the reinforcement learning training architecture for another policy network model is shown.

[0045] Figure 9 A schematic diagram of cross-layer module alignment after applying the layout planning method of the integrated circuit of this application to the public dataset circuit n50 and the public dataset circuit n100 respectively is shown.

[0046] Figure 10 A schematic diagram of the layout planning result after applying the layout planning method of this application to the integrated circuit n50 of the public dataset and having 6 preset modules is shown.

[0047] Figure 11 A schematic diagram of the layout planning result after applying the layout planning method of this application to the integrated circuit n100 of the public dataset circuit with 12 preset modules is shown.

[0048] Figure 12 The diagram illustrates the placement of SRAM0 under complex constraints: 1) optimization of the common edge between SRAM0 and SRAM1, 2) optimization of the common edge between logic0-4, 3) optimization of the alignment area between SRAM0-1 and logic0-4, 4) optimization of the alignment area between other0 and other1, and 5) SRAM0 adjacent to the two ports above it.

[0049] Figure 13 This diagram illustrates that the layout planning result generated by the layout planning method of the integrated circuit provided in this application conforms to the design constraints, as verified by HiSilicon's yellow zone verification.

[0050] Figure 14 A schematic diagram of the structure of an integrated circuit layout planning device provided in an embodiment of this application;

[0051] Figure 15 A schematic diagram of the structure of a computing device provided in an embodiment of this application. Detailed Implementation

[0052] The term "and / or" used in this article describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. The symbol " / " in this article indicates that the related objects are in an "or" relationship; for example, A / B means A or B.

[0053] The terms "first" and "second," etc., used in the specification and claims herein are used to distinguish different objects, not to describe a specific order of objects. It should be understood that such terms are interchangeable where appropriate; this is merely a way of distinguishing objects with the same properties in the description of embodiments of this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, so that a process, method, system, product, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such processes, methods, systems, products, or apparatus.

[0054] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0055] In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more, for example, multiple processing units means two or more processing units, multiple elements means two or more elements, etc.

[0056] Relevant layout planning techniques can be broadly categorized into three types: 1) heuristic algorithms, 2) analytical algorithms, and 3) deep learning algorithms. Heuristic algorithms utilize heuristic representations combined with search to perturb the current layout result and seek the optimal solution; analytical algorithms calculate the gradient of the objective function with respect to the module positions and update the layout result using gradient descent; deep learning algorithms largely rely on heuristic representations and use neural networks to decide whether to accept the current perturbation result.

[0057] For example, one related technique is the heuristic-based method. This type of method typically selects specific heuristic representations to model the layout, such as CBL, B*Tree, and SP, and uses simulated annealing to perturb the existing representation. Whether to accept the perturbation is determined based on the change in the objective function. Finally, a decoding algorithm converts it into a layout result, i.e., the coordinates of each module.

[0058] This approach cannot handle complex constraints, such as module alignment, module-to-module adjacency, and module-to-port adjacency.

[0059] The second related technology is gradient-based analytical algorithms. These methods calculate the gradient of the objective function with respect to the module coordinates and shape, and then use this gradient for gradient descent to update the current result.

[0060] This approach requires calling a legalization algorithm to eliminate overlap between modules. It struggles to handle complex constraints, and gradient descent fails when the objective function is non-differentiable.

[0061] The third related technology is deep learning-based algorithms. This combines heuristic representations with reinforcement learning. Instead of relying on changes in the objective function to decide whether to accept a perturbation in heuristic algorithms, it uses a neural network to make the decision, while the rest remains largely unchanged.

[0062] This approach also faces the same problems encountered by heuristic algorithms, namely, a lack of flexibility and an inability to handle complex constraints, such as module alignment, module-module adjacency, and module-port adjacency.

[0063] To address the aforementioned issues, this application provides a layout planning method for integrated circuits. This method does not rely on traditional heuristic search and representation; instead, it directly establishes a mapping relationship between the current state and deployment actions through a policy network model. It directly infers the deployment location and aspect ratio of the output module, and simultaneously uses constraints as input to the model. This allows the model to consider constraints during inference, enabling the handling of complex constraints and ensuring the quality of the final layout planning result.

[0064] To facilitate understanding of the solutions in the embodiments of this application, the technical terms involved in this document will be explained first.

[0065] An integrated circuit (IC) is a miniature electronic device or component. It is made by using certain processes to integrate the transistors, resistors, capacitors, inductors, and other components required for a circuit, as well as the interconnection of wiring, onto one or several small pieces of semiconductor wafers or dielectric substrates. These are then packaged in a casing, forming a miniature structure with the required circuit function. In other words, an IC is an integrated circuit consisting of a large number of microelectronic components (such as transistors, resistors, and capacitors) placed on a plastic substrate to form a chip.

[0066] Integrated circuit layout planning, also known as chip layout planning, is a crucial step in the physical design phase, and high-quality layout planning is a prerequisite for successful chip design. The purpose of layout planning is to determine the placement of modules on the die and the shape of the modules (e.g., aspect ratio).

[0067] A module refers to an object arranged in a chip layout plan. A chip can include multiple modules, which can be connected by wires to realize the chip's designed functions. A module can be understood as a chip logic unit, with each module having individual functional attributes. For example, a module can be various types of random access memory (RAM), read-only memory (ROM), and logic units. A module can also be understood as a collection of circuit components that can implement specific functions.

[0068] Various types of random access memory units can be, for example, dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), and double data rate synchronous dynamic random access memory (DDR SDRAM).

[0069] Aspect ratio (AR) is the ratio of a module's width to its height. The aspect ratio and area determine the module's shape. Based on whether the aspect ratio can be adjusted, modules can be divided into rigid modules and flexible modules. Rigid modules have a fixed shape (i.e., fixed aspect ratio and area), while flexible modules have a fixed area but a variable aspect ratio. Adjusting the aspect ratio of a flexible module changes its shape, increasing the flexibility of module placement, achieving uniform module distribution, and thus achieving chip temperature uniformity.

[0070] Interconnects refer to transmission lines that connect two modules. Based on their design layer, interconnects can be categorized as follows: interconnects on printed circuit boards (PCBs), cables connecting PCBs, internal interconnects within chips, and interconnects between pins and the chip during chip packaging. It should be noted that the interconnects mentioned in the embodiments of this application refer to internal chip interconnects, which can also be simply called interconnect lines.

[0071] The following detailed description, with reference to the accompanying drawings, details the specific implementation of the integrated circuit layout planning method and apparatus provided in the embodiments of this application.

[0072] Figure 1 A flowchart illustrating the chip design and manufacturing process is shown. (For example...) Figure 1As shown, the chip design and manufacturing process begins with specification definition. In the specification definition stage 110, the functional and performance requirements of the integrated circuit are determined. In the chip design stage 120, electronic design automation (EDA) software is used to design the circuit to obtain, for example, layout files for chip manufacturing. Depending on the circuit (e.g., digital or analog circuit), design 120 may include different design stages. In the manufacturing stage 130, integrated circuits are formed on the wafer using processes such as photolithography, etching, ion implantation, thin film deposition, and polishing. In the packaging stage 140, the wafer is diced to obtain bare dies, which are then packaged into chips using processes such as bonding, soldering, and molding. The resulting chips are tested in the testing stage 150 to ensure that the performance of the finished chip meets the requirements defined in specification definition 110. Chips that pass testing 160 can be delivered to the customer.

[0073] It is understood that the above process is merely illustrative and not intended to limit the scope of the embodiments of this application. In some cases, the chip design and manufacturing process may differ. For example, tape-out may be performed before manufacturing chip 130. A small number of chips obtained from tape-out can be used for testing to verify whether the chip design meets expectations. If it does not meet expectations, this indicates tape-out failure, and it may be necessary to adjust the chip design or redesign the chip.

[0074] In some embodiments, the design 120 of a digital circuit may exemplary include architecture design 121, register transfer level (RTL) design 122, functional simulation 123, synthesis 124, timing analysis 125, design for test (DFT) 126, verification and checking 127, place and route 128, design rule check (DRC) 129, and a generated version. Figure 12 .

[0075] Architecture design 121 includes, for example, designing the architecture of a chip. For instance, EDA software can be used to determine the types and number of components or sub-circuits included in a chip system, as well as the function, connections, and interactions of each component or sub-circuit.

[0076] During the RTL design phase 122, the defined chip architecture can be described in code at the RTL level using hardware programming languages ​​such as Verilog or VHDL.

[0077] Functional simulation, also known as RTL-level behavioral simulation or front-end simulation, aims to analyze the correctness of the logic relationships in a designed circuit.

[0078] Synthesis 124 can convert RTL into a gate-level netlist. Synthesis 124 may include, for example, translation, optimization, and mapping. In one embodiment, the EDA software used for synthesis can first convert the RTL code into a general Boolean equation and then compile it. The netlist can be optimized according to constraints such as delay and area imposed by the designer, and then the RTL netlist can be mapped to a technology library to generate a gate-level netlist.

[0079] Timing analysis (125) is typically static timing analysis, which mainly involves timing calculations and predictions for digital circuits. By performing timing analysis on paths within a digital circuit, it determines whether timing convergence has been achieved, thereby ensuring that the timing of various circuits meets various timing requirements. This verification of digital circuits is usually performed statically and does not require digital logic simulation.

[0080] During the DFT 126 stage, various hardware logics can be embedded in the design to improve chip testability (including controllability and observability). Using this logic, test vectors can be generated to achieve the testing of large-scale digital circuits. DFT may include, for example, scan chain-based testing methods or built-in self-test (BIST) circuitry.

[0081] During the verification and checking phase 127, formal verification and / or equivalence checks can be performed on the circuit. Formal verification can prove the correctness or incorrectness of a circuit using mathematical methods based on one or more formal specifications or properties. Formal verification can include, for example, abstract interpretation, formal model checking (also known as feature checking), and theorem proving. Equivalence checks can be used to verify the consistency between the register-transfer level design and the gate-level netlist, and between different gate-level netlists.

[0082] In the placement and routing stage 128, the chip circuitry can be placed and routed. Placement can be based on considerations such as area, critical path delay length, and power consumption, rationally arranging the gate-level netlist generated by logic synthesis 124 within a rectangular area corresponding to the chip. After this, the placed components or sub-circuits can be routed to connect them. Routing typically aims for short total traces, timing-compliant trace delays, and compliance with process routing rules (such as routing density). Although placement and routing are described separately herein, this is merely illustrative and not intended to limit the scope of this disclosure. In some cases, placement and routing can be performed simultaneously or alternately to optimize the placement and routing process.

[0083] During the DRC 129 stage, the layout can be checked for violations of design rules that could cause potential open circuits, short circuits, or adverse effects. After passing DRC, EDA software can generate a file representing the layout, such as a GDSII file.

[0084] It is understood that the above steps are merely illustrative and not intended to limit the scope of this disclosure. In actual design processes, these steps can be added, deleted, or modified according to design needs. Furthermore, some of the above steps can be implemented using different EDA software or integrated into one or more EDA software programs. This application's embodiments do not impose any limitations in this regard.

[0085] The integrated circuit layout planning scheme provided in this application embodiment can be applied to the physical synthesis stage of the synthesis process. It can handle complex constraints, improve the quality of layout planning, and thereby achieve the desired performance, power consumption, and area of ​​the circuit.

[0086] It is understood that although the operations are described in a specific order above, this should be understood as not being limited to requiring such operations to be performed in the specific order shown or in sequential order, or requiring all illustrated operations to be performed to achieve the desired result. In certain environments, multitasking and parallel processing may be advantageous. Similarly, although several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of the embodiments of this application. Certain features described in the context of individual embodiments may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented individually or in any suitable sub-combination in multiple implementations.

[0087] The integrated circuit layout planning method and apparatus provided in this application can be applied in EDA software, wherein the EDA can run on a terminal device or a cloud-side server.

[0088] For example, EDA can use the integrated circuit layout planning method provided in the embodiments of this application to process the task of integrated circuit layout planning. EDA can obtain the information required for layout planning, such as layout planning images, netlists, module placement sequences, etc. EDA can perform inference calculations based on the above information to obtain the chip layout planning results (such as module placement positions and aspect ratios), and display the layout planning results to the user. For example, the layout planning results can be displayed on the EDA interface of the terminal device.

[0089] Figure 2 A schematic diagram of a system architecture is shown. The system includes a terminal 210, a server 230, and a network 220 that communicatively connects the terminal 210 and the server 230. The server 230 may include one or more servers (…). Figure 1 (Using only one server as an example for illustration), server 220 can provide integrated circuit layout planning services for one or more terminals 210.

[0090] In some embodiments, server 130 may also provide other services or software applications, including both non-virtual and virtual environments. In some embodiments, these services may be provided as web-based services or cloud services, such as to end users under a Software as a Service (SaaS) model.

[0091] exist Figure 2 In the system shown, server 230 may include one or more components that implement the functions performed by server 230. These components may include software components, hardware components, or combinations thereof that can be executed by one or more processors. A user of operating terminal 210 can sequentially interact with server 230 and utilize the services provided by these components using one or more client applications. It should be understood that... Figure 2 This is merely one example of a system for implementing the various methods described in the embodiments of this application; other different configurations are possible, and the embodiments of this application do not limit this.

[0092] Terminal 210 may have an application related to integrated circuit layout planning installed, or a webpage related to integrated circuit layout planning opened. The application and webpage can provide an integrated circuit layout planning interface. Terminal 210 can receive the information required for the layout planning of the chip to be laid out (such as layout planning image, netlist, module placement sequence) input by the user on the integrated circuit layout planning interface, and send the above information to server 230. Server 230 can obtain the chip layout planning result based on the received layout planning information, such as the placement position and shape of the modules, and return the layout planning result to terminal 210 for display to the user.

[0093] Terminal 210 may include various types of computer devices, such as portable handheld devices, general-purpose computers (e.g., personal computers or laptop computers), workstation computers, wearable devices, etc. These computer devices may run various types and versions of software applications and operating systems, such as Microsoft Windows, Apple iOS, UNIX-like operating systems, Linux or Linux-like operating systems (e.g., Google Chrome OS); or various mobile operating systems, such as Microsoft Windows Mobile OS, Windows Phone, Android, iPhone OS, etc. Portable handheld devices may include cellular phones, smartphones, tablets, personal digital assistants (PDAs), etc. Wearable devices may include head-mounted displays and smartwatches, etc.

[0094] Network 220 can be any type of network well known to those skilled in the art, and can use any of a variety of available protocols, including but not limited to TCP / IP, SNA, IPX, 3G, 4G, 5G, etc., to support data communication. For example, one or more networks 120 can be a local area network (LAN), an Ethernet-based network, a token ring network, a wide area network (WAN), the Internet, a virtual network, a virtual private network (VPN), an intranet, an extranet, the public switched telephone network (PSTN), an infrared network, a wireless network (e.g., Bluetooth, Wi-Fi), and / or any combination of these and / or other networks.

[0095] Server 230 may include one or more general-purpose computers, special-purpose server computers (e.g., personal computer servers, UNIX servers, terminal servers), blade servers, mainframe computers, server clusters, or any other suitable arrangement or combination. Server 230 may include one or more virtual machines running a virtual operating system, or other computing architectures involving virtualization, such as one or more flexible pools of logical storage devices that can be virtualized to maintain virtual storage devices for the server. In various embodiments, server 130 may run one or more services or software applications that provide the functionality described below.

[0096] In some implementations, server 230 can be a server for a distributed system or a server integrated with blockchain. Server 230 can also be a cloud server, or an intelligent cloud computing server or intelligent cloud host with artificial intelligence technology. A cloud server is a host product in the cloud computing service system, designed to address the shortcomings of traditional physical hosts and virtual private servers (VPS) services, such as high management difficulty and weak business scalability.

[0097] It should be noted that in some other examples, the terminal 210 can also complete the inference of the chip layout planning result based on the information required for layout planning, without the need for the server to cooperate. This application does not make specific limitations on this.

[0098] Figure 3 This is a flowchart illustrating an integrated circuit layout planning method provided in an embodiment of this application. This method can be executed by any computing-capable device, equipment, platform, or cluster of devices. This application does not specifically limit the specific computing device executing this method; a suitable computing device can be selected as needed. For example, it can be implemented on a terminal device, a server, or a cloud device (e.g., a cloud server) to provide integrated circuit layout planning services to users via cloud services. For ease of description, the form of the executing entity will not be distinguished in the following text; all instances will be described as layout planning devices. Figure 3 As shown, the integrated circuit layout planning method provided in this application embodiment includes at least steps S301 to S303.

[0099] In step S301, the current status information is obtained, which includes image information, graph information, and sequence information.

[0100] Image information includes the current canvas image information and the mask image information. The current canvas image information indicates the distribution of modules on several dies at the moment. The mask image information indicates the constraints on the deployment action space of the current module to be deployed. The graph information indicates the connection relationship between multiple modules to be deployed. The sequence information indicates the order in which multiple modules to be deployed are deployed.

[0101] The current layout image information describes the current chip layout, such as the positions occupied by modules on the die. It's important to clarify that "modules on the die" here doesn't refer to actual modules being placed on the die, but rather a simulation of module placement on the die during the design phase. Initially, the canvas image information may be blank or a pre-defined distribution image of modules on the die. As the layout algorithm executes, new modules are continuously placed on the die, and the canvas image information is updated accordingly.

[0102] Figure 4 A schematic diagram of image information is shown. For example... Figure 4 As shown in (a), the canvas image shows that there are currently two modules placed on the die, and the position of the modules on the die can also be seen from the image.

[0103] The masking image information can include one or more masking images used to constrain the deployment action space of the currently deployed module (hereinafter referred to as the current module). For example, the masking image information can include one or more of the following: position mask image, alignment mask image, wire mask image, block-to-block adjacent mask image, and module-port adjacent mask image. The position mask image indicates the constraints on the deployable positions of the current module on the die, ensuring that the module placement does not lead to module overlap or exceeding boundaries (i.e., the module placement position exceeds the die boundary). For example, the position mask image could represent all deployable positions of the current module on the die using a yellow mask. That is, the positions on the die covered in yellow in the position mask image are the positions where the current module can be placed, and the areas not covered in yellow are the areas where the current module cannot be placed. Figure 4 As shown in (e), the yellow masked area represents the area on the die where the current module can be placed, while the non-yellow masked area represents the area where the current module cannot be placed.

[0104] The alignment mask image indicates the alignment constraints between the current module and its alignment partner module; it characterizes the alignment score between the current module and its alignment partner module after the current module is placed at a certain position on the die. For example, if the current module is module A, and its alignment partner module is module A', when module A is placed at position 'a' on the die, the alignment score between module A and module A' is displayed on the die. Figure 4 Images (b), (c), and (d) show the alignment mask on the x-axis, the alignment mask on the y-axis, and the alignment mask, respectively. Figure 4 The yellow masked area shown in (d) is the area with the highest alignment score, indicating that module A' is placed in the area covered by the yellow mask, and module A and module A' have the highest alignment score.

[0105] If the alignment involves one or more modules, the maximum value of each mask is taken element-wise, which corresponds to the union of the action space. For example, if the current module is module A, then the alignment companion modules of module A are module A' and module A''. The alignment score between module A and module A' is 80, and the alignment score between module A and module A'' is 90. Therefore, the alignment score between module A and its alignment companion modules is 90.

[0106] The line length mask image indicates the added line length constraint after the current module is deployed on the die; in other words, the line length mask image represents the increment of the aligned line length if the current module is placed at a certain position on the die. Optionally, the line length can be measured using half-perimeter line length.

[0107] The module and its adjacent mask image indicate the constraint of the length of the common edge between the current module and its adjacent modules; for example, it represents the length of the common edge between the current module and its corresponding module after the current module is placed at a certain position in the die. If there is a requirement for a common edge between the current module and multiple modules, the mask is calculated sequentially, and the maximum / minimum value is taken for each element, which corresponds to taking the union / intersection of the action space, respectively.

[0108] The module and port adjacency masking image indicates the constraints between the currently deployed module and the port.

[0109] The masking image information can be automatically generated using tools, such as tools that can automatically generate the current canvas image and the masking image.

[0110] It is understood that the above masking images are merely illustrative examples and do not constitute a limitation on the embodiments of this application. The embodiments of this application may use more or fewer masking images to constrain the action space, such as using only position masking images, or using more masking images to process more complex constraints, such as constraints on the proximity of modules and ports, constraints on the proximity of modules, etc.

[0111] Graph information indicates the connections between multiple modules that need to be deployed on the die. For example, graph information includes multiple nodes and connecting edges that connect different nodes. Different nodes represent different modules, and connecting edges indicate that there are connections between modules, that is, two modules need to be interconnected.

[0112] The layout information can be obtained through a netlist. For example, a layout planning device can read a design file, which includes a netlist. This design file can be created by a front-end engineer or through automated tools, and it may contain relevant information needed by the user for chip physical design. In practice, the design file can be imported into the layout planning device by a back-end engineer, and the layout planning device can parse the design file to obtain the relevant information needed for layout planning, such as the netlist. Alternatively, the layout planning device can obtain the design file from a device storing the design file (which could also be OBS in the cloud) via a network or physical connection, and then parse the design file to obtain the netlist. This application embodiment does not specifically limit the specific method of obtaining the design file.

[0113] The netlist describes the circuit structure of the chip, that is, the circuit connection relationship between multiple modules. Graph information can be obtained through the netlist, that is, an undirected graph is constructed with modules as nodes and interconnections as edges, which is used as graph information for modeling.

[0114] Sequence information indicates the deployment order of multiple modules. For 2D chip layout planning, i.e., single-layer die layout planning, the sequence information only includes one placement sequence. For 3D chip layout planning, i.e., layout planning with multiple dies, the sequence information includes multiple placement sequences, with one placement sequence for each die. For example, the modules contained in each die layer are sorted according to specific rules to form a sequence, such as sorting them in descending order by area, resulting in the sequence for each die layer.

[0115] For example, the 3D chip includes die 1, die 2, and die 3. Die 1 contains modules 11, 12, 13, 14, 15, and 16. The modules in die 1 are sorted in descending order of area to obtain the placement sequence: module 14, 11, 13, 12, 16, and 15. Die 2 contains modules 21, 22, 23, 24, 25, and 26. The modules in die 2 are sorted in descending order of area to obtain the placement sequence: module 26, 21, 24, 25, 22, and 23. die3 contains modules 31, 32, 33, 34, 35, and 36. The modules in die3 are sorted in descending order of area to obtain the placement sequence: module 33, 31, 32, 36, 35, and 34.

[0116] In another example, the sequence information also indicates the attribute information of each module in the multiple modules of each die layer. After obtaining the placement sequence of the multiple modules to which each die layer belongs, the sequence information is generated based on several attribute information of each module. For example, the several attribute information can be attribute information such as the module's position (i.e., the position of the module on the die), shape, and area. For example, the arrangement sequence of multiple modules in die 1 is module 14, module 11, module 13, module 12, module 16, and module 15. The position, shape, and area attribute values ​​of module 14 are (m1, n1, k1), those of module 11 are (m2, n2, k2), those of module 13 are (m3, n3, k3), those of module 12 are (m4, n4, k4), those of module 16 are (m5, n5, k5), and those of module 15 are (m6, n6, k6). Then the sequence information of die 1 (also known as the arrangement sequence) is (m1, n1, k1), (m2, n2, k2), (m3, n3, k3), (m4, n4, k4), (m5, n5, k5), and (m6, n6, k6).

[0117] Some module attribute information can be obtained from the design file, such as the module's area. Other module attribute information can be obtained from the layout planning results, such as the module's position and shape. That is, initially, the position and shape attributes of most modules are unknown, and their values ​​can be set to 0. As the layout planning algorithm executes, the module's position and shape attributes are obtained, and the position and shape attributes of the modules in the update sequence information are then updated.

[0118] This application embodiment uses data from three modalities—image, graph, and sequence—to characterize the state of layout planning. This can also be described as using multimodal data to perform multimodal characterization modeling of two-dimensional / three-dimensional layout planning, giving it good cross-chip transfer and generalization capabilities.

[0119] In step S302, image information, graph information, and sequence information are used as inputs to the policy network model, and the deployment action of the module to be deployed is output.

[0120] After obtaining image information, graph information, and sequence information, the layout planning device inputs these information into the policy network model. The policy network module then infers and outputs the deployment action for the current module. For layout planning of a single-layer 2D chip, the deployment action includes position and aspect ratio. Position refers to the placement of the current module on the die, and aspect ratio refers to the module's width and height. For layout planning of multi-layer dies, the deployment action includes position, layer, and aspect ratio. Layer refers to the die layer on which the current module is deployed, or in other words, the layer on which the module is deployed.

[0121] It should be understood that the placement of a module on the die can be either the coordinates of the module's geometric center on the die, or the coordinates of the module's lower left corner on the die.

[0122] Layout planning for 3D chips. Figure 5 This diagram illustrates the processing of input state data by a policy network model. Figure 5 As shown, the policy network model takes as input multi-modal state data composed of images, graphs, and sequences. The policy network model includes a layer decider network, an aspect ratio (AR) decider network, and a position decider network. Sequence information and image information serve as input to the layer decider network, outputting a layer probability distribution (layerprob); image information serves as input to the aspect ratio decider network, outputting an aspect ratio probability distribution; and image information and graph information serve as input to the position decider network, outputting a position probability distribution (posprob). Therefore, the output actions of this application include three aspects: module placement position, module aspect ratio, and module placement layer. These three actions constitute a hybrid action space, which can directly output module position, aspect ratio, and layer, enhancing flexibility. The module position space in the hybrid action space is a discrete space used to determine the position of each module. The module aspect ratio space is a continuous space controlled by a Gaussian distribution, determining the aspect ratio of the module. The module layer space is a discrete space used to determine which layer of die's placement sequence the next module should be taken from.

[0123] The layer decision network includes a sequence processing sub-network for processing sequence information and an image sub-network for processing image information. Optionally, the sequence processing sub-network can be a transformer network. Taking a 2-layer die as an example, the two placement sequences undergo self-attention operations, and then cross-attention operations are performed with the current module as the query vector to output the feature vector of the sequence information. The image sub-network can be a CNN network. The image information is used as the input of the CNN network, and the output is the feature vector of the image information. The two feature vectors are fused to obtain the final feature vector, which is then input to the layer classifier. The layer classifier outputs the layer probability distribution, and the layer probability distribution determines which module in the mixed action space should be selected as the module for the next placement.

[0124] Optionally, the layer classifier can be an MLP network.

[0125] The layer decision network configuration implements an asynchronous layer decision-making mechanism. Related technologies typically employ synchronous placement mechanisms, where one layer is placed before the next, or according to certain rules such as alternating placement. However, this application's embodiment implements an asynchronous layer decision-making mechanism, where the policy network model determines which layer of the layout module should be placed next, thus expanding the solution space.

[0126] The aspect ratio decision network can be constructed from a CNN network. The canvas image and the mask image are stacked in the feature channel dimension and then input into the CNN network for processing. The output is the aspect ratio probability distribution. The aspect ratio of the current module is output according to the aspect ratio probability distribution.

[0127] The location decision network includes an encoder and an MLP network. The encoder is used to extract features from image and graph information to obtain the target encoding vector. The target encoder vector is used as the input of the MLP network and outputs the probability distribution of the module placement position. Based on the probability distribution of the module placement position, the placement position of the module is determined. For example, the position with the highest probability is directly output as the placement position of the module.

[0128] In one example, the encoder includes an image sub-encoder and a graph sub-encoder. Image information is used as input to the image sub-encoder, which outputs a first encoded vector. Graph information is used as input to the graph sub-encoder, which outputs a second encoded vector. The first encoder vector and the second encoded vector are fused to obtain the target encoded vector. Optionally, the image sub-encoder may include a CNN, and the graph sub-encoder may include a graph neural network based on an attention mechanism. The canvas image and the mask image are stacked along the feature channel dimension and then input into the CNN network for processing, outputting the corresponding image representation vector (i.e., the first encoded vector). The graph information is input into the graph neural network based on an attention mechanism for processing to obtain node-level embedding vectors. Then, global pooling is used to obtain the total graph embedding vector representation. Finally, the image representation, the node-level embedding vectors, and the total graph embedding vector representation are fused (e.g., concatenated) to obtain the target encoded vector.

[0129] Back Figure 5 After the location decision network outputs the location probability distribution, this embodiment further includes using masked image information to correct the current module's location probability distribution, obtaining a masked location probability distribution (masked pos prob). For example, the masked image can be a location masking image, indicating constraints on the possible placement positions of the current module on the die. For instance, the location masking image could represent all possible placement positions of the current module on the die with a green mask. Correcting the location probability distribution output by the location decision network using the location masking image—for example, setting the probability of unmasked positions on the die in the deployment location probability distribution output by the location decision network to 0—achieves explicit constraints on location actions, filters the location probability distribution output by the location decision network, and further improves the accuracy of the location decision network's output. In other examples, multiple masking images can be used to correct the position probability distribution output by the position decision network. For example, by taking the intersection of multiple masks such as position masking image, alignment masking image, line length masking image, module-to-module adjacent masking image, and module-to-port adjacent masking image, explicit constraints on the action space can be achieved to ensure that the output module placement positions satisfy complex constraints such as module-port adjacent, module-to-module adjacent, module alignment, no overlap, and no boundary crossing.

[0130] Optionally, the policy network model in this embodiment can be trained using reinforcement learning. Reinforcement learning does not require a labeled training dataset, saving expensive labeling costs.

[0131] Figure 6 A schematic diagram of a reinforcement learning training architecture for a policy network model is shown. Figure 6As shown, the reinforcement learning training architecture includes a policy network model to be trained and an evaluation (critic) model; the evaluation model is used to evaluate the reward of the deployment action output by the policy network model, and adjust the weight parameters of the policy network model based on the reward.

[0132] Optionally, the evaluation model can share the encoder with the policy evaluation model (e.g., Figure 6 The shared encoder in the model increases training efficiency. For example, multiple chip design front-end design files can be collected as training datasets for reinforcement learning. Layout planning images, netlist circuit diagrams, and module placement sequences are obtained from the design files. Then, image information is generated from the layout planning image, graph information is generated from the netlist circuit diagram, and sequence information is generated from the module placement sequence. The image information, graph information, and sequence information constitute multimodal state information. The policy network model infers and outputs the actions of the modules in the mixed space based on the multimodal state information. The evaluation model evaluates the reward of the layout planning formed after the action is executed, that is, evaluates the reward value Vs of the action step. After the action is executed, the multimodal state information is updated, and the next round continues. This process is repeated multiple times, with the goal of maximizing the accumulated reward value. The parameters of the policy evaluation model are optimized and adjusted until the training completion condition is met (e.g., convergence or reaching a preset number of training rounds), resulting in a trained policy evaluation model.

[0133] For example, image information and sequence information are used as input to the layer decision network to output the current module layer; image information is used as input to the aspect ratio decision network to output the aspect ratio of the current module; image information and graph information are used as input to the shared encoder to output the target encoding vector; the target encoding vector is used as input to the MLP network to output the placement position of the current module; the current module layer, aspect ratio, and placement position constitute the action in the hybrid action space; after the action is executed and the multimodal state information is updated, image information and graph information are used as input to the shared encoder to output the target encoding vector; the target encoding vector and sequence information are fused to obtain a fused vector; the fused vector is used as input to a fully connected network (e.g., MLP) to output the reward value Vs; after the action output by the policy network model is executed, the multimodal state information is updated, and the next iteration continues, with the goal of maximizing the accumulated reward value, to optimize and adjust the parameters of the policy evaluation model.

[0134] The evaluation model is trained on a training dataset, which includes multiple labeled training samples. The training samples are deployment actions (i.e., the rewards of multimodal states after the deployment action is executed). The labels of the deployment actions are determined based on local advantage and global baseline. Local advantage indicates the reward value of the deployment action in the intermediate step, and global baseline indicates the reward value of the deployment action in the last step.

[0135] Based on local advantages and a global baseline, this method integrates local and global information. Local advantages accelerate training, while the global baseline helps the layer decision-making mechanism function better, preventing it from degenerating into a local solution of synchronous decision-making, and also stabilizing the training process. During trajectory / episode collection, for intermediate steps, the difference between the preceding and following steps is selected as the reward function, serving as a local advantage. After collecting the current trajectory, the metric corresponding to the last step is calculated and added to the previous intermediate steps as the global baseline, providing a global perception perspective.

[0136] It should be understood that the trajectory refers to a sequence of multi-step actions in the mixed action space. For example, the actions output by the decision network model are represented by triples (a, b, c), where a represents the module layer in the mixed action space, b represents the aspect ratio of the module in the mixed action space, and c represents the position of the module in the mixed action space. In Die 1, the modules that need to be mapped are module 1, module 2, module 3, module 4, and module 5. The actions of the above modules output by the decision network model are (a1, b1, c1), (a2, b2, c2), (a3, b3, c3), (a4, b4, c4), and (a5, b5, c5). Therefore, the collected trajectory is the sequence of actions output by the decision network model (a1, b1, c1), (a2, b2, c2), (a3, b3, c3), (a4, b4, c4), and (a5, b5, c5).

[0137] The reward function for the intermediate step is calculated using the following formula, where HPWL is the semi-perimeter line length, o is the overlapping area of ​​the module, a is the aligned area of ​​the module, and l is the reward function calculated based on the length of the adjacent common edge between modules:

[0138] r t =(HPWL t-1 -HPWL t )+(o t-1 -o t )+(a t -a t-1 )+(l t -l t-1 )

[0139] After completing the current trajectory collection, modify the intermediate step reward based on the final state metric and add a global baseline:

[0140] r` t =r t -HPWL T -o T +a T +l T

[0141] The reward value for each action is calculated according to the above formula, and this reward value is used as the label of the action. The evaluation model is trained using multiple labeled actions as a training dataset to obtain the trained evaluation model.

[0142] HPWL is the half-perimeter line length, o is the overlapping area of ​​the module, a is the aligned area of ​​the module, and l is the length of the adjacent common edge between modules. These can be understood as optimization indicators. Of course, optimization indicators can be added or reduced according to needs. For example, if you want to optimize the heat dissipation of the chip, thermal optimization can be included in the optimization indicators and participate in the calculation of the reward value r to optimize the heat accumulation problem in the chip.

[0143] Optionally, in embodiments of this application, reinforcement learning PPO algorithm can be used for reinforcement learning, that is, based on the above-mentioned hybrid action space, state space and reward function, reinforcement learning PPO algorithm is used for learning.

[0144] Of course, this application can also be used for layout planning of 2D chips. Figure 7 This diagram illustrates the processing of input state data by another strategy network model. Figure 7 The policy network model shown can be applied to the layout planning of 2D chips, i.e., the layout planning of single-layer dies. For example... Figure 7 As shown, since there is no need to decide which layer to deploy the module at, only the aspect ratio and placement position of the module are needed, the policy network model only includes the aspect ratio decision network and the position decision network, excluding the layer decision network. In actual execution, image information serves as the input to the aspect ratio decision network, outputting an aspect ratio probability distribution; sequence information, image information, and graph information serve as the input to the position decision network, outputting a position probability distribution. Therefore, the output actions of this application include two: the module placement position and the module aspect ratio. These two actions constitute a hybrid action space, which can directly output the module position and aspect ratio, enhancing flexibility. The module position space in the hybrid action space is a discrete space used to determine the position of each module. The module aspect ratio space is a continuous space controlled by a Gaussian distribution, determining the aspect ratio of the module.

[0145] Unlike the strategy network model for 3D chip layout planning, the encoder in the position decision network needs to process sequential data. Therefore, a transformer network is added to the encoder. The transformer network is used to extract feature vectors from the sequential information. Then, the feature vectors are fused with the image features extracted by the CNN and the graph features extracted by the attention-based graph neural network to obtain the target encoding vector. Finally, the target encoding vector is input into the MLP network to output the position probability distribution.

[0146] The policy network model is also trained using reinforcement learning. The training method for reinforcement learning is similar to that for the policy network model of 3D chip layout planning, and can be implemented by reference.

[0147] Figure 8 This diagram illustrates a reinforcement learning training architecture for another policy network model, utilizing... Figure 8 The reinforcement learning training architecture shown can train a policy network model that can be applied to the layout planning of 2D chips. The training method is similar to that of the policy network model for the layout planning of 3D chips, and can be followed accordingly. For the sake of simplicity, it will not be described in detail here.

[0148] In step S303, the deployment actions of each module to be deployed, output by the policy network model, are used to determine the layout planning results.

[0149] Through multiple iterations of the policy network model, the deployment actions of each module to be placed on the chip are obtained. Each module's deployment action indicates which die layer it should be placed on, its position on the die, and its aspect ratio. Based on the deployment actions of each module, a layout planning result can be generated.

[0150] Optionally, the layout planning results can be rendered and displayed to users. For example, the layout planning results can be displayed to users through the EDA layout planning interactive interface, so that backend engineers can understand the chip layout planning results.

[0151] The 3D layout planning implemented by the integrated circuit layout planning method provided in this application embodiment achieves good results in handling inter-layer alignment constraints and line length indices. Validation tests on the publicly available MCNC and GSRC datasets show that the integrated circuit layout planning method provided in this application embodiment improves the alignment score from 0.474 to 0.940, while reducing the line length index by 16%. Furthermore, the integrated circuit layout planning method provided in this application embodiment exhibits transfer and generalization performance. This application embodiment demonstrates good transfer and generalization performance; for example, when trained on the publicly available dataset circuit n100, and then directly tested on other circuits using zero-shot inference, the alignment score and line length are very close to those after retraining, with no significant decrease. Moreover, fine-tuning on larger-scale circuits such as n200 and n300 yields better results than retraining, saving significant training time and computational resources. See the appendix for specific results. Figures 9-12 .

[0152] Figure 9 A schematic diagram of cross-layer module alignment is shown after applying the layout planning method of the integrated circuit of this application to the public dataset circuit n50 and the public dataset circuit n100, respectively.

[0153] Figure 10 A schematic diagram of the layout planning result is shown after applying the layout planning method of this application to the public dataset circuit n50 with 6 preset modules.

[0154] Figure 11 A schematic diagram of the layout planning result is shown after applying the layout planning method of this application to a public dataset circuit n100 with 12 preset modules.

[0155] Figure 12 The diagram illustrates the placement of SRAM0 under complex constraints: 1) optimization of the common edge between SRAM0 and SRAM1, 2) optimization of the common edge between logic0-4, 3) optimization of the alignment area between SRAM0-1 and logic0-4, 4) optimization of the alignment area between other0 and other1, and 5) SRAM0 adjacent to the two ports above it.

[0156] The layout planning results generated by the integrated circuit layout planning method provided in the embodiments of this application, as verified by HiSilicon's yellow zone verification method, conform to the design constraints (see [link]). Figure 13 The technology features pre-built modules, heterogeneous top and bottom die bezels, aligned projections of modules on the top and bottom dies, no overlapping modules within the die, minimized line length, and maximized module projection area. It is currently being tested and optimized in the red zone Kirin chip market. Simultaneously, it is being tested in the 5031 Yellow Crane Tower 3DCC project to complete the modem and media sub-chips, representing 3D stacking technology for next-generation Kirin chips. This technology aims to ensure the core competitiveness of Kirin chips and help terminal products maintain industry leadership even without access to advanced manufacturing processes.

[0157] Based on the same concept as the aforementioned embodiment of an integrated circuit layout planning method, this application also provides an integrated circuit layout planning device 1400. This integrated circuit layout planning device 1400 can be integrated into an EDA (Electronic Design Automation) system to handle complex constraints and improve the quality of layout planning. The integrated circuit layout planning device 1400 includes components for implementing... Figure 3-13 The units or modules in each step of the layout planning method for the integrated circuit shown.

[0158] In some other examples, the integrated circuit layout planning device 1400 provided in this application embodiment can also be used as an external tool and integrated into a large language intelligent agent framework (LLM Agent) to complete task scheduling and tool invocation using a large language model, thereby handling complex constraints and improving the quality of layout planning.

[0159] Figure 14 This is a schematic diagram of an integrated circuit layout planning device provided in an embodiment of this application. Figure 14As shown, the layout planning device 1400 of the integrated circuit includes an acquisition module 1401, an inference module 1402, and a planning module 1403. The acquisition module 1401 is used to acquire current state information, which includes image information, graph information, and sequence information. The image information includes the current layout image information and the masking image information. The current layout image information indicates the distribution of modules on several dies, the masking image information indicates the constraints on the deployment action space of the current module to be deployed, the graph information indicates the connection relationship between multiple modules to be deployed, and the sequence information indicates the deployment order of multiple modules to be deployed. The inference module 1402 is used to take the image information, graph information, and sequence information as input to the policy network model and output the deployment action of the current module to be deployed. The deployment action indicates the deployment position of the current module to be deployed on the die and the aspect ratio of the current module to be deployed. The planning module 1403 is used to determine the layout planning result based on the deployment actions of each module to be deployed output by the policy network model. The layout planning result indicates the deployment position of each module to be deployed on the die and the aspect ratio of each module to be deployed.

[0160] In one possible implementation, several dies include multiple dies, and the deployment action also indicates the die layer to be deployed, i.e., the module to which the die layer should be placed. The policy network model includes an encoder, a layer decision network, an aspect ratio decision network, and a location decision network. The inference module 1402 is specifically used to: take image information and sequence information as input to the layer decision network and output the probability distribution of the die layer to which the module to be deployed is to be deployed; take image information as input to the aspect ratio decision network and output the aspect ratio probability distribution of the module to be deployed; take image information and graph information as input to the encoder and output the target encoding vector; take the target encoding vector as input to the location decision network and output the deployment location probability distribution of the module to be deployed; and determine the deployment action of the module to be deployed based on the probability distribution of the die layer to which the module to be deployed is to be deployed, the aspect ratio probability distribution of the module to be deployed, and the deployment location probability distribution of the module to be deployed.

[0161] In another possible implementation, the encoder includes an image sub-encoder and a graph sub-encoder; a specific implementation of using image information and graph information as input to the encoder and outputting a coded vector is as follows: using image information as input to the image sub-encoder and outputting a first coded vector; using graph information as input to the graph sub-encoder and outputting a second coded vector; and fusing the first encoder vector and the second coded vector to obtain the target coded vector.

[0162] Optionally, the image sub-encoder includes a convolutional neural network, the graph sub-encoder includes an attention-based graph neural network, the layer decision network includes a convolutional neural network and a transformer neural network, the aspect ratio decision network includes a convolutional neural network, and the position decision network includes a multilayer perceptron network.

[0163] In another possible implementation, the integrated circuit layout planning device 1400 provided in this application further includes a correction module 1404, which is used to correct the probability distribution of the deployment location of the module to be deployed based on the image information of the mask.

[0164] In another possible implementation, the masking image information includes one or more of the following: a position masking image, an alignment masking image, a line length masking image, a module and module adjacency masking image, and a module and port adjacency masking image; wherein, the position masking image indicates the constraints on the deployable location of the currently deployed module on the die; the alignment masking image indicates the constraints on the alignment of the currently deployed module with its alignment peer module; the line length masking image indicates the constraints on the increased line length after the currently deployed module is deployed on the die; the module and module adjacency image indicates the constraints on the length of the common edge between the currently deployed module and its adjacent modules; and the module and port adjacency masking image indicates the constraints on the adjacency of the currently deployed module with its ports.

[0165] In another possible implementation, the image information is determined based on the current layout planning image, the graph information is determined based on the netlist circuit diagram, the sequence information is determined based on the sorting information and several attribute information of each module to be deployed, and the sorting information is determined based on the sorting of multiple modules to be deployed according to the target attribute information.

[0166] In another possible implementation, the policy network model is trained based on a reinforcement learning training architecture. Reinforcement learning training does not require a labeled training dataset, saving expensive labeling costs.

[0167] In another possible implementation, the reinforcement learning training architecture includes a policy network model to be trained and an evaluation model; the evaluation model is used to evaluate the reward of the deployment action output by the policy network model and adjust the weight parameters of the policy network model based on the reward; the evaluation model is trained on a training dataset, which includes multiple labeled training samples, which are deployment actions. The labels of the deployment actions are determined based on local advantage and global baseline. Local advantage indicates the reward value of the deployment action in the intermediate step, and global baseline indicates the reward value of the deployment action in the last step.

[0168] In another possible implementation, local advantage is determined based on the difference between the optimization metric after the deployment action of the intermediate step and the optimization metric after the deployment action of the previous step, and the global baseline is used to correct the local advantage.

[0169] In another possible implementation, the evaluation model and the policy network model share the same encoder, increasing training efficiency.

[0170] The integrated circuit layout planning apparatus 1400 according to the embodiments of this application can correspond to the execution of the methods described in the embodiments of this application, and the above and other operations and / or functions of each module in the integrated circuit layout planning apparatus 1400 are respectively for implementing Figure 3-13 For the sake of brevity, the corresponding processes of each method in the code will not be elaborated here.

[0171] Figure 15 A schematic diagram of the structure of a computing device provided in an embodiment of this application.

[0172] like Figure 15 As shown, the computing device 1500 includes at least one processor 1501, a memory 1502, and a communication interface 1503. The processor 1501, memory 1502, and communication interface 1503 are communicatively connected, which can be achieved via a wired (e.g., bus) or wireless connection. The communication interface 1503 is used to send and / or receive data from other devices, such as video data. The memory 1502 stores computer instructions, which the processor 1501 executes to perform the methods described in the aforementioned method embodiments, thereby processing complex constraints and improving the quality of layout planning.

[0173] It should be understood that, in the embodiments of this application, the processor 1501 may be a central processing unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0174] The memory 1502 may include read-only memory and random access memory, and provides instructions and data to the processor 1501. The memory 1502 may also include non-volatile random access memory. Optionally, the random access memory may be, for example, high bandwidth memory (HBM).

[0175] The memory 1502 can be volatile memory or non-volatile memory, or it can include both. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0176] It should be understood that the computing device 1500 according to the embodiments of this application can perform the implementation of the embodiments of this application. Figure 3-13 The method shown is described in detail above, and will not be repeated here for the sake of brevity.

[0177] Embodiments of this application provide a computer-readable storage medium having a computer program stored thereon, wherein when the computer instructions are executed by a processor, the aforementioned method is implemented.

[0178] An embodiment of this application provides a chip including at least one processor and an interface, wherein the at least one processor determines program instructions or data through the interface; the at least one processor is used to execute the program instructions to implement the method mentioned above.

[0179] Embodiments of this application provide a computer program or computer program product that includes instructions that, when executed, cause a computer to perform the methods mentioned above.

[0180] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0181] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented using hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0182] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above description is only a specific embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A layout planning method for integrated circuits, characterized in that, include: Obtain current status information, which includes image information, graph information, and sequence information. The image information includes the current layout image information and the mask image information. The current layout image information indicates the distribution of modules on several bare chips. The mask image information indicates the constraints on the deployment action space of the modules to be deployed. The graph information indicates the connection relationship between multiple modules to be deployed. The sequence information indicates the order in which the multiple modules to be deployed are deployed. The image information, graph information, and sequence information are used as input to the policy network model, and the deployment action of the currently deployed module is output. The deployment action indicates the deployment position of the currently deployed module on the bare chip and the aspect ratio of the currently deployed module. Based on the deployment actions of each of the modules to be deployed output by the policy network model, a layout planning result is determined. The layout planning result indicates the deployment location of each module to be deployed on the bare chip and the aspect ratio of each module to be deployed.

2. The method according to claim 1, characterized in that, The plurality of bare chips includes multiple layers of bare chips, and the deployment action further indicates the bare chip layer to be deployed currently; The policy network model includes an encoder, a layer decision network, an aspect ratio decision network, and a location decision network. The step of using the image information, graph information, and sequence information as input to the policy network model and outputting the deployment action of the currently deployed module includes: The image information and sequence information are used as input to the layer decision network, and the probability distribution of the bare chip layer to be deployed by the current module to be deployed is output. The image information is used as input to the aspect ratio decision network, and the aspect ratio probability distribution of the current module to be deployed is output. The image information and graph information are used as input to the encoder, and the target encoding vector is output. The target encoding vector is used as the input to the location decision network, and the probability distribution of the deployment location of the module to be deployed is output. Based on the probability distribution of the bare chip layer to be deployed by the module to be deployed, the probability distribution of the aspect ratio of the module to be deployed, and the probability distribution of the deployment location of the module to be deployed, the deployment action of the module to be deployed is determined.

3. The method according to claim 2, characterized in that, The encoder includes an image sub-encoder and a map sub-encoder; The step of using the image information and graph information as input to the encoder and outputting an encoded vector includes: The image information is used as input to the image sub-encoder, and the first encoding vector is output. The graph information is used as input to the graph sub-encoder to output a second encoding vector; The first encoder vector and the second encoder vector are fused together to obtain the target encoder vector.

4. The method according to claim 3, characterized in that, The image sub-encoder includes a convolutional neural network, and the graph sub-encoder includes a graph neural network based on an attention mechanism.

5. The method according to any one of claims 2-4, characterized in that, The layer decision network includes convolutional neural networks and transformer neural networks; the aspect ratio decision network includes convolutional neural networks; and the position decision network includes a multilayer perceptron network.

6. The method according to any one of claims 2-5, characterized in that, The step of determining the deployment action of the module to be deployed based on the probability distribution of the bare chip layer to be deployed, the probability distribution of the aspect ratio of the module to be deployed, and the probability distribution of the deployment location of the module to be deployed, further includes: Based on the image information of the mask, the probability distribution of the deployment location of the current module to be deployed is corrected.

7. The method according to any one of claims 1-6, characterized in that, The image information of the mask includes one or more of the following: position mask image, alignment mask image, line length mask image, module and module adjacent mask image, and module and port adjacent mask image; The location masking image indicates the constraints on the deployable locations of the currently deployed module on the bare chip; The alignment mask image indicates the constraints for aligning the currently deployed module with its alignment peer module; The line length masking image indicates the line length constraint added after the current module to be deployed is deployed on the bare chip; The module and the module adjacency image indicate the constraint on the length of the common edge between the currently deployed module and its adjacent modules; The module and port adjacent masking image indicates the constraints of the current module to be deployed being adjacent to the port.

8. The method according to any one of claims 1-7, characterized in that, The image information is determined based on the current layout planning image, the graph information is determined based on the netlist circuit diagram, the sequence information is determined based on the sorting information and several attribute information of each of the modules to be deployed, and the sorting information is determined based on the sorting of the multiple modules to be deployed according to the target attribute information.

9. The method according to any one of claims 2-8, characterized in that, The policy network model is trained based on a reinforcement learning training architecture.

10. The method according to claim 9, characterized in that, The reinforcement learning training architecture includes a policy network model to be trained and an evaluation model; the evaluation model is used to evaluate the reward of the deployment action output by the policy network model, and adjust the weight parameters of the policy network model based on the reward. The evaluation model is trained on a training dataset, which includes multiple labeled training samples. The training samples are deployment actions, and the labels of the deployment actions are determined based on local advantage and global baseline. The local advantage indicates the reward value of the deployment action in an intermediate step, and the global baseline indicates the reward value of the deployment action in the final step.

11. The method according to claim 10, characterized in that, The local advantage is determined based on the difference between the optimization metric after the deployment action of the intermediate step and the optimization metric after the deployment action of the previous step of the intermediate step, and the global baseline is used to correct the local advantage.

12. The method according to claim 10 or 11, characterized in that, The evaluation model and the policy network model share the encoder.

13. A layout planning apparatus for integrated circuits, characterized in that, include: The acquisition module is used to acquire current status information, which includes image information, graph information, and sequence information. The image information includes the current layout image information and the mask image information. The current layout image information indicates the distribution of modules on several bare chips. The mask image information indicates the constraints on the deployment action space of the current module to be deployed. The graph information indicates the connection relationship between multiple modules to be deployed. The sequence information indicates the order in which the multiple modules to be deployed are deployed. The inference module is used to take the image information, graph information and sequence information as input to the policy network model and output the deployment action of the currently deployed module. The deployment action indicates the deployment position of the currently deployed module on the bare chip and the aspect ratio of the currently deployed module. The planning module is used to determine the layout planning result based on the deployment actions of each of the modules to be deployed output by the policy network model. The layout planning result indicates the deployment position of each module to be deployed on the bare chip and the aspect ratio of each module to be deployed.

14. A computing device, comprising a memory and a processor, characterized in that, The memory stores instructions that, when executed by a processor, cause the method described in any one of claims 1-12 to be implemented.

15. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it causes the method as described in any one of claims 1-12 to be implemented.

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