An AI-assisted chip layout planning method and system

Abstract

The application discloses an AI-assisted chip layout planning method and system, and belongs to the technical field of integrated circuit physical design. The method comprises the following steps: analyzing RTL code to construct a directed weighted graph; adopting a graph neural network to learn a module importance evaluation rule from the graph, and combining an area constraint to generate a recommended area proportion; analyzing a memory structure to generate a memory placement suggestion matched with a data flow direction; and comprehensively generating a module-level layout placement suggestion based on the above information. The application automatically analyzes a data flow interaction relationship through an AI algorithm, reduces manual intervention, optimizes area allocation and memory layout, speeds up physical design iteration, and improves timing convergence efficiency.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit physical design technology, specifically to an AI-assisted chip layout planning method and system, applicable to the comprehensive optimization of module layout, data flow direction, fan-out relationship, area allocation, and memory cell placement in the design of high-performance processors and complex system-on-chips (SoCs). Background Technology

[0002] In the physical design of modern high-performance processors and large-scale SoCs, the rationality of the floorplan directly affects the congestion, timing performance, and power consumption of subsequent placement and routing. An unreasonable floorplan often leads to multiple rounds of adjustments, significantly lengthening the design cycle.

[0003] Existing layout planning and design processes typically rely on engineers' detailed analysis of register-transfer-level (RTL) code and extensive communication with microarchitecture designers to confirm data transfer directions between modules, interface relationships, port (pin) placement, and the organization of internal logic and storage units within modules. Based on this, engineers then perform an initial placement of each functional module and its internal memory according to their personal experience.

[0004] However, the above methods have the following shortcomings: First, the rationality of the layout planning usually only becomes apparent after multiple rounds of layout routing and timing analysis, resulting in numerous design iterations and slow timing and performance convergence. Second, the layout planning design process is highly dependent on the communication efficiency among designers; if information is not transmitted in a timely or sufficient manner, unreasonable placement decisions can easily be introduced. In addition, the process heavily relies on the personal experience of engineers and the teamwork ability; the consistency of design results among different personnel is poor, and the overall design quality is difficult to guarantee stably. Summary of the Invention

[0005] The purpose of this invention is to provide an AI-assisted chip layout planning method and system. By automatically analyzing the data flow direction, logical interaction relationship, fan-out situation between modules and port connection characteristics in RTL code through algorithms, reasonable layout planning suggestions are automatically generated with minimal human intervention, thereby accelerating the physical design iteration process and improving the convergence efficiency of timing and performance.

[0006] To achieve the above objectives, the present invention provides an AI-assisted chip layout planning method, comprising the following steps:

[0007] Step S1: parse the RTL code of the target chip, extract the signal connection relationships and data read / write behavior between and within modules, and construct a directed weighted graph to characterize the data flow direction and fan-out characteristics.

[0008] This step automatically extracts the interaction relationships between modules from the RTL code, forming structured data that can be processed by the algorithm. Its benefits include reducing the workload of manually interpreting RTL code and avoiding layout planning errors caused by human misunderstanding.

[0009] Step S2: Using a learning method based on graph neural networks (GNN), learn the module importance evaluation rules from the directed weighted graph, and combine the target area constraints of the chip or subsystem and the module placement boundary conditions to generate the recommended area ratio of each module.

[0010] The module placement boundary conditions include physical constraints such as the overall shape of the chip or subsystem, core area restrictions, power loop location, and input / output port distribution, which are used to limit the feasible area of ​​module layout and ensure that the layout scheme conforms to the overall physical design specifications of the chip.

[0011] This step uses GNN to capture high-dimensional interaction features between modules, learns the weights of the impact of modules on timing and congestion, and performs area allocation based on objective data to avoid unreasonable allocation caused by differences in engineer experience, thereby reducing congestion and timing risks from the source.

[0012] Step S3: Analyze the internal memory structure of the module, partition the memory according to the data access relationship, and generate memory placement suggestions that match the data flow direction.

[0013] This step aligns the partitioning of the memory bank with the direction of data flow, reducing cross-region data access latency and wiring complexity, and improving memory access efficiency.

[0014] Step S4: Based on the recommended area ratio, memory placement suggestions, and data flow interaction relationships between modules, generate module-level layout suggestions.

[0015] This step outputs a layout scheme that can be directly used by physical design tools, reducing manual adjustment costs and improving the efficiency of layout planning initialization.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] (1) By introducing AI algorithms to automatically analyze the data interaction relationships in RTL code, this invention can obtain an accurate understanding of the data flow direction and module interaction characteristics in the early stage of physical design, which significantly reduces the time required for manual code interpretation and repeated communication.

[0018] (2) Based on objective data interaction analysis results, the present invention can make reasonable suggestions on module area allocation and memory placement, thereby reducing congestion and timing problems caused by unreasonable layout planning from the source and accelerating the convergence speed of the overall design.

[0019] (3) By automatically generating system-level layout planning and placement schemes, the present invention effectively reduces the dependence of layout planning and design on engineers' personal experience and teamwork ability, improves the consistency and repeatability of design results, and improves the overall iteration efficiency and engineering quality of high-performance chip design. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0021] Figure 1 This is a flowchart illustrating the AI-assisted chip layout planning method of the present invention.

[0022] Figure 2 This is a framework diagram of the AI-assisted chip layout planning system of the present invention. Detailed Implementation

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] The terms "first," "second," etc., used in this specification are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class, without limiting the number of objects; for example, the first object can be one or more. Furthermore, in the specification, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0025] Example 1

[0026] This embodiment 1 provides an AI-assisted chip layout planning method, such as... Figure 1As shown, it includes the following steps S1 to S4.

[0027] Step S1: Construct a directed weighted graph;

[0028] In this step, the algorithm automatically reads the RTL code of the target chip and performs syntax analysis on it. By analyzing the module instantiation relationship, signal connection relationship and data read and write behavior, it extracts the logical interaction relationship and data interaction path between modules, and then constructs the data interaction graph within and across modules to represent the data flow direction and fan-out characteristics of the overall design.

[0029] The data interaction graph is defined as a directed weighted graph G=(V,E,W), with the following structure:

[0030] Node V: Each node represents a low-level functional module, submodule, or memory bank (the memory bank refers to the logical partition unit of the memory array). Node attributes include module type (such as CPU core, peripheral interface, SRAM), number of ports, and minimum functional area. The minimum functional area refers to the minimum physical area required for the module to implement its basic functions, which can be estimated from the number of module gates and the area of ​​a standard cell. This node attribute characterizes the basic physical and functional features of the module, providing fundamental constraints for subsequent area allocation.

[0031] Edge E: Directed edge → Representation module To module There is a data-driven or read-write interaction relationship, such as modules. Output signal drive module Input, or module For modules The memory in the system is accessed for reading and writing, and the direction of the edges is consistent with the direction of the data flow.

[0032] Weight W: Edge weight The formula used to quantify the strength of interactions between modules is:

[0033] ;

[0034] in For module arrive The number of signal connections; Modules obtained from RTL parsing right Data read / write frequency; This serves as an identifier to determine whether the interaction path belongs to a critical timing path. A critical path is the path with the smallest timing margin, and is assigned a value of 1. Non-critical paths are assigned a value of 0.2. , , This is a configurable hyperparameter; the default value is... , , The weighting can be adjusted according to the project's time priority or cabling requirements.

[0035] This weighting calculation formula comprehensively quantifies the number of connections between modules, access frequency, and timing criticality, making the representation of data flow interaction intensity more accurate.

[0036] Step S2: Generate recommended area proportions;

[0037] This step employs a learning method based on graph neural networks (GNNs) to learn module importance evaluation rules from the directed weighted graph. Combined with the target area constraints of the chip or subsystem and the module placement boundary conditions, it generates the recommended area ratio for each module.

[0038] Specifically, a Graph Neural Network (GNN) is first used to encode the data interaction graph, learning the mapping relationship between inter-module interaction features and module importance. In this embodiment, the GNN adopts a Graph Attention Network (GAT) architecture, with the input being a module-level data interaction graph. Node features include module type encoding, number of ports, and minimum functional area, while edge features include normalized edge weights. The GNN aggregates neighborhood node features through multi-layer graph convolution operations, encoding inter-module interaction information into module importance vectors, which are then mapped through fully connected layers to represent the recommended area ratio and interaction priority score for each module.

[0039] The training data for the GNN model comes from the RTL, netlists, layout planning, and temporal congestion reports of historical design projects, constructing a supervised dataset of "data interaction graph → area allocation → temporal / congestion metrics". The supervision labels include the number of congestion hotspots, the temporal margin of critical paths, and module-level area utilization. Design samples that have successfully converged are given higher weights, allowing the model to learn "good area allocation" patterns.

[0040] It should be noted that during the specific training process of the GNN model, RTL code, netlists, placement planning results, and corresponding timing congestion reports from over 50 historical chip design projects were collected. For each design project, module-level data interaction graphs were extracted as input features, and the number of congestion hotspots, critical path timing margin, and module-level area utilization in the final placement plan were used as supervision labels. 80% of the data was used as the training set, 10% as the validation set, and 10% as the test set. The model was trained using the Adam optimizer with a learning rate of 0.001 for 200 training epochs. Training stopped when the validation set loss function did not decrease for 10 consecutive epochs.

[0041] Based on the importance score of the GNN output module, further optimization methods such as heuristic search or simulated annealing are adopted to iteratively optimize the area ratio of each bottom module with the objective function of target area constraint, minimizing wiring congestion and maximizing timing convergence probability.

[0042] It should be noted that during the simulated annealing optimization process, the initial solution is directly generated from the recommended area proportion output by the GNN. The initial temperature is set to 100, the termination temperature is set to 0.01, and the cooling coefficient is set to 0.95. At each temperature, the number of iterations is 100. The neighborhood search strategy involves randomly selecting a module, randomly adjusting its area proportion within its upper and lower area limits, and simultaneously adjusting the areas of other modules to maintain the total area constraint unchanged. The process terminates early when the optimal solution shows no improvement after three consecutive temperatures.

[0043] In the heuristic search / simulated annealing optimization process, the objective function can be expressed as:

[0044] ;

[0045] in To predict cabling congestion, For critical path timing margin, To maximize area utilization, , , This is a weighting coefficient; the default value can be set according to design priorities, for example... , , By iteratively optimizing to minimize the objective function, an area allocation scheme that balances congestion, timing, and area utilization can be obtained.

[0046] Among them, module importance Determined by both interaction density and temporal criticality, the calculation formula is as follows:

[0047] ;

[0048] Interaction density D i Representation module The level of interactive activity in the overall design is calculated as follows:

[0049] ;

[0050] i.e., module The sum of the weights of all incoming and outgoing edges divided by the total weight of all edges in the entire graph.

[0051] Timing criticality Representation module The degree of impact on overall timing convergence is calculated using the included module method. The proportion of critical paths to the total number of critical paths, where the critical path is the path with the smallest timing margin. Timing margin refers to the difference between the actual arrival time of a signal and its required arrival time; the smaller the margin, the more critical the path.

[0052] θ is a balancing coefficient, with a default value of 0.6, used to adjust the weighting of interaction density and temporal criticality. This calculation formula comprehensively evaluates the module's activity level in the data interaction network and its impact on timing, making the importance assessment more comprehensive.

[0053] Under the overall chip or subsystem target area Atotal constraint, the module Recommended area ratio The calculation formula is:

[0054] ;

[0055] in For module The basic area ratio is determined by the minimum functional area to ensure that the basic functions are not affected by the area compression. This is the base area weight, with a default value of 0.2, used to balance data-driven area allocation with the basic functional requirements of the module. For module The importance of For module The importance of [the concept], and satisfying the total area constraint and the preset upper and lower area limits; the constraint conditions are: and ,in , The upper and lower limits of module area are preset for the project to avoid extreme area allocation. The preset upper and lower limits of area can be preset by engineers based on module functions, process library characteristics and design experience. For example, for a CPU core module, its lower limit of area should ensure the implementation requirements of basic computing units, while the upper limit of area is constrained by the overall chip area budget.

[0056] This area ratio calculation formula strikes a balance between data-driven optimization and basic functional protection, avoiding the inability of module functions to be realized due to over-optimization.

[0057] Step S3: Generate memory placement suggestions;

[0058] In this step, the algorithm further analyzes the memory structure inside the module, automatically divides the memory banks, and divides different banks into regions based on data access and interaction relationships, generating memory placement suggestions that match the data flow direction.

[0059] Specifically, by analyzing the memory read and write operations in the RTL code, the access relationship matrix between each memory bank and the module is extracted. A clustering algorithm is used to divide memory banks that are frequently accessed by the same module or have strong data interaction relationships into the same region, and this region is placed close to the corresponding module.

[0060] It should be noted that, in one specific embodiment, the K-means clustering algorithm is used to partition the memory banks. The cluster feature vector is composed of the access frequency between each memory bank and each functional module. The number of clusters K is automatically determined based on the total number of memory banks. After clustering, memory banks of the same cluster are placed near the modules with the highest access frequency in that cluster.

[0061] This step reduces cross-region data access latency and wiring complexity, lowers memory access power consumption, and improves overall performance.

[0062] Step S4: Generate module-level layout suggestions.

[0063] In this step, the algorithm integrates the data flow interaction between modules, the recommended area ratio generated in step S2, and the memory placement strategy generated in step S3. Under the premise of meeting the overall layout planning constraints, it automatically completes the layout planning and placement exploration of all modules and outputs module-level layout placement suggestions that can be used by engineers for reference or directly used in the subsequent physical design stage.

[0064] The output module-level layout suggestions include the following three feasible engineering formats, adaptable to different physical design tools and engineer usage scenarios:

[0065] Structured configuration file (JSON / CSV format): contains fields such as module name, hierarchy, placement coordinates (x, y), width and height dimensions (w, h), and region division information, which can be directly imported into physical design tools or used for subsequent automated process parsing.

[0066] Visual layout sketches (SVG / PNG format): Visually display the distribution of module locations, the density of interactions between modules (represented by color depth or line thickness), and the results of memory bank area division in the form of heat maps or line diagrams, helping engineers quickly identify clusters of highly interactive modules and guide local layout adjustments.

[0067] Executable scripts (TCL / Python format): Generate scripts that can be run directly in physical design tools such as Innovus and ICC2, automatically complete module-level layout constraint settings, reduce manual adjustment costs, and improve layout planning initialization efficiency.

[0068] This step offers multiple output formats to meet the needs of different design processes and tools, lowering the barrier to engineering implementation.

[0069] Example 2

[0070] This embodiment 2 provides an AI-assisted chip layout planning system for executing the method described in embodiment 1. Figure 2 As shown, the system includes an RTL parsing module 1, an area analysis module 2, a memory layout module 3, and a layout generation module 4.

[0071] The RTL parsing module 1 is used to parse the RTL code of the target chip, extract the signal connection relationships and data read / write behaviors between and within modules, and construct a directed weighted graph. The nodes of the directed weighted graph represent the underlying functional modules, sub-modules, or memory banks. The node attributes include module type, number of ports, and minimum functional area. The directed edges represent the data driving or read / write interaction relationships between modules.

[0072] The area analysis module 2 is used to learn module importance evaluation rules from the directed weighted graph using a learning method based on graph neural networks, and to generate recommended area proportions for each module by combining the target area constraints of the chip or subsystem and the module placement boundary conditions. For the specific implementation of this module, please refer to the description of step S2 in Embodiment 1.

[0073] The memory layout module 3 is used to analyze the memory structure inside the module and generate memory placement suggestions based on data access relationships. For a detailed description of the implementation of this module, please refer to step S3 in Embodiment 1.

[0074] The layout generation module 4 is used to generate module-level layout suggestions by comprehensively considering the recommended area ratio, storage placement suggestions, and data flow interaction relationships between modules. The layout suggestions output by this module include at least one of structured configuration files, visual layout sketches, and executable scripts.

[0075] The system described in this embodiment corresponds to the method described in Embodiment 1. The functional implementation of each module can be referred to the corresponding steps in Embodiment 1, and will not be repeated here.

[0076] Example 3

[0077] This embodiment further explains the hybrid framework used in step S2.

[0078] This invention employs a hybrid framework that combines a learning method based on graph neural networks (GNNs) with an optimization method based on heuristic search, which has clear applicability in layout planning exploration.

[0079] The learning-based part (GNN) is used to learn the mapping relationship between module importance, interaction density, and area distribution in the data interaction graph parsed from RTL. Compared with traditional heuristic algorithms, GNN can better capture the complex correlation between cross-module data flow, fan-out features, and timing / congestion risks, and is more suitable for the high-dimensional constraints of chip design.

[0080] The optimization part (heuristic search / simulated annealing): Based on the learned module importance, the area ratio of each underlying module is iteratively optimized with the objective function of target area constraint, minimizing wiring congestion and maximizing timing convergence probability. This ensures that an area allocation suggestion that can be implemented in the project is given while meeting the global area budget, avoiding local optima.

[0081] This hybrid framework combines the intelligence of learning-based methods with the convergence guarantee of optimization-based methods, enabling it to learn excellent layout patterns from historical data and perform fine-grained optimization for specific design constraints.

[0082] Example 4

[0083] This embodiment provides supplementary explanation of the definition of the critical path in step S1.

[0084] The critical path described in this invention is the path with the smallest timing margin. Timing margin refers to the difference between the actual arrival time of a signal and its required arrival time; the smaller the margin, the more critical the path. In practical engineering applications, static timing analysis tools (such as PrimeTime and Tempus) can be used to perform timing analysis on the design to identify several paths with the smallest timing margins as critical paths. Typically, the paths with the worst margins (5%-10%) are selected as the statistical objects. For modules... The proportion of critical paths to the total number of critical paths Statistical calculations can be performed based on the path information in the static time series analysis report.

[0085] It should be noted that when a critical path contains multiple modules, the path is counted in the critical path count of each module containing it. For example, if a critical path passes through module A, module B, and module C in sequence, then the path contributes 1 count to each of module A, module B, and module C. The total number of critical paths is based on the top N worst paths reported by the time series analysis tool, where N is typically between 100 and 1000, determined based on the design scale.

[0086] This definition clarifies the criteria for identifying critical paths and ensures that the calculation of time-series criticality is feasible.

[0087] Example 5

[0088] This embodiment provides supplementary explanation of the preset method for the upper and lower limits of the module area in step S2.

[0089] The preset area upper and lower limits described in this invention and Engineers can pre-determine the area based on module functions, process library characteristics, and design experience. For example, for a CPU core module, its lower area limit should ensure the implementation requirements of basic arithmetic units, while the upper area limit is constrained by the overall chip area budget; for a memory module, its lower area limit is determined by storage capacity and bit width, while the upper area limit is limited by power consumption and timing constraints.

[0090] This preset method avoids extreme area allocation and ensures that the basic functions of each module are implemented.

[0091] Example 6

[0092] This embodiment provides supplementary explanations regarding the boundary conditions for module placement in step S2.

[0093] The module placement boundary conditions described in this invention include physical constraints such as the overall shape of the chip or subsystem, core area restrictions, power ring location, and input / output port distribution. Here, the overall shape refers to the rectangular or irregular outline of the chip or subsystem; the core area restriction refers to the legal area where logic circuits can be placed; the power ring location refers to the area occupied by the power supply network, typically prohibiting the placement of standard cells; and the input / output port distribution refers to the location of signal interfaces on the chip boundary. These constraints collectively define the feasible area for module layout, ensuring that the layout scheme conforms to the overall physical design specifications of the chip.

[0094] This definition clarifies the feasible areas for module placement, preventing the generated layout from violating physical design rules.

[0095] The above description is merely a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. An AI-assisted chip layout planning method, characterized in that, Includes the following steps: Step S1: Parse the RTL code of the target chip, extract the signal connection relationships and data read / write behaviors between and within modules, and construct a directed weighted graph to characterize the data flow direction and fan-out characteristics; the nodes of the directed weighted graph represent the underlying functional modules, sub-modules or memory banks, and the directed edges represent the data driving or read / write interaction relationships between modules. The edge weights are calculated based on the number of signal connections, the frequency of data read / write, and whether it is a critical timing path. Step S2: Using a learning method based on graph neural networks, module importance evaluation rules are learned from the directed weighted graph. Combined with the target area constraints of the chip or subsystem and the module placement boundary conditions, the recommended area ratio of each module is generated. The module importance evaluation rules include the calculation of interaction density and temporal criticality. Among them, interaction density The calculation method is as follows: module The sum of the weights of all incoming and outgoing edges divided by the sum of the weights of all edges in the entire graph; temporal criticality. For containing modules The proportion of the number of critical paths to the total number of critical paths, where the critical path is the path with the smallest timing margin; module importance. , This is the balance coefficient; Step S3: Analyze the internal memory structure of the module, partition the memory according to the data access relationship, and generate memory placement suggestions that match the data flow direction; Step S4: Based on the recommended area ratio, memory placement suggestions, and data flow interaction relationships between modules, generate module-level layout suggestions.

2. The AI-assisted chip layout planning method according to claim 1, characterized in that, The formula for calculating the edge weight is: ； in For module arrive The number of signal connections; For module right Data read / write frequency; Critical path identifier; , , These are configurable hyperparameters.

3. The AI-assisted chip layout planning method according to claim 1, characterized in that, The recommended area ratio The calculation method is as follows: ; The proportion of the basic area Determined by the minimum functional area, Based on the basic area weight, For module The importance of For module The importance of this is that it satisfies the total area constraint and the preset upper and lower area limits.

4. The AI-assisted chip layout planning method according to claim 1, characterized in that, Steps S1 to S4 are implemented using a hybrid framework that combines a learning method based on graph neural networks with an optimization method based on heuristic search. The learning method is used to learn the mapping relationship between module importance, interaction density and area allocation from the directed weighted graph, and the optimization method is used to optimize the module area allocation and layout scheme under area constraints.

5. The AI-assisted chip layout planning method according to claim 4, characterized in that, The training data for the learning method comes from the RTL, netlists, layout planning, and temporal congestion reports of historical design projects. The supervision labels include the number of congestion hotspots, the time margin of critical paths, and the module-level area utilization rate. The supervision labels are used to train the learning method.

6. The AI-assisted chip layout planning method according to claim 1, characterized in that, In step S4, the generated module-level layout suggestions include at least one of the following forms: The structured configuration file contains module name, hierarchical affiliation, placement coordinates, size, and affiliation area information; Visual layout sketches that graphically represent the distribution of module locations and interaction density; The tool is an executable script used to automatically complete module-level layout constraint settings in physical design tools.

7. An AI-assisted chip layout planning system for executing the AI-assisted chip layout planning method according to any one of claims 1-6, characterized in that, include: The RTL parsing module is used to parse the RTL code of the target chip, extract the signal connection relationships and data read / write behaviors between and within modules, and construct a directed weighted graph. The nodes of the directed weighted graph represent the underlying functional modules, sub-modules or memory banks. The node attributes include module type, number of ports and minimum functional area. The directed edges represent the data driving or read / write interaction relationships between modules. The area analysis module is used to learn the module importance evaluation rules from the directed weighted graph using a learning method based on graph neural networks, and generate the recommended area ratio of each module by combining the target area constraints of the chip or subsystem and the module placement boundary conditions. The memory layout module is used to analyze the internal memory structure of the module and generate memory placement suggestions based on data access relationships. The layout generation module is used to generate module-level layout suggestions by comprehensively considering the recommended area ratio, storage placement suggestions, and data flow interaction relationships between modules.

8. The AI-assisted chip layout planning system according to claim 7, characterized in that, The module-level layout suggestions output by the layout generation module include at least one of structured configuration files, visual layout sketches, and tool executable scripts.

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