Display device

Abstract

The invention provides a display device which can improve resolution. The display device comprises a plurality of first LEDs, a plurality of second LEDs, a plurality of third LEDs, a plurality of first sub-pixel circuits, a plurality of second sub-pixel circuits, a plurality of third sub-pixel circuits, a plurality of first common control units and a plurality of second common control units. In the first light emission mode, the first common control unit is turned off according to the first light emission signal, and the second common control unit is turned on according to the second light emission signal. Thus, the plurality of first sub-pixel circuits drive the plurality of first LEDs to form a first color light emitting path in which the plurality of first LEDs are connected in series. The plurality of second sub-pixel circuits drive the plurality of second LEDs to form a plurality of second color light emitting paths, respectively. The plurality of third sub-pixel circuits drive a plurality of third LEDs to form a plurality of third color light emitting paths, respectively.

Description

Technical Field

[0001] This invention relates to a display device, and more particularly to a display device that can emit light using a plurality of light-emitting diodes (LEDs) connected in series. Background Technology

[0002] A display can drive multiple LEDs to show an image using multiple pixel circuits. Each pixel circuit can include multiple sub-pixel circuits. The display drives multiple LEDs of different colors (including red, green, and blue) through these sub-pixel circuits. Multiple sub-pixel circuits corresponding to the same color can also share a control switch to connect their respective LEDs in series to form a single light-emitting path, thereby saving power for white screens.

[0003] However, because each color requires an additional shared control switch for its multiple sub-pixel circuits, current displays have complex circuit structures, increasing layout difficulty. Furthermore, since multiple red LEDs, multiple blue LEDs, and multiple green LEDs are connected in series to form a single red light-emitting unit, a single blue light-emitting unit, and a single green light-emitting unit, respectively, the display's resolution decreases accordingly based on the number of LEDs connected in series. Summary of the Invention

[0004] This invention provides a display device that can emit light using multiple light-emitting units connected in series, and can improve the resolution and layout complexity of the screen.

[0005] The display device of this invention includes a plurality of first light-emitting units, a plurality of second light-emitting units, a plurality of third light-emitting units, a plurality of first sub-pixel circuits, a plurality of second sub-pixel circuits, a plurality of third sub-pixel circuits, a plurality of first common control units, and a plurality of second common control units. The plurality of first sub-pixel circuits, the plurality of second sub-pixel circuits, and the plurality of third sub-pixel circuits are respectively coupled to the plurality of first light-emitting units, the plurality of second light-emitting units, and the plurality of third light-emitting units. The plurality of first common control units and the plurality of second common control units are coupled to the plurality of first sub-pixel circuits, the plurality of second sub-pixel circuits, and the plurality of third sub-pixel circuits. Each first common control unit and each second common control unit is used to receive a first light-emitting signal and a second light-emitting signal, respectively.

[0006] In the first emission mode, each first shared control unit is turned off according to the first emission signal, and each second shared control unit is turned on according to the second emission signal. Thus, multiple first sub-pixel circuits drive multiple first emission units to form a first color emission path consisting of multiple first emission units connected in series. Multiple second sub-pixel circuits drive multiple second emission units to form multiple second color emission paths. Multiple third sub-pixel circuits drive multiple third emission units to form multiple third color emission paths.

[0007] Based on the above, the display device of this embodiment controls multiple first sub-pixel circuits, multiple second sub-pixel circuits, and multiple third sub-pixel circuits corresponding to different colors to perform different light-emitting operations through multiple shared control units. It can connect multiple first light-emitting units corresponding to a first color in series to achieve power saving, and simultaneously drive multiple second light-emitting units and multiple third light-emitting units corresponding to other colors independently. In this way, the display device can improve screen resolution and reduce the layout complexity of various sub-pixel circuits while applying power saving functions.

[0008] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0009] Figure 1 This is a circuit block diagram of a display device according to an embodiment of the present invention.

[0010] Figure 2 This is a circuit diagram of a plurality of first sub-pixel circuits according to an embodiment of the present invention.

[0011] Figure 3 This is a circuit diagram of a plurality of first sub-pixel circuits according to another embodiment of the present invention.

[0012] Figure 4 This is a circuit diagram of a plurality of first sub-pixel circuits according to another embodiment of the present invention.

[0013] Explanation of reference numerals in the attached figures: 100, 200, 400: Display devices 110a~110d, 210a~210d: First sub-pixel circuit 120a~120d: Second sub-pixel circuit 130a~130d: Third sub-pixel circuit 141~1412, 241, 244, 249, 2412: First common control unit 151~1511, 251~253: Second shared control unit 310a~310d: Data writing circuit 320a~320d, 520d: Compensation circuit 330a~330d: Reset circuit 410d, 610d: Fourth-stage first sub-pixel circuit C1: Capacitor D_R1~D_R4, D_G1~D_G2, D_B1~D_B2: Data voltages EM1(n+1): The signal emitted by the subsequent stage EM1~EM2, EM1(n), EM2(n+1): Emitted signals LD11~LD14: Red LEDs LD21~LD24: Green LEDs LD31~LD34: Blue LEDs PXU: Pixel Unit S1~S2, S1(n), S2(n): Control signals S1(n+1), S2(n+1): Subsequent stage control signals SW1~SW2: Switching elements T1~T8: Transistors Td: Driving transistor VBS: Bias voltage VDD_R1~VDD_R3, VDD: High power supply voltage Vp, Vp2: Reference voltages VSS_R1~VSS_R3, VSS: Low power supply voltage Detailed Implementation

[0014] Some embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Component symbols used in the following description, when appearing in different drawings, are considered to be the same or similar components. These embodiments are only a part of the present invention and do not disclose all possible implementations of the invention. More precisely, these embodiments are merely examples within the scope of the present invention's patent application.

[0015] Figure 1 This is a circuit block diagram of a display device according to an embodiment of the present invention. (See reference) Figure 1 The display device 100 may be, for example, an automotive display using micron-sized light-emitting diodes (Micro LEDs). The display device 100 can emit light using multiple light-emitting units connected in series to achieve power saving. The display device 100 can also improve screen resolution and reduce circuit layout complexity in power-saving applications.

[0016] The display device 100 includes a plurality of first sub-pixel circuits 110a-110d, a plurality of second sub-pixel circuits 120a-120d, a plurality of third sub-pixel circuits 130a-130d, a plurality of first light-emitting units LD11-LD14, a plurality of second light-emitting units LD21-LD24, and a plurality of third light-emitting units LD31-LD34. The plurality of first sub-pixel circuits 110a-110d are respectively coupled to the plurality of first light-emitting units LD11-LD14 and are used to drive the plurality of first light-emitting units LD11-LD14. The plurality of first light-emitting units LD11-LD14 may, for example, be red light-emitting units (hereinafter referred to as red LEDs LD11-LD14).

[0017] Similarly, multiple second sub-pixel circuits 120a-120d are respectively coupled to multiple second light-emitting units LD21-LD24 and are used to drive the multiple second light-emitting units LD21-LD24. The multiple second light-emitting units LD21-LD24 may be, for example, green light-emitting units (hereinafter referred to as green LEDs LD21-LD24). Multiple third sub-pixel circuits 130a-130d are respectively coupled to multiple third light-emitting units LD31-LD34 and are used to drive the multiple third light-emitting units LD31-LD34. The multiple third light-emitting units LD31-LD34 may be, for example, blue light-emitting units (hereinafter referred to as blue LEDs LD31-LD34).

[0018] The display device 100 also includes a plurality of first common control units 141-1412 and a plurality of second common control units 151-1511. The plurality of first common control units 141-1412 and the plurality of second common control units 151-1511 are coupled to a plurality of first sub-pixel circuits 110a-110d, a plurality of second sub-pixel circuits 120a-120d, and a plurality of third sub-pixel circuits 130a-130d. The plurality of first common control units 141-1412 and the plurality of second common control units 151-1511 can be implemented as switches, for example, using p-type metal-oxide-semiconductor field-effect transistors (PMOSFETs).

[0019] Specifically, multiple first shared control units 141-1412 are respectively coupled to multiple first sub-pixel circuits 110a-110d and their corresponding multiple red LEDs LD11-LD14, multiple second sub-pixel circuits 120a-120d and their corresponding multiple green LEDs LD11-LD14, and multiple third sub-pixel circuits 130a-130d and their corresponding multiple blue LEDs LD11-LD14. Each first shared control unit 141-1412 receives a first light emission signal EM1 (hereinafter referred to as light emission signal EM1) and performs a switching action according to the light emission signal EM1.

[0020] Multiple second shared control units 151-153 are coupled to multiple first sub-pixel circuits 110a-110d and their corresponding multiple red LEDs LD11-LD14. Multiple second shared control units 154-1511 are respectively coupled to multiple second sub-pixel circuits 120a-120d and their corresponding green LEDs LD21-LD24, and multiple third sub-pixel circuits 130a-130d and their corresponding blue LEDs LD31-LD34. Each second shared control unit 151-153 and 154-1511 receives a second light-emitting signal EM2 (hereinafter referred to as light-emitting signal EM2) and performs a switching action according to the light-emitting signal EM2.

[0021] Multiple first sub-pixel circuits 110a-110d and their corresponding red LEDs LD11-LD14, multiple second sub-pixel circuits 120a-120d and their corresponding green LEDs LD21-LD24, multiple third sub-pixel circuits 130a-130d and their corresponding blue LEDs LD31-LD34, and various associated common control units 141-1412 and 151-1511 can serve as a single pixel unit PXU. The display device 100 may include multiple pixel units PXU, which can be configured in multiple ways, and the multiple pixel units can be arranged, for example, in an array.

[0022] In display operation, the display device 100 controls multiple pixel units (including pixel units PXU) according to multiple control signals S1~S2, various data voltages (including data voltages D_R1~D_R4, D_G1~D_G4, D_B1~D_B4), and various power supply voltages (including high power supply voltages VDD_R1~VDD_R3 and VDD, and low power supply voltages VSS_R1~VSS_R3 and VSS) through its own controller (including timing controller) and driver (including source driver and gate driver).

[0023] The display device 100 can selectively operate in a first light-emitting mode to apply a high-brightness function or a power-saving function. In the first light-emitting mode, the display device 100 scans multiple pixel units through multiple second common control units (including second common control units 151-153 and 154-1511) so that each pixel unit is driven to emit light.

[0024] Taking a single pixel unit PXU as an example, in the first emission mode, each of the first common control units 141-1412 is turned off according to the emission signal EM1. Each of the second common control units 151-153 and 154-1511 is turned on according to the emission signal EM2. At this time, the multiple first sub-pixel circuits 110a-110d drive multiple red LEDs LD11-LD14. The multiple red LEDs LD11-LD14 are connected in series with each other through the multiple turned-on second common control units 151-153. Thus, the multiple first sub-pixel circuits 110a-110d form a first color emission path (hereinafter referred to as the red emission path) connecting the multiple red LEDs LD11-LD14 in series.

[0025] In detail, the plurality of first sub-pixel circuits 110a-110d include a first-level first sub-pixel circuit 110a, a second-level first sub-pixel circuit 110b, a third-level first sub-pixel circuit 110c, and a fourth-level first sub-pixel circuit 110d. In the first light-emitting mode, the plurality of red LEDs LD11-LD14, which are respectively coupled to the first-level first sub-pixel circuit 110a, the second-level first sub-pixel circuit 110b, the third-level first sub-pixel circuit 110c, and the fourth-level first sub-pixel circuit 110d, are connected in series sequentially. Thus, the plurality of first sub-pixel circuits 110a-110d can, for example, form a red light-emitting path starting from red LED LD11, sequentially flowing through the second common control unit 151, red LED LD12, the second common control unit 152, red LED LD13, the second common control unit 153, and red LED LD14.

[0026] In the first light-emitting mode, multiple second sub-pixel circuits 120a-120d drive multiple green LEDs LD21-LD24. The multiple green LEDs LD21-LD24 are independent of each other through multiple activated second common control units 154, 156, 159, and 1511. Thus, the multiple second sub-pixel circuits 120a-120d each form multiple independent second color light-emitting paths (hereinafter referred to as green light-emitting paths). That is, the first-level second sub-pixel circuit 120a forms a green light-emitting path flowing through the second common control unit 154 and the green LED LD21. The second-level second sub-pixel circuit 120b forms a green light-emitting path flowing through the second common control unit 156 and the green LED LD22, and so on.

[0027] In the first light-emitting mode, multiple third sub-pixel circuits 130a-130d drive multiple blue LEDs LD31-LD34. The multiple blue LEDs LD31-LD34 are independent of each other through multiple second common control units 155, 157, 158, and 1510 that are turned on. Thus, the multiple third sub-pixel circuits 130a-130d each form multiple independent third-color light-emitting paths (hereinafter referred to as blue light-emitting paths). That is, the first-level third sub-pixel circuit 130a forms a blue light-emitting path flowing through the second common control unit 155 and the blue LED LD31. The second-level third sub-pixel circuit 130b forms a blue light-emitting path flowing through the second common control unit 157 and the blue LED LD32, and so on.

[0028] It is worth mentioning that, since multiple first sub-pixel circuits 110a~110d and their corresponding multiple red LEDs LD11~LD14 are interconnected through multiple second common control units 151~153 to form a single red light-emitting path, the display device 100 can achieve power saving based on the reduced total trans-voltage of these LEDs LD11~LD14. Simultaneously, since multiple second sub-pixel circuits 120a~120d and their corresponding multiple green LEDs LD21~LD24, and multiple third sub-pixel circuits 130a~130d and their corresponding multiple blue LEDs LD31~LD34 are interconnected through multiple second common control units 154~1511 to form multiple independent green light-emitting paths and multiple blue light-emitting paths, the display device 100 can maintain the resolution of blue and green while only reducing the resolution of red, thereby improving the resolution of the screen while applying power saving.

[0029] Furthermore, based on the arrangement of multiple second shared control units 151-1511, the display device 100 can omit too many shared control units to connect multiple green LEDs LD21-LD24 and multiple blue LEDs LD31-LD34 in series. In this way, the display device 100 can reduce the complexity of circuit layout while achieving power-saving functions.

[0030] exist Figure 1 In this embodiment, the display device 100 may also selectively operate in a second light-emitting mode, i.e., a general mode. In the second light-emitting mode, the display device 100 scans multiple pixel units through multiple first common control units (including first common control units 141-1412) so that each pixel unit is driven to emit light.

[0031] Taking a single pixel unit PXU as an example, in the second light emission mode, each of the first common control units 141-1412 is turned on according to the light emission signal EM1. Each of the second common control units 151-1511 is turned off according to the light emission signal EM2. At this time, multiple first sub-pixel circuits 110a-110d drive multiple red LEDs LD11-LD14. The multiple red LEDs LD11-LD14 are independent of each other through the multiple first common control units 141, 144, 149, and 1412 that are turned on. Thus, the multiple first sub-pixel circuits 110a-110d each form multiple independent red light emission paths. That is, the first-level first sub-pixel circuit 110a forms a red light emission path flowing through the first common control unit 141 and the red LED LD11. The second-level first sub-pixel circuit 110b forms a red light emission path flowing through the first common control unit 144 and the red LED L12, and so on.

[0032] In the second light-emitting mode, multiple second sub-pixel circuits 120a-120d drive multiple green LEDs LD21-LD24. The multiple green LEDs LD21-LD24 are independent of each other through multiple activated first common control units 142, 145, 148, and 1411. Thus, the multiple second sub-pixel circuits 120a-120d each form multiple independent green light-emitting paths. Furthermore, multiple third sub-pixel circuits 130a-130d drive multiple blue LEDs LD31-LD34. The multiple blue LEDs LD31-LD34 are independent of each other through multiple activated first common control units 143, 146, 147, and 1410. Thus, the multiple third sub-pixel circuits 130a-130d each form multiple independent blue light-emitting paths.

[0033] Figure 2 This is a circuit diagram of a plurality of first sub-pixel circuits according to an embodiment of the present invention. (See reference) Figure 2 The display device 200 includes first-level first sub-pixel circuits 210a to fourth-level first sub-pixel circuits 210d and their corresponding first light-emitting units LD11~LD14, multiple first shared control units 241, 244, 249 and 2412 associated with the multiple first sub-pixel circuits 210a~210d, and multiple second shared control units 251~253. Compared to Figure 1 The display device 100 and display device 200 shown omit information regarding the plurality of second sub-pixel circuits and their corresponding plurality of green light-emitting units, the plurality of third sub-pixel circuits and their corresponding plurality of third light-emitting units, and the associated first common control unit and second common control unit. The circuit architecture of the plurality of first sub-pixel circuits 210a to 210d is the same as that of the plurality of second sub-pixel circuits, and is also the same as that of the plurality of third sub-pixel circuits.

[0034] exist Figure 2 In this embodiment, the first-stage first sub-pixel circuit 210a receives a first high power supply voltage VDD_R1 (hereinafter referred to as high power supply voltage VDD_R1) and a first low power supply voltage VSS_R1 (hereinafter referred to as low power supply voltage VSS_R1). The second first sub-pixel circuit 210b and the third-stage first sub-pixel circuit 210c receive a second high power supply voltage (hereinafter referred to as high power supply voltage VDD_R2) and a second low power supply voltage VSS_R2 (hereinafter referred to as low power supply voltage VSS_R2). The fourth-stage first sub-pixel circuit 210d receives a third high power supply voltage VDD_R3 (hereinafter referred to as high power supply voltage VDD_R3) and a third low power supply voltage VSS_R3 (hereinafter referred to as low power supply voltage VSS_R3).

[0035] It should be noted that the low power supply voltage VSS_R1 received by the first-stage first sub-pixel circuit 210a and the high power supply voltage VDD_R3 received by the fourth-stage first sub-pixel circuit 210d are shared. Thus, based on this shared power supply voltage layout, the display device 200 can save circuit space.

[0036] In this embodiment, the voltage value of the high supply voltage VDD_R1 (e.g., 13V) is greater than the voltage value of the high supply voltage VDD_R2 (e.g., 6.5V). The voltage value of the high supply voltage VDD_R2 is equal to the voltage value of the low supply voltage VSS_R1 (e.g., 6.5V) and the voltage value of the high supply voltage VDD_R3 (e.g., 6.5V), and is also greater than the voltage values ​​of the low supply voltage VSS_R2 (e.g., 0V) and the low supply voltage VSS_R3 (e.g., 0V). The voltage value of the low supply voltage VSS_R2 is equal to the voltage value of the low supply voltage VSS_R3, and may be, for example, ground voltage.

[0037] Each first sub-pixel circuit 210a-210d includes the same or similar circuit architecture. Taking the first-level sub-pixel circuit 210a as an example, the first-level sub-pixel circuit 210a includes a driving transistor Td, a data writing circuit 310a, a first transistor T1 (hereinafter referred to as transistor T1), a compensation circuit 320a, and a reset circuit 330a. The driving transistor Td and transistor T1 can be implemented, for example, using PMOS.

[0038] The control terminal (i.e., gate terminal) of transistor T1 receives a first light-emitting signal EM1(n) (hereinafter referred to as light-emitting signal EM1(n)). The first terminal (i.e., source terminal) of transistor T1 receives one of a plurality of reference voltages (e.g., a first reference voltage Vp, hereinafter referred to as reference voltage Vp). The second terminal (i.e., drain terminal) of transistor T1 is coupled to a data writing circuit 310a, and is coupled to the control terminal (i.e., gate terminal) of drive transistor Td through the data writing circuit 310a. The first terminal (i.e., source terminal) of drive transistor Td receives one of a plurality of power supply voltages (e.g., a high power supply voltage VDD_R). The second terminal (i.e., drain terminal) of drive transistor Td is coupled to a compensation circuit 320a and the anode terminal of the corresponding red LED LD11.

[0039] The data writing circuit 310a is coupled to the control terminal (i.e., the gate terminal) of the driving transistor Td, and also to the first terminal of the compensation circuit 320a. The data writing circuit 310a receives the data voltage D_R1 and the first control signal S1(n) (hereinafter referred to as control signal S1(n)). The second terminal of the compensation circuit 320a is coupled to the second terminal (i.e., the drain terminal) of the driving transistor Td, and also to the anode terminal of the corresponding red LED LD11. The compensation circuit 320a receives the control signal S1(n). The first terminal of the reset circuit 330a is coupled to the third terminal of the compensation circuit 320a. The second terminal of the reset circuit 330a is coupled to the second terminal (i.e., the drain terminal) of the corresponding first common control unit 241, and receives the low power supply voltage VSS_R1. The reset circuit 330a also receives the second control signal S2(n) (hereinafter referred to as control signal S2(n)).

[0040] In detail, the data writing circuit 310a in the first-level sub-pixel circuit 210a includes a ninth transistor T9 (hereinafter referred to as transistor T9) and a capacitor C1. Transistor T9 may be implemented, for example, as a PMOS. The control terminal (i.e., gate terminal) of transistor T9 receives a control signal S1(n). The first terminal (i.e., source terminal) of transistor T9 receives a data voltage D_R1. The second terminal (i.e., drain terminal) of transistor T9 is coupled to the first terminal of capacitor C1 and the second terminal (i.e., drain terminal) of transistor T1. The second terminal of capacitor C1 is coupled to the control terminal (i.e., gate terminal) of driving transistor Td and the first terminal of compensation circuit 320a.

[0041] The compensation circuit 320a in the first-level sub-pixel circuit 210a includes a sixth transistor T6 (hereinafter referred to as transistor T6) and a seventh transistor T7 (hereinafter referred to as transistor T7). Transistors T6 and T7 can be implemented, for example, as PMOS. The control terminal (i.e., gate terminal) of transistor T6 receives a control signal S1(n). The first terminal (i.e., source terminal) of transistor T6 is coupled to the control terminal (i.e., gate terminal) of driving transistor Td and the second terminal of capacitor C1. The second terminal (i.e., drain terminal) of transistor T6 is coupled to the first terminal (i.e., source terminal) of transistor T7 and the first terminal of reset circuit 330a. The control terminal (i.e., gate terminal) of transistor T7 receives a control signal S1(n). The second terminal (i.e., drain terminal) of transistor T7 is coupled to the second terminal (i.e., drain terminal) of driving transistor Td and the anode terminal of the corresponding red LED LD11.

[0042] The reset circuit 330a at the second terminal (i.e., drain terminal) of the driving transistor Td includes an eighth transistor T8 (hereinafter referred to as transistor T8). Transistor T8 may be implemented, for example, as a PMOS. The control terminal (i.e., gate terminal) of transistor T8 receives a second control signal S2(n) (hereinafter referred to as control signal S2(n)). The first terminal (i.e., source terminal) of transistor T8 is coupled to the second terminal (i.e., drain terminal) of transistor T6 and the first terminal (i.e., source terminal) of transistor T7. The second terminal (i.e., drain terminal) of transistor T8 is coupled to the second terminal (i.e., drain terminal) of the corresponding first common control unit 241 to receive a low supply voltage VSS_R1.

[0043] The control terminal (i.e., gate terminal) of the first common control unit 241 associated with the first-stage sub-pixel circuit 210a receives the light-emitting signal EM1(n). The first terminal (i.e., source terminal) of the first common control unit 241 is coupled to the cathode terminal of the corresponding red LED LD11 and the first terminal (i.e., source terminal) of the corresponding second common control unit 251. The second terminal (i.e., drain terminal) of the second common control unit 251 is coupled to one end of the compensation circuit 320b included in the next stage (i.e., the second-stage sub-pixel circuit 210b), the second terminal (i.e., drain terminal) of the driving transistor Td, and the anode terminal of the corresponding red LED LD12. The control terminal (i.e., gate terminal) of the second common control unit 251 receives the second light-emitting signal EM2(n+1). The second light-emitting signal EM2(n+1) can be, for example, a follow-up stage to the second light-emitting signal EM2(n), and is hereinafter referred to as the light-emitting signal EM2(n+1).

[0044] Furthermore, the first-level sub-pixel circuit 210a also includes a second switching element SW2 (hereinafter referred to as switching element SW2). Switching element SW2 can be implemented, for example, as a PMOS. The control terminal (i.e., the gate terminal) of switching element SW2 receives the light emission signal EM2(n+1). The first terminal (i.e., the source terminal) of switching element SW2 is coupled to the first terminal (i.e., the source terminal) of transistor T1 to receive the reference voltage Vp. The second terminal (i.e., the drain terminal) of switching element SW2 is coupled to the second terminal (i.e., the drain terminal) of transistor T1.

[0045] The circuit architecture of the driving transistor Td, data writing circuit 310b, transistor T1, compensation circuit 320b, and reset circuit 330b included in the second-level sub-pixel circuit 210b can be deduced by referring to the relevant description of the first-level sub-pixel circuit 210a. Compared to the first-level sub-pixel circuit 210a, the second-level sub-pixel circuit 210b also includes a first switching element SW1 (hereinafter referred to as switching element SW1). Switching element SW1 can be implemented, for example, as a PMOS. The control terminal (i.e., gate terminal) of switching element SW1 receives the light emission signal EM2(n+1). The first terminal (i.e., source terminal) of switching element SW1 receives one of a plurality of power supply voltages (e.g., high power supply voltage VDD_R1) or a control signal S2(n). The second terminal (i.e., drain terminal) of switching element SW1 is coupled to the second terminal (i.e., drain terminal) of transistor T1.

[0046] The circuit architecture of the driving transistor Td, data writing circuit 310c, transistor T1, compensation circuit 320c, and reset circuit 330c included in the third-level sub-pixel circuit 210c can be deduced by referring to the relevant description of the first-level sub-pixel circuit 210a. Compared with the first-level sub-pixel circuit 210a, the second-level sub-pixel circuit 210b also includes a switching element SW1. The control terminal (i.e., gate terminal) of the switching element SW1 receives the light emission signal EM2(n+1). The first terminal (i.e., source terminal) of the switching element SW1 receives either the high power supply voltage VDD_R1 or the subsequent second control signal S2(n+1) (hereinafter referred to as the subsequent control signal S2(n+1). The second terminal (i.e., drain terminal) of the switching element SW1 is coupled to the second terminal (i.e., drain terminal) of the transistor T1.

[0047] It should be noted that in the first light-emitting mode, when the high-brightness or power-saving function is applied, each switching element SW1 in the second-level sub-pixel circuit 210b and the third-level sub-pixel circuit 210c is turned on according to the light-emitting signal EM2(n+1). Thus, regardless of the content of the data voltage D_R2 or D_R3 written by the data writing circuit 310b or 310c, the switching element SW1 can pull the voltage on the control terminal (i.e., the gate terminal) of the driving transistor Td to a high voltage level (i.e., the voltage value of the high power supply voltage VDD_R1, the control signal S2(n), or the subsequent control signal S2(n+1)). In other words, each driving transistor Td in the second-level sub-pixel circuit 210b and the third-level sub-pixel circuit 210c remains in the off state in the first light-emitting mode. Therefore, the display device 200 can reduce the interference of the multiple series-connected red LEDs LD11~LD14 caused by the high power supply voltage VDD_R2 through their corresponding driving transistors Td.

[0048] The circuit architecture of the driving transistor Td, data writing circuit 310d, and transistor T1 included in the fourth-level sub-pixel circuit 210d can be deduced by referring to the relevant description of the first-level sub-pixel circuit 210a. Compared to the first-level sub-pixel circuit 210a, the first terminal of the compensation circuit 320d in the fourth-level sub-pixel circuit 210d is coupled to the capacitor C1 in the data writing circuit 310d and the control terminal (i.e., the gate terminal) of the driving transistor Td. The second terminal of the compensation circuit 320d is coupled to the second terminal (i.e., the drain terminal) of the driving transistor Td, and is also coupled to the first terminal (i.e., the source terminal) of the corresponding first common control unit 2412. In addition, the first terminal of the reset circuit 330d in the fourth-level sub-pixel circuit 210d is coupled to the third terminal of the compensation circuit 320d. The second terminal of the reset circuit 330d is coupled to the cathode terminal of the corresponding red LED LD14 and receives the low power supply voltage VSS_R3.

[0049] In detail, the compensation circuit 320d in the fourth-level sub-pixel circuit 210d includes a second transistor T2 (hereinafter referred to as transistor T2) and a fourth transistor T4 (hereinafter referred to as transistor T4). Transistors T2 and T4 can be implemented, for example, as PMOS. The control terminal (i.e., gate terminal) of transistor T2 receives the subsequent first control signal S1(n+1) (hereinafter referred to as control signal S1(n+1)). The first terminal (i.e., source terminal) of transistor T2 is coupled to the control terminal (i.e., gate terminal) of the driving transistor Td and the second terminal of capacitor C1. The second terminal (i.e., drain terminal) of transistor T2 is coupled to the first terminal (i.e., source terminal) of transistor T4 and the first terminal of reset circuit 330d. The control terminal (i.e., gate terminal) of transistor T4 receives the subsequent control signal S1(n+1). The second terminal (i.e., drain terminal) of transistor T4 is coupled to the second terminal (i.e., drain terminal) of the driving transistor Td and the first terminal (i.e., source terminal) of the corresponding first common control unit 2412.

[0050] The control terminal (i.e., gate terminal) of the first common control unit 2412 associated with the fourth-level sub-pixel circuit 210d receives the subsequent stage of the light-emitting signal EM1(n), namely the subsequent stage first light-emitting signal EM1(n+1) (hereinafter referred to as the subsequent stage light-emitting signal EM1(n+1)). The second terminal (i.e., drain terminal) of the first common control unit 2412 is coupled to the anode terminal of the corresponding red LED LD11 and the second terminal (i.e., drain terminal) of the corresponding second common control unit 253. The first terminal (i.e., source terminal) of the second common control unit 253 is coupled to the cathode terminal of the red LED LD13 corresponding to the previous stage (i.e., the third-level sub-pixel circuit 210c) and the first terminal (i.e., source terminal) of the first common control unit 249. The control terminal (i.e., gate terminal) of the second common control unit 253 receives the second light-emitting signal EM2(n+1).

[0051] The reset circuit 330d in the fourth-level sub-pixel circuit 210d includes a fifth transistor T5 (hereinafter referred to as transistor T5). Transistor T5 can be implemented, for example, as a PMOS. The control terminal (i.e., gate terminal) of transistor T5 receives the subsequent control signal S2(n+1). The first terminal (i.e., source terminal) of transistor T5 is coupled to the second terminal (i.e., drain terminal) of transistor T2 and the first terminal (i.e., source terminal) of transistor T4. The second terminal (i.e., drain terminal) of transistor T5 is coupled to the cathode terminal of the corresponding red LED LD14 to receive the low supply voltage VSS_R3.

[0052] Furthermore, the fourth-level sub-pixel circuit 210d also includes a third switching element (hereinafter referred to as switching element SW3). Switching element SW3 can be implemented, for example, as a PMOS. The control terminal (i.e., the gate terminal) of switching element SW3 receives the light emission signal EM2(n+1). The first terminal (i.e., the source terminal) of switching element SW3 is coupled to the first terminal (i.e., the source terminal) of transistor T1 to receive the reference voltage Vp. The second terminal (i.e., the drain terminal) of switching element SW3 is coupled to the second terminal (i.e., the drain terminal) of transistor T1. In some embodiments, switching element SW3 may be omitted.

[0053] In this embodiment, the reference voltage Vp (e.g., 3.5V) is less than the low supply voltage VSS_R1 and greater than the low supply voltage VSS_R3. The light-emitting signals EM1(n) and EM2(n+1), the subsequent light-emitting signal EM1(n+1), the control signals S1(n) and S2(n), and the subsequent control signals S1(n+1) and S2(n+1) can be, for example, switching signals that toggle between logic high and logic low.

[0054] Figure 3 This is a circuit diagram of a plurality of first sub-pixel circuits according to another embodiment of the present invention. (See reference) Figure 3 Compared to Figure 2 In the display device 200 shown, the voltage value of the high power supply voltage VDD_R1 (e.g., 13V) received by the first-level first sub-pixel circuit 210a is equal to the voltage value of the high power supply voltage VDD_R2 (e.g., 13V) received by the second-level first sub-pixel circuit 210b and the third-level first sub-pixel circuit 210c, and is greater than the voltage value of the high power supply voltage VDD_R3 (e.g., 6.5V) received by the fourth-level first sub-pixel circuit 410d. The voltage value of the high power supply voltage VDD_R3 is equal to the voltage value of the low power supply voltage VSS_R1 (e.g., 6.5V) and the voltage value of the low power supply voltage VSS_R2 (e.g., 6.5V), and is greater than the voltage value of the low power supply voltage VSS_R3 (e.g., 0V).

[0055] Furthermore, in the fourth-level sub-pixel circuit 210d, the compensation circuit 520d includes, in addition to transistors T2 and T4, a third transistor T3 (hereinafter referred to as transistor T3). Transistor T3 can be implemented, for example, as a PMOS.

[0056] Specifically, the control terminal (i.e., gate terminal) of transistor T2 receives the subsequent control signal S1(n+1). The first terminal (i.e., source terminal) of transistor T2 is coupled to the control terminal (i.e., gate terminal) of driving transistor Td and capacitor C1 in data writing circuit 310d. The second terminal (i.e., drain terminal) of transistor T2 is coupled to the first terminal (i.e., source terminal) of transistor T3. The control terminal (i.e., gate terminal) of transistor T3 receives the bias voltage VBS. The second terminal (i.e., drain terminal) of transistor T3 is coupled to the first terminal (i.e., source terminal) of transistor T4. The control terminal (i.e., gate terminal) of transistor T4 receives the subsequent control signal S1(n+1). The second terminal (i.e., drain terminal) of transistor T4 is coupled to the second terminal (i.e., drain terminal) of driving transistor Td and the first terminal (i.e., source terminal) of the corresponding first common control unit 2412.

[0057] In this embodiment, the bias voltage VBS can be, for example, a switching signal that switches between logic high and logic low. The bias voltage VBS is independent of the subsequent control signals S1(n+1) and S2(n+1).

[0058] In the fourth-level sub-pixel circuit 210d, the control terminal (i.e., gate terminal) of transistor T5, included in the reset circuit 330d, receives the subsequent control signal S2(n+1). The first terminal (i.e., source terminal) of transistor T5 is coupled to the second terminal (i.e., drain terminal) of transistor T2 and the first terminal (i.e., source terminal) of transistor T3. The second terminal (i.e., drain terminal) of transistor T5 is coupled to the cathode terminal of the corresponding red LED LD14.

[0059] It should be noted that in the general mode, the fourth-level sub-pixel circuit 410d can form an independent red light-emitting path flowing through the driving transistor Td, the corresponding first common control unit 2412, and the corresponding red LED LD14. Each of the other sub-pixel circuits 210a to 210c, taking the first-level sub-pixel circuit 210a as an example, forms an independent red light-emitting path flowing through the driving transistor Td, the corresponding red LED LD11, and the corresponding first common control unit 241.

[0060] Thus, by adding an additional transistor T3 to the compensation circuit 520d of the fourth-level sub-pixel circuit 210d to be controlled by an independent bias voltage VBS, the display device 400 is able to reduce the difference between the multiple independent drive currents flowing through the multiple red LEDs LD11~LD14 in normal mode.

[0061] Figure 4 This is a circuit diagram of a plurality of first sub-pixel circuits according to another embodiment of the present invention. (See reference) Figure 3 Compared to Figure 2In the display device 200 shown, within the display device 600, the voltage value of the high power supply voltage VDD_R1 (e.g., 13V) received by the first-level first sub-pixel circuit 210a is equal to the voltage value of the high power supply voltage VDD_R2 (e.g., 13V) received by the second-level first sub-pixel circuit 210b and the third-level first sub-pixel circuit 210c, and is greater than the voltage value of the high power supply voltage VDD_R3 (e.g., 6.5V) received by the fourth-level first sub-pixel circuit 410d. The voltage value of the high power supply voltage VDD_R3 is equal to the voltage value of the low power supply voltage VSS_R1 (e.g., 6.5V) and the voltage value of the low power supply voltage VSS_R2 (e.g., 6.5V), and is greater than the voltage value of the low power supply voltage VSS_R3 (e.g., 0V).

[0062] Furthermore, the reference voltage received by the first terminal (i.e., the source terminal) of each transistor T1 in the first-stage first sub-pixel circuit 210a, the second-stage first sub-pixel circuit 210b, and the third-stage first sub-pixel circuit 210c is one of a plurality of reference voltages (e.g., reference voltage Vp). The reference voltage received by the first terminal (i.e., the source terminal) of the transistor T1 in the fourth-stage sub-pixel circuit 410d is another of a plurality of reference voltages (e.g., the second reference voltage Vp2, hereinafter referred to as reference voltage Vp2).

[0063] It should be noted that the reference voltage Vp2 (e.g., 3.6V) is slightly greater than the reference voltage Vp (e.g., 3.5V). Since the fourth-level sub-pixel circuit 410d can compensate for the critical voltage of the corresponding driving transistor Td by adjusting the independent reference voltage Vp2, the independent driving current flowing through the corresponding red LED LD14 can be adjusted accordingly in normal mode. Thus, the display device 600 can improve the inconsistency between the multiple independent driving currents flowing through the multiple red LEDs LD11~LD14 in normal mode.

[0064] In summary, the display device of this invention can achieve power saving by using multiple red LEDs connected in series to emit light, and simultaneously avoids excessive degradation of screen resolution by using multiple light-emitting paths formed by multiple green LEDs and multiple blue LEDs. By saving on the shared control unit and by using shared low and high power supply voltages, the display device can improve layout and save circuit space.

[0065] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the concept and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A display device, comprising: Multiple first light-emitting units, multiple second light-emitting units, and multiple third light-emitting units; Multiple first sub-pixel circuits, multiple second sub-pixel circuits, and multiple third sub-pixel circuits are respectively coupled to the first light-emitting units, the second light-emitting units, and the third light-emitting units; Multiple first shared control units and multiple second shared control units are coupled to the first sub-pixel circuits, the second sub-pixel circuits, and the third sub-pixel circuits. Each first shared control unit and each second shared control unit is used to receive a first light emission signal and a second light emission signal, respectively. In a first light emission mode, each of the first shared control units is turned off according to the first light emission signal, and each of the second shared control units is turned on according to the second light emission signal, so that the first sub-pixel circuits drive the first light emission units to form a first color light emission path in series with the first light emission units, the second sub-pixel circuits drive the second light emission units to form a plurality of second color light emission paths respectively, and the third sub-pixel circuits drive the third light emission units to form a plurality of third color light emission paths respectively.

2. The display device of claim 1, wherein the first sub-pixel circuits include a first-level first sub-pixel circuit, a second-level first sub-pixel circuit, a third-level first sub-pixel circuit, and a fourth-level first sub-pixel circuit, wherein in the first light-emitting mode, the first light-emitting units respectively coupled to the first-level first sub-pixel circuit, the second-level first sub-pixel circuit, the third-level first sub-pixel circuit, and the fourth-level first sub-pixel circuit are connected in series sequentially to form the first color light-emitting path.

3. The display device as claimed in claim 2, wherein the first-level first sub-pixel circuit receives a first high power supply voltage and a first low power supply voltage, the second-level first sub-pixel circuit and the third-level first sub-pixel circuit receive a second high power supply voltage and a second low power supply voltage, and the fourth-level first sub-pixel circuit receives a third high power supply voltage and a third low power supply voltage, wherein the first low power supply voltage received by the first-level first sub-pixel circuit and the third high power supply voltage received by the fourth-level first sub-pixel circuit are shared.

4. The display device of claim 3, wherein the voltage value of the first high power supply voltage is greater than the voltage value of the second high power supply voltage, wherein the voltage value of the second high power supply voltage is equal to the voltage value of the first low power supply voltage and the voltage value of the third high power supply voltage, and is greater than the voltage value of the second low power supply voltage and the voltage value of the third low power supply voltage, wherein the voltage value of the second low power supply voltage is equal to the voltage value of the third low power supply voltage.

5. The display device of claim 3, wherein the voltage value of the first high power supply voltage is equal to the voltage value of the second high power supply voltage and is greater than the voltage value of the third high power supply voltage, wherein the voltage value of the third high power supply voltage is equal to the voltage value of the first low power supply voltage and the voltage value of the second low power supply voltage, and is greater than the voltage value of the third low power supply voltage.

6. The display device of claim 1, wherein in a second light-emitting mode, each of the first common control units is turned on according to the first light-emitting signal, and each of the second common control units is turned off according to the second light-emitting signal, so that the first sub-pixel circuits drive the first light-emitting units to form a plurality of first color light-emitting paths, the second sub-pixel circuits drive the second light-emitting units to form the second color light-emitting paths, and the third sub-pixel circuits drive the third light-emitting units to form the third color light-emitting paths.

7. The display device of claim 2, wherein each of the first sub-pixel circuits comprises: A driving transistor having a first terminal that receives one of a plurality of power supply voltages; A data writing circuit is coupled to the control terminal of the driving transistor and receives a data voltage and a first control signal or a subsequent first control signal. A first transistor has a control terminal that receives the first light-emitting signal or the subsequent stage of the first light-emitting signal, a first terminal of the first transistor that receives one of a plurality of reference voltages, and a second terminal of the first transistor that is coupled to the control terminal of the driving transistor through the data writing circuit. A compensation circuit has a first terminal coupled to the control terminal of the driving transistor and the data writing circuit, and a second terminal coupled to the second terminal of the driving transistor and the anode of the corresponding first light-emitting unit or the first terminal of the corresponding first common control unit. The compensation circuit receives the first control signal or the subsequent first control signal. as well as A reset circuit has a first terminal coupled to the compensation circuit, a second terminal coupled to the second terminal of the corresponding first common control unit or the cathode terminal of the corresponding first light-emitting unit, and the reset circuit receives a second control signal or a subsequent second control signal.

8. The display device of claim 7, wherein each of the second-level first sub-pixel circuit and the third-level first sub-pixel circuit further comprises: A first switching element has a control terminal that receives the second light emission signal, a first terminal of the first switching element that receives a first high power supply voltage, the second control signal, or the subsequent second control signal, and a second terminal of the first switching element that is coupled to the second terminal of the first transistor.

9. The display device of claim 8, wherein in the first light-emitting mode, each of the first switching elements is turned on according to the second light-emitting signal, so that each of the driving transistors in the second-level first sub-pixel circuit and the third-level first sub-pixel circuit remains off.

10. The display device of claim 8, wherein the first-level first sub-pixel circuit further comprises: A second switching element has a control terminal for receiving the second light emission signal, a first terminal of the second switching element being coupled to a first terminal of the first transistor to receive a first reference voltage among the reference voltages, and a second terminal of the second switching element being coupled to a second terminal of the first transistor.

11. The display device of claim 10, wherein the fourth-level first sub-pixel circuit further comprises: A third switching element has a control terminal for receiving the second light emission signal, a first terminal of the third switching element coupled to the first terminal of the first transistor to receive the first reference voltage, and a second terminal of the third switching element coupled to the second terminal of the first transistor.

12. The display device of claim 10, wherein the compensation circuit in the fourth-level first sub-pixel circuit comprises: A second transistor has a control terminal that receives the first control signal from the subsequent stage, and a first terminal of the second transistor is coupled to the control terminal of the driving transistor and the data writing circuit. A third transistor has a control terminal that receives a bias voltage, and a first terminal of the third transistor is coupled to a second terminal of the second transistor. as well as A fourth transistor has a control terminal that receives the first control signal from the subsequent stage. The first terminal of the fourth transistor is coupled to the second terminal of the third transistor. The second terminal of the fourth transistor is coupled to the second terminal of the driving transistor and the first terminal of the corresponding first common control unit.

13. The display device of claim 12, wherein the reset circuit in the fourth-level first sub-pixel circuit comprises: A fifth transistor has a control terminal that receives the second control signal from the subsequent stage. The first terminal of the fifth transistor is coupled to the second terminal of the second transistor and the first terminal of the third transistor. The second terminal of the fifth transistor is coupled to the cathode terminal of the corresponding first light-emitting unit. The anode terminal of the corresponding first light-emitting unit is coupled to the second terminal of the corresponding first common control unit and the second terminal of the corresponding second common control unit.

14. The display device of claim 12, wherein each of the compensation circuits in the first-level first sub-pixel circuit, the second-level first sub-pixel circuit, and the third-level first sub-pixel circuit comprises: A sixth transistor has a control terminal that receives the first control signal or the subsequent first control signal, and a first terminal of the sixth transistor is coupled to the control terminal of the driving transistor and the data writing circuit. as well as A seventh transistor has a control terminal that receives the first control signal or the subsequent first control signal. The first terminal of the seventh transistor is coupled to the second terminal of the sixth transistor, and the second terminal of the seventh transistor is coupled to the second terminal of the driving transistor and the anode terminal of the corresponding first light-emitting unit.

15. The display device of claim 14, wherein each of the reset circuits in the first-level first sub-pixel circuit, the second-level first sub-pixel circuit, and the third-level first sub-pixel circuit comprises: An eighth transistor has a control terminal that receives the second control signal or the subsequent second control signal. The first terminal of the eighth transistor is coupled to the second terminal of the sixth transistor. The second terminal of the eighth transistor is coupled to the second terminal of the corresponding first common control unit. The first terminal of the corresponding first common control unit is coupled to the cathode terminal of the corresponding first light-emitting unit and the first terminal of the corresponding second common control unit.

16. The display device of claim 8, wherein the first terminal of each of the first transistors in the first-level first sub-pixel circuit, the second-level first sub-pixel circuit, and the third-level first sub-pixel circuit receives a first reference voltage among the reference voltages, and the first terminal of the first transistor in the fourth-level first sub-pixel circuit receives a second reference voltage among the reference voltages.

17. The display device of claim 15, wherein the voltage value of the second reference voltage is greater than the voltage value of the first reference voltage.

18. The display device of claim 8, wherein each of the data writing circuits comprises: A ninth transistor, having a control terminal to receive the first control signal or the subsequent first control signal, and a first terminal of the ninth transistor to receive the data voltage; as well as A capacitor having a first end coupled to a second end of the ninth transistor, the second end of the capacitor being coupled to a control terminal of the driving transistor.

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