Dynamic random access memory device
By introducing slave DRAM chips and master DRAM chips into the DRAM device, the operating state of the slave power supply circuit is dynamically controlled, solving the problem of power consumption not being reduced in the prior art and achieving more efficient energy management.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-27
- Publication Date
- 2026-04-10
AI Technical Summary
Existing DRAM devices still consume power even without using Category 2 DRAM chips, and this cannot be effectively reduced.
The design employs slave DRAM chips and master DRAM chips. The slave power supply circuit stops generating voltage when the slave DRAM chip is not in use, and the master DRAM chip operates independently to reduce power consumption.
This technology enables dynamic adjustment of the power supply circuit's operating state as needed in DRAM devices of different product categories, thereby reducing power consumption.
Smart Images
Figure CN121838835A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present disclosure relates to a memory device, and more particularly, to a dynamic random-access memory (DRAM) device. BACKGROUND
[0002] A dynamic random-access memory (DRAM) device includes a first category of DRAM chips and a second category of DRAM chips. DRAMs can be sold in different product categories. For example, a first product category of DRAM devices can use both the first category of DRAM chips and the second category of DRAM chips. A second product category of DRAM devices uses only the first category of DRAM chips.
[0003] It should be noted that in the first product category of DRAM devices and the second product category of DRAM devices, the second category of DRAM chips still generate power. That is, the power consumption of the second product category of DRAM devices is not reduced without using the second category of DRAM chips. SUMMARY
[0004] The present disclosure provides a dynamic random-access memory (DRAM) device capable of reducing power consumption according to a product category of the DRAM device.
[0005] In one embodiment of the present disclosure, a DRAM device includes at least one slave DRAM chip and a master DRAM chip. Each of the at least one slave DRAM chip includes a slave control circuit and a slave power supply circuit. The slave control circuit generates a slave control signal according to a slave category signal and a set signal. The slave power supply circuit is coupled to the slave control circuit. The slave power supply circuit stops generating at least one of a plurality of slave voltages in response to a first value of the slave control signal and generates the plurality of slave voltages in response to a second value of the slave control signal. The master DRAM chip is coupled to the at least one slave DRAM chip. The master DRAM chip controls operation of the at least one slave DRAM chip. The master DRAM chip includes a master control circuit. The master control circuit generates a master control signal according to a master category signal and the set signal and controls the master DRAM chip to generate a plurality of master voltages according to the master control signal. The slave category signal is different from the master category signal.
[0006] Based on the above, the slave power supply circuit of the slave DRAM chip stops generating at least one of the plurality of slave voltages in response to the first value of the slave control signal. Thus, when the DRAM device uses only the first type of DRAM chip, the slave power supply circuit of the slave DRAM chip can be controlled to stop generating at least one of the plurality of slave voltages. In this way, when the DRAM device uses only the first type of DRAM chip, the power consumption of the DRAM device can be reduced. BRIEF DESCRIPTION OF DRAWINGS
[0007] Figure 1 is a schematic diagram of a dynamic random-access memory (DRAM) device according to an embodiment of the disclosure;
[0008] Figure 2 is a schematic diagram of a DRAM device according to an embodiment of the disclosure;
[0009] Figure 3 is a schematic diagram of a slave control circuit according to an embodiment of the disclosure;
[0010] Figure 4 is a schematic diagram of a master control circuit according to an embodiment of the disclosure;
[0011] Figure 5 is a schematic diagram of a DRAM device according to an embodiment of the disclosure;
[0012] Figure 6 is a schematic diagram of a DRAM device according to an embodiment of the disclosure;
[0013] Figure 7 is a schematic diagram of a DRAM device according to an embodiment of the disclosure;
[0014] Figure 8 is a schematic diagram of a slave power supply circuit according to an embodiment of the disclosure;
[0015] Figure 9 is a schematic diagram of a master power supply circuit according to an embodiment of the disclosure.
[0016] REFERENCE SIGNS
[0017] 100, 200, 300, 300A, 300B: DRAM device
[0018] 110, 310: slave DRAM chip
[0019] 120, 220, 320: master DRAM chip
[0020] 111, 311: slave control circuit
[0021] 112, 312: slave power supply circuit
[0022] 1121, 2221: bandgap reference voltage generation circuit
[0023] 1122, 2222: voltage regulator
[0024] 1123, 2223: charge pump
[0025] 121, 221, 321: master control circuit
[0026] 222, 322: master power supply circuit
[0027] 330: setting circuit
[0028] CS: connection structure
[0029] INV1, INV2: inverter
[0030] NAND1, NAND2: NAND gate
[0031] SC1: slave control signal
[0032] SC2: master control signal
[0033] SM: master category signal
[0034] SSL: slave category signal
[0035] SST: setting signal
[0036] VSL1, VSL2, VSL3, VSL4, VSL5, VSL6, VSLn: slave voltage
[0037] VM1, VM2, VM3, VM4, VM5, VM6, VMn: master voltage DETAILED DESCRIPTION
[0038] The present disclosure can be understood by referring to the following detailed description in conjunction with the drawings described below. It should be noted that the various drawings of the present disclosure show portions of electronic devices and certain components in the various drawings can not be drawn to scale for purposes of clarity and ease of understanding by the reader. In addition, the number and size of each device shown in the drawings is merely illustrative and is not intended to limit the scope of the present disclosure.
[0039] Certain terms are used throughout the description and claims to refer to specific components. As those skilled in the art will understand, electronic device manufacturers may use different names to refer to components. This document is not intended to distinguish between components with different names rather than different functions. In the following description and in the claims, the terms “comprising,” “including,” and “having” are used in an open-ended manner and should therefore be construed as meaning “including, but not limited to…”. Thus, when the terms “comprising,” “including,” and / or “having” are used in the description of this disclosure, it indicates the presence, but is not limited to, the presence of one or more corresponding features, areas, steps, operations, and / or components.
[0040] It should be understood that when a component is referred to as "coupled to," "connected to," or "conducted to" another component, it can be directly connected to the other component and establish a direct electrical connection, or an intervening component can exist between these components for relay electrical connections (indirect electrical connections). In contrast, when a component is referred to as "directly coupled to," "directly conducted to," or "directly connected to" another component, there is no intervening component.
[0041] Please refer to Figure 1 , Figure 1 This is a schematic diagram of a dynamic random-access memory (DRAM) device according to an embodiment of the present disclosure. In this embodiment, the DRAM device 100 includes a slave DRAM chip 110 and a master DRAM chip 120. The slave DRAM chip 110 includes a slave control circuit 111 and a slave power supply circuit 112. The slave control circuit 111 generates a slave control signal SC1 based on a slave class signal SSL and a setting signal SST. The slave power supply circuit 112 is coupled to the slave control circuit 111. The slave power supply circuit 112 stops generating at least one of the slave voltages VSL1 to VSLn based on the slave control signal SC1.
[0042] In this embodiment, the slave power supply circuit 112 responds to a first value of the slave control signal SC1 by stopping the generation of at least one of the slave voltages VSL1 to VSLn. The slave power supply circuit 112 responds to a second value of the slave control signal SC1 by generating slave voltages VSL1 to VSLn. For example, the first value of the slave control signal SC1 can be a first voltage value, a first current value, a first logic value, or a first duty cycle. The second value of the slave control signal SC1 can be a second voltage value, a second current value, a second logic value, or a second duty cycle. The second value is different from the first value.
[0043] In this embodiment, the master DRAM chip 120 is coupled to the slave DRAM chip 110. The master DRAM chip 120 controls the operation of the slave DRAM chip 110. The master DRAM chip 120 includes a master control circuit 121. The master control circuit 121 generates a master control signal SC2 based on the master category signal SM and the setting signal SST, and controls the master DRAM chip 120 to generate master voltages VM1 to VMn based on the master control signal SC2.
[0044] In this embodiment, the subordinate category signal SSL is the category marker of the subordinate DRAM chip 110. The master category signal SM is the category marker of the master DRAM chip 120. Therefore, the subordinate category signal SSL is different from the master category signal SM. For example, the subordinate category signal SSL has a first value, and the master category signal SM has a second value.
[0045] It is worth mentioning that the slave power supply circuit 112 of the slave DRAM chip 110 stops generating at least one of the slave voltages VSL1 to VSLn in response to the first value of the slave control signal SC1. Therefore, when the DRAM device uses only the master DRAM chip 120, the slave power supply circuit 112 of the slave DRAM chip 110 can be controlled to stop generating at least one of the slave voltages VSL1 to VSLn. In this way, when the DRAM device 100 uses only the master DRAM chip 120, the power consumption of the DRAM device 100 can be reduced.
[0046] For example, the DRAM device 100 of the first product category uses a slave DRAM chip 110 and a master DRAM chip 120. Therefore, the slave DRAM chip 110 generates slave voltages VSL1 to VSLn. The master DRAM chip 120 generates master voltages VM1 to VMn. For example, the DRAM device 100 of the second product category uses only the master DRAM chip 120. Therefore, the master DRAM chip 120 generates master voltages VM1 to VMn. The slave DRAM chip 110 does not generate slave voltages VSL1 to VSLn. Therefore, the power consumption of the DRAM device 100 of the second product category is lower than that of the DRAM device 100 of the first product category.
[0047] In this embodiment, the slave DRAM chip 110 and the master DRAM chip 120 are stacked on top of each other. For example, the slave DRAM chip 110 and the master DRAM chip 120 are stacked to form a three-dimensional (3D) stacked DRAM structure, but this disclosure is not limited thereto.
[0048] For ease of explanation, this embodiment uses a single slave DRAM chip 110 as an example. However, this disclosure is not limited to the number of slave DRAM chips 110. In some embodiments, the number of slave DRAM chips 110 can be multiple.
[0049] In this embodiment, the slave voltages VSL1 to VSLn are the voltage signals required for the operation of the slave DRAM chip 110. The slave voltages VSL1 to VSLn can be one of a bandgap reference voltage, a power supply voltage, and a pumping voltage. The master voltages VM1 to VMn are the voltage signals required for the operation of the master DRAM chip 120. Similarly, the master voltages VM1 to VMn can be one of a bandgap reference voltage, a power supply voltage, and a pumping voltage.
[0050] Please refer to Figure 2 , Figure 2 This is a schematic diagram of a DRAM device according to an embodiment of the present disclosure. In this embodiment, the DRAM device 200 includes a slave DRAM chip 110 and a master DRAM chip 220. The slave DRAM chip 110 includes a slave control circuit 111 and a slave power supply circuit 112. The operation of the slave control circuit 111 and the slave power supply circuit 112 has already been... Figure 1 The embodiments are clearly illustrated and will not be repeated here.
[0051] In this embodiment, the main DRAM chip 220 controls the operation of the slave DRAM chip 110. The main DRAM chip 220 includes a main control circuit 221 and a main power supply circuit 222. The main control circuit 221 generates a main control signal SC2 based on a main category signal SM and a setting signal SST. The main power supply circuit 222 is coupled to the main control circuit 221. The main power supply circuit 222 stops generating at least one of the main voltages VM1 to VMn in response to a first value of the main control signal SC2, and generates the main voltages VM1 to VMn in response to a second value of the main control signal SC2.
[0052] For example, the logic value of the slave category signal SSL is set to a first logic value (i.e., the first value). The logic value of the master category signal SM is set to a second logic value (i.e., the second value). When the logic value of the setting signal SST is the first logic value, the logic value of the slave control signal SC1 is also the first logic value. Therefore, the slave power supply circuit 112 stops generating at least one of the slave voltages VSL1 to VSLn. On the other hand, when the logic value of the setting signal SST is the second logic value, the logic value of the slave control signal SC1 is also the second logic value. Therefore, the slave power supply circuit 112 generates slave voltages VSL1 to VSLn.
[0053] Please refer toFigure 2 , Figure 3 as well as Figure 4 , Figure 3 This is a schematic diagram of a slave control circuit shown in an embodiment of the present disclosure. Figure 4 This is a schematic diagram of a main control circuit according to an embodiment of the present disclosure. In this embodiment, the first logic value is, for example, a high logic value. The second logic value is, for example, a low logic value. The slave control circuit 111 performs a logical AND operation on the slave category signal SSL and the setting signal SST to generate a slave control signal SC1. For example, the slave control circuit 111 includes an inverting NAND gate NAND1 and an inverter INV1. The first input of the NAND gate NAND1 receives the slave category signal SSL. The second input of the NAND gate NAND1 receives the setting signal SST. The input of the inverter INV1 is coupled to the output of the NAND gate NAND1. The output of the inverter INV1 outputs the slave control signal SC1.
[0054] The main control circuit 221 performs a logical AND operation on the main category signal SM and the setting signal SST to generate the main control signal SC2. For example, the main control circuit 221 includes a NAND gate NAND2 and an inverter INV2. The first input of the NAND gate NAND2 receives the main category signal SM. The second input of the NAND gate NAND2 receives the setting signal SST. The input of the inverter INV2 is coupled to the output of the NAND gate NAND2. The output of the inverter INV2 outputs the main control signal SC2.
[0055] It should be noted that the first logic value is, for example, a high logic value. The second logic value is, for example, a low logic value. Therefore, the circuit design of the slave control circuit 111 and the master control circuit 221 are roughly similar. In this way, the complexity of the circuit design of the slave control circuit 111 and the master control circuit 221 can be reduced.
[0056] In some embodiments, the first logic value may be a low logic value. The second logic value may be, for example, a high logic value. Therefore, the slave control circuit 111 may perform a logical inverse OR (NOR) operation on the slave category signal SSL and the set signal SST to generate the slave control signal SC1. The master control circuit 221 may perform a logical NOR operation on the master category signal SM and the set signal SST to generate the master control signal SC2.
[0057] Please refer to Figure 5 , Figure 5This is a schematic diagram of a DRAM device according to an embodiment of the present disclosure. In this embodiment, the DRAM device 300 includes a slave DRAM chip 310, a master DRAM chip 320, and a setting circuit 330. The slave DRAM chip 310 includes a slave control circuit 311 and a slave power supply circuit 312. The master DRAM chip 320 includes a master control circuit 321 and a master power supply circuit 322. The setting circuit 330 is coupled to the slave control circuit 311 and the master control circuit 321. The setting circuit 330 generates a setting signal SST according to the setting operation of the DRAM device 300.
[0058] In this embodiment, the setting circuit 330 generates a setting signal SST based on the setting operation of the slave DRAM chip 310. The logic value of the slave category signal SSL is set to a first logic value (i.e., a first value). The logic value of the master category signal SM is set to a second logic value (i.e., a second value). For example, the first logic value is, for example, a high logic value. The second logic value is, for example, a low logic value. When both the slave DRAM chip 310 and the master DRAM chip 320 are used, the setting circuit 330 generates the setting signal SST based on the setting operation of the DRAM device 300. At this time, the logic value of the setting signal SST is the second logic value. Therefore, the slave control circuit 311 performs a logical AND operation on the slave category signal SSL and the setting signal SST to generate a slave control signal SC1. At this time, the logic value of the slave control signal SC1 is the second logic value. The master control circuit 321 performs a logical AND operation on the master category signal SM and the setting signal SST to generate a master control signal SC2. At this time, the logic value of the master control signal SC2 is the second logic value. Therefore, slave power supply circuit 312 generates slave voltages VSL1 to VSLn. Main power supply circuit 322 generates main voltages VM1 to VMn.
[0059] When the slave DRAM chip 310 is not in use, the setting circuit 330 can generate a setting signal SST according to the setting operation of the DRAM device 300. At this time, the logic value of the setting signal SST is the first logic value. Therefore, the logic value of the slave control signal SC1 is the first logic value. The logic value of the master control signal SC2 is the second logic value. Therefore, the slave power supply circuit 312 does not generate at least one of the slave voltages VSL1 to VSLn. The master power supply circuit 322 still generates the master voltages VM1 to VMn.
[0060] In this embodiment, the setting circuit 330 may be implemented by a fuse circuit, but this disclosure is not limited thereto.
[0061] In this embodiment, the slave control circuit 311 is, for example, a... Figure 3 The slave control circuit 111 is used for implementation. The main control circuit 321 is, for example, implemented by the slave control circuit 111.Figure 4 The main control circuit 221 is used to implement this.
[0062] Please refer to Figure 6 , Figure 6 This is a schematic diagram of a DRAM device according to an embodiment of the present disclosure. In this embodiment, the DRAM device 300A includes a slave DRAM chip 310, a master DRAM chip 320, and a setting circuit 330. Figure 5 The difference is that the setting circuit 330 in this embodiment is set in the slave DRAM chip 310.
[0063] In this embodiment, the setting circuit 330 can provide the setting signal SST to the main control circuit 321 through the connection structure CS. The connection structure CS is, for example, an electrical connection structure including a through silicon via (TSV), but this disclosure is not limited thereto.
[0064] In some embodiments, the DRAM device 300A includes a plurality of slave DRAM chips 310. A setting circuit 330 may be disposed in one of the plurality of slave DRAM chips 310. A setting signal SST may be provided to the master control circuit 321 and the slave control circuits 311 of the other slave DRAM chips 310 via a connection structure CS.
[0065] Please refer to Figure 7 , Figure 7 This is a schematic diagram of a DRAM device according to an embodiment of the present disclosure. In this embodiment, the DRAM device 300B includes a slave DRAM chip 310, a master DRAM chip 320, and a setting circuit 330. Figure 5 The difference is that the setting circuit 330 in this embodiment is located in the main DRAM chip 320. In this embodiment, the setting circuit 330 can provide the setting signal SST to the slave control circuit 311 through the connection structure CS.
[0066] Please refer to Figure 2 as well as Figure 8 , Figure 8This is a schematic diagram of a slave power supply circuit according to an embodiment of the present disclosure. In this embodiment, the slave power supply circuit 112 includes a bandgap reference voltage generation circuit 1121, a voltage regulator 1122, and a charge pump 1123. The bandgap reference voltage generation circuit 1121 is coupled to the slave control circuit 111. The bandgap reference voltage generation circuit 1121 stops generating slave voltages VSL1 and VSL2 in response to a first value of the slave control signal SC1. The bandgap reference voltage generation circuit 1121 generates slave voltages VSL1 and VSL2 in response to a second value of the slave control signal SC1. For example, the slave voltage VSL1 may be the bandgap reference voltage "AnlgRef" required by the slave DRAM chip 110, but the present disclosure is not limited thereto. The slave voltage VSL2 may be the bandgap reference voltage "VCCARef" required by the slave DRAM chip 110, but the present disclosure is not limited thereto. The bandgap reference voltage generation circuit 1121 of the present disclosure can generate at least one bandgap reference voltage, and is not limited to the number of bandgap reference voltages in this embodiment.
[0067] In this embodiment, voltage regulator 1122 is coupled to slave control circuit 111. Voltage regulator 1122 stops generating slave voltages VSL3 and VSL4 in response to a first value of slave control signal SC1. Voltage regulator 1122 generates slave voltages VSL3 and VSL4 in response to a second value of slave control signal SC1. For example, slave voltage VSL3 may be the power supply voltage "VCCA" required by slave DRAM chip 110, but this disclosure is not limited thereto. Slave voltage VSL4 may be the power supply voltage "VDLL" required by slave DRAM chip 110, but this disclosure is not limited thereto. The voltage regulator 1122 of this disclosure can generate at least one power supply voltage, and is not limited to the number of power supply voltages in this embodiment. For example, power supply voltage "VCCA" may be the power supply voltage for the memory cell array of slave DRAM chip 110. Power supply voltage "VDLL" may be the power supply voltage for the delay-line loop (DLL) of slave DRAM chip 110.
[0068] In this embodiment, charge pump 1123 is coupled to slave control circuit 111. Charge pump 1123 stops generating slave voltages VSL5 and VSL6 in response to a first value of slave control signal SC1. Charge pump 1123 generates slave voltages VSL5 and VSL6 in response to a second value of slave control signal SC1. For example, slave voltage VSL5 may be the pump-up voltage "VCCP" required by slave DRAM chip 110, but this disclosure is not limited thereto. Slave voltage VSL6 may be the pump-up voltage "VBB" required by slave DRAM chip 110, but this disclosure is not limited thereto. The charge pump 1123 of this disclosure can generate at least one pump-up voltage, and is not limited to the number of pump-up voltages in this embodiment. For example, pump-up voltage "VCCP" may be the character line voltage for the memory cell array of slave DRAM chip 110. Pump-up voltage "VBB" may be the negative bias voltage of slave DRAM chip 110.
[0069] In some embodiments, the slave power supply circuit 112 may include one of a bandgap reference voltage generation circuit 1121, a voltage regulator 1122, and a charge pump 1123. For example, the slave power supply circuit 112 includes the bandgap reference voltage generation circuit 1121, but this disclosure is not limited thereto. Therefore, the slave power supply circuit 112 stops generating slave voltages VSL1 and VSL2 in response to a first value of the slave control signal SC1.
[0070] In some embodiments, the slave power supply circuit 112 may include two of a bandgap reference voltage generation circuit 1121, a voltage regulator 1122, and a charge pump 1123. For example, the slave power supply circuit 112 includes a bandgap reference voltage generation circuit 1121 and a charge pump 1123, but this disclosure is not limited thereto. Therefore, the slave power supply circuit 112 stops generating slave voltages VSL1, VSL2, VSL5, and VSL6 in response to a first value of the slave control signal SC1.
[0071] Please refer to Figure 2 as well as Figure 9 , Figure 9This is a schematic diagram of a main power supply circuit according to an embodiment of the present disclosure. In this embodiment, the main power supply circuit 222 includes a bandgap reference voltage generation circuit 2221, a voltage regulator 2222, and a charge pump 2223. The bandgap reference voltage generation circuit 2221 is coupled to the main control circuit 221. The bandgap reference voltage generation circuit 2221 stops generating main voltages VM1 and VM2 in response to a first value of the main control signal SC2. The bandgap reference voltage generation circuit 2221 generates main voltages VM1 and VM2 in response to a second value of the main control signal SC2. For example, the main voltage VM1 may be the bandgap reference voltage "AnlgRef" required by the main DRAM chip 220, but the present disclosure is not limited thereto. The main voltage VM2 may be the bandgap reference voltage "VCCARef" required by the main DRAM chip 220, but the present disclosure is not limited thereto. The bandgap reference voltage generation circuit 2221 of the present disclosure can generate at least one bandgap reference voltage, and is not limited to the number of bandgap reference voltages in this embodiment.
[0072] In this embodiment, voltage regulator 2222 is coupled to main control circuit 221. Voltage regulator 2222 stops generating main voltages VM3 and VM4 in response to a first value of main control signal SC2. Voltage regulator 2222 generates main voltages VM3 and VM4 in response to a second value of main control signal SC2. For example, main voltage VM3 may be the power supply voltage "VCCA" required by main DRAM chip 220, but this disclosure is not limited thereto. Main voltage VM4 may be the power supply voltage "VDLL" required by main DRAM chip 220, but this disclosure is not limited thereto. The voltage regulator 2222 of this disclosure can generate at least one power supply voltage, and is not limited to the number of power supply voltages in this embodiment. For example, power supply voltage "VCCA" may be the power supply voltage for the memory cell array of main DRAM chip 220. Power supply voltage "VDLL" may be the power supply voltage for the delay-line loop (DLL) of main DRAM chip 220.
[0073] In this embodiment, charge pump 2223 is coupled to main control circuit 221. Charge pump 2223 stops generating main voltages VM5 and VM6 in response to a first value of main control signal SC2. Charge pump 2223 generates main voltages VM5 and VM6 in response to a second value of main control signal SC2. For example, main voltage VM5 may be the pump-up voltage "VCCP" required by main DRAM chip 220, but this disclosure is not limited thereto. Main voltage VM6 may be the pump-up voltage "VBB" required by main DRAM chip 220, but this disclosure is not limited thereto. The charge pump 2223 of this disclosure can generate at least one pump-up voltage, and is not limited to the number of pump-up voltages in this embodiment. For example, pump-up voltage "VCCP" may be the character line voltage for the memory cell array of main DRAM chip 220. Pump-up voltage "VBB" may be the negative bias voltage of main DRAM chip 220.
[0074] In some embodiments, the main power supply circuit 222 may include one of a bandgap reference voltage generation circuit 2221, a voltage regulator 2222, and a charge pump 2223. For example, the main power supply circuit 222 includes the bandgap reference voltage generation circuit 2221, but this disclosure is not limited thereto. Therefore, the main power supply circuit 222 stops generating main voltages VM1 and VM2 in response to a first value of the main control signal SC2.
[0075] In some embodiments, the main power supply circuit 222 may include two of a bandgap reference voltage generation circuit 2221, a voltage regulator 2222, and a charge pump 2223. For example, the main power supply circuit 222 includes a bandgap reference voltage generation circuit 2221 and a charge pump 2223, but this disclosure is not limited thereto. Therefore, the main power supply circuit 222 stops generating main voltages VM1, VM2, VM5, and VM6 in response to a first value of the main control signal SC2.
[0076] In summary, the DRAM device includes at least one slave DRAM chip and a master DRAM chip. The slave power supply circuit of the slave DRAM chip stops generating at least one of a plurality of slave voltages in response to a first value of the slave control signal. Therefore, when the DRAM device uses only DRAM chips of the first category, the slave power supply circuit of the slave DRAM chip can be controlled to stop generating at least one of the plurality of slave voltages. In this way, the power consumption of the DRAM device can be reduced when using only DRAM chips of the first category.
[0077] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A dynamic random access memory device, comprising: The dynamic random access memory device comprises: at least one slave dynamic random access memory chip, wherein each of the at least one slave dynamic random access memory chip comprises: a slave control circuit configured to generate a slave control signal in accordance with a slave category signal and a setting signal; and a slave power supply circuit coupled to the slave control circuit and configured to stop generating at least one of a plurality of slave voltages in response to a first value of the slave control signal and to generate the plurality of slave voltages in response to a second value of the slave control signal; and a master dynamic random access memory chip coupled to the at least one slave dynamic random access memory chip and configured to control operation of the at least one slave dynamic random access memory chip, wherein the master dynamic random access memory chip comprises: a master control circuit configured to generate a master control signal in accordance with a master category signal and the setting signal and to control the master dynamic random access memory chip to generate a plurality of master voltages in accordance with the master control signal, wherein the slave category signal is different from the master category signal.
2. The dynamic random access memory device of claim 1, wherein: a logic value of the slave category signal is a first logic value, and a logic value of the master category signal is a second logic value.
3. The dynamic random access memory device of claim 2, wherein: when a logic value of the setting signal is the first logic value, a logic value of the slave control signal is the first logic value, and when the logic value of the setting signal is the second logic value, the logic value of the slave control signal is the second logic value.
4. The dynamic random access memory device of claim 3, wherein: the first logic value is a high logic value, the second logic value is a low logic value, and the slave control circuit performs a logical AND operation on the slave category signal and the setting signal to generate the slave control signal.
5. The DRAM device of claim 1, wherein, The dynamic random access memory device further comprises: a setting circuit coupled to the slave control circuit and the master control circuit and configured to generate the setting signal in accordance with a setting operation of the dynamic random access memory device.
6. The DRAM device of claim 5, wherein, The setting circuit is implemented by a fuse circuit.
7. The DRAM device of claim 5, wherein, The setting circuit is disposed in one of the at least one slave dynamic random access memory chip.
8. The DRAM device of claim 5, wherein, The setting circuit is disposed in the master dynamic random access memory chip.
9. The DRAM device of claim 1, wherein, The slave power supply circuit comprises: a bandgap reference voltage generating circuit coupled to the slave control circuit and configured to stop generating at least one bandgap reference voltage among the plurality of slave voltages in response to the first value of the slave control signal and to generate the at least one bandgap reference voltage in response to the second value of the slave control signal.
10. The DRAM device of claim 1, wherein, The slave power supply circuit comprises: a voltage regulator coupled to the slave control circuit and configured to stop generating at least one supply voltage among the plurality of slave voltages in response to the first value of the slave control signal and to generate the at least one supply voltage in response to the second value of the slave control signal.
11. The DRAM device of claim 1, wherein, The slave power supply circuit comprises: A charge pump, coupled to the slave control circuit, configured to stop generating at least one boosted voltage among the plurality of slave voltages in response to a first value of the slave control signal and to generate the at least one boosted voltage in response to a second value of the slave control signal.
12. The DRAM device of claim 1, wherein, The master DRAM chip further includes: A main power supply circuit, coupled to the master control circuit, and configured to stop generating at least one of the plurality of main voltages in response to a first value of the master control signal and to generate the plurality of main voltages in response to a second value of the master control signal.
13. The DRAM device of claim 1, wherein, The at least one slave DRAM chip and the master DRAM chip are stacked with each other.