Managing programming operations in storage device

Abstract

Methods, devices, and systems for managing storage devices are provided. In one aspect, a memory device includes: a memory array including memory blocks; and a peripheral circuit coupled to the memory array. The memory block includes a set of strings. The peripheral circuit is configured to program the memory block. Programming the memory block includes programming a second string and a third string of the set of strings after programming a first string of the set of strings. The first string is between the second string and the third string.

Description

Technical Field

[0001] In general, this disclosure relates to storage devices and storage systems, and more specifically, to managing programming operations within storage devices. Background Technology

[0002] Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. Various operations (e.g., programming (writing) and erasing operations) can be performed on flash memory to change the threshold voltage of each storage cell to a corresponding level. For NAND flash memory, erasing operations can be performed at the block level, programming operations can be performed at the page level, and reading operations can be performed at the page level. Summary of the Invention

[0003] This disclosure relates to methods, apparatus, and systems for managing programming operations in a storage device. One aspect of this disclosure features an example storage device comprising: a storage array including storage blocks; and peripheral circuitry coupled to the storage array. The storage blocks comprise a set of strings. The peripheral circuitry is configured to program the storage blocks. Programming the storage blocks includes: programming a first string in the set of strings, followed by programming a second and a third string in the set of strings. The first string is located between the second and third strings.

[0004] In some implementations, the set of strings comprises N strings sequentially numbered from the first boundary of the storage block to the second boundary of the storage block. Programming the storage block sequentially includes the following operations: [The text abruptly ends here, so the translation stops.] Programming on strings; for the first Programming strings; and programming the first... Programming on strings, where N is an even number.

[0005] In some implementations, the set of strings comprises N strings sequentially numbered from the first boundary of the storage block to the second boundary of the storage block. Programming the storage block sequentially includes the following operations: [The text abruptly ends here, so the translation stops.] Programming on strings; for the first Programming strings; and programming the first... Programming on strings, where N is an odd number.

[0006] In some embodiments, the channel structure of the first string is larger in size than the channel structures of the second and third strings.

[0007] In some implementations, after the second and third strings are programmed, the read window of the first string is narrower than the read window of the second or third string.

[0008] In some embodiments, the storage block includes a first finger, a second finger, and a third finger, each finger including one or more strings from the set of strings. A second finger is located between the first finger and the third finger. The second finger includes the first string, the second string, and the third string.

[0009] In some embodiments, the first finger includes a fourth string, a fifth string, and a sixth string between the fourth and fifth strings. The third finger includes a seventh string, an eighth string, and a ninth string between the seventh and eighth strings. Programming the memory block includes: programming the sixth string after programming the first string; and programming the ninth string after programming the sixth string and before programming the second string.

[0010] In some embodiments, the first finger includes a fourth string, a fifth string, and a sixth string between the fourth and fifth strings. The third finger includes a seventh string, an eighth string, and a ninth string between the seventh and eighth strings. Programming the storage block includes: programming the sixth string; programming the fourth and fifth strings after programming the sixth string and before programming the first string; programming the ninth string after programming the second and third strings; and programming the seventh and eighth strings after programming the ninth string.

[0011] In some implementations, each of the strings in the set includes a channel structure with more than one row. The strings are separated from each other by drain select gate (DSG) cutouts.

[0012] In some implementations, the DSG cutouts are arranged on a single channel structure.

[0013] In some implementations, the DSG cutouts are arranged between two rows of channel structures.

[0014] In some embodiments, the storage device includes a NAND storage device. The storage array includes storage cells stacked in three dimensions.

[0015] Another aspect of this disclosure is a method of operating a storage device. The method includes programming a storage block comprising a set of strings. Programming the storage block includes programming a first string in the set of strings, followed by programming a second and a third string in the set of strings. The first string is arranged between the second and third strings.

[0016] In some implementations, the set of strings comprises N strings sequentially numbered from the first boundary of the storage block to the second boundary of the storage block. Programming the storage block sequentially includes the following operations: [The text abruptly ends here, so the translation stops.] Programming on strings; for the first Programming strings; and programming the first... Programming on strings, where N is an even number.

[0017] In some implementations, the set of strings comprises N strings sequentially numbered from the first boundary of the storage block to the second boundary of the storage block. Programming the storage block sequentially includes the following operations: [The text abruptly ends here, so the translation stops.] Programming on strings; for the first Programming strings; and programming the first... Programming on strings, where N is an odd number.

[0018] In some embodiments, the storage block includes a first finger, a second finger, and a third finger, each finger including one or more strings from the set of strings. A second finger is located between the first finger and the third finger. The second finger includes the first string, the second string, and the third string.

[0019] In some embodiments, the first finger includes a fourth string, a fifth string, and a sixth string between the fourth and fifth strings. The third finger includes a seventh string, an eighth string, and a ninth string between the seventh and eighth strings. Programming the memory block includes: programming the sixth string after programming the first string; and programming the ninth string after programming the sixth string and before programming the second string.

[0020] In some embodiments, the first finger includes a fourth string, a fifth string, and a sixth string between the fourth and fifth strings. The third finger includes a seventh string, an eighth string, and a ninth string between the seventh and eighth strings. Programming the storage block includes: programming the sixth string; programming the fourth and fifth strings after programming the sixth string and before programming the first string; programming the ninth string after programming the second and third strings; and programming the seventh and eighth strings after programming the ninth string.

[0021] In some implementations, each of the strings in the set includes a channel structure with more than one row. The strings are separated from each other by drain select gate (DSG) cutouts.

[0022] Another feature of this disclosure is a storage system. The storage system includes a storage device and a memory controller coupled to and configured to control the storage device. The storage device includes: a storage array including storage blocks, each storage block comprising a set of strings; and peripheral circuitry coupled to the storage array. The peripheral circuitry is configured to program the storage blocks. Programming the storage blocks includes: programming a first string in the set of strings, followed by programming a second and a third string in the set of strings. The first string is located between the second and third strings.

[0023] While generally described as computer-implemented software embodied on a tangible medium for processing and transforming corresponding data, some or all of these aspects may be computer-implemented methods or further included in a corresponding system or other apparatus for performing the functions described. Details of these and other aspects and implementations of this disclosure are set forth in the accompanying drawings and the following description. Other features, objects, and advantages of this disclosure will become apparent from the specification, drawings, and claims. Attached Figure Description

[0024] Figure 1 An example of a schematic diagram of a storage device including peripheral circuitry, according to some aspects of this disclosure.

[0025] Figure 2 An example of a side view of a cross-section of a storage array according to some aspects of this disclosure is shown.

[0026] Figure 3 An example of a schematic diagram showing a storage block including a string, according to some aspects of this disclosure.

[0027] Figure 4An example plan view showing a cross-section of a storage block including a string, according to some aspects of this disclosure.

[0028] Figure 5 Some example peripheral circuits are shown in accordance with some aspects of this disclosure.

[0029] Figure 6A An example process for programming a storage block is shown in accordance with some aspects of this disclosure.

[0030] Figure 6B This illustrates some aspects of the use of this disclosure, such as Figure 6A The process shown describes the reading windows for different strings after programming the storage block.

[0031] Figure 7A Another example process for programming a storage block is shown, based on some aspects of this disclosure.

[0032] Figure 7B This illustrates some aspects of the use of this disclosure, such as Figure 7A The process shown describes the reading windows for different strings after programming the storage block.

[0033] Figures 8 to 9 An example process for programming a storage block including fingers is shown in accordance with some aspects of this disclosure.

[0034] Figure 10 An example flowchart illustrating a method for programming a storage block in a storage device according to some aspects of this disclosure is shown.

[0035] Figure 11 A memory block diagram of an example system having a storage device is shown, according to some aspects of this disclosure.

[0036] Figure 12A A diagram showing a memory card with storage devices according to some aspects of this disclosure is provided.

[0037] Figure 12B A diagram illustrating a solid-state drive (SSD) with a storage device according to some aspects of this disclosure is shown.

[0038] Similar reference numerals and designations in the various figures indicate similar elements. Detailed Implementation

[0039] This specification relates to storage devices, memory systems, and methods for managing programming time in flash memory. In some cases, the storage blocks of a storage device (e.g., NAND flash memory) may include a set of strings. Due to manufacturing processes, strings within the same block may have different levels of quality (or performance). For example, strings closer to the boundaries of the storage block may have lower quality compared to strings farther from the boundaries. Lower quality strings may have narrower read windows compared to higher quality strings.

[0040] When programming a block of memory consisting of a set of strings, strings programmed earlier may be more affected by programming interference than strings programmed later. Therefore, strings programmed earlier may have a narrower read window compared to strings programmed later.

[0041] In some cases, when programming a memory block, a set of strings is programmed sequentially from the first boundary to the second boundary of the block, such that the outer strings (e.g., the strings closest to any boundary of the block and with the lowest quality) are programmed first. Combining the effects of manufacturing processes and programming interference, the read window of the outer strings may be substantially the same as the read window of the inner strings (e.g., the strings farthest from the block boundary and with the highest quality), which can reduce the reliability of the memory device.

[0042] This disclosure provides techniques for programming a memory block comprising a set of strings so that the set of strings can have a more uniform read window. In some embodiments, when programming the memory block, the set of strings is programmed sequentially from the inner string to the outer string, such that the inner strings are programmed first. Therefore, by balancing the effects from manufacturing processes and from programming interference, the difference between the read windows of the outer strings and the read windows of the inner strings can be reduced. The quality of the worst string in the memory block can be improved.

[0043] The described techniques can achieve one or more technical effects. For example, a set of strings of storage blocks can have a more uniform read window, which can increase the reliability of the storage device. As another example, the described techniques do not require changes to the manufacturing process of the storage device and can improve the reliability of the storage device in a cost-effective manner. In some implementations, additional or different technical effects can be achieved.

[0044] Figure 1Example of a schematic circuit diagram of a storage device 100 including peripheral circuitry according to some aspects of this disclosure. Storage device 100 may include a storage array 101 and peripheral circuitry 102 coupled to the storage array 101. Storage array 101 may be a NAND flash memory storage array including NAND storage cells 106 arranged in rows and columns. In some embodiments, the storage cells 106 in the columns (e.g., along the z-direction) of storage array 101 are coupled in series and stacked vertically. The storage cells 106 in the rows (e.g., along the x-direction) of storage array 101 are coupled to and controlled by word lines 118. Each storage cell 106 may maintain a continuous analog value (such as voltage or charge) depending on the number of electrons trapped within the storage layer of storage cell 106. The logic state (i.e., data) of each storage cell 106 may be based on a threshold voltage V of storage cell 106. th The determination is made based on this. Each memory cell 106 can be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0045] In some implementations, each storage cell 106 is a single-level cell (SLC) having two possible storage states capable of storing one bit of data. For example, a first storage state "0" (e.g., erase state) may correspond to a first voltage range, and a second storage state "1" (e.g., program state) may correspond to a second voltage range. In some implementations, to increase storage capacity, each storage cell 106 may be a multi-level cell (MLC), a three-level cell (TLC), or a four-level cell (QLC). An MLC stores 2 bits of data and has four logical states: logic {11, 10, 01, and 00}, i.e., erase state and program states P1, P2, and P3. A TLC stores 3 bits of data and has eight logical states: logic {111, 110, 101, 100, 011, 010, 001, 000}, i.e., erase state and program states P1-P7. QLC stores 4 bits of data and has 16 logical states: logical {1111,1110,1101,1100,1011,1010,1001,1000,0111,0110,0101,0100,0011,0010,0001,0000}, that is, erase state and programming state P1-P15.

[0046] like Figure 1As shown, memory cells 106 in a column of memory array 101 can be coupled at their source terminals to source select gate (SSG) transistors 110 and at their drain terminals to drain select gate (DSG) transistors 112. SSG transistors 110 and 112 can be configured to activate selected columns of memory array 101 during read and program operations. In some embodiments, the sources of SSG transistors in the same memory block 104 are coupled via the same source line 114. The drain of each DSG transistor is coupled to a corresponding bit line 116. From the bit line 116, data can be read from or written to memory cells in a column of memory array 101. In some implementations, each column of the memory array 101 is configured to be selected or deselected by applying a DSG select voltage or a DSG deselect voltage to the gate of the corresponding DSG transistor 112 via one or more DSG lines 113, and / or by applying a select voltage or a deselect voltage to the gate of the corresponding SSG transistor 110 via one or more SSG lines 115.

[0047] In some implementations, adjacent columns of memory cells can be coupled via word lines 118. Word lines 118 can select which row of the memory array 101 is affected by read and program operations. Each word line 118 may include a gate line coupled to a plurality of control gates (gate electrodes) of a plurality of memory cells 106. Figure 1 The example word lines shown include WL0, WL1, WL2, WL3, WL4, and WL5 between DSG line 113 and SSG line 115. In some embodiments, word lines may also include dummy word lines coupled to dummy memory cells.

[0048] In some implementations, the memory array 101 may include a plurality of memory blocks 104. Each memory block 104 may serve as a basic data unit for an erase operation, such that memory cells 106 within the same memory block 104 are erased simultaneously. To erase memory cells 106 in a selected memory block 104, source lines 114 coupled to the selected memory block 104 and unselected memory blocks in the same plane may be biased with an erase voltage. For example, the erase voltage may be a high positive voltage (e.g., 20V or higher). In some implementations, the erase operation may be performed at the half-block level, the quarter-block level, or at a level with any suitable number of memory blocks or a fraction of memory blocks.

[0049] Peripheral circuitry 102 can be coupled to memory array 101 via bit line 116, word line 118, source line 114, SSG line 115, and DSG line 113. Peripheral circuitry 102 may include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of memory array 101 by applying voltage and / or current signals to each target memory cell 106 via bit line 116, word line 118, source line 114, SSG line 115, and DSG line 113, and by sensing voltage and / or current signals from each target memory cell 106. Peripheral circuitry 102 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology.

[0050] Figure 2 An example of a side view of a cross-section of a storage array 101 according to some aspects of this disclosure is shown. Figure 2 As shown, memory cells 106 in columns of memory array 101 can be coupled in series and extend vertically through memory stack 204 above substrate 202. Substrate 202 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0051] The memory stack 204 may include pairs of interleaved gate conductive layers 206 and gate-to-gate dielectric layers 208. The number of pairs of interleaved gate conductive layers 206 and gate-to-gate dielectric layers 208 in the memory stack 204 determines the number of memory cells 106 in the memory array 101. The gate conductive layers 206 may include conductive materials, including but not limited to one or more of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, or silicides. In some embodiments, each gate conductive layer 206 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 206 includes a doped polysilicon layer. Each gate conductive layer 206 may include a control gate surrounding a memory cell 106, a DSG transistor 112, or an SSG transistor 110, and may extend laterally as a DSG line 113 at the top of the memory stack 204, an SSG line 115 at the bottom of the memory stack 204, or a word line 118 between DSG lines 113 and SSG lines 115. The memory stack 204 may include one or more channel structures 210 extending vertically through pairs of interleaved gate conductive layers 206 and gate-to-gate dielectric layers 208. The channel structures 210 may include semiconductor materials, including but not limited to polysilicon. In some embodiments, the channel structures 210 may be cylindrical, such that the cross-section of the channel structures 210 in the xy plane may have a circular shape.

[0052] Figure 3An example illustrating a memory block 104 including strings 310 according to some aspects of this disclosure is shown. In some embodiments, memory block 104 may include a plurality of strings 310. Each string 310 may include memory cells 106 arranged in rows (e.g., coupled to word lines along the x-direction) and columns (e.g., connected in series along the z-direction). DSG transistors 112 of the same string 310 are coupled to the same DSG lines (e.g., ...). Figure 1 DSG line 113). DSG lines of different strings 310 pass through DSG cutouts (e.g., Figure 4 The DSG cutouts (404) are separated from each other, such that each string 310 in memory block 104 can be selected or deselected by applying a selection voltage or a deselection voltage to the corresponding DSG line. For example, the DSG transistors 112 of the first string in memory block 104 are coupled to the first DSG line represented by DSG0; the DSG transistors 112 of the second string in memory block 104 are coupled to the second DSG line represented by DSG1; the DSG transistors 112 of the third string in memory block 104 are coupled to the third DSG line represented by DSG2; and the DSG transistors 112 of the fourth string in memory block 104 are coupled to the fourth DSG line represented by DSG3.

[0053] In some implementations, storage cells 106 in adjacent strings 310 can be coupled via word lines. Figure 4 The example word lines shown include dummy WL, WL1, WL2, WL3, WL4, and WL5. For example, memory cells 106 at the same vertical position (e.g., along the z-direction) in adjacent strings 310 are coupled to the same word line.

[0054] In some implementations, the storage block 104 may be divided into fingers 334a, 334b ​​(collectively referred to as 334). Each finger 334 may include one or more strings 310. The SSG transistors 110 of the strings 310 in the same finger 334 are coupled to the same SSG line (e.g., Figure 1 The SSG line 115 allows each finger 334 to be selected or deselected by applying a selection voltage or a deselection voltage to the corresponding SSG line 115. The SSG lines of the different fingers 334 are connected by SSG notches (e.g., Figure 4 The SSG cutouts 406 are separated from each other. For example, the SSG transistor 110 of string 310 in the first finger 334a is coupled to the first SSG line represented by SSG0; the SSG transistor 110 of string 310 in the second finger 334b ​​is coupled to the second SSG line represented by SSG1.

[0055] In some embodiments, memory block 104 may include a different number of fingers 334, and each finger 334 may include a different number of strings 310. In some embodiments, for example, the strings 310 are not arranged as fingers 334 by coupling the SSG transistors of all strings 310 of memory block 104 to the same SSG line. Therefore, the entire memory block 104 can be selected or deselected by applying a select or deselect voltage to the SSG line in memory block 104.

[0056] Figure 4 An example plan view showing a cross-section of a memory block 104 including string 310 according to some aspects of this disclosure is shown. In some embodiments, memory block 104 is connected to adjacent memory blocks via gate slot structures 402a, 402b. Figure 4 Separation (not shown in the image). For example, gate gap structure 402a can be the first boundary of memory block 104, and gate gap structure 402b can be the second boundary of memory block 104.

[0057] In some embodiments, storage block 104 may include a plurality of strings 310. Each string 310 may include a plurality of channel structures 210 extending vertically to connect a series of storage cells. The channel structures 210 are arranged in rows along the x-direction. In some embodiments, each string 310 may include more than one row of channel structures 210.

[0058] The strings 310 are separated from each other by DSG cutouts 404, which electrically isolate the DSG lines 113 of different strings 310. Therefore, each string 310 can be individually selected or deselected by applying a DSG voltage to the corresponding DSG line 113. In some embodiments, each DSG cutout 404 is arranged between two rows of channel structures 210, such as... Figure 4 As shown. In some other embodiments, each DSG cutout 404 is arranged on a row of channel structures 210, as... Figure 6A As shown.

[0059] In some embodiments, the string 310 may be arranged as fingers 334. The fingers are separated from each other by an SSG cutout 406, which electrically isolates the SSG lines 115 of different fingers 334. Thus, each finger 334 can be individually selected or deselected by applying an SSG voltage to the respective SSG line 115.

[0060] As Figure 4In the example shown, storage block 104 includes three fingers 334 separated by SSG cutout 406, and each finger 334 includes three strings 310 separated by DSG cutout 404. For example, the first finger (finger 1) includes strings 1-3, the second finger (finger 2) includes strings 4-6, and the third finger (finger 3) includes strings 7-9. In some embodiments, storage block 104 may include a different number of fingers 334, and each finger 334 may include a different number of strings 310.

[0061] In some implementations, the storage block 104 is not divided into fingers 334, such that the SSG lines 115 of all strings 310 in the same storage block 104 are electrically connected without having SSG cutouts 406.

[0062] Figure 5 Examples of peripheral circuitry according to some aspects of this disclosure are shown. These example peripheral circuitry include a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic unit 512, a register 515, an interface 516, and a data bus. In some examples, additional peripheral circuitry may also be included. Figure 5 Additional peripheral circuitry not shown.

[0063] Page buffer / sensor amplifier 504 can be configured to read data from memory array 101 and program (write) data to memory array 101 according to control signals from control logic unit 512. In one example, page buffer / sensor amplifier 504 can store one page of programming data (write data) in a page to be programmed into memory array 101. In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 106 coupled to selected word line 118. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 116 representing a data bit stored in memory cell 106 during a read operation and amplify a small voltage swing to a recognizable logic level. Column decoder / bit line driver 506 can be configured to be controlled by control logic unit 512 and select one or more strings 310 by applying a bit line voltage generated from voltage generator 510.

[0064] The row decoder / word line driver 508 can be configured to be controlled by the control logic unit 512 and to select / deselect memory blocks 104 of the memory array 101 and to select / deselect word lines 118 of memory blocks 104. The row decoder / word line driver 508 can also be configured to drive word lines 118 using word line voltages generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive SSG lines 115 and DSG lines 113. As described in detail below, the row decoder / word line driver 508 is configured to apply a programming voltage to the selected word line 118 during programming operations on memory cells 106 coupled to the selected word line 118.

[0065] Voltage generator 510 can be configured to be controlled by control logic unit 512 and generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory array 101.

[0066] Control logic unit 512 can be coupled to each of the aforementioned peripheral circuits and configured to control the operation of each peripheral circuit. Register 515 can be coupled to control logic unit 512 and includes a status register, a command register, and an address register for storing status information, command opcode (OP code), and command address for controlling the operation of each peripheral circuit.

[0067] Interface 516 can be coupled to control logic unit 512 and act as a control buffer to buffer and relay control commands received from the host (not shown) to control logic unit 512, and to buffer and relay status information received from control logic unit 512 to the host. Interface 516 can also be coupled to column decoder / bit line driver 506 via data bus and act as a data input / output (I / O) interface and data buffer to buffer and relay data to and from memory array 101.

[0068] Figure 6A This disclosure illustrates some aspects of storage devices (e.g., Figure 1 and Figure 5 Storage block 600 of storage device 100 (e.g., storage device 100) Figure 1 and Figures 3 to 4 The process of programming the storage block 104. The storage block 600 includes a set of N strings (e.g., from the first boundary 602a (e.g., gate slot structure 402a) to the second boundary 602b (e.g., gate slot structure 402b) of the storage block 600 in order from 1 to N. Figures 3 to 4 The string is 310, where N is a positive integer.

[0069] In some implementations, strings at different locations within storage block 600 can have different levels of quality due to manufacturing processes. For example, strings closer to the boundary 602 of storage block 600 (e.g., string 1 or string N, each referred to as the outer string) and strings further away from the boundary 602 (e.g., when N is even) can have different qualities. Or when N is odd, the string Each of them (referred to as the inner string) has lower quality and is less reliable. For example, the channel structure 210 of the outer string is smaller in size than the channel structure 210 of the inner string (e.g., has a smaller diameter when measured from the same layer), and / or the channel structure 210 of the outer string is not as uniformly circular as the channel structure 210 of the inner string.

[0070] In some implementations, in the storage stack (e.g., storage blocks) Figure 2 In or near the same layer of the storage stack 204, the diameter of the channel structure of the outer string may be smaller than the diameter of the channel structure of the inner string. For example, the diameter of the channel structure of the outer string measured at or near the surface layer of the storage stack may be smaller than the diameter of the channel structure of the inner string measured at or near the surface layer of the storage stack, and / or the diameter of the channel structure of the outer string measured at or near the bottom layer of the storage stack may be smaller than the diameter of the channel structure of the inner string measured at or near the bottom layer of the storage stack.

[0071] In some implementations, the diameter of the channel structure can vary along the vertical direction (e.g., decreasing from the surface layer of the storage stack to the bottom layer). In some cases, when measured at different layers, the diameter of the channel structure of the outer string, measured at or near the surface layer of the storage stack, can be larger than that at or near the bottom layer and / or in the intermediate layers between the surface and bottom layers of the storage stack (e.g., ...). Figure 2 The diameter of the internal string channel structure is measured at the gate conductive layer 206 or the gate-to-gate dielectric layer 208.

[0072] In some implementations, the quality of the channel structure 210 in the memory block decreases from the inner string to the outer string. Lower quality strings can have a narrower read window compared to higher quality strings.

[0073] In some implementations, during the programming of storage block 600, a set of strings is programmed in order from the string closest to one boundary 602 to the string closest to another boundary 602. For example, storage block 600 is programmed according to the order of string 1, string 2, ..., string N-1 and string N (as indicated by arrow 610). In another example, the storage block is programmed by programming string N, string N-1, ..., string 2 and string 1 in sequence.

[0074] In some implementations, strings programmed earlier are more susceptible to programming interference than strings programmed later. For example, the threshold voltage of a memory cell in a programmed string may be shifted due to programming pulses applied to other strings. Consequently, the read window of an earlier programmed string may be narrower than the read window of a later programmed string.

[0075] Figure 6B This illustrates some aspects of the use of this disclosure. Figure 6A The process shown represents a set of read windows for a series of strings after the memory block 600 has been programmed (e.g., programmed from string 1 to string N). The read window of a string represents the sum of voltage ranges in a threshold voltage distribution corresponding to different data states (e.g., erase and programmed states P1-P7 for TLC, or erase and programmed states P1-P15 for QLC). Strings with narrower read windows may be more susceptible to read failures compared to strings with wider read windows.

[0076] like Figure 6B As shown, by comparing memory cells coupled to the same word line, the read window of the outer string (e.g., string 1, which has lower quality and was programmed first) can have the narrowest read window, and the read window of the inner string (e.g., string N / 2, which has higher quality and was programmed in the middle) can have the widest read window. The read windows of other strings, including other outer strings (e.g., string N, which has lower quality and was programmed last), can fall between the narrowest and widest read windows. In some cases, by using... Figure 6A The process shown is used to program storage block 600, and the difference between the narrowest read window and the largest read window may be large.

[0077] Figure 7A This disclosure illustrates some aspects of storage devices (e.g., Figure 1 and Figure 5 Storage block 700 of storage device 100 (e.g., storage device 100) Figure 1 and Figures 3 to 4 Another process involves programming the storage block 104. Similar to... Figure 6A The storage block 700 includes a set of N strings (e.g., from the first boundary 702a (e.g., gate slot structure 402a) to the second boundary 702b (e.g., gate slot structure 402b) of the storage block 700, numbered in order from 1 to N. Figures 3 to 4 The quality of the channel structure 210 in storage block 700 is derived from the internal string (e.g., when N is even, the string 310), where N is a positive integer. Or when N is odd, the string The outer string (e.g., string 1 and string N) is reduced.

[0078] In some implementations, during the programming of memory block 700, a set of strings is programmed in order from the inner string to the outer string. Strings closer to the inner string are programmed earlier than strings farther from the inner string. For example, when N is even, this is done by programming according to the strings... string string The storage block 700 is programmed by programming strings 1, 2, 3, 4, 5, 1, and 6 in the order of ... . For example, if storage block 700 has a set of six strings numbered from 1 to 6 from the first boundary 702a to the second boundary 702b, then storage block 700 can be programmed by programming strings 3, 4, 2, 5, 1, and 6 in the order of ... . When N is odd, the strings are programmed by programming strings in the order of ... string string The storage block 700 can be programmed by programming strings 1, 2, 3, 4, 5, 6, 1, and 7 in sequence. For example, if the storage block 700 has a set of seven strings numbered from 1 to 7 from the first boundary 702a to the second boundary 702b, then the storage block 700 can be programmed by programming strings 4, 3, 5, 2, 6, 1, and 7 in sequence.

[0079] Figure 7B This illustrates some aspects of the use of this disclosure. Figure 7A The process shown is a read window of a set of strings after the storage block 700 is programmed (e.g., programmed from an inner string to an outer string).

[0080] By using Figure 7A The process shown illustrates that higher-quality strings are programmed earlier and therefore more susceptible to programming interference, while lower-quality strings are programmed later and therefore less susceptible to programming interference. Therefore, compared to using... Figure 6A Compared to the scenario where the process shown programs memory block 600, the read window for different strings in memory block 700 is more uniform. For example, as Figure 7B As shown, by comparing memory cells coupled to the same word line, internal strings (e.g., strings...) The reading window of the string and the reading window of the outer string (e.g., string 1 and string N) are close to each other. Figure 6B Compared to the external string reading window in the middle, Figure 7B The read window for the outer string is wider. Therefore, the outer string is less affected by read failures. In some cases, after programming the outer string, the read window for the inner string may become narrower than that for the outer string due to programming interference.

[0081] Figure 8 This disclosure illustrates some aspects of the use of a plurality of fingers (e.g., Figures 3 to 4 Storage block 800 (e.g., finger-like structure 334) Figures 3 to 4 The process of programming the storage block 104.

[0082] The storage block comprises K fingers numbered from 1 to K, from a first boundary 802a (e.g., gate slot structure 402a) to a second boundary 802b (e.g., gate slot structure 402b), where K is a positive integer. The fingers are separated from each other by SSG cutouts 406. Each finger may include M strings numbered from 1 to M, from the first boundary (e.g., SSG cutout 406) to the second boundary (e.g., SSG cutout 406), where M is a positive integer.

[0083] Within each finger, the string further away from the boundary of the finger (e.g., when M is even, the string...) Or when M is odd, the string A string can be an inner string of a finger, and a string closer to the boundary of the finger (e.g., string 1 or string M) can be an outer string of the finger.

[0084] In some implementations, the fingers further away from the boundary 802 of the storage block 800 (e.g., when K is even, the fingers) Or when K is odd, finger-like objects A string in an internal finger (referred to as an internal finger) can be programmed earlier than a string in a finger closer to the boundary 802 of the storage block 800 (e.g., finger 1 or finger K, both referred to as external fingers). In some implementations, such as Figure 9 As shown, the memory block can be programmed by first programming the internal strings of all the fingers and finally programming the external strings of all the fingers.

[0085] For example, at 902, first address the internal fingers (e.g., fingers). The internal string of the internal finger is programmed. At 904, the finger adjacent to the internal finger (e.g., finger) is programmed. Programming is done within the internal string of ). After 904 and before 906, follow the fingering. finger-shaped objects finger-shaped objects The internal strings of each of the other fingers (except finger 1 and finger K) are programmed in the following order. At 906, the internal strings of the external fingers (e.g., finger 1 and finger K) are programmed. After 906 and before 912, the other strings (except the external strings) in each finger are programmed in the same way. At 912, the external strings of the internal fingers are programmed. At 914, the external strings of the fingers adjacent to the internal fingers are programmed. After 914 and before 916, the internal strings of the fingers are programmed in the following order. finger-shaped objects finger-shaped objects The outer strings of each of the other fingers (except finger 1 and finger K) are programmed in sequence. At 916, the outer strings of the outer fingers (e.g., finger 1 and finger K) are programmed last.

[0086] As an example, see reference Figure 4 Storage block 104 can be programmed by programming strings 5, 2, 8, 4, 1, 7, 6, 3, and 9 in sequence.

[0087] In some implementations, the fingers are programmed sequentially from finger 1 to finger K, while the strings within each finger are programmed from the inner string to the outer string. For example, the strings of finger 1 are programmed first sequentially. string string We program the finger K by sequentially programming strings 1, 2, and 3. string string We will use strings 1, 2, and 3 to program the finger K. As an example, refer to... Figure 4 Storage block 104 can be programmed by programming strings 2, 1, 3, 5, 4, 6, 8, 7, and 9 in sequence.

[0088] In some implementations, the fingers are programmed sequentially from the inner fingers to the outer fingers, and the string within each finger is programmed from the first boundary of the finger to the second boundary of the finger. For example, the fingers are first programmed sequentially... Programming strings 1, 2, ..., M-1, M to represent finger-like objects Programming is then performed. Finally, finger 1 and finger K are programmed by sequentially programming strings 1, 2, ..., M-1, M for each of finger 1 and finger K. As an example, refer to... Figure 4Storage block 104 can be programmed by programming strings 5, 4, 6, 2, 1, 3, 8, 7, and 9 in sequence.

[0089] In some implementations, the storage block 800, which includes multiple fingers, can be programmed in different orders or methods, such that at least one string of lower quality can be programmed later than a string of higher quality.

[0090] Figure 10 This disclosure illustrates some aspects of the use of storage devices (e.g., Figure 1 and Figure 5 Storage device 100 Figures 11 to 12B A flowchart of an example process 1000 for programming a storage block in a storage device 1104. Process 1000 can, for example, be based on... Figures 1 to 9 The example techniques described herein are performed by any suitable apparatus or system as described herein. For example, process 1000 may be performed by a storage device (such as...) Figure 1 and Figure 5 The storage device 100, including the storage array 101, performs the operation. The storage array 101 may include one or more storage blocks (e.g., Figure 1 and Figures 3 to 4 Storage block 104 Figure 6A Storage block 600, Figure 7A Storage block 700 or Figure 8 Storage blocks 800), each storage block includes a set of strings (e.g., Figures 3 to 4 (Series 310). In some embodiments, the storage device may also include peripheral circuitry (e.g., Figure 1 (External circuitry 102). The storage device may be a memory system (such as...) Figure 11 It is part of the memory system 1102.

[0091] The operations shown in process 1000 are not exhaustive, and other operations can be performed before, after, or between any of the shown operations. Furthermore, some operations can be performed simultaneously, or in conjunction with... Figure 10 The different sequences of execution are shown. In some implementations, some operations in the operation may be performed by one or more components of the device or system (such as the peripheral circuitry of the storage device).

[0092] At position 1002, for a set of strings in the storage block (e.g., Figure 4 The first string in the string 1-9) (for example, Figure 4 The first string (5) can be programmed. The first string can be further from the boundary of the storage block than the other strings (e.g., ...). Figure 4 The internal string of the gate slot structure 402).

[0093] At position 1004, after programming the first string, the second string (e.g., Figure 4 The first string and the third string (for example, Figure 4 Programming with string 9). The first string is located between the second and third strings. The second and third strings can be outer strings that are closer to the boundaries of the storage block than the other strings.

[0094] In some implementations, the storage block includes a first finger (e.g., Figure 4 finger-like object 1), second finger-like object (e.g., Figure 4 The second finger and the third finger (e.g., Figure 4 The fingers 3), each finger comprising one or more strings. A second finger is located between the first and third fingers. The first finger may include a fourth string (e.g., Figure 4 String 1), the fifth string (for example, Figure 4 The third string) and the sixth string between the fourth and fifth strings (for example, Figure 4 (string 2). The second finger may include the first, second, and third strings. The third finger may include the seventh string (e.g., Figure 4 The seventh string), the eighth string (for example, Figure 4 The string 9) and the ninth string between the seventh and eighth strings (for example, Figure 4 (string 8).

[0095] In some implementations, the storage block can be programmed by programming the first string, then the sixth string, then the ninth string, and then the second string.

[0096] In some implementations, the storage block can be programmed by programming the sixth string, then the fourth and fifth strings, then the first string, then the second and third strings, then the ninth string, and then the seventh and eighth strings.

[0097] In some implementations, the memory block can be programmed in a different order or sequence by programming at least one internal string earlier than at least one external string, for example, to reduce the difference in quality (e.g., the size of the read window) between at least one internal string and at least one external string.

[0098] Figure 11A memory block diagram of an example system 1100 having storage devices according to some aspects of this disclosure is shown. System 1100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage. System 1100 may include a host 1108 and a memory system 1102 having one or more storage devices 1104 and a memory controller 1106. Host 1108 may be a processor (such as a central processing unit (CPU)) or a system-on-a-chip (SoC) (such as an application processor (AP)). Host 1108 may be configured to send data to or receive data from storage device 1104.

[0099] Storage device 1104 can be any storage device disclosed herein. According to some embodiments, memory controller 1106 is coupled to storage device 1104 and host 1108 and configured to control storage device 1104. Memory controller 1106 can manage data stored in storage device 1104 and communicate with host 1108. In some embodiments, memory controller 1106 is designed to operate in a low duty cycle environment, such as a Secure Digital Storage (SD) card, Compact Flash (CF) card, Universal Serial Bus (USB) flash drive, or other media for electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, memory controller 1106 is designed to operate in a high duty cycle environment, such as an SSD or embedded multimedia card (eMMC) used for data storage in mobile devices such as smartphones, tablets, laptops, etc., and enterprise storage arrays. Memory controller 1106 can be configured to control the operation of storage device 1104, such as read, erase, and program operations. The memory controller 1106 may also be configured to manage various functions relating to data stored or to be stored in the storage device 1104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 1106 is also configured to handle error correction codes (ECC) relating to data read from or written to the storage device 1104. Any other suitable functions may also be performed by the memory controller 1106, such as formatting the storage device 1104.

[0100] The memory controller 1106 can communicate with an external device (e.g., host 1108) according to a specific communication protocol. For example, the memory controller 1106 can communicate with the external device through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, FireWire protocol, etc.

[0101] The memory controller 1106 and one or more storage devices 1104 can be integrated into various types of storage devices. For example, the memory controller 1106 and one or more storage devices 1104 can be packaged in a universal flash memory (UFS) package or an eMMC package. Figure 12A In one example shown, the memory controller 1106 and a single storage device 1104 can be integrated into a memory card 1202. The memory card 1202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 1202 may further include a connection between the memory card 1201 and a host (e.g., Figure 11 The memory card connector 1204 is coupled to the host 1108. In such a... Figure 12B In another example shown, the memory controller 1106 and multiple storage devices 1104 can be integrated into the SSD 1206. The SSD 1206 may also include an SSD connector 1208 that connects the SSD 1206 to a host computer (e.g., Figure 11 The SSD 1206 is coupled to the host 1108 in the memory card 1202. In some implementations, the storage capacity and / or operating speed of the SSD 1206 is greater than that of the memory card 1202.

[0102] While this specification contains numerous specific implementation details, these should not be construed as limiting the scope of the claims, but rather as descriptions of features that may be specific to particular embodiments. Certain features described in the context of individual embodiments in this specification may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually in multiple embodiments, or in any sub-combination. Furthermore, although previously described features may be described as functioning in certain combinations and even initially claimed, in some cases, one or more features from a claimed combination may be removed from the combination, and the claimed combination may be for sub-combinations or variations thereof.

[0103] As used in this disclosure, unless the context clearly indicates otherwise, the terms "a" or "the" are used to include one or more. Unless otherwise indicated, the term "or" is used to mean a non-exclusive "or". The phrase "at least one of A and B" has the same meaning as "A, B, or A and B". Furthermore, all wording and terms used in this disclosure unless otherwise defined are for descriptive purposes only and not for limitation. Any use of section headings is intended to aid in reading the document and is not to be construed as restrictive; information relating to a section heading may appear within or outside that particular section.

[0104] As used in this disclosure, the terms “about” or “approximately” may allow for a degree of variability in a value or range, for example, within 10%, 5%, or 1% of the stated value or range.

[0105] As used in this disclosure, the term “substantially” means the majority or most, at least about 50%, 60%, 70%, 80%, 90%, 95%, 96%, 97%, 98%, 99%, 99.5%, 99.9%, 99.99%, or at least about 99.999% or higher.

[0106] Values ​​expressed in range format should be interpreted flexibly to include not only the numerical values ​​explicitly stated as the limits of the range, but also all individual numerical values ​​or subranges contained within that range, as if each numerical value and subrange were explicitly stated. For example, a range of “0.1% to about 5%” or “0.1% to 5%” should be interpreted to include about 0.1% to about 5%, as well as individual values ​​(e.g., 1%, 2%, 3%, and 4%) and subranges (e.g., 0.1% to 0.5%, 1.1% to 2.2%, 3.3% to 4.4%) within the indicated range. Unless otherwise stated, the statement “X to Y” has the same meaning as “about X to about Y”. Similarly, unless otherwise stated, the statement “X, Y, or Z” has the same meaning as “about X, about Y, or about Z”.

[0107] Specific embodiments of the subject matter have been described. Other embodiments, modifications, and substitutions of the described embodiments are within the scope of the appended claims and will be apparent to those skilled in the art. Although operations are depicted in a specific order in the drawings or claims, such operations do not necessarily need to be performed in the specific order shown or in a sequential order, or all shown operations need to be performed (some operations may be considered optional) to achieve the desired result. In some cases, multitasking or parallel processing (or a combination of multitasking and parallel processing) may be advantageous and considered appropriate.

[0108] Furthermore, not all implementations require the separation or integration of the various system modules and components described in the previously described implementations, and the described components and systems can generally be integrated together or packaged into multiple products.

[0109] Therefore, the exemplary embodiments described above do not limit or restrict the scope of this disclosure. Other changes, substitutions, and modifications are possible without departing from the spirit and scope of this disclosure.

Claims

1. A storage device, comprising: A storage array, the storage array comprising storage blocks, wherein the storage blocks comprise a set of strings; and Peripheral circuitry coupled to the memory array and configured to program the memory blocks, wherein programming the memory blocks includes: After programming the first string in the set of strings, the second and third strings in the set of strings are programmed, wherein the first string is between the second string and the third string.

2. The storage device according to claim 1, wherein, The set of strings comprises N strings sequentially numbered from the first boundary to the second boundary of the storage block, wherein programming the storage block sequentially includes the following operations: For the String programming; For the String programming; and For the Programming on strings, where N is an even number.

3. The storage device according to claim 1, wherein, The set of strings comprises N strings sequentially numbered from the first boundary to the second boundary of the storage block, wherein programming the storage block sequentially includes the following operations: For the String programming; For the String programming; and For the Programming on strings, where N is an odd number.

4. The storage device according to any one of claims 1 to 3, wherein, The channel structure of the first string is larger in size than the channel structures of the second and third strings.

5. The storage device according to any one of claims 1 to 4, wherein, After programming the second string and the third string, the reading window of the first string is narrower than the reading window of the second string or the third string.

6. The storage device according to any one of claims 1 to 5, wherein, The storage block includes a first finger, a second finger, and a third finger, each of which includes one or more strings from the set of strings, wherein the second finger is located between the first finger and the third finger. The second finger-like object includes the first string, the second string, and the third string.

7. The storage device according to claim 6, wherein, The first finger-like structure includes a fourth string, a fifth string, and a sixth string between the fourth and fifth strings. The third finger-like structure includes a seventh string, an eighth string, and a ninth string between the seventh and eighth strings. Programming the storage block includes: Programming the sixth string after programming the first string; and The ninth string is programmed after the sixth string is programmed and before the second string is programmed.

8. The storage device according to claim 6, wherein, The first finger-like structure includes a fourth string, a fifth string, and a sixth string between the fourth and fifth strings. The third finger-like structure includes a seventh string, an eighth string, and a ninth string between the seventh and eighth strings. Programming the storage block includes: Program the sixth string; The fourth and fifth strings are programmed after the sixth string is programmed and before the first string is programmed. After programming the second and third strings, the ninth string is programmed; and After programming the ninth string, the seventh and eighth strings are programmed.

9. The storage device according to any one of claims 1 to 8, wherein, Each of the strings in the set includes a channel structure with more than one row, wherein the set of strings is separated from each other by a drain select gate (DSG) cutout.

10. The storage device according to claim 9, wherein, The DSG cut is arranged on a single channel structure.

11. The storage device according to claim 9, wherein, The DSG cut is positioned between the two rows of channel structures.

12. The storage device according to any one of claims 1 to 11, wherein, The storage device includes a NAND storage device, and wherein the storage array includes storage cells stacked in three dimensions.

13. A method for operating a storage device, comprising: Programming a storage block comprising a set of strings, wherein programming the storage block includes: After programming the first string in the set of strings, programming the second and third strings in the set of strings, wherein the first string is arranged between the second string and the third string.

14. The method according to claim 13, wherein, The set of strings comprises N strings sequentially numbered from the first boundary to the second boundary of the storage block, wherein programming the storage block sequentially includes the following operations: For the String programming; For the String programming; and For the Programming on strings, where N is an even number.

15. The method according to claim 13, wherein, The set of strings comprises N strings sequentially numbered from the first boundary to the second boundary of the storage block, wherein programming the storage block sequentially includes the following operations: For the String programming; For the String programming; and For the Programming on strings, where N is an odd number.

16. The method according to any one of claims 13 to 15, wherein, The storage block includes a first finger, a second finger, and a third finger, each of which includes one or more strings from the set of strings, wherein the second finger is located between the first finger and the third finger. The second finger-like object includes the first string, the second string, and the third string.

17. The method according to claim 16, wherein, The first finger-like structure includes a fourth string, a fifth string, and a sixth string between the fourth and fifth strings. The third finger-like structure includes a seventh string, an eighth string, and a ninth string between the seventh and eighth strings. Programming the storage block includes: Programming the sixth string after programming the first string; and The ninth string is programmed after the sixth string is programmed and before the second string is programmed.

18. The method according to claim 16, wherein, The first finger-like structure includes a fourth string, a fifth string, and a sixth string between the fourth and fifth strings. The third finger-like structure includes a seventh string, an eighth string, and a ninth string between the seventh and eighth strings. Programming the storage block includes: Program the sixth string; The fourth and fifth strings are programmed after the sixth string is programmed and before the first string is programmed. After programming the second and third strings, the ninth string is programmed; and After programming the ninth string, the seventh and eighth strings are programmed.

19. The method according to any one of claims 13 to 18, wherein, Each of the strings in the set includes a channel structure with more than one row, wherein the set of strings is separated from each other by a drain select gate (DSG) cutout.

20. A storage system, comprising: Storage device, the storage device comprising: A storage array, the storage array comprising storage blocks, wherein the storage blocks comprise a set of strings; and Peripheral circuitry coupled to the memory array and configured to program the memory blocks, wherein programming the memory blocks includes: After programming the first string in the set of strings, programming the second and third strings in the set of strings, wherein the first string is arranged between the second and third strings; and A memory controller, which is coupled to the storage device and configured to control the storage device.

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