Full-range optimal modulation method for bus capacitor current of three-level inverter

Abstract

The application discloses a full-range optimization modulation method for bus capacitor current of a three-level inverter, which realizes suppression of DC bus capacitor current ripple and prolongs capacitor life by systematically identifying and replacing small vectors in traditional SVPWM which cause large current ripple. The application realizes effective suppression of high-frequency current ripple of the DC bus capacitor in the full modulation range and full power factor angle range of the TNPC three-phase three-level inverter, and can solve the problem from the source of the capacitor current ripple through simple software programming, without introducing additional hardware cost, relaxing the requirements for selection of the DC bus support capacitor, and without the need to select a large-capacity capacitor with large ripple current, so that the volume of the equipment is reduced, the power density is improved, and the predicted life of the DC bus support capacitor is greatly prolonged.

Description

Technical Field

[0001] This invention belongs to the field of power electronics technology, and more specifically, it is a full-range optimized modulation method for high-frequency current ripple of DC bus capacitor in a three-phase three-level inverter. Background Technology

[0002] Three-level NPC inverters are widely used in medium-to-high power applications such as wind power generation, grid-connected photovoltaics, and energy storage systems due to their advantages in output voltage harmonic characteristics and device withstand voltage ratings. These inverters typically require capacitors to stabilize the DC bus voltage and absorb ripple current. Electrolytic capacitors are widely used in DC buses due to their low cost and large capacitance per unit volume. The size, weight, and lifespan of power electronic converters are often limited by the DC bus support capacitors. However, electrolytic capacitors have a high equivalent series resistance (ESR), and high-frequency current ripple flowing through them causes losses, leading to increased core temperature, intensified internal self-heating, and increased ESR. Furthermore, electrolytic capacitors have weak tolerance to electrothermal stress, which accelerates electrolyte evaporation and reduces capacitance. When the capacitance drops to 80% of its current value or the ESR doubles, it is generally considered the end of the electrolytic capacitor's service life. To alleviate the burden of these stresses, large-capacity capacitors with high ripple current tolerance or capacitors in series should be selected, but these solutions increase system size and cost. Therefore, optimizing and suppressing capacitor current ripple is crucial for improving the reliability of DC bus support capacitors, extending capacitor life, reducing equipment size, and increasing equipment power density. However, existing three-phase inverter modulation methods have problems such as being unsuitable for three-level converters, insufficient suppression of capacitor current ripple, and only being able to optimize capacitor current ripple under specific modulation intensities or power factor angles. Summary of the Invention

[0003] To address the aforementioned problems, this invention provides a full-range optimized modulation method for the bus capacitor current of a three-level inverter.

[0004] A method for full-range optimized modulation of the bus capacitor current of a three-level inverter includes the following steps:

[0005] Step A: Determine the quantitative relationship between the DC bus capacitor ripple current and the neutral point current of the three-level inverter, and clarify the core control basis for reducing capacitor ripple current by suppressing the neutral point current ripple; analyze the neutral point current amplitude corresponding to different switching states of the three-level inverter, identify the target small vector that will introduce the maximum phase current to the neutral point and generate the highest neutral point current ripple, and use the target small vector that will introduce the maximum phase current to the neutral point and generate the highest neutral point current ripple as the core object for subsequent virtual small vector replacement and reconstruction;

[0006] Step B: Reconstruct the spatial vector diagram of the three-level inverter by sector, dividing it into six large sectors on average, and then dividing each large sector into four small sectors on average to achieve fine matching of the reference voltage vector. At the same time, determine the sector matching rules to ensure that the desired reference voltage vector can be synthesized linearly and without distortion within the modulation range of 0 to 1.

[0007] Step C: Detect the power factor angle of the three-level inverter, and match the corresponding virtual small vector synthesis method for different power factor angle ranges. The virtual small vector synthesis method satisfies:

[0008] (i) A virtual small vector is synthesized proportionally from pairs of basic voltage vectors that have opposite effects on the neutral point potential; (ii) The synthesized virtual small vector can accurately synthesize the desired reference voltage vector through the volt-second balance principle; (iii) When the synthesized virtual small vector is in effect, the current introduced to the neutral point is the minimum value among the three-phase currents of the current sector, so as to maximize the suppression of the neutral point current ripple.

[0009] Step D: Redesign the vector action sequence based on the virtual small vector synthesis method selected in Step C, and calculate the action time of each basic vector to ensure smooth switching, prevent PN state transitions, and minimize the number of switching operations.

[0010] Step E: Design the driving PWM signals for each power switching device based on the vector action sequence designed in Step D.

[0011] In a further improvement, the quantitative relationship between the DC bus capacitor current and the midpoint current in step A is as follows:

[0012]

[0013] in This represents the capacitor current on the DC bus. This represents the capacitor current under the DC bus. Indicates the midpoint current;

[0014] The target small vector that introduces the maximum phase current to the neutral point and generates the highest midpoint current ripple is the small vector closest to the reference voltage vector in the SVPWM method.

[0015] Further improvements are made, and the specific steps of step B are as follows:

[0016] B1: The spatial vector map is divided into 6 large sectors according to the SVPWM method, and each large sector is reconstructed from 6 small sectors into 4 small sectors; a virtual zero vector is included in a large sector. V VZ First virtual small vector V VS1 Second virtual small vectorV VS2 Virtual vector V VM First virtual large vector V VL1 Second virtual large vector V VL2 ;

[0017] B2: Determine the sector where the reference voltage vector is located, and synthesize the reference voltage vector using three neighboring virtual vectors, as follows: In the first sector A1, use... V VS1 , V VZ , V VM Synthesize reference voltage vector; in the second small sector A2, use V VS2 , V VZ , V VM Synthesize the reference voltage vector; in the third sector A3, use V VS1 , V VM , V VL1 Synthesize the reference voltage vector; in the fourth sector A4, use V VS2 , V VM , V VL2 Synthesize a reference voltage vector.

[0018] Further improvements are made, and the specific steps of step C are as follows:

[0019] Step C1: First virtual small vector V VS1 Second virtual small vector V VS2 Two fundamental voltage vectors with opposite effects on the neutral point potential are used for synthesis. There are three synthesis methods with different contributions to the neutral point current amplitude: method one introduces the neutral point current amplitude as |Ib|, method two introduces the neutral point current amplitude as |Ic|, and method three introduces the neutral point current amplitude as |Ia|. |Ia|, |Ib|, and |Ic| represent the three-phase load current amplitudes at the current moment, respectively; virtual zero vector. V VZ Using the basic zero vector V OOO Virtual vector V VM Using basic vectors VPON First virtual large vector V VL1 Second virtual large vector V VL2 Using basic large vectors V PNN and V PPN ;

[0020] Step C2: Determine the load type and switch the first virtual small vector for different power factor angles. V VS1 Second virtual small vector V VS2 The synthesis strategy ensures that the midpoint current flowing through the neutral point is the minimum value among the three-phase currents of the current sector.

[0021] Further improvements include the following steps in step C2: Vector synthesis method three is used within the power factor angle range of (-5π / 12, -π / 6); vector synthesis method one is used within the power factor angle range of (-π / 6, π / 6); vector synthesis method two is used within the power factor angle range of (π / 6, 5π / 12); and the SVPWM synthesis strategy is used within the power factor angle ranges of (-π / 2, -5π / 12) and (5π / 12, π / 2).

[0022] In vector composition method one:

[0023]

[0024] Where P represents the P state, i.e., the output voltage of the inverter. for state, The voltage at state 0 is the DC power supply voltage; the voltage at state 0 is the inverter output voltage. The N state is the inverter's output voltage; the N state is the inverter's output voltage. for The state;

[0025] This indicates that the three-phase switch state is OOO, meaning that the three phases A, B, and C are connected to the basic zero vector of the neutral point O. This indicates that the three-phase switch is in the PON state, meaning that phase A is connected to the positive busbar P, phase B is connected to the neutral point O, and phase C is connected to the negative busbar N. This indicates that the three-phase switch is in the ONO state, meaning that phases A and C are connected to the neutral point O, and phase B is connected to the negative bus N. This indicates that the three-phase switch is in the state of OPO, meaning that phases A and C are connected to the neutral point O, and phase B is connected to the positive busbar P. This is the basic small vector. The basic large vector representing the three-phase switch state as PNN, i.e., phase A is connected to the positive busbar P, and phases B and C are connected to the negative busbar N; This indicates that the three-phase switch state is PPN, meaning that phases A and B are connected to the positive busbar P, and phase C is connected to the negative busbar N.

[0026] In vector synthesis method two:

[0027]

[0028] in, The three-phase switch state is PNO, which means that phase A is connected to the positive busbar P, phase B is connected to the negative busbar N, and phase C is connected to the neutral point O. This indicates that the three-phase switch is in the OON state, meaning that phases A and B are connected to the neutral point O, and phase C is connected to the negative bus N. The three-phase switch state is PPO, meaning that phases A and B are connected to the positive busbar P, and phase C is connected to the neutral point O. This is the basic small vector.

[0029] Vector composition method three:

[0030]

[0031] in, This indicates that the three-phase switch state is POO, meaning phase A is connected to the positive bus P, and phases B and C are connected to the neutral point O. This is represented by the basic small vector. This indicates that the three-phase switch is in the ONN state, meaning phase A is connected to the neutral point O, and phases B and C are connected to the negative bus N. This is represented by the basic small vector. This indicates that the three-phase switch is in the OPN state, meaning that phase A is connected to the neutral point O, phase B is connected to the positive busbar P, and phase C is connected to the negative busbar N.

[0032] Further improvements are made, and the vector action sequence for the corresponding vector synthesis method one of the four small sectors is as follows:

[0033] A1: [PON]-[OOO]-[ONO]-[OOO]-[PON];

[0034] A2: [PON]-[OOO]-[OPO]-[OOO]-[PON];

[0035] A3: [PON]-[PNN]-[ONO]-[PNN]-[PON];

[0036] A4: [PON]-[PPN]-[OPO]-[PPN]-[PON];

[0037] The vector action sequence of the corresponding vector synthesis method 2 for the four small sectors is as follows:

[0038] A1: [OOO]-[OON]-[PON]-[PNO]-[PON]-[OON]-[OOO];

[0039] A2: [OOO]-[OON]-[PON]-[PPO]-[PON]-[OON]-[OOO];

[0040] A3: [OON]-[PON]-[PNN]-[PNO]-[PNN]-[PON]-[OON];

[0041] A4: [OON]-[PON]-[PPN]-[PPO]-[PPN]-[PON]-[OON];

[0042] The vector action sequence of the corresponding vector synthesis method three for the four small sectors is as follows:

[0043] A1: [OOO]-[POO]-[PON]-[ONN]-[PON]-[POO]-[OOO];

[0044] A2: [OOO]-[POO]-[PON]-[OPN]-[PON]-[POO]-[OOO];

[0045] A3: [POO]-[PON]-[PNN]-[ONN]-[PNN]-[PON]-[POO];

[0046] A4: [POO]-[PON]-[PPN]-[OPN]-[PPN]-[PON]-[POO].

[0047] In a further improvement, in step D, the vector action sequence follows the following principles:

[0048] D1: When the switching state changes from P to N or from N to P, a transition through state O is required to prevent the switch from being shot-through and causing serious damage to the inverter.

[0049] D2: Prioritize vector action sequences with fewer switching operations per phase.

[0050] In a further improvement, in step E, the required modulation wave signal is calculated based on the vector action sequence and the vector action time, and the carrier signal for different segments is calculated. The modulation wave signal and the carrier signal are compared to output a PWM signal to control the switching transistor.

[0051] Further improvements include the three-level inverter being a T-type inverter, an NPC-type inverter, or a hybrid ANPC inverter.

[0052] A further improvement is that the three-level inverter includes a DC power supply U. dc DC power supply U dc The positive terminal is connected to one end of capacitor C1 and the A-side switch S. a1 The drain of the B-switch transistor - S b1 The drain and C switching transistor - S c1 The drain electrode;

[0053] DC power supply U dc The negative terminal of capacitor C2 is connected to the four-phase switching transistor A. a4 The source, B switch, four S b4 The source and C switch of the four S c4 The source of the capacitor; the other end of the upper capacitor C1 and the other end of the lower capacitor C2 are electrically connected to the neutral point O;

[0054] Neutral point O electrical connection A switch transistor two S a2 The drain of the B-switch transistor is S. b2 The drain and C switching transistor 2S c2 The drain electrode;

[0055] A switching transistor 2S a2 The source of the A-type switching transistor is connected to the S-type source. a3 The source of the A-switch transistor is a three-S switch. a3 The drain of the A-S switch is connected to the S-S switch. a1 The source terminal is connected to one end of the A-phase filter inductor, and the other end of the A-phase filter inductor is electrically connected to the A-phase terminal of the load.

[0056] B-switch transistor 2S b2 The source of the B-type switching transistor is connected to the S-type transistor. b3 The source of the B-switch transistor is a three-phase S-type transistor. b3 The drain of the B-side switch is connected to the S-side. b1 The source terminal is connected to one end of the B-phase filter inductor, and the other end of the B-phase filter inductor is electrically connected to the B-phase terminal of the load.

[0057] C-switching transistor 2S C2 The source of the C-type switching transistor is connected to the S-type source. c3 The source of the C-type switching transistor is a three-stage S-type transistor. c3 The drain of the C-switching transistor is connected to the S-S. c1 The source terminal is connected to one end of the C-phase filter inductor, and the other end of the C-phase filter inductor is electrically connected to the C-phase terminal of the load.

[0058] Advantages of this invention:

[0059] 1. This invention achieves effective suppression of high-frequency current ripple of DC bus capacitors across the entire modulation range and power factor angle range of a TNPC-type three-phase three-level inverter by employing different vector synthesis methods according to different load characteristics.

[0060] 2. Due to the significant reduction in ripple current of the DC bus capacitor, the ESR loss and hot spot temperature of the DC bus support capacitor decrease accordingly, which can greatly extend the predicted lifespan of the DC bus support capacitor.

[0061] 3. Due to the significant reduction in the effective value of the DC bus capacitor ripple current, the requirements for selecting DC bus support capacitors are relaxed. It is not necessary to select large-capacity capacitors with large allowable ripple current, which reduces the size of the equipment and increases the power density.

[0062] 4. This invention is a pure software modulation algorithm improvement that solves the problem at its source of capacitor current ripple without increasing hardware costs. It can be implemented in existing digital controllers through software programming, making it economical and efficient. Attached Figure Description

[0063] Figure 1 It is a T-type three-level inverter topology.

[0064] Figure 2 It is a three-level SVPWM space vector diagram.

[0065] Figure 3 This is a schematic diagram of the first major sector division.

[0066] Figure 4a This is a diagram showing the switching state and midpoint current amplitude of a traditional SVPWM circuit.

[0067] Figure 4b This is a diagram showing the switching state and midpoint current amplitude of the present invention.

[0068] Figure 5a This is a schematic diagram of a virtual small vector synthesis method.

[0069] Figure 5b This is a schematic diagram of virtual small vector synthesis method two.

[0070] Figure 5c This is a schematic diagram of virtual small vector synthesis method three.

[0071] Figure 6 This is a comparison chart of the effective values ​​of the current supporting capacitor on the upper DC bus.

[0072] Figure 7a This is a diagram showing the output voltage, output current, and ripple current of the upper DC bus support capacitor for the SVPWM method.

[0073] Figure 7b This is a diagram showing the output voltage, output current, and ripple current of the upper DC bus support capacitor in the method of this invention. Detailed Implementation

[0074] The present invention will now be described in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein and the accompanying drawings are for illustrative purposes only and should not be construed as limiting the present invention.

[0075] Figure 1 A TNPC three-phase three-level inverter was demonstrated, with each phase consisting of four switching transistors. The DC side is powered by a DC power supply. U dc It consists of upper and lower capacitors C1 and C2.

[0076] This invention provides a full-range optimized modulation method for the bus capacitor current of a three-level inverter, comprising:

[0077] X is taken as the common phase for phases A, B, and C, and the potential at point O is taken as the reference potential. When the switching transistor S... X1 S X2 On, switch S X3 S X4 When turned off, the inverter's output voltage for The circuit state at this time is called the P state; when the switching transistor S... X2 S X3 On, switch S X1 S X4 When turned off, the inverter's output voltage When the value is 0, the circuit state at this time is called the O state; when the switching transistor S... X3 S X4 On, switch S X1 S X2 When turned off, the inverter's output voltage for The circuit state at this time is called state N. X = a, b, or c.

[0078] During the zero state, current flows through the neutral point, charging or discharging the DC bus support capacitor, causing a change in the capacitor voltage. Therefore, the ripple current of the DC bus support capacitor is composed of the midpoint current flowing through the neutral point. Caused by.

[0079] According to Kirchhoff's current law, the midpoint current Expressed as:

[0080]

[0081] Indicates the current of the upper capacitor. This represents the current in the lower capacitor. If the capacitances of the upper and lower capacitors are equal, the currents in the upper and lower capacitors can be expressed as:

[0082]

[0083]

[0084] Indicates the voltage across the capacitor. Let represent the voltage across the capacitor. Combining the above equations, we can derive:

[0085]

[0086] As shown in the above formula, the ripple current of the DC bus capacitor is half of the midpoint current, which can be mitigated by suppressing the midpoint current. The fluctuations in the ripple current of the bus capacitor are used to suppress the ripple current. Therefore, the ripple current of the upper and lower DC support capacitors can be reduced by reducing the midpoint ripple current.

[0087] Only in the O state does the phase current flow to the neutral point through the inner switch Sx2 or Sx3 connected to the neutral point. For example, if the switching state is [PON], the b-phase current... I The current in phase b flows towards the neutral point O; conversely, in the [POO] case, the currents in phase b and phase c flow towards the neutral point O. I b + I c flows towards the neutral point. The magnitude of the neutral point current is equal to the sum of the currents in the phase corresponding to the zero state. In a balanced three-phase circuit, the sum of the three-phase currents is zero. Therefore, when two phase currents flow through the neutral point, their sum is equal to the magnitude of the third phase current.

[0088] Table 1 shows the midpoint current amplitude corresponding to each switching state. The resulting midpoint current is the amplitude of the three-phase current or its inverse. Observing all sectors, it can be found that the smallest vector closest to the reference voltage will produce the highest midpoint current.

[0089] Table 1. Midpoint current amplitude under different switching states

[0090]

[0091] Figure 2 This shows a vector diagram of a traditional SVPWM, specifically in the first large sector. The reference voltage vector is synthesized using small vectors [POO], [ONN], [PPO], and [OON], and the introduced midpoint current amplitude is | I a |、| I c | represents the phase with a larger current amplitude, while the B-phase current is within this sector.| I b | is the phase with the smallest amplitude, therefore the small vector synthesis method is reconstructed.

[0092] A virtual miniature vector is synthesized using a medium vector [PON] and a small vector [POP] in equal proportions. V VS1 A virtual small vector is synthesized using a medium vector [PON] and a small vector [NON] in equal proportions. V VS2 , V VS1 and V VS2 The amplitude of the generated midpoint current is | I b |, vector composition is represented as:

[0093]

[0094] Figure 3 The results of the proposed method for sector reconstruction of the spatial vector graph are shown, dividing it into six large sectors, each of which is further divided into four smaller sectors. In the first smaller sector, the method is used... V VS1 , V VZ , V VM Synthesize reference voltage vector; in the second small sector, use V VS2 , V VZ , V VM Synthesize the reference voltage vector; in the third sector, use V VS1 , V VM , V VL1 Synthesize the reference voltage vector; in the fourth sub-sector, use V VS2 , V VM , V VL2 A synthetic reference voltage vector is used to ensure that the proposed algorithm can operate at the modulation level. The required reference voltage is synthesized linearly and without distortion over a wide range from 0 to 1.

[0095] Table 2 shows the virtual vector action time in each small sector, calculated using the volt-second balance principle.

[0096] Table 2. Virtual vector action time of each sub-sector within the first major sector.

[0097]

[0098] Table 3 shows the redesigned vector action sequence based on the proposed optimized modulation scheme.

[0099] Table 3 Vector Action Sequence 1

[0100]

[0101] If the reference voltage vector is located in another large sector, it is mapped to the first large sector to ensure the effectiveness of the proposed method across the entire cycle.

[0102] Figure 4a This demonstrates the switching sequence and neutral point current of the 6th sub-sector within the first large sector when using conventional space vector pulse width modulation (SVPWM). The switching sequence is: [OON] - [PON] - [PPN] - [PPO] - [PPN] - [PON] - [OON]. The magnitude relationship of the three-phase currents in this sector is | I c|>| I a|>| I b|, therefore, when small vectors [PPO] and [OON] are applied, the maximum phase current (corresponding to phase C) flows through the neutral point.

[0103] Figure 4b The diagram illustrates the switching sequence and midpoint current with the same reference voltage vector when using the proposed method. The switching sequence is: [PON] - [PPN] - [OPO] - [PPN] - [PON]. As can be seen from the diagram, the smaller B-phase current replaces the maximum C-phase current, which significantly reduces the midpoint current ripple, thereby suppressing the DC bus capacitor current ripple, and without introducing additional switching operations.

[0104] The above method is called vector synthesis method one. Vector synthesis method one guarantees the power factor angle... This means that it can suppress the midpoint current ripple when carrying a purely resistive load. However, if the power factor angle is not zero, the current leads or lags the voltage, and the relationship between the three-phase currents changes, making it impossible to guarantee that the voltage will not be rippled under a purely resistive load. The amplitude of the B-phase current is the smallest, which makes it impossible to guarantee the suppression effect of the midpoint current ripple. Therefore, it is necessary to extend the above-mentioned bus capacitor current ripple suppression strategy to the full range of power factor angle.

[0105] When phase C is the phase with the smallest current amplitude, the typical operating condition is as follows: At this point, phases A and B in the first major sector have larger current amplitudes. Analogous to the purely resistive operating condition described above, the virtual small vector synthesis method is reconstructed. The definition of vector synthesis method two is as follows:

[0106]

[0107] Figure 5b This demonstrates a second vector composition method, which uses a medium vector [PNO] and a small vector [OON] in equal proportions to create a virtual small vector.V VS1 A virtual mini-vector is synthesized using mini-vectors [PPO] and [OON] in equal proportions. V VS2 , V VS1 and V VS2 The amplitude of the generated midpoint current is | I c At this point, the midpoint current ripple is minimized, thus achieving the purpose of suppressing the DC bus capacitor current ripple.

[0108] Table 4 shows the redesigned vector action sequence under this vector composition method.

[0109] Table 4 Vector Action Sequence 2

[0110]

[0111] When phase A is the phase with the smallest current amplitude, the typical operating condition is as follows: At this point, phases B and C in the first major sector have larger current amplitudes. The virtual small vector synthesis method is reconstructed, and the vector synthesis method three is expressed as follows:

[0112]

[0113] Figure 5c This demonstrates vector composition method three, which uses small vectors [POO] and [ONN] in equal proportions to create virtual small vectors. V VS1 A virtual small vector is synthesized using a medium vector [OPN] and a small vector [POO] in equal proportions. V VS2 , V VS1 and V VS2 The amplitude of the generated midpoint current is | I a At this point, the midpoint current ripple is minimized, thus achieving the purpose of suppressing the DC bus capacitor current ripple.

[0114] Table 5 shows the redesigned vector action sequence under this vector synthesis method.

[0115] Table 5 Vector Action Sequence 3

[0116]

[0117] Figure 6 This paper demonstrates the effective values ​​of DC capacitor ripple current under different power factor angles for traditional SVPWM and various vector synthesis methods. Therefore, for different load types, the optimal vector synthesis method is selected, i.e., [the method is chosen]. Figure 6 By using vector synthesis method three for the lower envelope of the effective value of the capacitor current within the power factor angle range of (-5π / 12, -π / 6); vector synthesis method one for the power factor angle range of (-π / 6, π / 6); vector synthesis method two for the power factor angle range of (π / 6, 5π / 12); and traditional SVPWM for the power factor angle ranges of (-π / 2, -5π / 12) and (5π / 12, π / 2), high-frequency current ripple of the DC bus capacitor can be suppressed across the entire modulation range and the entire power factor angle range.

[0118] Figure 7a The output voltage, output current, and upper DC bus support capacitor ripple current are shown when the power factor angle is 0 using conventional SVPWM. Figure 7b The output voltage, output current, and ripple current of the upper DC bus support capacitor using the proposed method are shown. Comparative observation reveals that the high-frequency current ripple of the DC bus capacitor is significantly suppressed after using the proposed method, reducing its effective value by 64.3%, thus verifying the effectiveness of the proposed method.

[0119] The above is only one specific implementation method of the present invention, but the design concept of the present invention is not limited thereto. Any non-substantial modifications made to the present invention using this concept shall be considered as infringing the protection scope of the present invention.

Claims

1. A method for full-range optimized modulation of the bus capacitor current of a three-level inverter, characterized in that, Includes the following steps: Step A: Determine the quantitative relationship between the DC bus capacitor ripple current and the neutral point current of the three-level inverter, and clarify the core control basis for reducing capacitor ripple current by suppressing the neutral point current ripple; analyze the neutral point current amplitude corresponding to different switching states of the three-level inverter, identify the target small vector that will introduce the maximum phase current to the neutral point and generate the highest neutral point current ripple, and use the target small vector that will introduce the maximum phase current to the neutral point and generate the highest neutral point current ripple as the core object for subsequent virtual small vector replacement and reconstruction; Step B: Reconstruct the spatial vector diagram of the three-level inverter by sector, dividing it into six large sectors on average, and then dividing each large sector into four small sectors on average to achieve fine matching of the reference voltage vector. At the same time, determine the sector matching rules to ensure that the desired reference voltage vector can be synthesized linearly and without distortion within the modulation range of 0 to 1. Step C: Detect the power factor angle of the three-level inverter, and match the corresponding virtual small vector synthesis method for different power factor angle ranges. The virtual small vector synthesis method satisfies: (i) A virtual small vector is synthesized proportionally from pairs of basic voltage vectors that have opposite effects on the neutral point potential; (ii) The synthesized virtual small vector can accurately synthesize the desired reference voltage vector through the volt-second balance principle; (iii) When the synthesized virtual small vector is in effect, the current introduced to the neutral point is the minimum value among the three-phase currents of the current sector, so as to maximize the suppression of the neutral point current ripple. Step D: Redesign the vector action sequence based on the virtual small vector synthesis method selected in Step C, and calculate the action time of each basic vector to ensure smooth switching, prevent PN state transitions, and minimize the number of switching operations. Step E: Design the driving PWM signal for each power switching device based on the vector action sequence designed in Step D; The specific steps of step B are as follows: B1: The spatial vector map is divided into 6 large sectors according to the SVPWM method, and each large sector is reconstructed from 6 small sectors into 4 small sectors; a virtual zero vector is included in a large sector. VVZ First virtual small vector VVS1 Second virtual small vector VVS2 Virtual vector VVM First virtual large vector VVL1 Second virtual large vector VVL2 ; B2: Determine the sector where the reference voltage vector is located, and synthesize the reference voltage vector using three adjacent virtual vectors, as follows: In the first sector A1, use... VVS1 , VVZ , VVM Synthesize reference voltage vector; in the second small sector A2, use VVS2 , VVZ , VVM Synthesize the reference voltage vector; in the third sector A3, use VVS1 , VVM , VVL1 Synthesize the reference voltage vector; in the fourth sector A4, use VVS2 , VVM , VVL2 Synthesized reference voltage vector; The specific steps of step C are as follows: Step C1: First virtual small vector VVS1 Second virtual small vector VVS2 Two fundamental voltage vectors with opposite effects on the neutral point potential are used for synthesis. There are three synthesis methods with different contributions to the neutral point current amplitude: method one introduces the neutral point current amplitude as |Ib|, method two introduces the neutral point current amplitude as |Ic|, and method three introduces the neutral point current amplitude as |Ia|. |Ia|, |Ib|, and |Ic| represent the three-phase load current amplitudes at the current moment, respectively; virtual zero vector. VVZ Using the basic zero vector VOOO Virtual vector VVM Using basic vectors VPON First virtual large vector VVL1 Second virtual large vector VVL2 Using basic large vectors VPNN and VPPN ; Step C2: Determine the load type and switch the first virtual small vector for different power factor angles. VVS1 Second virtual small vector VVS2 The synthesis strategy ensures that the midpoint current flowing through the neutral point is the minimum value among the three-phase currents of the current sector. In step C2, vector synthesis method three is used within the power factor angle range of (-5π / 12, -π / 6); vector synthesis method one is used within the power factor angle range of (-π / 6, π / 6); vector synthesis method two is used within the power factor angle range of (π / 6, 5π / 12); and the SVPWM method synthesis strategy is used within the power factor angle ranges of (-π / 2, -5π / 12) and (5π / 12, π / 2). In vector composition method one: Where P represents the P state, i.e., the output voltage of the inverter. u XO It is 0.5 u dc state, u dc The voltage at state 0 is the DC power supply voltage; the voltage at state 0 is the inverter output voltage. u XO The N state is the inverter's output voltage; the N state is the inverter's output voltage. u XO -0.5 u dc The state; This indicates that the three-phase switch state is OOO, meaning that phases A, B, and C are connected to the basic zero vector of the neutral point (O). The basic neutral vector indicates that the three-phase switch is in the PON state, that is, phase A is connected to the positive bus (P), phase B is connected to the neutral point (O), and phase C is connected to the negative bus (N). The basic small vector indicates that the three-phase switch is in the ONO state, that is, phases A and C are connected to the neutral point (O) and phase B is connected to the negative bus (N); The basic small vector indicates that the three-phase switch is in the state of OPO, that is, phases A and C are connected to the neutral point (O) and phase B is connected to the positive bus (P). The basic large vector representing the three-phase switch state as PNN, that is, phase A is connected to the positive bus (P), and phases B and C are connected to the negative bus (N); The basic large vector indicates that the three-phase switch state is PPN, that is, phases A and B are connected to the positive bus (P) and phase C is connected to the negative bus (N); In vector composition method two: in, The three-phase switch state is PNO, which means that phase A is connected to the positive bus (P), phase B is connected to the negative bus (N), and phase C is connected to the neutral point (O). The basic small vector indicates that the three-phase switch is in the OON state, that is, phases A and B are connected to the neutral point (O) and phase C is connected to the negative bus (N); The three-phase switch state is PPO, meaning that phases A and B are connected to the positive bus (P) and phase C is connected to the neutral point (O). In vector composition method three: in, The three-phase switch state is represented by POO, meaning phase A is connected to the positive bus (P), and phases B and C are connected to the neutral point (O). The basic small vector indicates that the three-phase switch is in the ONN state, meaning that phase A is connected to the neutral point (O), and phases B and C are connected to the negative bus (N). The basic neutral vector indicates that the three-phase switch is in the OPN state, meaning that phase A is connected to the neutral point (O), phase B is connected to the positive bus (P), and phase C is connected to the negative bus (N).

2. The full-range optimized modulation method for the bus capacitor current of a three-level inverter as described in claim 1, characterized in that, In step A, the quantitative relationship between the DC bus capacitor current and the midpoint current is as follows: in iC1 This represents the capacitor current on the DC bus. iC2 This represents the capacitor current under the DC bus. inp Indicates the midpoint current; The target small vector that introduces the maximum phase current to the neutral point and generates the highest midpoint current ripple is the small vector closest to the reference voltage vector in the SVPWM method.

3. The full-range optimized modulation method for the bus capacitor current of a three-level inverter as described in claim 1, characterized in that, The vector action sequence of the corresponding vector synthesis method 1 for the four small sectors is as follows: A1: [PON]-[OOO]-[ONO]-[OOO]-[PON]; A2: [PON]-[OOO]-[OPO]-[OOO]-[PON]; A3: [PON]-[PNN]-[ONO]-[PNN]-[PON]; A4: [PON]-[PPN]-[OPO]-[PPN]-[PON]; The vector action sequence of the corresponding vector synthesis method 2 for the four small sectors is as follows: A1: [OOO]-[OON]-[PON]-[PNO]-[PON]-[OON]-[OOO]; A2: [OOO]-[OON]-[PON]-[PPO]-[PON]-[OON]-[OOO]; A3: [OON]-[PON]-[PNN]-[PNO]-[PNN]-[PON]-[OON]; A4: [OON]-[PON]-[PPN]-[PPO]-[PPN]-[PON]-[OON]; The vector action sequence of the corresponding vector synthesis method three for the four small sectors is as follows: A1: [OOO]-[POO]-[PON]-[ONN]-[PON]-[POO]-[OOO]; A2: [OOO]-[POO]-[PON]-[OPN]-[PON]-[POO]-[OOO]; A3: [POO]-[PON]-[PNN]-[ONN]-[PNN]-[PON]-[POO]; A4: [POO]-[PON]-[PPN]-[OPN]-[PPN]-[PON]-[POO].

4. The full-range optimized modulation method for the bus capacitor current of a three-level inverter as described in claim 1, characterized in that, In step D, the vector action sequence follows the following principles: D1: When the switching state changes from P to N or from N to P, a transition through state O is required to prevent the switch from being shot-through and causing serious damage to the inverter. D2: Prioritize vector action sequences with fewer switching operations per phase.

5. The full-range optimized modulation method for the bus capacitor current of a three-level inverter as described in claim 1, characterized in that, In step E, the required modulation wave signal is calculated based on the vector action sequence and vector action time, and the carrier signal for different segments is calculated. The modulation wave signal and the carrier signal are compared to output a PWM signal to control the switching transistor.

6. The full-range optimized modulation method for the bus capacitor current of a three-level inverter as described in claim 1, characterized in that, The three-level inverter is a T-type inverter, an NPC-type inverter, or a hybrid ANPC inverter.

7. The full-range optimized modulation method for the bus capacitor current of a three-level inverter as described in claim 6, characterized in that, The three-level inverter is a T-type inverter, which includes a DC power supply (U... dc DC power supply (U) dc The positive terminal is connected to one end of capacitor (C1) and the first terminal of switch A (S). a1 The drain of the B-switch transistor (S) b1 The drain of the C-type switching transistor (S) c1 The drain electrode of ) DC power supply (U dc The negative terminal of the capacitor (C2) is connected to one end of the lower capacitor and the fourth terminal of the A-switch transistor (S). a4 The source of the B-switch transistor (S) b4 The source and C-switch of the four (S) transistors c4 The source of the capacitor; the other end of the upper capacitor (C1) and the other end of the lower capacitor (C2) are electrically connected to the neutral point (O); Neutral point (O) electrical connection A switch transistor two (S) a2 The drain of the B-switch transistor (S) b2 The drain of the C-type switching transistor (S) c2 The drain electrode of ) A switching transistor two (S) a2 The source of the transistor is connected to the A-side switch (S). a3 The source of the A switch transistor (S) a3 The drain of the switch transistor A is electrically connected to the drain of the transistor S. a1 The source of the inductor is connected to one end of the A-phase filter inductor, and the other end of the A-phase filter inductor is electrically connected to the A-phase terminal of the load. B-switch transistor two (S) b2 The source of the transistor is connected to the B-side switch (S). b3 The source of the B-switch transistor (S) b3 The drain of the B-side switch is electrically connected to the S-side switch. b1 The source of the inductor is connected to one end of the B-phase filter inductor, and the other end of the B-phase filter inductor is electrically connected to the B-phase terminal of the load. C-switching transistor two (S) C2 The source of the transistor is connected to the C-type switching transistor (S). c3 The source of the C-type switching transistor (S) c3 The drain of the C-type switching transistor is connected to the S-type transistor. c1 The source of the C-phase filter inductor is connected to one end of the C-phase filter inductor, and the other end of the C-phase filter inductor is electrically connected to the C-phase terminal of the load.

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