Bulk acoustic wave resonator packaging structure and preparation method thereof

Abstract

The invention discloses a bulk acoustic wave resonator packaging structure and a preparation method thereof. The method comprises the following steps: providing a substrate; depositing a barrier layer on the substrate; sequentially manufacturing a lower electrode layer, a piezoelectric layer and an upper electrode layer on the barrier layer, and forming a resonant structure corresponding to the lower electrode layer, the piezoelectric layer and the upper electrode layer; and packaging one side, far away from the substrate, of the resonant structure by using the substrate.

Description

Technical Field

[0001] This application relates to the field of bulk acoustic wave device technology, and in particular to a bulk acoustic wave resonator packaging structure and its fabrication method. Background Technology

[0002] Bulk Acoustic Wave (BAW) resonators, as high-performance radio frequency front-end devices, are core components for high-frequency signal filtering and selection in modern mobile communications, IoT, and other devices. With the evolution of 5G / 6G technologies, more stringent requirements have been placed on the performance, cost, size, and reliability of BAW resonators. Therefore, optimizing their manufacturing processes and structural designs has become crucial for technological competition.

[0003] Figure 1 A schematic diagram of a bulk acoustic resonator in the prior art is shown. (Reference) Figure 1 As shown, the bulk acoustic wave resonator includes an upper electrode, a piezoelectric layer, a lower electrode, a barrier layer, and other functional layers such as a sacrificial layer. In conventional fabrication processes, a carrier wafer is first used as a temporary support structure via bonding, followed by the sequential deposition of the upper electrode, piezoelectric layer, and lower electrode. Then, the barrier layer and other functional layers are deposited. Further, after the device wafer is fabricated, the entire structure is flipped. Finally, the bonded carrier wafer is removed. However, the above methods are complex and costly.

[0004] Furthermore, the high temperatures required for depositing the barrier layer introduce thermal stress, causing pressure variations in the upper electrode, lower electrode, and piezoelectric layer. Therefore, even with the fabrication sequence of depositing the upper electrode, piezoelectric layer, and lower electrode first, followed by the barrier layer, this additional thermal stress can lead to thin-film interface failure in the bulk acoustic wave resonator, resulting in leakage of the sacrificial layer and consequently affecting the reliability of the bulk acoustic wave resonator.

[0005] Furthermore, to form the cavity required for resonance, conventional designs typically place the release holes used for etching the sacrificial layer on the front side of the wafer (i.e., the active layer side). After the cavity is formed, these front-side release holes require complex secondary sealing using a capped wafer (CAPwafer), which is costly and may also become a weak point for leakage, compromising the long-term reliability of the bulk acoustic wave resonator.

[0006] There is currently no effective solution to the technical problems of high manufacturing cost and insufficient reliability of bulk acoustic resonators in the existing technology. Summary of the Invention

[0007] This disclosure provides a bulk acoustic wave resonator packaging structure and its fabrication method, which at least solves the technical problems of high fabrication cost and insufficient reliability of bulk acoustic wave resonators in the prior art.

[0008] According to one aspect of this application, a method for fabricating a bulk acoustic wave resonator packaging structure is provided, comprising: providing a substrate; depositing a barrier layer on the substrate; sequentially fabricating a lower electrode layer, a piezoelectric layer, and an upper electrode layer on the barrier layer, and forming a resonant structure corresponding to the lower electrode layer, the piezoelectric layer, and the upper electrode layer; and encapsulating the side of the resonant structure away from the substrate using a substrate.

[0009] According to another aspect of this application, a bulk acoustic wave resonator packaging structure is provided, comprising: a substrate, a barrier layer deposited on the substrate, and a lower electrode layer, a piezoelectric layer, and an upper electrode layer formed on the barrier layer. The lower electrode layer, the piezoelectric layer, and the upper electrode layer form a corresponding resonant structure; and further comprising: a substrate for packaging the side of the resonant structure away from the substrate.

[0010] To address the problems existing in the prior art, this application provides a method for fabricating a bulk acoustic wave (BAW) resonator packaging structure. In fabricating the BAW resonator, a barrier layer is first deposited on a substrate, and then a lower electrode layer, a piezoelectric layer, and a top electrode layer are sequentially fabricated on the barrier layer to form a resonant structure corresponding to the lower electrode layer, piezoelectric layer, and top electrode layer. Therefore, unlike the prior art where the top electrode, piezoelectric layer, and lower electrode are deposited first, followed by the barrier layer, and the additional thermal stress may lead to thin-film interface failure of the BAW resonator, this application deposits the barrier layer first, followed by the upper electrode layer, piezoelectric layer, and lower electrode layer. Therefore, even if the barrier layer needs to be deposited at a higher temperature, the thermal stress will not affect the undeposited upper electrode layer, piezoelectric layer, and lower electrode layer. That is, the above method can avoid the influence of thermal stress introduced by the high temperature during barrier layer deposition on the resonant structure. This prevents leakage caused by thin-film interface failure in the BAW resonator, thereby improving the reliability of the BAW resonator packaging structure.

[0011] Furthermore, unlike existing technologies that require first using a carrier wafer as a temporary support structure through a bonding process, then flipping the entire structure after the device wafer is fabricated, and finally removing the bonded carrier wafer, this application eliminates the need to bond with a temporary carrier wafer before fabricating the resonant structure. In other words, the above method avoids the step of flipping the entire structure and removing the carrier wafer after fabrication. This simplifies the fabrication process and reduces fabrication costs.

[0012] In summary, the fabrication method provided in this application can improve the reliability of the bulk acoustic wave resonator packaging structure and reduce the fabrication cost. This solves the technical problems of high fabrication cost and insufficient reliability of existing bulk acoustic wave resonators.

[0013] The above and other objects, advantages and features of this application will become more apparent to those skilled in the art from the following detailed description of specific embodiments of this application in conjunction with the accompanying drawings. Attached Figure Description

[0014] The following sections will describe some specific embodiments of this application in detail by way of example and not limitation, with reference to the accompanying drawings. The same reference numerals in the drawings denote the same or similar parts or components. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings: Figure 1 This is a schematic diagram of the structure of a bulk acoustic resonator in the prior art; Figure 2 This is a flowchart illustrating the fabrication method of the bulk acoustic wave resonator packaging structure according to the embodiments of this application; Figure 3 This is a schematic diagram of the bulk acoustic wave resonator packaging structure according to the embodiments of this application; Figure 4 This is a schematic diagram of the substrate and dielectric layer structure according to the embodiments of this application; Figure 5 This is a schematic diagram of the structure of the filling layer according to the embodiments of this application; Figure 6 This is a schematic diagram of the barrier layer structure according to an embodiment of this application; Figure 7 This is a schematic diagram of the sacrificial layer structure according to an embodiment of this application; Figure 8A This is a schematic diagram of the structure of the lower electrode layer according to an embodiment of this application; Figure 8B This is a schematic diagram of the lower electrode layer of the ramp structure according to the embodiments of this application; Figure 9 This is a schematic diagram of the structure of the piezoelectric layer and the upper electrode layer according to the embodiments of this application; Figure 10 This is a schematic diagram of the structure of the fourth region according to the embodiments of this application; Figure 11 This is a schematic diagram of the structure of the fifth region according to an embodiment of this application; Figure 12 This is a schematic diagram of the structure of the release hole according to an embodiment of this application; Figure 13 This is a schematic diagram of the resonant cavity structure according to an embodiment of this application; Figure 14 This is a schematic diagram of the structure of the first pad and the second pad according to the embodiments of this application; Figure 15 This is a schematic diagram of the structure of the first and second solder balls according to embodiments of this application; and Figure 16 This is a schematic diagram of the bulk acoustic wave resonator packaging structure with a ramp structure in the lower electrode layer according to the embodiments of this application. Detailed Implementation

[0015] It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0016] To enable those skilled in the art to better understand the present disclosure, the technical solutions of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present disclosure, and not all embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present disclosure.

[0017] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0018] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0019] Figure 2 A flowchart illustrating a method for fabricating a bulk acoustic wave resonator packaging structure according to an embodiment of this application is shown. Figure 3 A schematic diagram of the bulk acoustic wave resonator packaging structure according to an embodiment of this application is shown. (Reference) Figure 2 and Figure 3 As shown, according to one aspect of this application, a method for fabricating a bulk acoustic wave resonator packaging structure is provided, comprising: S202: Provides a substrate; S204: Deposit a barrier layer on the substrate; S206: A lower electrode layer, a piezoelectric layer, and an upper electrode layer are sequentially fabricated on the barrier layer, forming a resonant structure corresponding to the lower electrode layer, the piezoelectric layer, and the upper electrode layer; and S208: The side of the resonant structure furthest from the substrate is encapsulated using a substrate.

[0020] Specifically, in the fabrication process of the bulk acoustic wave resonator packaging structure, firstly, a substrate 100 is provided as a support for the bulk acoustic wave resonator (S202).

[0021] Then, a barrier layer 200 is deposited on the substrate 100 (S204).

[0022] Furthermore, on the barrier layer 200, a lower electrode layer 300, a piezoelectric layer 400, and an upper electrode layer 500 are sequentially fabricated from bottom to top, and a resonant structure corresponding to the lower electrode layer 300, the piezoelectric layer 400, and the upper electrode layer 500 is formed (S206). The resonant structure includes a working region corresponding to the overlapping region of the lower electrode layer 300, the piezoelectric layer 400, and the upper electrode layer 500, and a non-working region surrounding the working region.

[0023] Finally, the side of the resonant structure away from the substrate 100 is encapsulated using the substrate 610 to form a bulk acoustic wave resonator encapsulation structure (S208).

[0024] Therefore, unlike existing technologies that deposit the upper electrode, piezoelectric layer, and lower electrode first, followed by the barrier layer, where additional thermal stress may lead to thin-film interface failure of the bulk acoustic wave resonator, this application deposits the barrier layer 200 first, followed by the lower electrode layer 300, piezoelectric layer 400, and upper electrode layer 500. Therefore, even if the barrier layer 200 needs to be deposited at a higher temperature, the thermal stress will not affect the undeposited lower electrode layer 300, piezoelectric layer 400, and upper electrode layer 500. In other words, this method avoids the impact of thermal stress introduced by the high temperature during barrier layer 200 deposition on the resonant structure. This prevents leakage caused by thin-film interface failure in the bulk acoustic wave resonator, thereby improving the reliability of the bulk acoustic wave resonator packaging structure.

[0025] As described in the background section, bulk acoustic wave (BAW) resonators, as high-performance radio frequency front-end devices, are core components for high-frequency signal filtering and selection in modern mobile communications, IoT, and other devices. With the evolution of 5G / 6G technologies, more stringent requirements have been placed on the performance, cost, size, and reliability of BAW resonators, making the optimization of their manufacturing processes and structural design crucial for technological competition. A BAW resonator includes an upper electrode, a piezoelectric layer, a lower electrode, a barrier layer, and other functional layers such as a sacrificial layer. In traditional fabrication processes, a carrier wafer is first bonded as a temporary support structure, followed by the sequential deposition of the upper electrode, piezoelectric layer, and lower electrode. Then, the barrier layer and other functional layers are deposited. Further, after the device wafer is fabricated, the entire structure is flipped. Finally, the bonded carrier wafer is removed. However, the above methods are complex and costly.

[0026] Furthermore, the high temperatures required for depositing the barrier layer introduce thermal stress, causing pressure variations in the upper electrode, lower electrode, and piezoelectric layer. Therefore, even with the fabrication sequence of depositing the upper electrode, piezoelectric layer, and lower electrode first, followed by the barrier layer, this additional thermal stress can lead to thin-film interface failure in the bulk acoustic wave resonator, resulting in leakage of the sacrificial layer and consequently affecting the reliability of the bulk acoustic wave resonator.

[0027] In view of this, this application provides a method for fabricating a bulk acoustic wave (BAW) resonator packaging structure. When fabricating the BAW resonator, a barrier layer is first deposited on a substrate, and then a lower electrode layer, a piezoelectric layer, and an upper electrode layer are sequentially fabricated on the barrier layer to form a resonant structure corresponding to the lower electrode layer, piezoelectric layer, and upper electrode layer. Therefore, unlike the prior art where the upper electrode, piezoelectric layer, and lower electrode are deposited first, followed by the barrier layer, and the additional thermal stress may lead to thin-film interface failure of the BAW resonator, this application deposits the barrier layer first, followed by the upper electrode layer, piezoelectric layer, and lower electrode layer. Therefore, even if the barrier layer needs to be deposited at a higher temperature, the thermal stress will not affect the undeposited upper electrode layer, piezoelectric layer, and lower electrode layer. That is, the above method can avoid the influence of thermal stress introduced by the high temperature during barrier layer deposition on the resonant structure. This can prevent leakage caused by thin-film interface failure in the BAW resonator, thereby improving the reliability of the BAW resonator packaging structure.

[0028] Optionally, the operation of depositing a barrier layer 200 on the substrate 100 includes: sequentially depositing a dielectric layer 700 and a filler layer 800 on the substrate 100; etching the filler layer 800 to form a first region 810 for exposing the dielectric layer 700; and depositing the barrier layer 200 on the first region 810 and the filler layer 800 to form a second region 210, wherein the second region 210 corresponds to the position of the first region 810.

[0029] Specifically, Figure 4 A schematic diagram of the substrate and dielectric layer according to an embodiment of this application is shown. Figure 5 A schematic diagram of the structure of the filling layer according to an embodiment of this application is shown. Figure 6 A schematic diagram of the barrier layer according to an embodiment of this application is shown. (Reference) Figures 4-6 As shown, firstly, a dielectric layer 700 is deposited on the substrate 100.

[0030] The dielectric layer 700 can be made of materials such as undoped silicate glass (USG) or phosphosilicate glass (PSG) to balance the thermal stress generated during the deposition of the barrier layer 200. The dielectric layer 700 can be formed using processes such as physical vapor deposition (PVD) or chemical vapor deposition (CVD). Furthermore, the dielectric layer 700 can be replaced with a trap-rich (TR) layer to improve the performance of the bulk acoustic wave resonator.

[0031] Then, a filler layer 800 is deposited on the dielectric layer 700, and the filler layer 800 is etched to form a first region 810 for exposing the dielectric layer 700. The material of the filler layer 800 can be, for example, undoped silicate glass (USG) or phosphosilicate glass (PSG). The filler layer 800 can be formed by, for example, physical vapor deposition (PVD) or chemical vapor deposition (CVD). Furthermore, the thickness of the filler layer 800 is 500 nm to 5000 nm.

[0032] Finally, a barrier layer 200 is deposited on the first region 810 and the filler layer 800 to form a second region 210 corresponding to the position of the first region 810. The barrier layer 200 is made of a material resistant to hydrofluoric acid or buffered oxide etchant (BOE), such as silicon nitride (SiN) or polysilicon (poly-Si). The barrier layer 200 can be formed, for example, by low-pressure chemical vapor deposition (LPCVD). Furthermore, the thickness of the barrier layer 200 is 100 nm to 2000 nm, and the thickness uniformity is less than 5%.

[0033] Optionally, it also includes: depositing a sacrificial layer 900 within the second region 210.

[0034] Specifically, Figure 7 A schematic diagram of the sacrificial layer structure according to an embodiment of this application is shown. (Reference) Figure 7As shown, a sacrificial layer 900 is deposited in the second region 210, and the sacrificial layer 900 is planarized by a chemical mechanical polishing (CMP) process. The material of the sacrificial layer 900 can be, for example, undoped silicate glass (USG) or phosphosilicate glass (PSG). Furthermore, the thickness of the sacrificial layer 900 is 1.1 to 2 times the thickness of the filler layer 800, and the thickness uniformity is less than 5%.

[0035] Optionally, the operation of sequentially fabricating a lower electrode layer 300, a piezoelectric layer 400, and an upper electrode layer 500 on the barrier layer 200 includes: depositing and etching the lower electrode layer 300 on the barrier layer 200 and the sacrificial layer 900 to form a third region 310 for exposing the barrier layer 200 and the sacrificial layer 900; depositing the piezoelectric layer 400 on the third region 310 and the lower electrode layer 300; depositing and etching the upper electrode layer 500 on the piezoelectric layer 400 to form a fourth region 510 for exposing the piezoelectric layer 400, wherein the third region 310 and the fourth region 510 are formed on both sides of the sacrificial layer 900; and etching the piezoelectric layer 400 at the corresponding position of the fourth region 510 to form a fifth region 410 for exposing the lower electrode layer 300.

[0036] Specifically, Figure 8A A schematic diagram of the structure of the lower electrode layer according to an embodiment of this application is shown. Figure 8B A schematic diagram of the lower electrode layer of the ramp structure according to an embodiment of this application is shown. Figure 9 A schematic diagram of the structure of the piezoelectric layer and the upper electrode layer according to an embodiment of this application is shown. Figure 10 A schematic diagram of the structure of the fourth region according to an embodiment of this application is shown. Figure 11 A schematic diagram of the structure of the fifth region according to an embodiment of this application is shown.

[0037] refer to Figure 8A as well as Figures 9-11 As shown, firstly, a lower electrode layer 300 is deposited on the barrier layer 200 and the sacrificial layer 900 using methods including, but not limited to, evaporation, magnetron sputtering, etc. Then, the lower electrode layer 300 is etched using processes such as exposure, development, and etching to form a third region 310 for exposing the barrier layer 200 and the sacrificial layer 900. Furthermore, the lower electrode layer 300 in this application may, for example, have a certain etching angle. (Reference) Figure 8B As shown, the etching angle of the lower electrode layer 300 ranges from 10° to 30°, thereby forming a lower electrode layer 300 with a slope structure.

[0038] Then, a piezoelectric layer 400 is deposited on the third region 310 and the lower electrode layer 300. The piezoelectric layer 400 can be formed by, for example, physical vapor deposition (PVD) or chemical vapor deposition (CVD).

[0039] Furthermore, on the piezoelectric layer 400, an upper electrode layer 500 is deposited using methods including but not limited to evaporation and magnetron sputtering, and the upper electrode layer 500 is etched using processes such as exposure, development, and etching to form a fourth region 510 for exposing the piezoelectric layer 400. The third region 310 and the fourth region 510 are formed on both sides of the sacrificial layer 900.

[0040] Finally, the piezoelectric layer 400 is etched at the corresponding position in the fourth region 510 to form a fifth region 410 for exposing the lower electrode layer 300. The orthogonal projection of the fourth region 510 onto the lower electrode layer 300 completely covers the fifth region 410.

[0041] Optionally, the operation of forming a resonant structure corresponding to the lower electrode layer 300, the piezoelectric layer 400 and the upper electrode layer 500 includes: etching the side of the substrate 100 away from the barrier layer 200 and forming a release hole 110 communicating with the sacrificial layer 900; and etching the sacrificial layer 900 through the release hole 110 and forming a resonant cavity 1000 inside the resonant structure.

[0042] Specifically, Figure 12 A schematic diagram of the structure of the release hole according to an embodiment of this application is shown. Figure 13 A schematic diagram of the resonant cavity according to an embodiment of this application is shown. (Reference) Figure 12 and Figure 13 As shown, firstly, the substrate 100 is thinned from the side away from the barrier layer 200 using a wafer thinning process. The thickness of the thinned substrate 100 is 150μm to 300μm.

[0043] Then, on the side of the substrate 100 away from the barrier layer 200, etching is performed using methods such as dry etching or wet etching to form a release hole 110 communicating with the sacrificial layer 900. Furthermore, during the etching of the release hole 110, the depth of the etching endpoint of the release hole 110 does not exceed the thickness of the sacrificial layer 900, thereby avoiding damage to the lower electrode layer 300. The opening area of ​​the release hole 110 is 10 μm. 2 ~100μm 2 The opening shape of the release hole 110 can be, for example, circular or elliptical, and is not limited here.

[0044] Finally, the sacrificial layer 900 is etched using hydrofluoric acid (HF) or buffered oxide etchant (BOE) through the release hole 110, and a resonant cavity 1000 is formed inside the resonant structure.

[0045] Because existing technologies require reserving space for the release hole 110 near the resonant operating region in the resonant structure, this results in wasted device area. Therefore, this application places the release hole 110 on the back side of the bulk acoustic wave resonator package structure (i.e., on the side of the substrate 100 away from the barrier layer 200), thereby reducing the size of the bulk acoustic wave resonator package structure.

[0046] Furthermore, since the release hole 110 is located on the back side of the bulk acoustic wave resonator package structure, the risk of leakage during the process of etching to form the resonant cavity 1000 through the release hole 110 can be avoided, thereby improving the reliability of the bulk acoustic wave resonator package structure.

[0047] In addition, the release hole 110 is opened on the back of the bulk acoustic wave resonator package structure, and the front of the bulk acoustic wave resonator package structure can also be etched, thereby enhancing the process compatibility of the bulk acoustic wave resonator package structure.

[0048] Optionally, the operation of encapsulating the side of the resonant structure away from the substrate 100 using the substrate 610 includes: depositing and etching pad layers on the upper electrode layer 500, the piezoelectric layer 400, and the lower electrode layer 300 to form a first pad 621 on the upper electrode layer 500 and a second pad 622 on the fifth region 410; forming a first solder ball 631 on the first pad 621 and a second solder ball 632 on the second pad 622 through a ball-mounting process; and connecting the substrate 610 to the first solder ball 631 and the second solder ball 632 by soldering, respectively, and encapsulating the side of the resonant structure away from the substrate 100.

[0049] Specifically, Figure 14 A schematic diagram of the structure of the first pad and the second pad according to an embodiment of this application is shown. Figure 15 A schematic diagram of the structure of the first solder ball and the second solder ball according to an embodiment of this application is shown. Figure 16 A schematic diagram of the bulk acoustic wave resonator packaging structure according to an embodiment of this application is shown.

[0050] refer to Figures 14-16 As shown, firstly, pad layers are deposited on the upper electrode layer 500, piezoelectric layer 400, and lower electrode layer 300 by methods such as sputtering or electron beam evaporation. Then, the pad layers are etched using a lift-off lithography process to form a first pad 621 on the upper electrode layer 500 and a second pad 622 on the fifth region 410. The materials of the first pad 621 and the second pad 622 can be, for example, titanium or copper, or other materials compatible with conventional CSP packaging processes; no limitations are imposed here.

[0051] Then, through a ball-planting process, a first solder ball 631 is formed on the first solder pad 621, and a second solder ball 632 is formed on the second solder pad 622.

[0052] Finally, using CSP packaging technology, the substrate 610 is connected to the first solder ball 631 and the second solder ball 632 by welding, and the side of the resonant structure away from the substrate 100 is packaged to form a bulk acoustic wave resonator package structure.

[0053] Therefore, the bulk acoustic wave resonator packaging structure fabricated based on the preparation method provided in this application can avoid the influence of thermal stress introduced by the high temperature during the deposition of the barrier layer 200 on the resonant structure, and prevent leakage caused by thin film interface failure in the bulk acoustic wave resonator. This improves the reliability of the bulk acoustic wave resonator packaging structure.

[0054] Furthermore, the above method eliminates the need for bonding with a temporary carrier wafer before fabricating the resonant structure, avoiding the step of flipping the entire structure and removing the carrier wafer after fabrication. Unlike existing technologies that require bonding a cap wafer for secondary sealing, this application utilizes a substrate to encapsulate the resonant structure. This simplifies the fabrication process and reduces costs.

[0055] Therefore, the fabrication method provided in this application can improve the reliability of the bulk acoustic wave resonator packaging structure and reduce the fabrication cost.

[0056] According to another aspect of this application, a bulk acoustic wave resonator packaging structure is provided, comprising: a substrate 100, a barrier layer 200 deposited on the substrate 100, and a lower electrode layer 300, a piezoelectric layer 400, and an upper electrode layer 500 formed on the barrier layer 200. The lower electrode layer 300, the piezoelectric layer 400, and the upper electrode layer 500 form corresponding resonant structures, and the resonant structures further include a resonant cavity 1000; and further comprising: a substrate 610 for packaging the side of the resonant structure away from the substrate 100.

[0057] Specifically, refer to Figure 3 As shown, in the bulk acoustic wave resonator package structure, a barrier layer 200 is deposited on the substrate 100. A resonant structure is disposed on the barrier layer 200. The resonant structure includes a lower electrode layer 300, a piezoelectric layer 400, and an upper electrode layer 500 disposed sequentially from bottom to top, and a resonant cavity 1000 located between the barrier layer 200, the lower electrode layer 300, and the piezoelectric layer 400. Furthermore, a substrate 610 for packaging is disposed on the side of the resonant structure away from the substrate 100.

[0058] Therefore, the bulk acoustic wave resonator packaging structure provided in this application first deposits a barrier layer 200 on the substrate 100, and then forms a resonant structure corresponding to the lower electrode layer 300, the piezoelectric layer 400, and the upper electrode layer 500. This avoids the influence of thermal stress introduced by the high temperature during the deposition of the barrier layer 200 on the resonant structure, and prevents leakage caused by thin-film interface failure in the bulk acoustic wave resonator. This further improves the reliability of the bulk acoustic wave resonator packaging structure.

[0059] Furthermore, the above method eliminates the need for bonding with a temporary carrier wafer before fabricating the resonant structure, avoiding the step of flipping the entire structure and removing the carrier wafer after fabrication. Unlike existing technologies that require bonding a cap wafer for secondary sealing, this application utilizes a substrate to encapsulate the resonant structure. This simplifies the fabrication process and reduces fabrication costs.

[0060] Therefore, the bulk acoustic wave resonator packaging structure provided in this application can achieve the technical effect of improving the reliability of the bulk acoustic wave resonator packaging structure and reducing the manufacturing cost.

[0061] Optionally, it includes: a dielectric layer 700 and a filler layer 800, wherein the dielectric layer 700 is deposited on the substrate 100; the filler layer 800 is deposited on the dielectric layer 700; and a barrier layer 200 is deposited on the filler layer 800 and the dielectric layer 700.

[0062] Specifically, refer to Figure 3 As shown, in the bulk acoustic wave resonator package structure, a dielectric layer 700 and a filler layer 800 are disposed between the substrate 100 and the barrier layer 200. The dielectric layer 700 is deposited on the substrate 100, the filler layer 800 is deposited on the dielectric layer 700, and the barrier layer 200 is deposited on the filler layer 800 and the dielectric layer 700.

[0063] Preferably, the material of the dielectric layer 700 is selected to balance the thermal stress generated when the barrier layer 200 is deposited.

[0064] Optionally, a lower electrode layer 300 is deposited and etched on a barrier layer 200; a piezoelectric layer 400 is deposited on the lower electrode layer 300 and the barrier layer 200, and a fifth region 410 for exposing the lower electrode layer 300 is formed; and an upper electrode layer 500 is deposited on the piezoelectric layer 400, and a fourth region 510 for exposing the lower electrode layer 300 is formed, wherein the position of the fifth region 410 corresponds to the position of the fourth region 510.

[0065] Specifically, refer to Figure 3As shown, a lower electrode layer 300 is disposed on the barrier layer 200, and a piezoelectric layer 400 is deposited on the lower electrode layer 300 and the barrier layer 200. A fifth region 410 for exposing the lower electrode layer 300 is formed on the piezoelectric layer 400. Further, an upper electrode layer 500 is deposited on the piezoelectric layer 400, and a fourth region 510 for exposing the lower electrode layer 300 is formed on the upper electrode layer 500. The position of the fifth region 410 corresponds to the position of the fourth region 510, and the orthographic projection of the fourth region 510 on the lower electrode layer 300 completely covers the fifth region 410.

[0066] Optionally, it also includes a release hole 110 formed on the side of the substrate 100 away from the barrier layer 200, wherein the release hole 110 passes through the substrate 100, the dielectric layer 700 and the barrier layer 200.

[0067] Specifically, refer to Figure 3 As shown, the bulk acoustic wave resonator package structure also includes a release hole 110. The release hole 110 is located on the side of the substrate 100 away from the barrier layer 200, and the release hole 110 passes through the substrate 100, the dielectric layer 700, and the barrier layer 200.

[0068] Because existing technologies require reserving space for the release hole 110 near the resonant operating region in the resonant structure, this results in wasted device area. Therefore, this application places the release hole 110 on the back side of the bulk acoustic wave resonator package structure (i.e., on the side of the substrate 100 away from the barrier layer 200), thereby reducing the size of the bulk acoustic wave resonator package structure.

[0069] Furthermore, since the release hole 110 is located on the back side of the bulk acoustic wave resonator package structure, the risk of leakage during the process of etching to form the resonant cavity 1000 through the release hole 110 can be avoided, thereby improving the reliability of the bulk acoustic wave resonator package structure.

[0070] In addition, the release hole 110 is located on the back side of the bulk acoustic wave resonator package structure, and the front side of the bulk acoustic wave resonator package structure can also be etched, thereby enhancing the process compatibility of the bulk acoustic wave resonator package structure.

[0071] Optionally, a first pad 621 is provided on the upper electrode layer 500, and a second pad 622 is provided on the lower electrode layer 300; a first solder ball 631 is provided on the first pad 621, and a second solder ball 632 is provided on the second pad 622; and the substrate 610 is soldered to the first solder ball 631 and the second solder ball 632.

[0072] Specifically, refer to Figure 3As shown, a first pad 621 is disposed on the upper electrode layer 500, and a first solder ball 631 is disposed on the first pad 621. A second pad 622 is located within the fifth region 410, disposed on the lower electrode layer 300, and a second solder ball 632 is disposed on the second pad 622. Further, a substrate 610 is soldered to the first solder ball 631 and the second solder ball 632.

[0073] Thus, the above structure enables the encapsulation of the side of the resonant structure away from the substrate 100, thereby forming a bulk acoustic wave resonator encapsulation structure.

[0074] Optionally, the etching angle of the lower electrode layer 300 is 10° to 30°.

[0075] Specifically, Figure 16 A schematic diagram of a bulk acoustic wave resonator package structure with a ramped lower electrode layer according to an embodiment of this application is shown. (Reference) Figure 16 As shown, the etching angle of the lower electrode layer 300 is 10°~30°, forming a lower electrode layer 300 with a slope structure.

[0076] This can improve the deposition quality of the piezoelectric layer 400 on the lower electrode layer 300.

[0077] Unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure. It should also be understood that, for ease of description, the dimensions of the various parts shown in the drawings are not drawn to actual scale. Techniques, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters in the following drawings denote similar items; therefore, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

[0078] For ease of description, spatial relative terms such as "above," "on top of," "on the upper surface of," "above," etc., are used herein to describe the spatial positional relationship of a device or feature as shown in the figures to other devices or features. It should be understood that spatial relative terms are intended to encompass different orientations in use or operation beyond the orientation of the device as described in the figures. For example, if the device in the figures were inverted, a device described as "above" or "on top of" other devices or structures would subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein will be interpreted accordingly.

[0079] In the description of this disclosure, it should be understood that the orientation or positional relationship indicated by directional terms such as "front, back, up, down, left, right", "horizontal, vertical, horizontal" and "top, bottom" is generally based on the orientation or positional relationship shown in the accompanying drawings and is only for the convenience of describing this disclosure and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this disclosure; the directional terms "inner" and "outer" refer to the inner and outer contours relative to the outline of each component itself.

[0080] The above description is merely a preferred embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for fabricating a bulk acoustic wave resonator packaging structure, characterized in that, include: Substrate (100) is provided; A barrier layer (200) is deposited on the substrate (100); A lower electrode layer (300), a piezoelectric layer (400), and an upper electrode layer (500) are sequentially fabricated on the barrier layer (200), and a resonant structure corresponding to the lower electrode layer (300), the piezoelectric layer (400), and the upper electrode layer (500) is formed. as well as The side of the resonant structure away from the substrate (100) is encapsulated using a substrate (610).

2. The preparation method according to claim 1, characterized in that, The operation of depositing a barrier layer (200) on the substrate (100) includes: A dielectric layer (700) and a filler layer (800) are sequentially deposited on the substrate (100). The filler layer (800) is etched to form a first region (810) for exposing the dielectric layer (700); and The barrier layer (200) is deposited on the first region (810) and the filler layer (800) to form a second region (210), wherein the second region (210) corresponds to the position of the first region (810).

3. The preparation method according to claim 2, characterized in that, Also includes: A sacrificial layer (900) is deposited in the second region (210).

4. The preparation method according to claim 3, characterized in that, The operation of sequentially fabricating a lower electrode layer (300), a piezoelectric layer (400), and an upper electrode layer (500) on the barrier layer (200) includes: The lower electrode layer (300) is deposited and etched on the barrier layer (200) and the sacrificial layer (900) to form a third region (310) for exposing the barrier layer (200) and the sacrificial layer (900). The piezoelectric layer (400) is deposited on the third region (310) and the lower electrode layer (300). The upper electrode layer (500) is deposited and etched on the piezoelectric layer (400) to form a fourth region (510) for exposing the piezoelectric layer (400), wherein the third region (310) and the fourth region (510) are formed on both sides of the sacrificial layer (900); and The piezoelectric layer (400) is etched at the corresponding position in the fourth region (510) to form a fifth region (410) for exposing the lower electrode layer (300).

5. The preparation method according to claim 4, characterized in that, The operation of forming a resonant structure corresponding to the lower electrode layer (300), the piezoelectric layer (400), and the upper electrode layer (500) includes: The substrate (100) is etched on the side away from the barrier layer (200) to form a release hole (110) communicating with the sacrificial layer (900); and The sacrificial layer (900) is etched through the release hole (110), and a resonant cavity (1000) is formed inside the resonant structure.

6. The preparation method according to claim 5, characterized in that, The operation of encapsulating the side of the resonant structure away from the substrate (100) using a substrate (610) includes: A pad layer is deposited and etched on the upper electrode layer (500), the piezoelectric layer (400) and the lower electrode layer (300) to form a first pad (621) on the upper electrode layer (500) and a second pad (622) on the fifth region (410). A first solder ball (631) is formed on the first pad (621) and a second solder ball (632) is formed on the second pad (622) using a ball-planting process; and The substrate (610) is connected to the first solder ball (631) and the second solder ball (632) by welding, and the side of the resonant structure away from the substrate (100) is encapsulated.

7. A bulk acoustic wave resonator packaging structure, characterized in that, include: A substrate (100), a barrier layer (200) deposited on the substrate (100), and a lower electrode layer (300), a piezoelectric layer (400), and an upper electrode layer (500) formed on the barrier layer (200), wherein the lower electrode layer (300), the piezoelectric layer (400), and the upper electrode layer (500) form a corresponding resonant structure, and the resonant structure includes a resonant cavity (1000); and It also includes a substrate (610) for encapsulating the side of the resonant structure away from the substrate (100).

8. The bulk acoustic wave resonator packaging structure according to claim 7, characterized in that, include: The dielectric layer (700) and the filler layer (800), wherein The dielectric layer (700) is deposited on the substrate (100); The filler layer (800) is deposited on the dielectric layer (700); as well as The barrier layer (200) is deposited on the filler layer (800) and the dielectric layer (700).

9. The bulk acoustic wave resonator packaging structure according to claim 8, characterized in that, The lower electrode layer (300) is deposited and etched onto the barrier layer (200); The piezoelectric layer (400) is deposited on the lower electrode layer (300) and the barrier layer (200), and a fifth region (410) is formed for exposing the lower electrode layer (300); and The upper electrode layer (500) is deposited on the piezoelectric layer (400) and a fourth region (510) is formed for exposing the piezoelectric layer (400) and the lower electrode layer (300), wherein the position of the fifth region (410) corresponds to the position of the fourth region (510).

10. The bulk acoustic wave resonator packaging structure according to claim 9, characterized in that, Also includes: A release hole (110) is formed on the side of the substrate (100) away from the barrier layer (200), wherein the release hole (110) passes through the substrate (100), the dielectric layer (700) and the barrier layer (200).

11. The bulk acoustic resonator packaging structure according to claim 7, characterized in that, The upper electrode layer (500) is provided with a first pad (621), and the lower electrode layer (300) is provided with a second pad (622). The first pad (621) is provided with a first solder ball (631), and the second pad (622) is provided with a second solder ball (632); and The substrate (610) is soldered to the first solder ball (631) and the second solder ball (632).

12. The bulk acoustic wave resonator packaging structure according to claim 7, characterized in that, The etching angle of the lower electrode layer (300) is 10°~30°.

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