Low-voltage mos tube power-off high-voltage fault safety io circuit

Abstract

This invention relates to the field of analog integrated circuit technology, specifically to a low-voltage MOS transistor power-down high-voltage fault-safe I / O circuit. The circuit mainly includes a dynamic I / O power supply voltage generation circuit, a protection voltage bias generation circuit, and a PAD output drive circuit, all implemented using standard low-voltage MOS transistors. The dynamic I / O power supply voltage generation circuit outputs a normal power supply voltage when the chip is powered on, and maintains operation using the ESD bus voltage when power is off. The protection voltage bias generation circuit generates a high-voltage protection bias voltage based on the dynamic power supply voltage. The PAD output drive circuit uses this bias voltage to drive the output and protect the internal transistors. This invention eliminates the need for high-voltage devices or additional process steps, reducing costs, while ensuring that the chip can safely withstand high-voltage signals and prevent current backflow under both power-on and power-off states, achieving complete fault-safe protection. It is suitable for high-reliability interface applications in advanced semiconductor processes.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit technology, and specifically to a low-voltage MOSFET power-down fault-resistant high-voltage fault-safe I / O circuit. Background Technology

[0002] In complex electronic system applications, direct electrical connections and signal communication are often required between different chips or modules. Since the chips within the system may employ different process nodes and operate at different voltages, the signal voltage on the communication interface (IO) often exceeds the chip's own power supply voltage. This requires the chip's IO interface not only to correctly identify signals under normal operating conditions but also to possess a certain voltage withstand capability to prevent reliability issues such as latch-up, gate oxide breakdown, or increased leakage current caused by high voltage.

[0003] Meanwhile, as semiconductor processes continue to evolve, the operating voltage of core chip devices is constantly decreasing in pursuit of higher performance and lower power consumption. However, at the system level, due to considerations of compatibility, driving capability, or industry standards, it is often necessary to maintain higher interface levels (such as 3.3V, 5V, etc.). This contradiction presents a severe challenge to the I / O design of advanced process chips: core devices with relatively lower voltage tolerance must be used to safely handle higher system voltages.

[0004] Specifically, high-pressure withstand requirements can be divided into two typical operating conditions:

[0005] (1) Chip power-on state: When the chip is powered on normally, its IO circuit must be able to withstand and correctly process external signals that are higher than its power supply voltage.

[0006] (2) Chip Power-Down State: When the chip itself is powered down (VDD=0V) while the communicating party is still powered on, a high voltage signal may still exist on its IO pins. At this time, the circuit not only needs to physically withstand this high voltage to avoid damage, but also must ensure that no significant current flows back from the IO pins to the chip's internal power network or ground. This backflow current may cause unexpected voltage rises in internal nodes, leading to logic misjudgments, system failure to power on or restart normally, or even functional malfunctions. The chip's ability to prevent such situations is called the "failsafe" function.

[0007] To address the above requirements, existing technologies mainly offer the following two implementation paths:

[0008] (1) Use dedicated high-voltage devices: Integrate dedicated high-voltage MOS transistors in the IO design. Such devices usually require additional process steps or mask layers, which leads to a significant increase in manufacturing costs, which is contrary to the trend of advanced processes pursuing low cost and high integration.

[0009] (2) Using a low-voltage MOSFET cascade structure: Standard low-voltage MOSFETs are used to form a common-source, common-gate configuration, and the gate of the upper-level MOSFET is dynamically biased to distribute the high voltage when the chip is powered on, thereby improving the overall voltage withstand capability. However, this solution usually relies on an effective on-chip power supply to generate a suitable bias voltage. When the chip is completely powered off, the bias circuit fails, the cascade structure cannot maintain its voltage withstand characteristics, and it is difficult to block the reverse current path. Therefore, it generally cannot support the high voltage withstand and fault safety requirements under power-down conditions.

[0010] In summary, existing I / O voltage withstand solutions are either incompatible with advanced processes in terms of cost or fail to meet the system requirements for high voltage withstand and fault safety under power-down conditions. Therefore, there is an urgent need for an I / O circuit design technology that can reliably withstand high voltage and has fault safety functions under both power-on and power-off states, based on standard low-voltage processes, without additional mask costs.

[0011] Therefore, existing technologies still need further development. Summary of the Invention

[0012] The purpose of this invention is to overcome the above-mentioned technical deficiencies and provide a low-voltage MOSFET power-down fault-resistant, high-voltage fault-safe I / O circuit to solve the problems existing in the prior art.

[0013] To achieve the above technical objectives, this invention provides a low-voltage MOSFET power-down fault-resistant, high-voltage fault-safe I / O circuit, comprising:

[0014] A dynamic IO power supply voltage generation circuit is used to generate a dynamic power supply voltage in the chip's power-on and power-off states; a protection voltage bias generation circuit is connected to the dynamic IO power supply voltage generation circuit and is used to generate a high-voltage protection bias voltage based on the dynamic power supply voltage; and a PAD output drive circuit is connected to the protection voltage bias generation circuit and is used to drive the output signal. The dynamic IO power supply voltage generation circuit, the protection voltage bias generation circuit, and the PAD output drive circuit are all implemented using low-voltage MOS transistors, so that the circuit can withstand the high voltage on the IO interface and prevent current backflow when the chip is powered off.

[0015] Specifically, the dynamic IO power supply voltage generation circuit (VDDIO_I_GEN) includes multiple low-voltage MOS transistors (MN1, MP1, MP2, MP3, MP4, MP5, MP6, MP7). These multiple low-voltage MOS transistors (MN1, MP1, MP2, MP3, MP4, MP5, MP6, MP7) are connected to form a network to receive external input voltages (VDDIO, VDDESD, V16N, V16P) and output the dynamic power supply voltage (VDDIO_I). When the chip is powered on, the dynamic power supply voltage (VDDIO_I) is equal to the first power supply voltage (VDDIO). When the chip is powered off, the dynamic power supply voltage (VDDIO_I) is generated based on the ESD bus voltage (VDDESD).

[0016] Specifically, the protection voltage bias generation circuit (VBIAS_GEN) includes a voltage divider module and an output module. The voltage divider module consists of low-voltage MOS transistors (MN10, MP10, MP11, MP12) and resistors (R10, R11) and is used to divide the dynamic power supply voltage (VDDIO_I). The output module consists of low-voltage MOS transistors (MN11, MP13) and resistors (R12, R13) and is used to generate the high-voltage protection bias voltage (V16N, V16P).

[0017] Specifically, the PAD output driving circuit (PAD) includes driving low-voltage MOS transistors (MP20, MN20) and protecting low-voltage MOS transistors (MP21, MN21). The driving low-voltage MOS transistors (MP20, MN20) are used to receive internal chip signals (DP, DN) and drive the output. The gates of the protecting low-voltage MOS transistors (MP21, MN21) are connected to the high-voltage protection bias voltages (V16P, V16N) to protect the driving low-voltage MOS transistors (MP20, MN20) under high-voltage conditions.

[0018] Specifically, the low-voltage MOS transistors in the dynamic IO power supply voltage generation circuit (VDDIO_I_GEN) include N-type MOS transistors (MN1) and P-type MOS transistors (MP1, MP2, MP3, MP4, MP5, MP6, MP7). The N-type MOS transistors (MN1) and P-type MOS transistors (MP1, MP2, MP3, MP4, MP5, MP6, MP7) are cross-connected through their gates and drains to maintain voltage output using the ESD diode effect in the power-down state.

[0019] Specifically, the dynamic IO power supply voltage generation circuit (VDDIO_I_GEN) also includes a bias input node for receiving bias voltages (V16N, V16P) from the protection voltage bias generation circuit (VBIAS_GEN) to control the conduction state of the P-type MOS transistors (MP3, MP4, MP5).

[0020] Specifically, the voltage divider module in the protection voltage bias generation circuit (VBIAS_GEN) includes a first voltage divider branch and a second voltage divider branch. The first voltage divider branch is composed of a low-voltage MOS transistor (MP12, MN10) and a resistor (R10) connected in series, and the second voltage divider branch is composed of a low-voltage MOS transistor (MP10, MP11) and a resistor (R11) connected in series, used to generate an intermediate voltage divider signal.

[0021] Specifically, the low-voltage MOS transistors (MN11, MP13) in the output module are configured as source follower structures to buffer and output the intermediate voltage divider signal as the high-voltage protection bias voltage (V16N, V16P).

[0022] Specifically, the resistors (R12, R13) are connected between the high-voltage protection bias voltages (V16N, V16P) to stabilize the output voltage value.

[0023] Specifically, the circuit is integrated into a single chip, and all low-voltage MOS transistors are manufactured using standard CMOS technology, without the need for high-voltage devices or additional masking steps.

[0024] Beneficial effects:

[0025] This invention achieves significant benefits by employing a collaborative design of a dynamic IO power supply voltage generation circuit and a protection voltage bias generation circuit. This enables the IO circuit based on a low-voltage MOSFET to withstand high voltage and possess fault-safe functionality in both the power-on and power-off states of the chip.

[0026] First, in terms of cost, this solution uses standard low-voltage MOS transistors without the need to integrate dedicated high-voltage devices or add extra masking steps. It is highly compatible with advanced semiconductor processes, significantly reducing manufacturing costs and complexity. It is suitable for large-scale integrated circuit production, promoting process advancement and economic efficiency.

[0027] Secondly, in terms of performance reliability, the dynamic IO power supply voltage generation circuit can output a normal power supply voltage when the chip is powered on, and maintain the circuit operation by using the ESD bus voltage when the power is off, ensuring that the bias voltage is continuously generated, thereby achieving the continuity of high voltage withstand; the protection voltage bias generation circuit generates a stable bias voltage through the voltage divider module and the output module, providing precise protection for the PAD output drive circuit, effectively preventing device damage or increased leakage current caused by high voltage, and improving the overall reliability and lifespan of the circuit.

[0028] Furthermore, in terms of fault safety, this design can suppress current backflow from the I / O pins to the internal power network when the chip is powered down, avoiding system malfunctions or restart failures caused by unexpected voltage rises, and ensuring the stable operation of the electronic system. This circuit structure also has good adaptability and compatibility, can adapt to different operating voltage scenarios, and can achieve automatic switching without external adjustment, reducing design complexity and maintenance requirements.

[0029] Meanwhile, by integrating it onto a single chip and using standard CMOS technology, this approach enhances the compactness and scalability of the circuit, providing a solid foundation for high-performance chip applications.

[0030] Overall, this invention not only solves the cost and functional deficiencies of existing technologies, but also achieves efficient, economical and reliable I / O interface protection through innovative circuit layout, which is of great value to promoting the development of semiconductor technology. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the transistor-level circuit of the dynamic IO power supply voltage generation circuit provided in a specific embodiment of the present invention;

[0032] Figure 2 This is a schematic diagram of the transistor-level circuit of the protection voltage bias generation circuit provided in a specific embodiment of the present invention;

[0033] Figure 3 This is a schematic diagram of the overall circuit implementation of the low-voltage MOS transistor power-down high-voltage fault-resistant safe I / O circuit provided in a specific embodiment of the present invention;

[0034] Figure 4 This is a schematic diagram of the transistor-level circuit of the PAD output driving circuit provided in a specific embodiment of the present invention. Detailed Implementation

[0035] To enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Based on the embodiments in this application, other similar embodiments obtained by those skilled in the art without creative effort should all fall within the scope of protection of this application. Furthermore, directional terms mentioned in the following embodiments, such as "up," "down," "left," and "right," are only for reference to the directions in the accompanying drawings; therefore, the directional terms used are for illustrative purposes and not for limiting the invention.

[0036] The present invention will be further described below with reference to the accompanying drawings and preferred embodiments.

[0037] Please see Figure 1 This invention provides a low-voltage MOSFET power-down fault-resistant, high-voltage fault-safe I / O circuit, comprising:

[0038] Please see Figure 1 This invention provides a low-voltage MOS transistor power-down high-voltage fault-safe I / O circuit, comprising: a dynamic I / O power supply voltage generation circuit (VDDIO_I_GEN) for generating a dynamic power supply voltage (VDDIO_I) in both the chip's power-on and power-down states; a protection voltage bias generation circuit (VBIAS_GEN) connected to the dynamic I / O power supply voltage generation circuit (VDDIO_I_GEN) for generating high-voltage protection bias voltages (V16N, V16P) based on the dynamic power supply voltage (VDDIO_I); and a PAD output drive circuit (PAD) connected to the protection voltage bias generation circuit (VBIAS_GEN) for driving an output signal (PADOUT). The dynamic I / O power supply voltage generation circuit (VDDIO_I_GEN), the protection voltage bias generation circuit (VBIAS_GEN), and the PAD output drive circuit (PAD) are all implemented using low-voltage MOS transistors, enabling the circuit to withstand high voltage on the I / O interface and prevent current backflow when the chip is powered down, thus achieving a fault-safe function.

[0039] It should be further noted that the overall architecture of this circuit can be found in the appendix. Figure 3The structure shown is as follows: VDDIO_I_GEN is the dynamic IO power supply voltage generation circuit, VBIAS_GEN is the protection voltage bias generation circuit, and PAD is the PAD output driver circuit. External input voltages include VDDIO, VDDESD, VSS, DP, and DN, where VDDIO is the IO power supply voltage (e.g., 3.3V), VDDESD is the ESD bus voltage, VSS is analog ground, and DP and DN are internal chip signals. VDDIO_I_GEN outputs the VDDIO_I voltage, which powers VBIAS_GEN; VBIAS_GEN outputs V16P and V16N voltages, providing bias for VDDIO_I_GEN and PAD; PAD outputs PADOUT as the final output voltage. During the workflow, when the chip is powered on, VDDIO_I_GEN provides a VDDIO_I voltage of 3.3V, and VBIAS_GEN generates bias voltages V16P and V16N to protect the PAD circuit. When the chip is powered off and there is high voltage on the PAD, VDDIO_I_GEN uses the VDDESD voltage (about 2.6V) to maintain the VDDIO_I output, and VBIAS_GEN generates a reduced bias voltage to ensure high voltage protection and fault safety.

[0040] Understandably, this integrated circuit design enables the chip to withstand high voltage in both power-on and power-off states without the need for high-voltage components under advanced processes, effectively preventing current backflow, reducing manufacturing costs, and improving system reliability.

[0041] Specifically, the dynamic IO power supply voltage generation circuit (VDDIO_I_GEN) includes multiple low-voltage MOS transistors (MN1, MP1, MP2, MP3, MP4, MP5, MP6, MP7). These multiple low-voltage MOS transistors (MN1, MP1, MP2, MP3, MP4, MP5, MP6, MP7) are connected to form a network to receive external input voltages (VDDIO, VDDESD, V16N, V16P) and output the dynamic power supply voltage (VDDIO_I). When the chip is powered on, the dynamic power supply voltage (VDDIO_I) is equal to the first power supply voltage (VDDIO). When the chip is powered off, the dynamic power supply voltage (VDDIO_I) is generated based on the ESD bus voltage (VDDESD).

[0042] It should be further noted that the transistor-level connections of the dynamic IO power supply voltage generation circuit can be found in the appendix. Figure 1As shown, MN1, MP1, MP2, MP3, MP4, MP5, MP6, and MP7 are all standard low-voltage MOS transistors. The gate of transistor MN1 is connected to the gates of transistors MP4 and MP5, and the drains of transistors MP1 and MP2. Its source is connected to the external input voltage V16N, and its drain is connected to the drain of transistor MP5 and the gate of transistor MP7. The gate of transistor MP1 is connected to the external input voltage VDDIO and the source of transistor MP2. Its source is connected to the external input voltage V16N, and its drain is connected to the gates of transistors MN1, MP4, and MP5, and the drain of transistor MP2. The gate of transistor MP2 is connected to the external input voltage V16N and the source of transistor MP1. Its source is connected to the external input voltage VDDIO, and its drain is connected to the gates of transistors MN1, MP4, and MP5, and the drain of transistor MP1. The gate of the MP3 transistor is connected to the external input voltage V16P, its source is connected to the external input voltage VDDESD, and its drain is connected to the source of the MP4 and MP5 transistors. The gate of the MP4 transistor is connected to the gates of the MN1 and MP5 transistors, as well as the drains of the MP1 and MP2 transistors. Its source is connected to the drain of the MP3 transistor and the source of the MP5 transistor. Its drain is connected to the drain of the MP7 transistor and the output voltage VDDIO_I. The gate of the MP5 transistor is connected to the gates of the MN1 and MP4 transistors, as well as the drains of the MP1 and MP2 transistors. Its source is connected to the drain of the MP3 transistor and the source of the MP4 transistor. Its drain is connected to the drain of the MN1 transistor and the gate of the MP7 transistor. The gate of the MP6 transistor is connected to the external input voltage V16N, its source is connected to the external input voltage VDDIO, and its drain is connected to the source of the MP7 transistor. The gate of the MP7 transistor is connected to the drain of the MN1 and MP5 transistors, the source is connected to the drain of the MP6 transistor, and the drain is connected to the drain of the MP4 transistor and the output voltage VDDIO_I.

[0043] Furthermore, in the external input voltages, VDDIO is the IO power supply voltage of 3.3V, VDDESD is the ESD bus voltage, which is approximately 2.6V when power is off, and V16N and V16P are bias voltages. The circuit works as follows: When power is on, MP2 is turned on, VDDIO is transmitted to the gate terminals of MN1, MP4, and MP5, MP4 and MP5 are turned off, MN1 is turned on, causing V16N to transmit to the gate terminal of MP7, MP6 and MP7 are turned on, and VDDIO_I outputs 3.3V; when power is off, VDDIO is 0, MP6 is turned off, MP1 is turned on, causing V16N to transmit to the gate terminal of MP4, MP3 is turned on, transmitting VDDESD to the source terminal of MP4, MP4 is turned on, and VDDIO_I outputs 2.6V.

[0044] Understandably, this circuit utilizes the cross-connection of low-voltage MOSFETs and the ESD effect to achieve dynamic switching of power supply voltage between power-on and power-off states, ensuring continuous operation of the bias circuit, thereby improving withstand voltage and fault safety.

[0045] Specifically, the protection voltage bias generation circuit (VBIAS_GEN) includes a voltage divider module and an output module. The voltage divider module consists of low-voltage MOS transistors (MN10, MP10, MP11, MP12) and resistors (R10, R11) and is used to divide the dynamic power supply voltage (VDDIO_I). The output module consists of low-voltage MOS transistors (MN11, MP13) and resistors (R12, R13) and is used to generate the high-voltage protection bias voltage (V16N, V16P).

[0046] It should be further noted that the transistor-level connections of the protection voltage bias generation circuit can be found in the appendix. Figure 2 As shown, MN10, MN11, MP10, MP11, MP12, and MP13 are standard low-voltage MOS transistors, and R10, R11, R12, and R13 are resistors. The gate and drain of transistor MN10 are connected, as well as the gate of transistor MN11 and the drain of transistor MP12. Its source is connected to resistor R10. The gate and drain of transistor MN11 are connected, as well as the gate and drain of transistor MN10 and the drain of transistor MP12. Its source is connected to the circuit output voltage V16N, and its drain is connected to the external input voltage VDDIO_I. The gate and drain of transistor MP10 are connected, as well as the external input voltage VSS. Its source is connected to the gate and drain of transistor MP11 and the gate of transistor MP13. The gate and drain of transistor MP11 are connected, as well as the source of transistor MP10 and the drain of transistor MP13. Its source is connected to resistor R11. The gate and source of transistor MP12 are connected to the external input voltage VDDIO_I. Its drain is connected to the gate and drain of transistor MN10 and the gate of transistor MN11. The gate of transistor MP13 is connected to the gate and drain of transistor MP11 and the source of transistor MP10. Its source is connected to the circuit output voltage V16P, and its drain is connected to the external input voltage VSS. Resistor R10 is connected to the source of transistor MN10 and resistor R11. Resistor R11 is connected to the source of transistor MP11 and resistor R10. Resistor R12 is connected to the circuit output voltage V16N and resistor R13. Resistor R13 is connected to the circuit output voltage V16P and resistor R12. The external input voltage VDDIO_I is provided by the dynamic IO power supply voltage generation circuit, and VSS is analog ground.

[0047] Furthermore, the circuit working principle of the above circuit is as follows: when powered on, VDDIO_I is 3.3V, MP12, MN10, R10 and MP10, MP11, R11 complete the voltage division, and output V16N (about 1.73V) and V16P (about 1.6V) through MN11 and MP13; when powered off, VDDIO_I is 2.6V, and after voltage division, output V16N and V16P are about 1.2V.

[0048] Understandably, this circuit generates a stable bias voltage through a voltage divider structure using resistors and MOSFETs, adapting to different power supply states, providing precise bias for high-voltage protection, and enhancing circuit reliability.

[0049] Specifically, the PAD output driving circuit (PAD) includes driving low-voltage MOS transistors (MP20, MN20) and protecting low-voltage MOS transistors (MP21, MN21). The driving low-voltage MOS transistors (MP20, MN20) are used to receive internal chip signals (DP, DN) and drive the output. The gates of the protecting low-voltage MOS transistors (MP21, MN21) are connected to the high-voltage protection bias voltages (V16P, V16N) to protect the driving low-voltage MOS transistors (MP20, MN20) under high-voltage conditions.

[0050] It should be further noted that the transistor-level connections of the PAD output drive circuit can be found in the appendix. Figure 4 As shown, MN20, MN21, MP20, and MP21 are all standard low-voltage MOS transistors. The gate of transistor MN20 is connected to the external input voltage DN, its source is connected to the external input voltage VSS, and its drain is connected to the source of transistor MN21. The gate of transistor MN21 is connected to the external input voltage V16N, its source is connected to the drain of transistor MN20, and its drain is connected to the drain of transistor MP21 and the circuit output voltage PADOUT. The gate of transistor MP20 is connected to the external input voltage DP, its source is connected to the external input voltage VDDIO, and its drain is connected to the source of transistor MP21. The gate of transistor MP21 is connected to the external input voltage V16P, its source is connected to the drain of transistor MP20, and its drain is connected to the drain of transistor MN21 and the circuit output voltage PADOUT. In the external input voltages, VDDIO is the IO circuit power supply voltage of 3.3V, VSS is analog ground, and DN and DP are internal chip signals. PADOUT is the final output voltage. During operation, the driving transistors MP20 and MN20 drive the output according to the DP and DN signals, while the protection transistors MP21 and MN21, under the control of the bias voltages V16P and V16N, share the high voltage and prevent damage to the driving transistors.

[0051] Understandably, this structure protects the transistor from high voltage, ensuring the safe operation of the drive circuit under abnormal conditions, reducing the risk of leakage and damage, and improving the lifespan and stability of the I / O interface.

[0052] Specifically, the low-voltage MOS transistors in the dynamic IO power supply voltage generation circuit (VDDIO_I_GEN) include N-type MOS transistors (MN1) and P-type MOS transistors (MP1, MP2, MP3, MP4, MP5, MP6, MP7). The N-type MOS transistors (MN1) and P-type MOS transistors (MP1, MP2, MP3, MP4, MP5, MP6, MP7) are cross-connected through their gates and drains to maintain voltage output using the ESD diode effect in the power-down state.

[0053] It should be further explained that in the dynamic IO power supply voltage generation circuit, the cross-connection of N-type MOS transistor MN1 and P-type MOS transistors MP1 to MP7 allows the VDDESD voltage (e.g., 2.6V) to be transferred to the output through the conduction of transistors MP1, MP3, and MP4 during power failure, utilizing the diode effect between the PAD and the ESD bus, thereby maintaining circuit operation. The conduction of transistors MP1, MP3, and MP4 utilizes the diode effect between the PAD and the ESD bus...

[0054] Understandably, this design makes full use of ESD protection structures, providing backup power during power outages without the need for additional components, thus enhancing the circuit's automatic recovery capability and fault-safe performance.

[0055] Specifically, the dynamic IO power supply voltage generation circuit (VDDIO_I_GEN) also includes a bias input node for receiving bias voltages (V16N, V16P) from the protection voltage bias generation circuit (VBIAS_GEN) to control the conduction state of the P-type MOS transistors (MP3, MP4, MP5).

[0056] It should be further explained that the bias input node is directly connected to the gate of the MP3, MP4 and MP5 transistors. The switching state of these transistors is adjusted by the V16N and V16P voltages, thereby precisely controlling the voltage delivery path and ensuring smooth switching between power-on and power-down modes.

[0057] Understandably, by controlling the bias voltage, the circuit achieves dynamic self-adaptation, improving the accuracy and efficiency of voltage generation and reducing power consumption fluctuations.

[0058] Specifically, the voltage divider module in the protection voltage bias generation circuit (VBIAS_GEN) includes a first voltage divider branch and a second voltage divider branch. The first voltage divider branch is composed of a low-voltage MOS transistor (MP12, MN10) and a resistor (R10) connected in series, and the second voltage divider branch is composed of a low-voltage MOS transistor (MP10, MP11) and a resistor (R11) connected in series, used to generate an intermediate voltage divider signal.

[0059] It should be further explained that in the first voltage divider branch, transistors MP12 and MN10 are connected in series with resistor R10, and in the second voltage divider branch, transistors MP10 and MP11 are connected in series with resistor R11. These two branches generate an intermediate voltage signal by dividing the VDDIO_I voltage, providing a reference for the output module.

[0060] Understandably, the dual-branch voltage divider structure improves the stability and anti-interference capability of the voltage divider, ensuring the consistency of the bias voltage under different power supply conditions.

[0061] Specifically, the low-voltage MOS transistors (MN11, MP13) in the output module are configured as source follower structures to buffer and output the intermediate voltage divider signal as the high-voltage protection bias voltage (V16N, V16P).

[0062] It should be further explained that the MN11 and MP13 transistors are connected in the form of source followers to buffer and amplify the intermediate signal generated by the voltage divider module, and output low-impedance V16N and V16P voltages to reduce the impact of the load.

[0063] Understandably, the source follower structure improves the driving capability and stability of the bias voltage, prevents voltage drops, and ensures reliable operation of the protection circuit.

[0064] Specifically, the resistors (R12, R13) are connected between the high-voltage protection bias voltages (V16N, V16P) to stabilize the output voltage value.

[0065] It should be further explained that resistors R12 and R13 are used as load resistors and connected to the output terminals of V16N and V16P. They smooth voltage fluctuations and suppress noise through current shunting.

[0066] Understandably, this resistor network enhances the DC stability of the bias voltage, prevents false protection due to transient changes, and improves the circuit's noise immunity.

[0067] Specifically, the circuit is integrated into a single chip, and all low-voltage MOS transistors are manufactured using standard CMOS processes, eliminating the need for high-voltage devices or additional masking steps.

[0068] It should be further explained that the entire circuit is implemented on a single chip, and all MOS transistors such as MN1 and MP1 use low-voltage devices with standard CMOS technology. The manufacturing process does not require modification of the mask or addition of special steps, and is compatible with advanced processes.

[0069] Understandably, this integrated solution significantly reduces production costs and complexity while maintaining high performance, making it suitable for large-scale semiconductor applications and driving process advancements.

[0070] The technical features described above can be combined arbitrarily. Although not all possible combinations of these technical features are described, any combination of these technical features should be considered to be covered by this specification, provided that such combination does not contain contradictions.

[0071] The specific embodiments of the present invention described above do not constitute a limitation on the scope of protection of the present invention. Any other corresponding changes and modifications made in accordance with the technical concept of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A low voltage MOSFET high voltage fault safe IO circuit during power down, characterized by, include: A dynamic IO power supply voltage generation circuit is used to generate a dynamic power supply voltage in the chip's power-on and power-off states; a protection voltage bias generation circuit is connected to the dynamic IO power supply voltage generation circuit and is used to generate a high-voltage protection bias voltage based on the dynamic power supply voltage; and a PAD output drive circuit is connected to the protection voltage bias generation circuit and is used to drive the output signal. The dynamic IO power supply voltage generation circuit, the protection voltage bias generation circuit, and the PAD output drive circuit are all implemented using low-voltage MOS transistors, so that the circuit can withstand the high voltage on the IO interface and prevent current backflow when the chip is powered off. The dynamic IO power supply voltage generation circuit (VDDIO_I_GEN) includes multiple low-voltage MOS transistors (MN1, MP1, MP2, MP3, MP4, MP5, MP6, MP7), which are connected in a network to receive external input voltages (VDDIO, VDDESD, V16N, V16P) and output the dynamic power supply voltage (VDDIO_I). When the chip is powered on, the dynamic power supply voltage (VDDIO_I) is equal to the first power supply voltage (VDDIO), and when the chip is powered off, the dynamic power supply voltage (VDDIO_I) is generated based on the ESD bus voltage (VDDESD). The protection voltage bias generation circuit (VBIAS_GEN) includes a voltage divider module and an output module. The voltage divider module consists of low-voltage MOS transistors (MN10, MP10, MP11, MP12) and resistors (R10, R11) for dividing the dynamic power supply voltage (VDDIO_I). The output module consists of low-voltage MOS transistors (MN11, MP13) and resistors (R12, R13) for generating the high-voltage protection bias voltage (V16N, V16P). The PAD output drive circuit (PAD) includes driving low-voltage MOS transistors (MP20, MN20) and protecting low-voltage MOS transistors (MP21, MN21). The driving low-voltage MOS transistors (MP20, MN20) are used to receive internal chip signals (DP, DN) and drive the output. The gates of the protecting low-voltage MOS transistors (MP21, MN21) are connected to the high-voltage protection bias voltages (V16P, V16N) to protect the driving low-voltage MOS transistors (MP20, MN20) under high-voltage conditions.

2. The low-voltage MOSFET power-down fault-resistant high-voltage fault-safe I / O circuit according to claim 1, characterized in that, The low-voltage MOS transistors in the dynamic IO power supply voltage generation circuit (VDDIO_I_GEN) include N-type MOS transistors (MN1) and P-type MOS transistors (MP1, MP2, MP3, MP4, MP5, MP6, MP7). The N-type MOS transistors (MN1) and P-type MOS transistors (MP1, MP2, MP3, MP4, MP5, MP6, MP7) are cross-connected through their gates and drains to maintain voltage output using the ESD diode effect in the power-down state.

3. The low-voltage MOSFET power-down fault-resistant high-voltage fault-safe I / O circuit according to claim 2, characterized in that, The dynamic IO power supply voltage generation circuit (VDDIO_I_GEN) also includes a bias input node for receiving bias voltages (V16N, V16P) from the protection voltage bias generation circuit (VBIAS_GEN) to control the conduction state of the P-type MOS transistors (MP3, MP4, MP5).

4. The low-voltage MOSFET power-down fault-resistant high-voltage fault-safe I / O circuit according to claim 1, characterized in that, The voltage divider module in the protection voltage bias generation circuit (VBIAS_GEN) includes a first voltage divider branch and a second voltage divider branch. The first voltage divider branch is composed of a low-voltage MOS transistor (MP12, MN10) and a resistor (R10) connected in series, and the second voltage divider branch is composed of a low-voltage MOS transistor (MP10, MP11) and a resistor (R11) connected in series, used to generate an intermediate voltage divider signal.

5. The low-voltage MOSFET power-down fault-resistant high-voltage fault-safe I / O circuit according to claim 4, characterized in that, The low-voltage MOS transistors (MN11, MP13) in the output module are configured as source follower structures to buffer and output the intermediate voltage divider signal as the high-voltage protection bias voltage (V16N, V16P).

6. The low-voltage MOSFET power-down fault-resistant high-voltage fault-safe I / O circuit according to claim 5, characterized in that, The resistors (R12, R13) are connected between the high-voltage protection bias voltages (V16N, V16P) to stabilize the output voltage value.

7. The low-voltage MOSFET power-down fault-resistant high-voltage fault-safe I / O circuit according to claim 1, characterized in that... The circuit is integrated into a single chip, and all low-voltage MOS transistors are manufactured using standard CMOS technology, eliminating the need for high-voltage devices or additional masking steps.

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