Voltage level shifter

Abstract

The invention provides a voltage level shifter. The voltage level shifter includes a voltage level shift circuit and a boost circuit. The voltage level shift circuit operates between a first voltage and a second voltage. The voltage level shift circuit includes a cross-coupled transistor pair and a differential transistor pair. The differential transistor pair couples the cross-coupled transistor pair and receives the input signal pair. The boost circuit is coupled to the voltage level shift circuit. The boost circuit performs a pre-charging operation on a plurality of boost input terminals of the cross-coupled transistor pair, generates a voltage pulse wave based on a charge pump operation according to a control pulse wave signal, and provides the voltage pulse wave to the boost input terminals. The control pulse signal is generated corresponding to the transition edge of the input signal pair. In this way, the voltage pull is reduced.

Description

TECHNICAL FIELD

[0001] The present invention relates to an electronic circuit, and more particularly, to a voltage level shifter. BACKGROUND

[0002] Generally, electronic products can design voltage level shifters according to respective requirements, and switch between target operating voltage ranges through the voltage level shifters, so as to achieve various functions. For example, memory devices include voltage level shifters, and perform shifting operations between different voltage values through the voltage level shifters.

[0003] However, in applications (e.g., energy-saving applications) where the voltage value of the power supply voltage is low (e.g., below 1.8 volts), the voltage level shifters cannot effectively perform voltage shifting operations due to the intense voltage fighting on the output end. Thus, the current voltage level shifters are not conducive to implementation in energy-saving applications, and consume too much power, thereby reducing the signal transition speed. SUMMARY

[0004] Embodiments of the present invention provide a voltage level shifter capable of reducing voltage fighting, thereby improving the signal transition speed.

[0005] According to embodiments of the present invention, the voltage level shifter includes a voltage level shifting circuit and a boost circuit. The voltage level shifting circuit operates between a first voltage and a second voltage. The voltage level shifting circuit includes a cross-coupled transistor pair and a differential transistor pair. The differential transistor pair is coupled to the cross-coupled transistor pair and receives an input signal pair. The boost circuit is coupled to the voltage level shifting circuit. The boost circuit is configured to perform a pre-charge operation on a plurality of boost input terminals of the cross-coupled transistor pair, and generate at least one voltage pulse based on a charge pump operation according to at least one control pulse signal, and provide the voltage pulse to the boost input terminals. The control pulse signal is generated corresponding to a transition edge of the input signal pair.

[0006] Based on the above, the voltage level shifter of embodiments of the present invention can improve the voltage value on the boost input terminals by performing a pre-charge operation on the boost input terminals through the boost circuit, thereby reducing voltage fighting. The voltage level shifter can also protect the voltage level shifting circuit by providing the voltage pulse to the boost input terminals based on the charge pump operation through the boost circuit, thereby enabling implementation in energy-saving applications, and further reducing voltage fighting, thereby accelerating the signal transition speed. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a block diagram of a voltage level shifter according to an embodiment of the present invention;

[0008] Figure 2 is a circuit diagram of a voltage level shifter according to an embodiment of the present application;

[0009] Figure 3 is a schematic diagram of the operation of a voltage level shifter according to an embodiment of the present application; Figure 2

[0010] Figure 4 is a circuit diagram of a voltage level shifter according to another embodiment of the present application;

[0011] Figure 5 is a schematic diagram of the operation of a voltage level shifter according to another embodiment of the present application. Figure 4

[0012] BRIEF DESCRIPTION OF DRAWINGS

[0013] 100, 200, 400: voltage level shifter

[0014] 110, 210, 410: voltage level shifting circuit

[0015] 111, 211, 411: cross-coupled transistor pair

[0016] 112, 212, 412: differential transistor pair

[0017] 120, 220, 420: boost circuit

[0018] 221: first boost block

[0019] 222: second boost block

[0020] 230, 430: inverter

[0021] VCC: power supply voltage

[0022] C1-C2, C41: capacitor

[0023] CS: control pulse signal

[0024] IN: input signal pair

[0025] IN1: first input signal

[0026] IN2: second input signal

[0027] M1-M8, M41: transistor

[0028] N1: first boost input terminal

[0029] N2: second boost input terminal

[0030] ​​N3: first reference input;

[0031] N4: second reference input;

[0032] N5-N6: nodes;

[0033] O / P: output voltage;

[0034] O / PN: voltage at node N5;

[0035] PD: control pulse signal;

[0036] PS: voltage pulse;

[0037] t0-t2: time;

[0038] V1: first voltage value;

[0039] V2: second voltage value;

[0040] V3: third voltage value;

[0041] Vboost: voltage at first boost input and second boost input;

[0042] VH: first voltage;

[0043] VM1: voltage at first boost input;

[0044] VM2: voltage at second boost input;

[0045] VSS: second voltage. DETAILED DESCRIPTION

[0046] Referring to Figure 1 , the voltage level shifter 100 can be, for example, a high voltage voltage level shifter. The voltage level shifter 100 can be implemented in an application where the voltage value of the supply voltage is low (e.g., below 1.8 volts), such as a power saving application. The aforementioned supply voltage can be, for example, the supply voltage VCC as shown in Figure 2 or Figure 4 , where the voltage value of the supply voltage VCC can be, for example, 1.2 volts. The voltage level shifter 100 can be, for example, a single ended output, and differential input circuit configuration.

[0047] In Figure 1In an embodiment, the voltage level shifter 100 includes a voltage level shifting circuit 110 and a boost circuit 120. The voltage level shifting circuit 110 is coupled to the boost circuit 120. The voltage level shifting circuit 110 is configured to operate between a first voltage VH and a second voltage VSS, such that a voltage level shifting operation is performed between a voltage value of the first voltage VH and a voltage value of the second voltage VSS. The first voltage VH can be, for example, a high supply voltage. The second voltage VSS can be, for example, a low supply voltage.

[0048] In the present embodiment, the voltage level shifting circuit 110 includes a cross-coupled transistor pair 111 and a differential transistor pair 112. The cross-coupled transistor pair 111 is coupled to the differential transistor pair 112. The cross-coupled transistor pair 111 has a plurality of boost input terminals N1-N2. The boost input terminals N1-N2 are coupled to the boost circuit 120. The differential transistor pair 112 receives an input signal pair IN. The input signal pair IN can be, for example, a differential signal configured to drive the differential transistor pair 112.

[0049] In the voltage level shifting operation, the boost circuit 120 performs a pre-charge operation on the plurality of boost input terminals N1-N2 of the cross-coupled transistor pair 111. The boost circuit 120 also generates at least one voltage pulse PS based on a charge pump operation according to at least one control pulse signal CS. That is, the boost circuit 120 is controlled by the control pulse signal CS to perform the charge pump operation to generate the voltage pulse PS corresponding to the control pulse signal CS. The boost circuit 120 provides the voltage pulse PS to the plurality of boost input terminals N1-N2.

[0050] In the present embodiment, the control pulse signal CS is generated corresponding to a transition edge of the input signal pair IN. That is, when the input signal pair IN switches between different voltage levels to generate a rising edge or a falling edge, the control pulse signal CS is generated to drive the boost circuit 120 to perform the charge pump operation.

[0051] It is worth mentioning that by performing the pre-charge operation on the plurality of boost input terminals N1-N2 by the boost circuit 120, the voltage level shifter 100 is able to increase the voltage values on these input terminals N1-N2. Based on the increased voltage values, the pull-down capability of the cross-coupled transistor pair 111 is able to be strengthened, thereby reducing voltage pulling. Furthermore, by providing the voltage pulse PS to the plurality of boost input terminals N1-N2 by the boost circuit 120 based on the charge pump operation, the voltage level shifter 100 is able to reduce voltage pulling and also able to protect the differential transistor pair 112 from being damaged by the first voltage VH. As such, the voltage level shifter 100 is able to be implemented in energy saving applications and is able to speed up the speed of signal transitions.

[0052] Reference is made to Figure 2The voltage level shifter 200 includes a voltage level shifting circuit 210 and a boost circuit 220. The voltage level shifting circuit 210 includes a cross-coupled transistor pair 211 and a differential transistor pair 212. The voltage level shifting circuit 210 and the boost circuit 220 can be deduced by referring to the relevant description of the voltage level shifter 100.

[0053] exist Figure 2 In this embodiment, the boost circuit 220 includes a first boost block 221 and a second boost block 222. The first boost block 221 receives the power supply voltage VCC. The first boost block 221 is coupled to the first boost input terminal N1 of the cross-coupled transistor pair 211. The first boost block 221 is coupled to the first reference input terminal N3 of the differential transistor pair 212. The first boost block 221 receives a first input signal IN1 at the first reference input terminal N3 as a first control pulse signal (i.e., Figure 1 The control pulse signal CS in the embodiment.

[0054] Specifically, the first boost circuit block 221 includes a transistor M1 and a capacitor C1. Transistor M1 can be implemented, for example, as an n-type metal-oxide-semiconductor field-effect transistor (NMOSFET). In this embodiment, transistor M1 is a native transistor. That is, the threshold voltage of transistor M1 is close to zero. In other embodiments, transistor M1 can also be a normal transistor, and the threshold voltage is less than the supply voltage VCC (e.g., ...). Figure 3 The third voltage value V3 is shown.

[0055] In detail, the control terminal (i.e., the gate terminal) and the first terminal (i.e., the first source / drain terminal) of transistor M1 are coupled together and receive the power supply voltage VCC. That is, transistor M1 is in a diode-connected state. The second terminal (i.e., the second source / drain terminal) of transistor M1 is coupled to the first boost input terminal N1 and the first terminal of capacitor C1. The second terminal of capacitor C1 is coupled to the first reference input terminal N3.

[0056] In this embodiment, the second boost block 222 receives the power supply voltage VCC. The second boost block 222 is coupled to the second boost input terminal N2 of the cross-coupled transistor pair 211. The second boost block 222 is coupled to the second reference input terminal N4 of the differential transistor pair 212. The second boost block 222 receives the second input signal IN2 at the second reference input terminal N4 as a second control pulse signal (i.e., Figure 1 The control pulse signal CS in the embodiment.

[0057] In particular, the second voltage boosting block 222 includes a transistor M2 and a capacitor C2. The transistor M2 can be implemented, for example, as an NMOSFET. In the present embodiment, the transistor M2 is a native transistor and has a threshold voltage value close to zero. In other embodiments, the transistor M2 can also be a general transistor and has a threshold voltage value less than the voltage value of the power supply voltage VCC (e.g., the third voltage value V3 as shown below). The following is described with both transistors Ml and M2 as native transistors. Figure 3

[0058] In detail, the control terminal (i.e., the gate terminal) and the first terminal (i.e., the first source / drain terminal) of the transistor M2 are coupled together and receive the power supply voltage VCC. That is, the transistor M2 is in a diode-connected state. The second terminal (i.e., the second source / drain terminal) of the transistor M2 is coupled to the second voltage boosting input terminal N2 and the first terminal of the capacitor C2. The second terminal of the capacitor C2 is coupled to the second reference input terminal N4.

[0059] In the present embodiment, the cross-coupled transistor pair 211 includes a plurality of transistors M3-M6. The transistors M3 and M4 can be implemented, for example, as p-type Metal-Oxide-Semiconductor Field-Effect Transistors (PMOSFETs). The transistors M5 and M6 can be implemented, for example, as NMOSFETs.

[0060] In detail, the first terminal (i.e., the first source / drain terminal) of the transistor M3 receives the first voltage VH. The first terminal (i.e., the first source / drain terminal) of the transistor M4 receives the first voltage VH. The control terminal (i.e., the gate terminal) of the transistor M5 serves as the first voltage boosting input terminal Nl. The first terminal (i.e., the first source / drain terminal) of the transistor M5 is coupled to the second terminal (i.e., the second source / drain terminal) of the transistor M3 and the control terminal (i.e., the gate terminal) of the transistor M4 at a node N5. The second terminal (i.e., the second source / drain terminal) of the transistor M5 is coupled to the differential transistor pair 212.

[0061] Continuing from the above description, the control terminal (i.e., the gate terminal) of the transistor M6 serves as the second voltage boosting input terminal N2. The first terminal (i.e., the first source / drain terminal) of the transistor M6 is coupled to the second terminal (i.e., the second source / drain terminal) of the transistor M4 and the control terminal (i.e., the gate terminal) of the transistor M3 at a node N6. The node N6 serves as the output terminal of the voltage level shifting circuit 210. The second terminal (i.e., the second source / drain terminal) of the transistor M6 is coupled to the differential transistor pair 212.

[0062] ​It should be noted that the pull-down components of the cross-coupled transistor pair 211 (i.e., transistors M5 and M6) are inserted between the pull-up components of the cross-coupled transistor pair 211 (i.e., transistors M3 and M4) and the differential transistor pair 212 as the pull-down components. The transistors M5 and M6 can withstand the first voltage VH, and their threshold voltage values are higher than those of the transistors M7 and M8, and even substantially equal to the voltage value of the power supply voltage VCC (e.g., the third voltage value V3 as shown) if the power supply voltage VCC is a low voltage (e.g., 1.2 V). Figure 3

[0063] In the present embodiment, the differential transistor pair 212 includes a plurality of low-voltage tolerant transistors M7-M8. It should be noted that the plurality of threshold voltage values of the differential transistor pair 212 are respectively lower than the voltage value of the power supply voltage VCC (e.g., the third voltage value V3 as shown). Figure 3 That is, the threshold voltage values of the transistors M7 and M8 are respectively lower than the third voltage value.

[0064] In particular, the differential transistor pair 212 includes a plurality of transistors M7-M8. The transistors M7 and M8 can be implemented, for example, in NMOSFETs.

[0065] In detail, the control terminal (i.e., the gate terminal) of the transistor M7 is the first reference input terminal N3 and receives the first input signal IN1. The first terminal (i.e., the first source / drain terminal) of the transistor M7 is coupled to the second terminal (i.e., the second source / drain terminal) of the transistor M5. The second terminal (i.e., the second source / drain terminal) of the transistor M7 receives the second voltage VSS.

[0066] In succession to the above description, the control terminal (i.e., the gate terminal) of the transistor M8 is the second reference input terminal N4 and receives the second input signal IN2. The first terminal (i.e., the first source / drain terminal) of the transistor M8 is coupled to the second terminal (i.e., the second source / drain terminal) of the transistor M6. The second terminal (i.e., the second source / drain terminal) of the transistor M8 receives the second voltage VSS.

[0067] In the present embodiment, the voltage level shifter 200 further includes an inverter 230. The first terminal (i.e., the input terminal) of the inverter 230 is coupled to the control terminal (i.e., the first reference input terminal N3) of the transistor M7. The second terminal (i.e., the output terminal) of the inverter 230 is coupled to the control terminal (i.e., the second reference input terminal N4) of the transistor M8. That is, the inverter 230 provides the differential signal pair IN (i.e., the first differential signal IN1 and the second differential signal IN2) with inversions on the first reference input terminal N3 and the second reference input terminal N4.

[0068] Please refer to Figure 2 and​Figure 3 In Figure 3 the horizontal axis is the operating time of the voltage level shifter 200, and the vertical axis is the voltage value. In the present embodiment, the first voltage VH has a first voltage value VI. The second voltage VSS has a second voltage value V2. The power supply voltage VCC has a third voltage value V3. The first voltage value VI is greater than the third voltage value V3, and can be, for example, 10 volts (V). The third voltage value V3 is greater than the second voltage value V2, and can be, for example, 1.2 volts. The second voltage value V2 can be, for example, a reference ground voltage value.

[0069] In the present embodiment, the boost circuit 220 performs a pre-charge operation according to the power supply voltage VCC. That is, in different periods corresponding to the shift operation, the boost circuit 220 respectively pre-charges the first boost input terminal N1 and the second boost input terminal N2 to the third voltage value V3 of the power supply voltage VCC. The boost circuit 220 also operates based on a charge pump to respectively boost the first boost input terminal N1 and the second boost input terminal N2 to another voltage value. In this way, the voltage VM1 on the first boost input terminal N1 and the voltage VM2 on the second boost input terminal N2 are respectively switched between the third voltage value V3 and the other voltage value (e.g., twice the third voltage value V3).

[0070] In the shift operation, the voltage level shifter 200 switches the output voltage O / P from a high voltage value (i.e., the first voltage value VI) to a low voltage value (i.e., the second voltage value V2), for example, at time tl.

[0071] In detail, before time tl, the transistor M7 is turned on. The transistor M1 is turned on to perform a pre-charge operation on the first boost input terminal N1 according to the power supply voltage VCC. Since the transistor M1 is a native transistor, the voltage VM1 on the first boost input terminal N1 is pre-charged to a voltage value equal to or substantially equal to the power supply voltage VCC (i.e., the third voltage value V3). Furthermore, the transistor M1 and the capacitor CI operate according to the first differential signal IN1 as a control pulse signal to generate a voltage pulse (i.e., the voltage VM1) on the first boost input terminal N1 corresponding to the first differential signal IN1 based on a charge pump operation. That is, the voltage on the first reference input terminal N3 (i.e., the first differential signal IN1 having the third voltage value V3) is provided to the first boost input terminal N1 through the capacitor CI to make the voltage VM1 equal to or substantially equal to twice the third voltage value V3.

[0072] Similarly, the voltage VM2 on the second boosted input terminal N2 is precharged to a voltage value (i.e., the third voltage value V3) equal to or substantially equal to the supply voltage VCC by the transistor M2. Moreover, since the second differential signal IN2 has the second voltage value V2 (i.e., the reference ground voltage value), the voltage VM2 on the second boosted input terminal N2 is maintained at the third voltage value V3.

[0073] At time t1, the first differential signal IN1 switches from the third voltage value V3 to the second voltage value V2. The transistor M7 is turned off under the control of the first differential signal IN1. The second differential signal IN2 switches from the second voltage value V2 to the third voltage value V3. The transistor M8 is turned on under the control of the second differential signal IN2. The transistor M2 and the capacitor C2 operate based on the charge pump operation on the second boosted input terminal N2 to generate a voltage pulse (i.e., the voltage VM2) corresponding to the second differential signal IN2 as the control pulse signal, thereby causing the voltage VM2 on the second boosted input terminal N2 to be pulled up to the third voltage value V3 equal to or substantially equal to twice.

[0074] At this time, the transistor M6 is turned on under the control of the voltage VM2. The output voltage O / P on the node N6 is pulled down to the voltage value of the second voltage VSS (i.e., the second voltage value V2) through the transistors M6 and M8. The transistor M3 is turned on under the control of the output voltage O / P on the node N6 to cause the voltage O / PN on the node N5 to start being pulled up to the voltage value of the first voltage VH (i.e., the first voltage value V1). Until the voltage O / PN on the node N5 is pulled up to the voltage value of the first voltage VH (i.e., the first voltage value V1), the transistor M4 is turned off to end the switching operation.

[0075] It is noted that the voltage VM2 on the second boosted input terminal N2 is precharged to the voltage value of the supply voltage VCC (i.e., the third voltage value V3) by the transistor M2 and further boosted to twice the third voltage value V3 by the capacitor C2. Therefore, in the switching operation, the turned-on capability of the pull-down component (including the transistor M6) in the cross-coupled transistor pair 211 is enhanced, thereby reducing the voltage pull.

[0076] In this way, the pull-down component (including the transistor M6) in the cross-coupled transistor pair 211 and the pull-down component (including the transistor M8) in the differential transistor pair 212 are able to pull down the output voltage O / P to the second voltage value V2 more easily and more quickly, thereby shortening the period during which the transistor M8 is subjected to the first voltage VH. Therefore, the voltage VM2 with twice the third voltage value V3 is able to protect the differential transistor pair 212 from being damaged by the first voltage VH. Moreover, the voltage O / PN on the node N5 is also able to be pulled up to the first voltage value V1 more quickly, thereby speeding up the speed of signal transition.

[0077] The operation of the voltage level shifter 200 at time t2may be referred to the related description of the voltage level shifter 200 at time tl and be analogized.

[0078] It is noted that at time t2, the voltage VM1 on the first boosted input terminal N1 is pre-charged to the voltage value of the supply voltage VCC (i.e., the third voltage value V3) through the transistor M1 and is further boosted to twice the third voltage value V3 through the capacitor Cl. Therefore, in the switching operation, the turn-on ability of the pull-down component (including the transistor M5) in the cross-coupled transistor pair 211 is enhanced, thereby reducing the voltage pull. As a result, the pull-down component (including the transistor M5) in the cross-coupled transistor pair 211 and the pull-down component (including the transistor M7) in the differential transistor pair 212 can more easily and more quickly pull down the voltage O / PN to the second voltage value V2, thereby accelerating the speed of signal transition. In this way, the period during which the transistor M7 bears the first voltage VH can be shortened, thereby avoiding the damage of the differential transistor pair 212 by the first voltage VH.

[0079] Please refer to Figure 4 , the voltage level shifter 400 includes a voltage level shifting circuit 410 and a boosting circuit 420. The voltage level shifting circuit 410 includes a cross-coupled transistor pair 411 and a differential transistor pair 412. The voltage level shifting circuit 410 and the boosting circuit 420 can be referred to the related description of the voltage level shifter 100 and be analogized.

[0080] In Figure 4 the embodiment, the boosting circuit 420 includes a transistor M41 and a capacitor C41. The transistor M41 can be implemented by, for example, an NMOSFET. In the present embodiment, the transistor M41 is a native transistor and has a threshold voltage value close to zero.

[0081] In detail, the control terminal (i.e., the gate terminal) and the first terminal (i.e., the first source / drain terminal) of the transistor M41 are coupled together and receive the supply voltage VCC. That is, the transistor M41 is in a diode-connected state. The second terminal (i.e., the second source / drain terminal) of the transistor M41 is coupled to the first boosted input terminal N1, the second boosted input terminal N2, and the first terminal of the capacitor C41. The second terminal of the capacitor C41 receives the control pulse signal PD.

[0082] In this embodiment, the cross-coupled transistor pair 411 includes a plurality of transistors M3-M6. The differential transistor pair 412 includes a plurality of transistors M7-M8. The voltage level shifter 400 also includes an inverter 430. The transistors M3-M6, the transistors M7-M8, and the inverter 430 can be referred to the related descriptions of the voltage level shifter 200 and be analogized.

[0083] Please refer to Figure 4 and Figure 5 , in Figure 5 , the horizontal axis is the operation time of the voltage level shifter 400, and the vertical axis is the voltage value.

[0084] Compared with Figure 2 and Figure 3 the shift operation, before the time t1, the transistor M41 is turned on to perform a pre-charge operation on the first boost input terminal N1 and the second boost input terminal N2 according to the power supply voltage VCC. Since the transistor M41 is a native transistor, the voltage Vboost on the first boost input terminal N1 and the second boost input terminal N2 is pre-charged to a voltage value equal to or substantially equal to the power supply voltage VCC (i.e., the third voltage value V3).

[0085] In addition, the transistor M41 and the capacitor C41 are based on the charge pump operation to generate a voltage pulse (i.e., the voltage Vboost) corresponding to the control pulse signal PD on the first boost input terminal N1 and the second boost input terminal N2, respectively. That is, the control pulse signal PD with the second voltage value V2 (i.e., the reference ground voltage value) is provided to the first boost input terminal N1 and the second boost input terminal N2 through the capacitor C41, so that the voltage Vboost is maintained at the third voltage value V3.

[0086] At the time t1, the first differential signal IN1 is switched from the third voltage value V3 to the second voltage value V2. The transistor M7 is turned off under the control of the first differential signal IN1. The second differential signal IN2 is switched from the second voltage value V2 to the third voltage value V3. The transistor M8 is turned on under the control of the second differential signal IN2.

[0087] It should be noted that the control pulse signal PD is generated corresponding to the rising edge of the second differential signal IN2 (i.e., the falling edge of the first differential signal IN1) to switch from the second voltage value V2 to the third voltage value V3. The transistor M41 and the capacitor C41 are based on the charge pump operation to generate a voltage pulse (i.e., the voltage Vboost) corresponding to the second differential signal IN2 on the first boost input terminal N1 and the second boost input terminal N2, respectively, so that the voltage Vboost is pulled up to equal to or substantially equal to twice the third voltage value V3.

[0088] At this time, the transistors M5 and M6 are turned on under the control of the voltage Vboost. The output voltage O / P on the node N6 is pulled down to the voltage value of the second voltage VSS (i.e., the second voltage value V2) through the transistors M6 and M8. Then, the transistor M3 is turned on according to the output voltage O / P on the node N6, so that the voltage O / PN on the node N5 starts to be pulled up to the voltage value of the first voltage VH (i.e., the first voltage value V1). Until the voltage O / PN on the node N5 is pulled up to the voltage value of the first voltage VH (i.e., the first voltage value V1), the transistor M4 is turned off to end the switching operation.

[0089] It should be noted that the voltage Vboost on the first boost input N1 and the second boost input N2 is pre-charged to the voltage value of the power supply voltage VCC (i.e., the third voltage value V3) through the transistor M41, and is further boosted to twice the third voltage value V3 through the capacitor C41. Therefore, in the switching operation, the pull-down path (i.e., the discharge path) between the pull-down component (including the transistor M6) in the cross-coupled transistor pair 411 and the second voltage value V2 and the pull-down component (including the transistor M8) in the differential transistor pair 412 is enhanced, thereby reducing the voltage pull.

[0090] In this way, the pull-down component (including the transistor M6) in the cross-coupled transistor pair 411 and the pull-down component (including the transistor M8) in the differential transistor pair 412 can more easily and quickly pull down the output voltage O / P to the second voltage value V2, thereby shortening the period during which the transistor M8 is subjected to the first voltage VH. Therefore, the voltage Vboost with twice the third voltage value V3 can protect the differential transistor pair 412 from being damaged by the first voltage VH. In addition, the voltage O / PN on the node N5 can also be more quickly pulled up to the first voltage value V1, thereby accelerating the speed of signal transition.

[0091] The operation of the voltage level shifter 400 at time t2 can be referred to the related description of the voltage level shifter 400 at time t1 and be analogized.

[0092] In summary, the voltage level shifter of the embodiment of the present application can be applied in the situation where the voltage value of the power supply voltage is low. By performing the pre-charging operation on the plurality of boost inputs through the boost circuit and boosting the plurality of boost inputs again based on the charge pump operation, the voltage level shifter can reduce the voltage pull, thereby accelerating the speed of signal transition, and also can protect the differential transistor pair from being damaged by the high power supply voltage (i.e., the first voltage).

[0093] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit the present application; although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications can be made to the technical solutions described in the above embodiments, or some or all of the technical features can be replaced by equivalent replacements; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A voltage level shifter, characterized in that, include: A voltage level shifting circuit, operating between a first voltage and a second voltage, includes a cross-coupled transistor pair and a differential transistor pair, wherein the differential transistor pair is coupled to the cross-coupled transistor pair and receives an input signal pair; as well as A boost circuit, coupled to the voltage level shift circuit, is used to perform a pre-charge operation on the plurality of boost inputs of the cross-coupled transistor pair, and to generate at least one voltage pulse based on charge pump operation according to at least one control pulse signal, and to provide the at least one voltage pulse to the plurality of boost inputs. The at least one control pulse signal is generated in accordance with the transition edge of the input signal pair.

2. The voltage level shifter according to claim 1, characterized in that, The boost circuit performs a pre-charge operation based on the power supply voltage, wherein the power supply voltage has a third voltage value.

3. The voltage level shifter according to claim 2, characterized in that, The critical voltage values ​​of the differential transistor pair are each less than the third voltage value.

4. The voltage level shifter according to claim 1, characterized in that, The differential transistor pair includes multiple low-voltage-tolerance transistors.

5. The voltage level shifter according to claim 1, characterized in that, The boost circuit includes: The first boost block is coupled to the first boost input terminal of the cross-coupled transistor pair and coupled to the first reference input terminal of the differential transistor pair to receive a first input signal as a first control pulse signal; and The second boost block is coupled to the second boost input of the cross-coupled transistor pair and to the second reference input of the differential transistor pair to receive a second input signal as a second control pulse signal.

6. The voltage level shifter according to claim 5, characterized in that, The first boost block includes: A first transistor has a control terminal and a first terminal for receiving a power supply voltage; and A first capacitor has a first terminal coupled to a second terminal of the first transistor and a first boost input terminal, the second terminal of the first capacitor being coupled to the first reference input terminal.

7. The voltage level shifter according to claim 6, characterized in that, The first transistor is a native transistor.

8. The voltage level shifter according to claim 6, characterized in that, The second boost block includes: The second transistor has a control terminal and a first terminal for receiving the power supply voltage; and The second capacitor has a first terminal coupled to the second terminal of the second transistor and the second boost input terminal, and the second terminal of the second capacitor is coupled to the second reference input terminal.

9. The voltage level shifter according to claim 8, characterized in that, The second transistor is a native transistor.

10. The voltage level shifter according to claim 1, characterized in that, The boost circuit includes: A first transistor has a control terminal and a first terminal for receiving a power supply voltage; and A first capacitor has a first terminal coupled to a second terminal of the first transistor, a first boost input terminal of the cross-coupled transistor pair, and a second boost input terminal of the cross-coupled transistor pair, wherein the second terminal of the second capacitor receives the at least one control pulse signal.

11. The voltage level shifter according to claim 10, characterized in that, The first transistor is a native transistor.

12. The voltage level shifter according to claim 1, characterized in that, The cross-coupled transistor pair includes: A first transistor has a first terminal that receives the first voltage; The second transistor has a first terminal that receives the first voltage; A third transistor has a control terminal serving as a first boost input terminal. A first terminal of the third transistor is coupled to a second terminal of the first transistor and the control terminal of the second transistor. The second terminal of the third transistor is coupled to the differential transistor pair. The fourth transistor has a control terminal as a second boost input terminal, a first terminal of the fourth transistor is coupled to the second terminal of the second transistor and the control terminal of the first transistor, and the second terminal of the fourth transistor is coupled to the differential transistor pair.

13. The voltage level shifter according to claim 12, characterized in that, The differential transistor pair includes: A fifth transistor has a control terminal that receives a first input signal, a first terminal of the fifth transistor coupled to a second terminal of the third transistor, and a second terminal of the fifth transistor receiving the second voltage; and The sixth transistor has a control terminal that receives a second input signal, a first terminal of the sixth transistor that is coupled to a second terminal of the fourth transistor, and a second terminal of the sixth transistor that receives the second voltage.

14. The voltage level shifter according to claim 13, characterized in that, Also includes: An inverter having a first terminal coupled to the control terminal of the fifth transistor, and a second terminal coupled to the control terminal of the sixth transistor.

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