Flexible direct current transmission control protection system and communication control method thereof
By configuring the local clock reference and determining the frame gap, combined with the bare MAC frame injection and static MAC binding mechanism, the clock phase jitter problem in the flexible DC transmission control and protection system was solved, and stable transmission with low bit error rate was achieved.
Patent Information
- Application Number
- CN202511747932.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-26
- Publication Date
- 2026-04-10
AI Technical Summary
The flexible DC transmission control and protection system suffers from clock phase jitter, which causes timing shifts in the rising/falling edges of the signal and results in a high bit error rate.
By configuring a local clock reference, determining the frame gap, and presetting the frame structure, the TCP/IP protocol stack is bypassed, and a raw MAC frame injection and static MAC binding mechanism are used to perform timing control and scheduling of transmission.
It achieves consistent transmission frame timing, reduces bit error rate, and meets the real-time and reliability requirements of flexible DC transmission systems.
Smart Images
Figure CN121841572A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application belongs to the technical field of flexible direct current transmission control, and particularly relates to a flexible direct current transmission control protection system and a communication control method thereof. BACKGROUND
[0002] The synchronization precision of the flexible direct current transmission control protection structure is insufficient, and clock phase jitter can cause signal rising / falling edge timing offset, so that the sampling point of the receiving end deviates and the bit error rate significantly rises. SUMMARY
[0003] In order to overcome the deficiencies of the prior art, in a first aspect, the application provides a communication method of a flexible direct current transmission control protection system, comprising: Based on the transmission requirement of the to-be-transmitted data in the flexible direct current transmission control protection system, a local clock reference is configured, and the frame gap of the to-be-transmitted data in the Ethernet is determined. Based on the to-be-transmitted data, a plurality of data frames are generated in combination with the frame gap and a preset frame structure. The plurality of data frames are encapsulated into corresponding plurality of transmission frames through a bare MAC frame injection and a static MAC binding mechanism by bypassing the TCP / IP protocol stack. The plurality of transmission frames are scheduled and transmitted by using a timing control mechanism.
[0004] Preferably, the local clock reference configuration based on the transmission requirement of the to-be-transmitted data in the flexible direct current transmission control protection system comprises: Based on the clock accuracy requirement in the transmission requirement of the to-be-transmitted data in the flexible direct current transmission control protection system and the clock of the Ethernet, a phase-locked loop of an FPGA is used to lock the phase and output a phase-shifted clock to complete the local clock reference configuration; the phase-shifted clock is used to compensate the timing offset during the transmission in the Ethernet.
[0005] Preferably, the determination of the frame gap of the to-be-transmitted data in the Ethernet based on the transmission requirement of the to-be-transmitted data in the flexible direct current transmission control protection system comprises: Based on the clock reference after the phase locking by the phase-locked loop, the initial frame gap of the to-be-transmitted data in the Ethernet is determined. A counter is used to control each initial frame gap to maintain at a preset minimum frame interval to form a final frame gap.
[0006] Preferably, the preset process of the frame structure comprises: Based on the current communication period and the IFG time, an effective data sending window is determined. Based on the effective data sending window, the length of the data payload field is determined. determine a frame structure of a bare MAC frame injection based on the length of the data payload field; The frame structure comprises the following fields: a preamble field, a start-of-frame delimiter field, a MAC header field, a data payload field, and a frame check sequence field. If the communication period is 50μs, the length of the preamble field is 7 bytes, the length of the start-of-frame delimiter field is 1 byte, the length of the MAC header field is 14 bytes, the length of the data payload field is 5050 bytes, and the length of the frame check sequence field is 4 bytes.
[0007] Preferably, the generating a plurality of data frames based on the data to be transmitted and in combination with the frame gap and a preset frame structure comprises: controlling the data timing alignment before and after each frame gap based on the data to be transmitted to form a plurality of groups of timing-aligned data to be transmitted; and encapsulating each group of timing-aligned data to be transmitted into a data frame according to the preset frame structure to generate a plurality of data frames.
[0008] Preferably, the scheduling transmission of the plurality of transmission frames using a timing control mechanism comprises: performing CRC32 checking on the plurality of transmission frames to obtain a checking result; performing a direct discarding and non-retransmission operation on an erroneous transmission frame in the checking result; performing a pre-caching mechanism on a correct transmission frame in the checking result to inject the correct transmission frame into a sending queue for scheduling transmission.
[0009] Preferably, after the scheduling transmission of the plurality of transmission frames using the timing control mechanism, the method further comprises: performing jitter filtering processing on each transmission frame according to a preset jitter threshold. After the transmission of any transmission frame ends, a preset length of idle bytes is inserted to avoid collision between transmission frames.
[0010] Preferably, the encapsulating each group of timing-aligned data to be transmitted into a data frame according to the preset frame structure to generate a plurality of data frames comprises: performing byte number detection on each group of timing-aligned data to be transmitted to obtain a detection result; if the detection result is that the byte number length of the data to be transmitted is less than a preset byte number, filling non-data bits of the data to be transmitted with padding bytes to the preset byte number, and then encapsulating the data to be transmitted into a data frame; if the detection result is that the byte number length of the data to be transmitted is equal to or greater than the preset byte number, encapsulating the data to be transmitted into a data frame.
[0011] In a second aspect, the present application also provides a flexible DC power transmission control and protection system, comprising: a sending end and a receiving end; the sending end is integrated with a plurality of control system hosts and a plurality of protection system hosts; The sending end is configured to: based on the transmission requirements of the to-be-transmitted data in the flexible DC power transmission control and protection system, configure a local clock reference, and determine the interframe gap of the to-be-transmitted data in the Ethernet, based on the to-be-transmitted data, generate a plurality of data frames in combination with the interframe gap and a preset frame structure, bypass the TCP / IP protocol stack, encapsulate the plurality of data frames into a plurality of transmission frames through a bare MAC frame injection and static MAC binding mechanism, and adopt a timing control mechanism to schedule and transmit the plurality of transmission frames. The receiving end is configured to adopt a timing control mechanism to receive and process the plurality of transmission frames from the sending end.
[0012] Preferably, the sending end is specifically configured to: Based on the clock accuracy requirement in the transmission requirements of the to-be-transmitted data in the flexible DC power transmission control and protection system and the clock of the Ethernet, the phase is locked through the phase-locked loop of the FPGA, and a phase-shift clock is outputted to complete the local clock reference configuration; the phase-shift clock is used to compensate for the timing offset during transmission in the Ethernet.
[0013] Preferably, the sending end is specifically configured to: Based on the clock reference after the phase is locked through the phase-locked loop, the initial interframe gap of the to-be-transmitted data in the Ethernet is determined. A counter is adopted to control each initial interframe gap to maintain a preset minimum frame interval to form a final interframe gap.
[0014] Preferably, the preset process of the frame structure comprises: Based on the current communication period and the IFG time, an effective data transmission window is determined. Based on the effective data transmission window, the length of the data payload field is determined. Based on the length of the data payload field, the frame structure of the bare MAC frame injection is determined. The frame structure comprises the following fields: a preamble field, a start delimiter field, a MAC header field, a data payload field, and a frame check sequence field. If the communication period is 50 μs, the length of the preamble field is 7 bytes, the length of the start delimiter field is 1 byte, the length of the MAC header field is 14 bytes, the length of the data payload field is 5050 bytes, and the length of the frame check sequence field is 4 bytes.
[0015] Preferably, the sending end is specifically used for: Based on the to-be-transmitted data, the data timing alignment before and after each of the frame gaps is controlled to form a plurality of groups of timing-aligned to-be-transmitted data; and each group of the timing-aligned to-be-transmitted data is encapsulated as a data frame according to a preset frame structure, so as to generate a plurality of data frames.
[0016] Preferably, the sending end is specifically used for: The CRC32 is enabled for the plurality of transmission frames to obtain a check result; The transmission frame with error in the check result is directly discarded and not retransmitted; The transmission frame with error in the check result is directly discarded and not retransmitted;
[0017] Preferably, the sending end is further used for: for each of the transmission frames, jitter filtering processing is performed according to a preset jitter threshold; After transmission of any one of the transmission frames ends, a preset length of idle bytes is inserted to avoid collision between the transmission frames.
[0018] Preferably, the sending end is specifically used for: The to-be-transmitted data in each group is subjected to byte number detection to obtain a detection result; If the detection result is that the byte number length of the to-be-transmitted data is less than the set byte number, the non-data bits of the to-be-transmitted data are filled with padding bytes to the set byte number, and then the to-be-transmitted data is encapsulated as a data frame; If the detection result is that the byte number length of the to-be-transmitted data is equal to or greater than the set byte number, the to-be-transmitted data is encapsulated as a data frame.
[0019] In a third aspect, the present application further provides an electronic device, comprising: at least one processor and a memory; the memory and the processor are connected through a bus; The memory is used for storing one or more programs; When the one or more programs are executed by the at least one processor, the communication control method of the flexible direct current power transmission control and protection system is implemented.
[0020] In a fourth aspect, the present application further provides a readable storage medium, which has an execution program stored thereon, and when the execution program is executed, the communication control method of the flexible direct current power transmission control and protection system is implemented.
[0021] Compared with the closest prior art, the present application has the following beneficial effects: This invention discloses a flexible DC transmission control and protection system and its communication control method. Based on the transmission requirements of the data to be transmitted in the flexible DC transmission control and protection system, it configures a local clock reference and determines the frame interval for the data to be transmitted in the Ethernet. Based on the data to be transmitted, combined with the frame interval and a preset frame structure, multiple data frames are generated. By bypassing the TCP / IP protocol stack, the multiple data frames are encapsulated into corresponding multiple transmission frames through raw MAC frame injection and static MAC binding mechanisms. A timing control mechanism is used to schedule the transmission of the multiple transmission frames. By configuring the clock reference and the frame interval, the multiple data frames, after passing through the raw MAC frame injection and static MAC binding mechanisms, form transmission frames with identical timing, ensuring stable transmission. This overcomes the signal rising / falling edge timing offset caused by clock phase jitter, ensuring no deviation in the sampling point at the receiving end and reducing the bit error rate. Attached Figure Description
[0022] Figure 1 A flowchart of a communication control method for a flexible DC transmission control and protection system provided in this application; Figure 2 An architecture diagram of a flexible DC transmission control and protection system provided in this application; Figure 3 A specific use case architecture diagram of a flexible DC transmission control and protection system provided in this invention application; Figure 4 This is a schematic diagram of the operation of an electronic device provided in this invention application. Detailed Implementation
[0023] The specific embodiments of this invention will be further described in detail below with reference to the accompanying drawings.
[0024] Example 1: like Figure 1 As shown, this invention application proposes a communication control method for a flexible DC transmission control and protection system, which may include: Step 1: Based on the transmission requirements of the data to be transmitted in the flexible DC transmission control and protection system, configure the local clock reference and determine the frame interval for the data to be transmitted in the Ethernet. Step 2: Based on the data to be transmitted, combined with the inter-frame gap and the preset frame structure, generate multiple data frames; Step 3: Bypass the TCP / IP (Transmission Control Protocol / Internet Protocol) protocol stack, and encapsulate the multiple data frames into multiple corresponding transmission frames through raw MAC (Media Access Control) frame injection and static MAC binding mechanism; Step 4: Use a timing control mechanism to schedule the transmission of the multiple transmission frames.
[0025] In step 1 above, configuring the local clock reference based on the transmission requirements of the data to be transmitted in the flexible DC transmission control and protection system includes: Based on the clock accuracy requirements of the data to be transmitted in the flexible DC transmission control and protection system, and the Ethernet clock, the phase is locked by the phase-locked loop of the FPGA (Field Programmable Gate Array) to output a phase-shifted clock and complete the local clock reference configuration; the phase-shifted clock is used to compensate for the timing offset during transmission in Ethernet.
[0026] The Ethernet mentioned above can be Gigabit Ethernet, and its clock can be a 125MHz clock (period 8ns). After the phase is locked by the FPGA's PLL (Phase Locked Loop), the time base error is determined to be ≤±100ppm, and the phase-shifted clock is output to complete the local clock base configuration (125MHz clock).
[0027] In step 1 above, determining the frame interval for transmitting the data to be transmitted in the Ethernet based on the transmission requirements of the data to be transmitted in the flexible DC transmission control and protection system includes: Step 1.1: Based on the clock reference after the phase is locked by the phase-locked loop, determine the initial inter-frame gap for the data to be transmitted in the Ethernet. Step 1.2: Use a counter to control each initial frame gap to maintain at a preset minimum frame gap, thus forming the final frame gap.
[0028] As mentioned above, the preset minimum frame interval can be set to 96-bit time (9.6ns) to control the frame gap, so that the frame gap is forced to maintain the minimum frame interval at 96-bit time (9.6ns). Specifically, the inter-frame idle time can be strictly controlled by a hardware counter to achieve precise control of the inter-frame gap (IFG).
[0029] Furthermore, the frame structure preset process in step 2 above includes: Step A: Determine the effective data transmission window based on the current communication cycle and IFG time; Step B: Determine the length of the data payload field based on the valid data transmission window; Step C: Determine the frame structure for injecting the raw MAC frame based on the length of the data payload field; The frame structure includes the following fields: preamble field, startFrameDelimiter field (SOF), MAC header field, data payload field, and frame check sequence field (FCS). Step D: If the communication period is 50μs, the length of the preamble field is 7 bytes, the length of the start-of-frame delimiter field is 1 byte, the length of the MAC header field is 14 bytes, the length of the data payload field is 5050 bytes, and the length of the frame check sequence field is 4 bytes.
[0030] As mentioned above, the current communication period can be 50μs. After deducting the IFG time, the effective data transmission window is 40.4μs. The length of the data payload field needs to be calculated as follows:
[0031] When the actual data payload is insufficient, the actual data payload needs to be adjusted according to the protocol header and footer, which can be filled with extension bits between data.
[0032] Further, in step 2 above, generating multiple data frames based on the data to be transmitted, combined with the inter-frame gap and a preset frame structure, includes: Step 2.1: Based on the data to be transmitted, control the timing alignment of the data before and after each frame gap to form multiple sets of timing-aligned data to be transmitted; Step 2.2: According to the preset frame structure, encapsulate each set of timing-aligned data to be transmitted into a data frame, thereby generating multiple data frames.
[0033] As described above, by accurately measuring the inter-frame interval time, the timing of the data before and after each inter-frame interval is aligned, thus achieving the function of timing alignment of data before and after the inter-frame interval. This allows for accurate communication cycle timing control without using the IEEE (Institute of Electrical and Electronics Engineers) 1588 time protocol.
[0034] Further, in step 2.2 above, the step of encapsulating each group of time-aligned data to be transmitted into a data frame according to a preset frame structure, thereby generating multiple data frames, includes: Step 2.2.1: Perform byte count detection on each group of time-aligned data to be transmitted to obtain the detection result; Step 2.2.2: If the detection result indicates that the length of the data to be transmitted is less than the set number of bytes, then the non-data bits of the data to be transmitted are padded with padding bytes until the set number of bytes is reached, and then it is encapsulated into a data frame. Step 2.2.3: If the detection result is that the length of the number of bytes of the data to be transmitted is equal to or greater than the set number of bytes, then the data to be transmitted is encapsulated into a data frame.
[0035] The example above shows that the number of bytes can be 512 bytes. When the length of the data to be transmitted is less than 512 bytes, padding bytes (frame extension technology) are used to fill the non-data bits to 512 bytes, ensuring that the transmission time of a single frame is constant at 5.12μs (512×8bit÷1Gbps).
[0036] Furthermore, in step 4 above, the use of a timing control mechanism to schedule the transmission of the multiple transmission frames includes: Step 4.1: Perform CRC32 verification on the multiple transmission frames to obtain the verification results; Step 4.2: For the transmission frames with errors in the verification results, perform the operation of directly discarding them without retransmission; Step 4.3: For the correct transmission frames in the verification results, a pre-buffering mechanism is used to inject the correct transmission frames into the sending queue for scheduled transmission.
[0037] As mentioned above, when implementing the pre-buffer, a Synchronous Dynamic Random Access Memory (SDRAM) can be introduced for caching. The correct transmission frames can be injected into the transmission queue in advance, which can avoid the processing delay of scheduled transmission and form a data pipeline.
[0038] Furthermore, after the timing control mechanism is used to schedule the transmission of the multiple transmission frames, the method further includes: Step 5.1: For each transmission frame, jitter filtering is performed according to a preset jitter threshold; Step 5.2: After any of the transmission frames has finished transmitting, insert a pre-set length of idle bytes to avoid collisions between transmission frames.
[0039] As mentioned above, when performing jitter filtering, the RGMII (Reduced Gigabit Media Independent Interface) interface of the Ethernet connection can be sampled on both edges (using ODDR (Output Double Data Rate) and IDDR (Input Double Data Rate) (control signal is sent on the rising edge and data is sent on the falling edge). Based on the sampling results, jitter filtering is performed on each transmission frame according to a preset jitter threshold, ensuring that the processing error is <±1ns. Therefore, periodic jitter within 50μs±0.2μs can be achieved.
[0040] This invention, based on an FPGA hardware platform, constructs a deterministic communication channel through local high-precision clock reference configuration, fixed frame gap control, and a custom Jumbo Frame structure. The core lies in bypassing the non-real-time TCP / IP protocol stack, employing a raw MAC frame injection and static MAC binding mechanism, combined with time-aware shaping scheduling, to achieve nanosecond-level precision scheduling of data frames. Testing has shown that this method can achieve end-to-end transmission cycles within 50μs ± 0.2μs with a low bit error rate, effectively meeting the stringent requirements of flexible DC transmission systems for real-time performance, reliability, and determinism.
[0041] In specific implementation of this invention, the high-speed transmission characteristics of the fiber optic gigabit Ethernet physical layer can be utilized to achieve 1Gbps communication capability on a hardware platform integrating standard MAC IP cores from mainstream FPGA manufacturers, through the architecture of FPGA+RGMII interface PHY chips (such as 88E1111 / 88E1512). The hardware layer employs a PHY-forced gigabit full-duplex configuration (register 0x00=0x0140 disables auto-negotiation), coupled with RGMII timing compensation (IDELAY input delay adjustment ±0.15ns); the protocol layer bypasses the TCP / IP protocol stack, eliminating ARP (Address Resolution Protocol) broadcast overhead through raw MAC frame injection (custom EtherType 0xBEEF) and static MAC binding; the frame structure is designed to extend the payload to 5040 bytes (which can be based on a Jumbo Frame, minus 18 bytes of header and footer), and fix IFG=12 bytes (96ns) to avoid dynamic jitter adjustment; in terms of timing control, it relies on the FPGA hard-core MAC to achieve ns-level scheduling (Time-Aware Shaper), with a measured end-to-end delay of 50μs±200ns (oscilloscope calibration). After 72 hours of BERT testing, the system's bit error rate is less than 1E-12, with a theoretical throughput of 806.4Mbps (5040B / 50μs) and an actual effective throughput of 98.4Mbps (excluding protocol overhead). The core advantage of using jumbo frames is that, compared to the standard 1518-byte Ethernet frame, it can significantly improve the effective data transmission efficiency and reduce the proportion of protocol overhead, thereby maximizing throughput within a fixed 50μs communication cycle, meeting the requirements of industrial-grade hard real-time communication, and reducing costs by more than 30%.
[0042] Compared with the prior art, the present invention also has the following beneficial effects: (1) Achieve period jitter control within 50μs±0.2μs (4 orders of magnitude better than millisecond-level jitter in ordinary Ethernet); (2) In scenarios such as power synchronization control, it can replace dedicated industrial buses (e.g., Ethernet EtherCAT used for control automation technology), reducing costs by more than 30%; (3) It provides a technical solution that is different from that of this industry.
[0043] In existing technologies, the internal communication mechanism of flexible DC transmission control and protection systems is the core to ensure reliable system operation. Significant differences exist in the technical solutions of major domestic and international manufacturers: ABB (Hierarchical Architecture) adopts a layered architecture, with the control layer using a bus-based (Versa Module Eurocard, VME) real-time controller with a communication cycle as low as 50μs. The protection layer transmits sampled values via IEC (Communication Networks and Systems for Power Utility Automation) 61850-9-2, with a latency of <100μs. Another technology achieves multi-converter synchronization with jitter control within ±200ns. Yet another technology uses the PROFINETIRT (Process Field Network) protocol, with a control cycle of 100μs and protection action time <2ms. A unique feature is the use of Time Sensitive Networking (TSN) technology, achieving sub-microsecond clock synchronization via IEEE (Institute of Electrical and Electronics Engineers) 802.1AS. Among domestic manufacturers, one technology utilizes a dedicated communication chip developed based on domestically produced FPGAs, achieving a control cycle of 100μs and a protection command transmission delay of <500μs. Its innovation lies in a hybrid "dual-ring network + star" topology, achieving a reliability of 99.9999%. Another technology offers a configurable control cycle of 50-200μs and a GOOSE (Generic Object Oriented Substation Event) message transmission delay of <250μs. This technology achieves deterministic transmission over 1Gbps Ethernet through a combination of Gigabit Ethernet communication architecture and the IEEE 1588v2 time synchronization protocol (PTP). Yet another technology achieves precise time synchronization through hardware timestamps, with a control cycle of 100μs and a protection action time of <3ms. Its key feature is the integration of a 5G communication module into the control and protection system. Finally, a technology employs a direct fiber optic connection architecture, achieving a control cycle of 25μs, but only supports point-to-point communication, limiting its scalability. Overall, foreign manufacturers lead in communication protocol standardization, while domestic manufacturers have an advantage in customized hardware and topology innovation. All systems comply with the IEC 61850 standard, but their implementation paths differ significantly.
[0044] This invention relates to a communication transmission method based on a novel Gigabit Ethernet communication platform. The Gigabit Ethernet technology involved can be extended to industrial control applications beyond this field. This technology, based on traditional Gigabit Ethernet communication, also achieves precise communication cycle control, realizing two communication cycles: (50µs) ± 0.2µs and (1ms) ± 5µs.
[0045] Example 2: like Figure 2 As shown, the present invention also provides a flexible DC transmission control and protection system, including: a transmitting end and a receiving end; the transmitting end integrates multiple control system hosts and multiple protection system hosts; The transmitting end is used to configure a local clock reference and determine the frame gap for the data to be transmitted in the Ethernet based on the transmission requirements of the data to be transmitted in the flexible DC transmission control and protection system, through the multiple control system hosts and the multiple protection system hosts; generate multiple data frames based on the data to be transmitted, combined with the frame gap and a preset frame structure; bypass the TCP / IP protocol stack and encapsulate the multiple data frames into corresponding multiple transmission frames through raw MAC frame injection and static MAC binding mechanisms; and schedule the transmission of the multiple transmission frames using a timing control mechanism. The receiving end is used to receive and process multiple transmission frames from the sending end using a timing control mechanism.
[0046] Furthermore, the sending end is specifically used for: Based on the clock accuracy requirements of the data to be transmitted in the flexible DC transmission control and protection system, and the Ethernet clock, the phase is locked by the phase-locked loop of the FPGA, and a phase-shifted clock is output to complete the local clock reference configuration; the phase-shifted clock is used to compensate for the timing offset during transmission in Ethernet.
[0047] Furthermore, the sending end is specifically used for: Based on the clock reference after the phase is locked by the phase-locked loop, the initial inter-frame gap for the data to be transmitted in the Ethernet is determined. A counter is used to control each initial frame gap to maintain at a preset minimum frame gap, thus forming the final frame gap.
[0048] Furthermore, the preset process of the frame structure includes: Determine the effective data transmission window based on the current communication cycle and IFG time; Based on the effective data transmission window, determine the length of the data payload field; The frame structure for injecting a raw MAC frame is determined based on the length of the data payload field. The frame structure includes the following fields: preamble field, start-of-frame delimiter field, MAC header field, data payload field, and frame check sequence field; If the communication period is 50μs, the length of the preamble field is 7 bytes, the length of the start-of-frame delimiter field is 1 byte, the length of the MAC header field is 14 bytes, the length of the data payload field is 5050 bytes, and the length of the frame check sequence field is 4 bytes.
[0049] Furthermore, the sending end is specifically used for: Based on the data to be transmitted, the timing alignment of the data before and after each frame gap is controlled to form multiple sets of timing-aligned data to be transmitted; according to the preset frame structure, each set of timing-aligned data to be transmitted is encapsulated into a data frame, thereby generating multiple data frames.
[0050] Furthermore, the sending end is specifically used for: For the multiple transmission frames, CRC32 is used for verification to obtain the verification result; For any erroneous transmission frames in the verification results, the operation is to discard them directly without retransmission. For the correct transmission frames in the verification results, a pre-buffering mechanism is used to inject the correct transmission frames into the sending queue for scheduled transmission.
[0051] Furthermore, the transmitting end is also configured to: perform jitter filtering processing on each of the transmission frames according to a preset jitter threshold; After any of the transmission frames has finished transmitting, a pre-defined length of idle bytes is inserted to avoid collisions between transmission frames.
[0052] Furthermore, the sending end is specifically used for: Perform byte count detection on each group of time-aligned data to be transmitted to obtain the detection result; If the detection result indicates that the length of the data to be transmitted is less than the set number of bytes, then the non-data bits of the data to be transmitted are padded with padding bytes until the set number of bytes is reached, and then it is encapsulated into a data frame. If the detection result indicates that the length of the data to be transmitted is equal to or greater than the set number of bytes, then the data to be transmitted is encapsulated into a data frame.
[0053] To illustrate the system of the present invention, a specific use case of the system of the present invention is given as follows: Figure 3 The diagram shows the components and communication architecture. The system includes two control systems and three protection systems, with the following components: (1) Controlling System A: Controlling System A host, controlling System A AI1, controlling System A AI2, controlling System A IO1, controlling System A IO2, controlling System A IO3; (2) Controlling System B: Controlling System B host, controlling System B AI1, controlling System B AI2, controlling System B IO1, controlling System B IO2, controlling System B IO3; (3) Protect System A: Protect System A host, protect System A AI1, protect System A AI2; (4) Protect System B: Protect System B host, protect System B AI1, protect System B AI2; (5) Protect C system: Protect C system host, protect C system AI1, protect C system AI2; (6) Ethernet, using three-out-of-two unit A and three-out-of-two unit B for network communication.
[0054] The various systems described above are networked via fiber optic communication. The control A real-time network A, control A real-time network B, control B real-time network A, control B real-time network B, protection A real-time network A, protection A real-time network A, protection A real-time network B, protection B real-time network A, protection B real-time network B, protection C real-time network A, and protection C real-time network B utilize the invented precise 50µs+1ms Gigabit Ethernet communication technology. Communication between control A / B systems and IO1 / 2 / 3 is 1ms cycle communication, while the others are 50µs communication. When this control and protection system is deployed to converter stations at different locations, the control and protection systems at different stations also possess the capability for Gigabit Ethernet inter-station communication with a 1ms cycle communication. The invented control and protection system also possesses visual programming capabilities, the ability to communicate with SCADA (Supervisory Control and Data Acquisition System) systems on servers, workstations, and engineering workstations via IEC61850, and has telemetry, remote signaling, remote adjustment, and remote control functions. Tables 5-1 and 5-2 provide statistics and explanations of the various communication types within the invented system.
[0055] Table 5-1 Operation Configuration
[0056] Table 5-2 System Network Architecture Table
[0057] The present invention constructs a flexible DC transmission control and protection system. Its goal is to realize the communication function of two precise periodic control of 50us + 1ms within the control and protection system, with the control time period error not exceeding (50us) ± 0.2us and (1ms) ± 5us.
[0058] Example 3: like Figure 4 As shown, the present invention also provides an electronic device, which may be a computer device, a microcontroller device, a smart mobile device, etc. The electronic device in this embodiment may include a processor, a memory, a transceiver component, etc. The memory, processor, and transceiver component are connected via a bus; the memory can be used to store executable programs, and an exemplary executable program may include instructions; the processor is used to execute the instructions stored in the memory. The memory can also be used to store data, which can be accessed and / or modified when instructions are executed.
[0059] The processor may be a Central Processing Unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. It is the computing core and control core of the terminal, and it is suitable for implementing one or more instructions. Specifically, it is suitable for loading and executing one or more instructions in the storage medium to realize the corresponding method flow or corresponding function, so as to realize the steps of the communication control method of a flexible DC transmission control and protection system in the above embodiments.
[0060] Example 4: Based on the same inventive concept, this invention also provides a readable storage medium, specifically an electronic device readable storage medium (Memory). This readable storage medium is a memory device within an electronic device used to store programs and data. It is understood that the storage medium here can include both built-in storage media within the electronic device and extended storage media supported by the electronic device. The storage medium provides storage space, which stores the terminal's operating system. Furthermore, this storage space also stores one or more instructions suitable for loading and execution by a processor. These instructions can be one or more executable programs (including program code). It should be noted that the storage medium here can be high-speed RAM or non-volatile memory, such as at least one disk storage device. Loading and executing one or more instructions stored in the storage medium by the processor can implement the steps of the communication control method of a flexible DC transmission control and protection system in the above embodiments.
[0061] Those skilled in the art will understand that embodiments of this invention can be provided as methods, systems, or computer program products. Therefore, this invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0062] This invention application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0063] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.
[0064] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0065] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit its protection scope. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that after reading the present invention, they can still make various changes, modifications or equivalent substitutions to the specific implementation of the application, but these changes, modifications or equivalent substitutions are all within the protection scope of the claims pending approval.
Claims
1. A communication method for a flexible DC transmission control and protection system, characterized in that, include: Based on the transmission requirements of the data to be transmitted in the flexible DC transmission control and protection system, a local clock reference is configured, and the frame interval of the data to be transmitted in the Ethernet is determined. Based on the data to be transmitted, combined with the inter-frame gap and the preset frame structure, multiple data frames are generated. By bypassing the TCP / IP protocol stack, the multiple data frames are encapsulated into multiple corresponding transmission frames through raw MAC frame injection and static MAC binding mechanisms; A timing control mechanism is used to schedule the transmission of the multiple transmission frames.
2. The method according to claim 1, characterized in that, The local clock reference configuration for the data to be transmitted in the flexible DC transmission control and protection system includes: Based on the clock accuracy requirements of the data to be transmitted in the flexible DC transmission control and protection system, and the Ethernet clock, the phase is locked by the phase-locked loop of the FPGA, and a phase-shifted clock is output to complete the local clock reference configuration; the phase-shifted clock is used to compensate for the timing offset during transmission in Ethernet.
3. The method according to claim 2, characterized in that, The transmission requirements of the data to be transmitted in the flexible DC transmission control and protection system, and the determination of the frame interval for the transmission of the data in the Ethernet, include: Based on the clock reference after the phase is locked by the phase-locked loop, the initial inter-frame gap for the data to be transmitted in the Ethernet is determined. A counter is used to control each initial frame gap to maintain at a preset minimum frame gap, thus forming the final frame gap.
4. The method according to claim 1, characterized in that, The pre-setting process for the frame structure includes: Determine the effective data transmission window based on the current communication cycle and IFG time; Based on the effective data transmission window, determine the length of the data payload field; The frame structure for injecting a raw MAC frame is determined based on the length of the data payload field. The frame structure includes the following fields: preamble field, start-of-frame delimiter field, MAC header field, data payload field, and frame check sequence field; If the communication period is 50μs, the length of the preamble field is 7 bytes, the length of the start-of-frame delimiter field is 1 byte, the length of the MAC header field is 14 bytes, the length of the data payload field is 5050 bytes, and the length of the frame check sequence field is 4 bytes.
5. The method according to claim 1, characterized in that, The process of generating multiple data frames based on the data to be transmitted, combined with the inter-frame gap and a preset frame structure, includes: Based on the data to be transmitted, the timing alignment of the data before and after each frame gap is controlled to form multiple sets of timing-aligned data to be transmitted; according to the preset frame structure, each set of timing-aligned data to be transmitted is encapsulated into a data frame, thereby generating multiple data frames.
6. The method according to claim 1, characterized in that, The timing control mechanism is used to schedule the transmission of the multiple transmission frames, including: For the multiple transmission frames, CRC32 is used for verification to obtain the verification result; For any erroneous transmission frames in the verification results, the operation is to discard them directly without retransmission. For the correct transmission frames in the verification results, a pre-buffering mechanism is used to inject the correct transmission frames into the sending queue for scheduled transmission.
7. The method according to claim 6, characterized in that, After the timing control mechanism is used to schedule the transmission of the multiple transmission frames, the method further includes: performing jitter filtering processing on each transmission frame according to a preset jitter threshold. After any of the transmission frames has finished transmitting, a pre-defined length of idle bytes is inserted to avoid collisions between transmission frames.
8. The method according to claim 5, characterized in that, The step of encapsulating each group of time-aligned data to be transmitted into a data frame according to a preset frame structure, thereby generating multiple data frames, includes: Perform byte count detection on each group of time-aligned data to be transmitted to obtain the detection result; If the detection result indicates that the length of the data to be transmitted is less than the set number of bytes, then the non-data bits of the data to be transmitted are padded with padding bytes until the set number of bytes is reached, and then it is encapsulated into a data frame. If the detection result indicates that the length of the data to be transmitted is equal to or greater than the set number of bytes, then the data to be transmitted is encapsulated into a data frame.
9. A flexible DC transmission control and protection system, characterized in that, include: The transmitting end and the receiving end; the transmitting end integrates multiple control system hosts and multiple protection system hosts; The transmitting end is used to configure a local clock reference and determine the frame interval for the data to be transmitted in the Ethernet, based on the transmission requirements of the data to be transmitted in the flexible DC transmission control and protection system, through the multiple control system hosts and the multiple protection system hosts. Based on the data to be transmitted, combined with the inter-frame gap and the preset frame structure, multiple data frames are generated; bypassing the TCP / IP protocol stack, the multiple data frames are encapsulated into multiple corresponding transmission frames through raw MAC frame injection and static MAC binding mechanisms; A timing control mechanism is used to schedule the transmission of the multiple transmission frames. The receiving end is used to receive and process multiple transmission frames from the sending end using a timing control mechanism.
10. An electronic device, characterized in that, include: At least one processor and memory; The memory and processor are connected via a bus; The memory is used to store one or more programs; When the one or more programs are executed by the at least one processor, the communication method based on the flexible DC transmission control and protection system as described in any one of claims 1-8 is implemented.