Semiconductor structure and preparation method thereof

Abstract

The invention relates to the technical field of semiconductors, and discloses a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a semiconductor substrate layer; an epitaxial layer located on the semiconductor substrate layer; the electric field shielding region and the doped region are located in the epitaxial layer, the doped region is located on the side, away from the semiconductor substrate layer, of the electric field shielding region, and the doped region is exposed out of the surface of the side, away from the semiconductor substrate layer, of the epitaxial layer; the metal layer is located on the surface, deviating from the semiconductor substrate layer, of the epitaxial layer, and at least part of an opposite region between the metal layer and the electric field shielding region does not coincide with the doped region; and the electric field shielding region and the doped region have the same conduction type and are opposite to the conduction type of the epitaxial layer. The reverse voltage withstanding characteristic of the semiconductor structure is improved, and the reverse electric leakage characteristic is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] Silicon carbide (SiC) materials possess advantages such as wide bandgap, high thermal conductivity, high breakdown field strength, and high saturation velocity, making them ideal for fabricating high-temperature, high-power semiconductor devices. High-power SiC semiconductor devices can fully leverage their high-temperature, high-frequency, and low-loss characteristics, making them highly promising for applications in high-voltage, high-temperature, high-frequency, high-power, and high-radiation fields. In particular, several manufacturers have already launched commercial SiC diodes. In the field of SiC diodes, strip cell technology is currently the most widely used semiconductor structure.

[0003] However, with the development of semiconductor technology and increasingly stringent application requirements, the reverse breakdown voltage and reverse leakage current characteristics of current semiconductor structures are poor. Therefore, how to improve the reverse breakdown voltage characteristics and reduce the reverse leakage current characteristics of semiconductor structures is a technical challenge that urgently needs to be solved. Summary of the Invention

[0004] The purpose of this invention is to provide at least a semiconductor structure and its fabrication method, which can at least solve the problem of poor reverse breakdown voltage and reverse leakage current characteristics of the semiconductor structure, and at least achieve the effect of improving the reverse breakdown voltage characteristics and reducing the reverse leakage current characteristics of the semiconductor structure.

[0005] To address the aforementioned technical problems, the present invention provides a semiconductor structure comprising: a semiconductor substrate layer; an epitaxial layer located on the semiconductor substrate layer; an electric field shielding region and a doped region located in the epitaxial layer, wherein the doped region is located on the side of the electric field shielding region away from the semiconductor substrate layer, and the doped region is exposed on the side of the epitaxial layer away from the semiconductor substrate layer; a metal layer located on the surface of the epitaxial layer away from the semiconductor substrate layer, wherein at least a portion of the area directly opposite the electric field shielding region does not overlap with the doped region; the electric field shielding region and the doped region have the same conductivity type and are opposite to the conductivity type of the epitaxial layer.

[0006] In this embodiment, a metal-semiconductor junction is formed by contacting the epitaxial layer and a metal layer located on the surface of the epitaxial layer opposite to the semiconductor substrate, resulting in a small forward voltage drop in the semiconductor structure. An electric field shielding region and a doped region are provided in the epitaxial layer. The electric field shielding region and the doped region have the same conductivity type but opposite to that of the epitaxial layer. The electric field shielding region and the doped region are suitable for depletion when the semiconductor structure is subjected to reverse voltage, shielding the electric field of the metal-semiconductor junction. This improves the reverse breakdown voltage of the semiconductor structure. Furthermore, the electric field shielding region and the doped region reduce the electric field strength of the metal-semiconductor junction, reducing the leakage current at the metal-semiconductor junction and thus reducing the reverse leakage current of the semiconductor structure. Since the maximum electric field of the metal-semiconductor junction is located at the furthest point from the doped region, by ensuring that at least part of the area directly opposite the metal layer and the electric field shielding region does not overlap with the doped region, the electric field shielding region can directly shield the maximum electric field of the metal-semiconductor junction when the semiconductor structure is subjected to reverse voltage, weakening the concentration effect of the electric field in the metal-semiconductor junction. This further improves the reverse breakdown voltage of the semiconductor structure and reduces the reverse leakage current. In summary, the reverse breakdown voltage of the semiconductor structure is improved, while the reverse leakage current is reduced.

[0007] Furthermore, the orthographic projection of the electric field shielding region onto the semiconductor substrate and the orthographic projection of the doped region onto the semiconductor substrate do not overlap at least partially. The doped region shields the electric field of the nearby metal-semiconductor junction, and the shielding effect of the electric field shielding region is enhanced at the point of maximum electric field of the metal-semiconductor junction directly opposite the electric field shielding region. The combined effect of the doped region and the electric field shielding region enhances the effect of increasing the reverse breakdown voltage of the semiconductor structure and reducing the reverse leakage current of the semiconductor structure.

[0008] Furthermore, the electric field shielding region includes multiple separately arranged electric field shielding sub-regions; these sub-regions are periodically arranged along both a first direction and a second direction; wherein both the first and second directions are parallel to the surface of the semiconductor substrate, and their extension directions are different. The multiple electric field shielding sub-regions can shield the electric field of the metal-semiconductor junction in both the first and second directions, enhancing the reduction of the electric field strength of the metal-semiconductor junction, increasing the reverse breakdown voltage of the semiconductor structure, and enhancing the reduction of the reverse leakage current of the semiconductor structure. Secondly, the separate arrangement of the multiple electric field shielding sub-regions can further reduce the forward voltage drop while maintaining a comparable reverse withstand voltage level.

[0009] Furthermore, the doped region comprises multiple discretely arranged doped sub-regions; these sub-regions are periodically arranged along both a third and a fourth direction; both the third and fourth directions are parallel to the surface of the semiconductor substrate, and their extension directions are different. In a semiconductor structure of the same size, the discrete arrangement of multiple doped sub-regions increases the probability of a metal-semiconductor junction forming between the metal layer and the epitaxial layer. The increased area of ​​the metal-semiconductor junction further reduces the forward voltage drop of the semiconductor structure. The enhanced probability of forming a metal-semiconductor junction in the third and fourth directions by the multiple doped sub-regions further strengthens the reduction in the forward voltage drop of the semiconductor structure.

[0010] Furthermore, the first and third directions are the same, and the second and fourth directions are the same; multiple electric field shielding sub-regions and multiple doped sub-regions are staggered along the first direction and / or staggered along the second direction; or, multiple electric field shielding sub-regions and multiple doped sub-regions are aligned along the first direction and / or aligned along the second direction. The neat arrangement of the multiple electric field shielding sub-regions and multiple doped sub-regions improves the consistency of their arrangement. When the semiconductor structure is subjected to reverse voltage, the combined effect of the multiple electric field shielding sub-regions and multiple doped sub-regions makes the shielding effect on the metal-semiconductor junction more uniform, increases the reverse breakdown voltage of the semiconductor structure, and enhances the reduction of the reverse leakage current of the semiconductor structure.

[0011] Furthermore, the first projection patterns of each electric field shielding sub-region on the surface of the semiconductor substrate are identical, and the second projection patterns of each doped sub-region on the surface of the semiconductor substrate are identical in shape. The first and second projection patterns may be the same or different. The electric field shielding region and the doped region can be fabricated using the same set of photomasks, which can save on manufacturing tooling costs.

[0012] Furthermore, when the first and second projected patterns are identical, the second projected pattern is obtained by rotating and / or translating the first projected pattern on the surface of the semiconductor substrate by a first angle. During the process, the electric field shielding region and the doped region can be fabricated simply by rotating or translating the same set of photomasks, making the process operation simple and convenient.

[0013] In addition, the first angle is 90 degrees. The shielding effect of the electric field shielding region and the doped region on the electric field of the metal-semiconductor junction is enhanced, which increases the reverse breakdown voltage of the semiconductor structure and enhances the effect of reducing the reverse leakage current of the semiconductor structure.

[0014] In addition, the shape of the first projected graphic includes one of the following: bar shape, circle shape, square shape, and regular hexagon shape; the shape of the second projected graphic includes one of the following: bar shape, circle shape, square shape, and regular hexagon shape.

[0015] Furthermore, the doping concentration in the electric field shielding region is lower than that in the doped region. Under forward conduction of the semiconductor structure, this reduces the impact on the carrier transport path, enhancing the effect of lower forward voltage drop.

[0016] Additionally, the epitaxial layer includes a drift layer located on a semiconductor substrate and a current spreading layer located on the surface of the drift layer facing away from the semiconductor substrate. An electric field shielding region is located in the drift layer, or alternatively, in the current spreading layer. A doped region is located in the current spreading layer, and the doped region is exposed on the surface of the current spreading layer facing away from the semiconductor substrate. The drift layer and the current spreading layer have the same conductivity type. The doping concentration of the current spreading layer is greater than that of the drift layer. The current spreading layer is suitable for improving carrier diffusion and reducing the resistance between doped regions when the semiconductor structure is forward-biased. The drift layer is suitable for depletion when the semiconductor structure is reverse-biased.

[0017] In addition, the metal layer is located on the surface of the doped region away from the semiconductor substrate; the semiconductor structure also includes: an anode layer located on the surface of the metal layer away from the semiconductor substrate; and a cathode layer located on the surface of the semiconductor substrate away from the epitaxial layer.

[0018] In addition, the metal layer includes a Schottky metal layer, and the semiconductor structure includes a junction barrier Schottky diode. When a forward voltage is applied to the semiconductor structure, the junction barrier Schottky diode exhibits Schottky diode characteristics.

[0019] The present invention also provides a method for fabricating a semiconductor structure, comprising: forming an epitaxial layer on a semiconductor substrate; forming an electric field shielding region in the epitaxial layer; forming a doped region on the side of the electric field shielding region in the epitaxial layer away from the semiconductor substrate, wherein the doped region is exposed on the surface of the epitaxial layer away from the semiconductor substrate; forming a metal layer on the surface of the epitaxial layer away from the semiconductor substrate, wherein at least a portion of the area directly opposite the electric field shielding region does not overlap with the doped region; the electric field shielding region and the doped region have the same conductivity type and are opposite to the conductivity type of the epitaxial layer.

[0020] Furthermore, the steps of forming an electric field shielding region in the epitaxial layer and forming a doped region on the side of the electric field shielding region in the epitaxial layer opposite to the semiconductor substrate include: performing ion implantation on the epitaxial layer using the same set of masks to ensure that the electric field shielding region and the doped region have the same shape. This can save on manufacturing tooling costs, and the process operation is simple and convenient.

[0021] Additionally, the step of forming an epitaxial layer on a semiconductor substrate includes: forming a drift layer on the semiconductor substrate; forming a current spreading layer on the surface of the drift layer facing away from the semiconductor substrate; the step of forming an electric field shielding region in the epitaxial layer includes: forming an electric field shielding region in the drift layer before forming the current spreading layer on the surface of the drift layer facing away from the semiconductor substrate, or forming an electric field shielding region in the current spreading layer; the step of forming a doped region on the side of the electric field shielding region in the epitaxial layer away from the semiconductor substrate includes: forming a doped region in the current spreading layer, and exposing the doped region on the surface of the current spreading layer facing away from the semiconductor substrate; wherein the drift layer and the current spreading layer have the same conductivity type; and the doping concentration of the current spreading layer is greater than the doping concentration of the drift layer.

[0022] In addition, during the process of forming a metal layer on the surface of the epitaxial layer away from the semiconductor substrate, a metal layer is formed on the surface of the doped region away from the semiconductor substrate; the method for fabricating the semiconductor structure also includes: forming an anode layer on the surface of the metal layer away from the semiconductor substrate; and forming a cathode layer on the surface of the semiconductor substrate away from the epitaxial layer. Attached Figure Description

[0023] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0024] Figure 1 This is a schematic diagram of a semiconductor structure provided in Embodiment 1 of the present invention;

[0025] Figure 2 This is a schematic diagram of a semiconductor structure provided in Embodiment 1 of the present invention;

[0026] Figure 3 This is another schematic diagram of the semiconductor structure provided in Embodiment 1 of the present invention;

[0027] Figure 4 This is another schematic diagram of the semiconductor structure provided in Embodiment 1 of the present invention;

[0028] Figure 5 A top view of the electric field shielding region and doped region provided in Embodiment 1 of the present invention;

[0029] Figure 6 This is another top view of the electric field shielding region and doped region provided in Embodiment 1 of the present invention;

[0030] Figure 7 This is another top view of the electric field shielding region and doped region provided in Embodiment 1 of the present invention;

[0031] Figure 8 This is another top view of the electric field shielding region and doped region provided in Embodiment 1 of the present invention;

[0032] Figure 9 This is another top view of the electric field shielding region and doped region provided in Embodiment 1 of the present invention;

[0033] Figure 10 This is a schematic flowchart of the method for preparing the semiconductor structure provided in Embodiment 2 of the present invention;

[0034] Figures 11 to 16 This is a schematic diagram of the process for preparing the semiconductor structure provided in Embodiment 2 of the present invention. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the various embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been presented in the various embodiments of the present invention to enable the reader to better understand the present invention. However, the technical solutions claimed in the present invention can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0036] Example 1

[0037] Reference Figures 1 to 9 This invention provides a semiconductor structure, including: a semiconductor substrate 100; an epitaxial layer 200 on the semiconductor substrate 100; an electric field shielding region 300 and a doped region 400 located in the epitaxial layer 200, wherein the doped region 400 is located on the side of the electric field shielding region 300 away from the semiconductor substrate 100, and the doped region 400 is exposed on the side of the epitaxial layer 200 away from the semiconductor substrate 100; a metal layer 500 located on the surface of the epitaxial layer 200 away from the semiconductor substrate 100, wherein at least a portion of the area directly opposite between the metal layer 500 and the electric field shielding region 300 does not coincide with the doped region 400; the electric field shielding region 300 and the doped region 400 have the same conductivity type and are opposite to the conductivity type of the epitaxial layer 200.

[0038] In this embodiment, a metal-semiconductor junction is formed by contacting the epitaxial layer 200 and the metal layer 500 located on the surface of the epitaxial layer 200 away from the semiconductor substrate layer 100, resulting in a small forward conduction voltage drop in the semiconductor structure. An electric field shielding region 300 and a doped region 400 are provided in the epitaxial layer 200. The electric field shielding region 300 and the doped region 400 have the same conductivity type but opposite to that of the epitaxial layer 200. The electric field shielding region 300 and the doped region 400 are suitable for depletion when the semiconductor structure is subjected to reverse voltage, thus shielding the electric field of the metal-semiconductor junction and improving the reverse breakdown voltage of the semiconductor structure. The voltage, and the reduction of the electric field strength of the metal-semiconductor junction by the electric field shielding region 300 and the doped region 400 can reduce the leakage current at the metal-semiconductor junction, thereby reducing the reverse leakage current of the semiconductor structure. Since the maximum electric field of the metal-semiconductor junction is at the farthest point of the electric field from the doped region, by ensuring that at least part of the area directly opposite the metal layer 500 and the electric field shielding region 300 does not coincide with the doped region 400, the electric field shielding region 300 can directly shield the maximum electric field of the metal-semiconductor junction when the semiconductor structure is subjected to reverse voltage, weakening the concentration effect of the electric field of the metal-semiconductor junction. This further improves the reverse breakdown voltage of the semiconductor structure and reduces the reverse leakage current. In summary, the reverse breakdown voltage characteristic of the semiconductor structure is improved, and the reverse leakage current characteristic is reduced.

[0039] In one embodiment, the semiconductor substrate 100 is doped with N-type conductive ions, and the material of the semiconductor substrate 100 is an N-type silicon carbide substrate. In other embodiments, the material of the semiconductor substrate is not limited.

[0040] In one embodiment, the epitaxial layer 200 is made of the same material as the semiconductor substrate 100, and the doping concentration of the epitaxial layer 200 is less than that of the semiconductor substrate 100. In one embodiment, the epitaxial layer is an N-type silicon carbide layer. The N-type conductive ions can be phosphorus ions or nitrogen ions.

[0041] In one embodiment, when the conductivity type of the epitaxial layer 200 is N-type, the conductivity type of both the electric field shielding region 300 and the doped region 400 is P-type, and the P-type conductive ions can be aluminum ions. In other embodiments, the conductivity type of the epitaxial layer is P-type, and the conductivity type of both the electric field shielding region and the doped region is N-type.

[0042] In one embodiment, the doping concentration of the electric field shielding region 300 is lower than that of the doping region 400. Under forward conduction of the semiconductor structure, this reduces the impact on the carrier transport path and enhances the effect of a smaller forward conduction voltage drop.

[0043] In other embodiments, the doping concentration of the electric field shielding region is greater than or equal to the doping concentration of the doped region. The doping concentrations of the electric field shielding region and the doping concentrations of the doped region can be set according to actual needs.

[0044] In one embodiment, the top surface of the electric field shielding region 300 and the bottom surface of the doped region 400 can be in contact or spaced apart. No limitation is imposed.

[0045] In one embodiment, the orthographic projections of the electric field shielding region 300 and the doped region 400 on the semiconductor substrate 100 at least partially do not overlap. This can be either partially overlapping and partially non-overlapping, or completely non-overlapping. When the orthographic projections of the electric field shielding region 300 and the doped region 400 on the semiconductor substrate 100 do not overlap, the doped region 400 shields the electric field of the nearby metal-semiconductor junction. The shielding effect of the electric field shielding region 300 at the point of maximum electric field in the metal-semiconductor junction directly opposite the electric field shielding region 300 is enhanced. The combined effect of the doped region 400 and the electric field shielding region 300 enhances the increase in the reverse breakdown voltage of the semiconductor structure and the reduction in the reverse leakage current of the semiconductor structure.

[0046] Figure 1 , Figure 3 and Figure 4 for Figures 5 to 8 Cross-sectional view along AA'. Figure 2 for Figures 5 to 8 Cross-sectional view along the middle edge BB'; Figures 1 to 8 The diagram illustrates that the orthographic projection of the electric field shielding region 300 on the semiconductor substrate 100 and the orthographic projection of the doped region 400 on the semiconductor substrate 100 do not overlap at all. Figure 9 The orthographic projection of the electric field shielding region 300 on the semiconductor substrate 100 and the orthographic projection of the doped region 400 on the semiconductor substrate 100 partially overlap and partially do not overlap as an illustration.

[0047] In one embodiment, reference Figures 5 to 9The electric field shielding region 300 includes multiple separately arranged electric field shielding sub-regions 300a. These sub-regions 300a are periodically arranged along a first direction X1 and a second direction Y1. Both the first direction X1 and the second direction Y1 are parallel to the surface of the semiconductor substrate layer 100, and their extension directions are different. The multiple electric field shielding sub-regions 300a can shield the electric field of the metal-semiconductor junction along both the first direction X1 and the second direction Y1, enhancing the reduction of the electric field strength of the metal-semiconductor junction, increasing the reverse breakdown voltage of the semiconductor structure, and enhancing the reduction of the reverse leakage current of the semiconductor structure. Furthermore, the separate arrangement of the multiple electric field shielding sub-regions 300a can further reduce the forward voltage drop while maintaining a comparable reverse withstand voltage level. In other embodiments, the multiple electric field shielding sub-regions have a strip-like structure.

[0048] Figures 6 to 8 In the illustration, the first direction X1 is perpendicular to the second direction Y1. At this time, the adjacent electric field shielding sub-regions 300a are aligned along the first direction X1 and the second direction Y1. Figure 5 and Figure 9 In the illustration, the first direction X1 and the second direction Y1 are not perpendicular. In this case, adjacent electric field shielding sub-regions 300a are staggered along the first direction X1 and the second direction Y1. In other embodiments, the first and second directions are not limited, as long as the extension directions of the first and second directions are different.

[0049] In one embodiment, the doped region 400 includes a plurality of discretely arranged doped sub-regions 400a; the plurality of doped sub-regions 400a are periodically arranged along a third direction X2 and a fourth direction Y2. The third direction X2 and the fourth direction Y2 are both parallel to the surface of the semiconductor substrate layer 100, and their extension directions are different. In a semiconductor structure of the same size, the discrete arrangement of the plurality of doped sub-regions 400a increases the probability of the metal layer 500 and the epitaxial layer 200 forming a metal-semiconductor junction. The increased area of ​​the metal-semiconductor junction further reduces the forward voltage drop of the semiconductor structure. The enhanced probability of the plurality of doped sub-regions 400a increasing the probability of the metal layer 500 and the epitaxial layer 200 forming a metal-semiconductor junction along the third direction X2 and the fourth direction Y2 strengthens the reduction of the forward voltage drop of the semiconductor structure. In other embodiments, the plurality of doped sub-regions are arranged in a strip-like structure.

[0050] Figures 6 to 8 The diagram illustrates a third direction X2 perpendicular to a fourth direction Y2. In this case, adjacent doped sub-regions 400a are aligned along both the third direction X2 and the fourth direction Y2. Figure 5 and Figure 9The diagram illustrates a scenario where the third direction X2 and the fourth direction Y2 are not perpendicular. In this case, adjacent doped sub-regions 400a are staggered along both the third direction X2 and the fourth direction Y2. Preferably, in this embodiment, adjacent doped sub-regions 400a are staggered along both the third direction X2 and the fourth direction Y2. This shortens the distance between the metal-semiconductor junction and the doped sub-regions 400a, reducing the electric field strength at the point of maximum electric field in the metal-semiconductor junction. In other embodiments, the third and fourth directions are not limited, as long as their extension directions are different.

[0051] It should be noted that the number of electric field shielding sub-regions 300a and doped sub-regions 400a can be selected according to actual needs. The number of electric field shielding sub-regions 300a and doped sub-regions 400a can be the same or different, and there is no restriction here.

[0052] In one embodiment, reference Figures 6 to 9 The first direction X1 and the third direction X2 are in the same direction, and the second direction Y1 and the fourth direction Y2 are in the same direction. Multiple electric field shielding sub-regions 300a and multiple doped sub-regions 400a are staggered along the first direction X1 and / or staggered along the second direction Y1; alternatively, the multiple electric field shielding sub-regions 300a and multiple doped sub-regions 400a are aligned along the first direction X1 and / or aligned along the second direction Y1. The neat arrangement of the multiple electric field shielding sub-regions 300a and multiple doped sub-regions 400a improves the consistency of their arrangement. When the semiconductor structure is subjected to reverse voltage, the combined effect of the multiple electric field shielding sub-regions 300a and multiple doped sub-regions 400a makes the shielding effect on the metal-semiconductor junction more uniform, increases the reverse breakdown voltage of the semiconductor structure, and enhances the reduction of the reverse leakage current of the semiconductor structure. Figure 5 The diagram illustrates the alignment of multiple electric field shielding sub-regions 300a and multiple doped sub-regions 400a along the first direction X1 and the second direction Y1. Figures 6 to 8 The diagram illustrates multiple electric field shielding sub-regions 300a and multiple doped sub-regions 400a staggered along a first direction X1 and a second direction Y1. In another embodiment, reference... Figure 9 Multiple electric field shielding sub-regions 300a and multiple doped sub-regions 400a are aligned along a first direction X1 and staggered along a second direction Y1, with the electric field shielding sub-regions 300a and doped sub-regions 400a partially overlapping along the first direction X1 and the second direction Y1. It should be noted that the arrangement of the multiple electric field shielding sub-regions 300a and multiple doped sub-regions 400a is not limited to this.

[0053] In other embodiments, the first direction and the third direction are different directions, and the second direction and the fourth direction are different directions.

[0054] In one embodiment, the first projection patterns of each electric field shielding sub-region 300a on the surface of the semiconductor substrate 100 are identical, and the second projection patterns of each doped sub-region 400a on the surface of the semiconductor substrate 100 are identical in shape. The first projection pattern and the second projection pattern may be the same or different. The electric field shielding region 300 and the doped region 400 can be fabricated using the same set of photomasks, which can save on manufacturing tooling costs.

[0055] In one embodiment, when the first projection pattern and the second projection pattern are identical, the second projection pattern is obtained by rotating the first projection pattern by a first angle and / or translating it on the surface of the semiconductor substrate 100. During the process, the electric field shielding region and the doped region can be fabricated simply by rotating or translating the same set of photomasks, making the process operation simple and convenient.

[0056] In one embodiment, the first angle is 90 degrees. That is, the extending directions of each electric field shielding sub-region 300a and each doped sub-region 400a are perpendicular to each other. The shielding effect of the electric field shielding region 300 and the doped region 400 on the electric field of the metal-semiconductor junction is enhanced, thereby increasing the reverse breakdown voltage of the semiconductor structure and enhancing the effect of reducing the reverse leakage current of the semiconductor structure.

[0057] In other embodiments, the first projection patterns of each electric field shielding sub-region on the surface of the semiconductor substrate are different; the second projection patterns of each doped sub-region on the surface of the semiconductor substrate are different.

[0058] In one embodiment, the shape of the first projected image includes one of a bar, a circle, a square, and a regular hexagon; the shape of the second projected image includes one of a bar, a circle, a square, and a regular hexagon. The shapes of the first and second projected images can be flexibly designed according to process requirements. In other embodiments, the shape of the first projected image includes other shapes, such as a trapezoid or a rhombus; the shape of the second projected image includes other shapes, such as a trapezoid or a rhombus.

[0059] refer to Figure 5 The first projected pattern is rod-shaped, and the second projected pattern is also rod-shaped. The second projected pattern is obtained by rotating and translating the first projected pattern by a first angle on the surface of the semiconductor substrate. (Reference) Figure 9 The first projection pattern is rod-shaped, the second projection pattern is rod-shaped, and the second projection pattern is obtained by rotating the first projection pattern by a first angle on the surface of the semiconductor substrate. Figure 5 and Figure 9 Both ends of each electric field shielding sub-region 300a and both ends of each doped sub-region 400a are set as arcs; Figures 6 to 8The first projected pattern is translated onto the surface of the semiconductor substrate to obtain the second projected pattern. (Reference) Figure 6 The first projected image is square in shape, and the second projected image is square in shape; Reference Figure 7 The first projected figure is a regular hexagon, and the second projected figure is a regular hexagon. Figure 6 and Figure 7 In the diagram, the apex corners of each electric field shielding sub-region 300a and each doped sub-region 400a are all set as arcs (not shown); Reference Figure 8 The first and second projected images are both circular, used as illustrations. The arc-shaped design, when a semiconductor structure of the same size is forward-biased, helps to increase the current-carrying area ratio, thereby reducing the forward voltage drop.

[0060] It is known that reducing the forward voltage drop can lower the junction temperature of the metal-semiconductor junction in the semiconductor structure, thereby improving the reliability of the semiconductor structure.

[0061] In one embodiment, the epitaxial layer 200 includes a drift layer 210 located on the semiconductor substrate 100 and a current spreading layer 220 located on the surface of the drift layer 210 facing away from the semiconductor substrate 100. The current spreading layer 220 is adapted to improve carrier diffusion and reduce the resistance of the current spreading layer 220 between the doped sub-regions 400a when the semiconductor structure is forward-biased; the drift layer 210 is adapted to deplete when the semiconductor structure is reverse-biased. It should be noted that the reduced resistance of the current spreading layer 220 between the doped sub-regions 400a reduces the forward conduction resistance of the semiconductor structure. With the same forward current, the size of the semiconductor structure can be smaller, which can save material resources and reduce production costs.

[0062] In one embodiment, the drift layer 210 and the current spreading layer 220 have the same conductivity type, and the doping concentration of the current spreading layer 220 is greater than that of the drift layer 210. The drift layer 210 is well depleted under reverse voltage, while the current spreading layer 220 allows for better carrier diffusion under forward voltage. In one embodiment, both the drift layer 210 and the current spreading layer 220 are doped with N-type conductive ions. In other embodiments, the drift layer and the current spreading layer are made of other materials.

[0063] refer to Figures 1 to 4 The doped region 400 is located in the current spreading layer 220, and the doped region 400 is exposed on the side of the current spreading layer 220 facing away from the semiconductor substrate layer 100. Figure 1 and Figure 3 The electric field shielding region 300 is located in the drift layer 210 as an illustration; Figure 4 The electric field shielding region 300 is located in the current spreading layer 220 as an illustration.

[0064] The electric field shielding region 300 is located in the drift layer 210, including the electric field shielding region 300 being located inside the drift layer 210 and spaced apart from the current spreading layer 220, and the electric field shielding region 300 being located on the surface of the drift layer 210 and in contact with the current spreading layer 220; the electric field shielding region 300 is located in the current spreading layer 220, including the electric field shielding region 300 being located inside the current spreading layer 220 and spaced apart from the drift layer 210, and the electric field shielding region 300 being located on the surface of the current spreading layer 220 and in contact with the drift layer 210.

[0065] In one embodiment, the metal layer 500 is also located on the surface of the doped region 400 away from the semiconductor substrate layer 100; the semiconductor structure further includes: an anode layer 600 located on the surface of the metal layer 500 away from the semiconductor substrate layer; and a cathode layer 700 located on the surface of the semiconductor substrate layer 100 away from the epitaxial layer 200.

[0066] In one embodiment, the anode layer 600 is made of one or a combination of titanium and aluminum; the cathode layer 700 is made of an alloy material. In other embodiments, the anode layer is made of other conductive materials, and the cathode layer is made of other conductive materials.

[0067] In one embodiment, the metal layer 500 comprises a Schottky metal layer, and the semiconductor structure comprises a junction barrier Schottky diode. When a forward voltage is applied to the semiconductor structure, the junction barrier Schottky diode exhibits Schottky diode characteristics. In other embodiments, the metal layer comprises other metallic materials.

[0068] It should be noted that since the Schottky metal layer and the epitaxial layer 200 form a Schottky junction through contact, the metal layer 500 also includes a Schottky junction (not shown).

[0069] In one embodiment, the semiconductor structure further includes an ohmic contact layer 800 located between the cathode layer 700 and the semiconductor substrate layer 100, thereby improving the contact effect between the semiconductor substrate layer and the cathode layer.

[0070] Example 2

[0071] refer to Figure 10 This invention provides a method for preparing a semiconductor structure, comprising:

[0072] S1: An epitaxial layer is formed on a semiconductor substrate;

[0073] S2: An electric field shielding region is formed in the epitaxial layer;

[0074] S3: A doped region is formed on the side of the electric field shielding region in the epitaxial layer away from the semiconductor substrate, and the doped region is exposed on the surface of the epitaxial layer away from the semiconductor substrate.

[0075] S4: A metal layer is formed on the surface of the epitaxial layer away from the semiconductor substrate layer. At least part of the area between the metal layer and the electric field shielding region does not overlap with the doped region. The electric field shielding region and the doped region have the same conductivity type and are opposite to the conductivity type of the epitaxial layer.

[0076] In one embodiment, the steps of forming an electric field shielding region in the epitaxial layer and forming a doped region on the side of the electric field shielding region in the epitaxial layer opposite to the semiconductor substrate include: performing ion implantation on the epitaxial layer using the same set of masks to ensure that the electric field shielding region and the doped region have the same shape. This can save on manufacturing tooling costs, and the process operation is simple and convenient.

[0077] In one embodiment, the step of forming an epitaxial layer on a semiconductor substrate includes: forming a drift layer on the semiconductor substrate; forming a current spreading layer on the surface of the drift layer facing away from the semiconductor substrate; the step of forming an electric field shielding region in the epitaxial layer includes: forming the electric field shielding region in the drift layer before forming the current spreading layer on the surface of the drift layer facing away from the semiconductor substrate, or forming the electric field shielding region in the current spreading layer; the step of forming a doped region on the side of the electric field shielding region in the epitaxial layer away from the semiconductor substrate includes: forming a doped region in the current spreading layer, and exposing the doped region on the surface of the current spreading layer facing away from the semiconductor substrate; wherein the drift layer and the current spreading layer have the same conductivity type; and the doping concentration of the current spreading layer is greater than the doping concentration of the drift layer.

[0078] In one embodiment, during the process of forming a metal layer on the surface of the epitaxial layer away from the semiconductor substrate, a metal layer is formed on the surface of the doped region away from the semiconductor substrate; the method for fabricating the semiconductor structure further includes: forming an anode layer on the surface of the metal layer away from the semiconductor substrate; and forming a cathode layer on the surface of the semiconductor substrate away from the epitaxial layer.

[0079] The following is for reference. Figures 11 to 16 This section provides a detailed introduction to the fabrication process of semiconductor structures.

[0080] refer to Figure 11 Provides a semiconductor substrate layer 100.

[0081] In one embodiment, the doping concentration of the semiconductor substrate 100 is greater than 5E18 atom / cm³. 3 .

[0082] The materials for the semiconductor substrate layer are described in the foregoing embodiments.

[0083] refer to Figures 12 to 13 An epitaxial layer 200 is formed on a semiconductor substrate 100; and an electric field shielding region 300 is formed in the epitaxial layer 200.

[0084] In one embodiment, the step of forming an epitaxial layer 200 on a semiconductor substrate 100 includes: forming a drift layer 210 on the semiconductor substrate 100; and forming a current spreading layer 220 on the surface of the drift layer 210 facing away from the semiconductor substrate 100. The conductivity type of the current spreading layer 220 is the same as that of the drift layer 210. In other embodiments, neither a drift layer nor a current spreading layer may be formed.

[0085] In one embodiment, the step of forming an electric field shielding region 300 in the epitaxial layer 200 includes: forming an electric field shielding region 300 in the drift layer 210 before forming a current spreading layer 220 on the surface of the drift layer 210 away from the semiconductor substrate layer, or forming an electric field shielding region 300 in the current spreading layer 220.

[0086] In one embodiment, the step of forming an electric field shielding region 300 in the drift layer 210 includes: performing ion implantation on the drift layer 210 using a mask. The pattern on the mask is transferred to the electric field shielding region 300 after ion implantation. Ion implantation of the drift layer 210 can be performed directly using a hard mask, or it can be performed by first transferring the pattern on the mask to the photoresist, and then using the photoresist as a mask to perform ion implantation on the drift layer 210.

[0087] The conductivity type of the electric field shielding region 300 is opposite to that of the drift layer 210.

[0088] In one embodiment, the step of forming an electric field shielding region 300 in the current spreading layer 220 includes: performing ion implantation on the current spreading layer 220 using a mask. Ion implantation on the current spreading layer 220 can be performed directly using a hard mask, or it can be performed using photoresist, where the pattern on the mask is first transferred to the photoresist, and then the photoresist is used as a mask to perform ion implantation on the current spreading layer 220.

[0089] The conductivity type of the electric field shielding region 300 is opposite to that of the current spreading layer 220.

[0090] In one embodiment, the doping concentration of the electric field shielding region 300 is greater than 1E18 atom / cm³. 3 .

[0091] For material, structural and shape descriptions of the electric field shielding region 300, please refer to the descriptions in the foregoing embodiments.

[0092] In one embodiment, the length of the first projection pattern of each electric field shielding sub-region in the electric field shielding region 300 on the surface of the semiconductor substrate layer 100 is 6μm to 9μm, for example, 6μm, 8μm or 9μm, and the width is 1μm to 2μm, for example, 1μm, 1.5μm or 2μm.

[0093] In one embodiment, forming an electric field shielding region 300 in the drift layer 210 includes: forming the electric field shielding region 300 inside the drift layer 210, or forming the electric field shielding region 300 on the surface of the drift layer 210. When the electric field shielding region 300 is formed on the surface of the drift layer 210, a current spreading layer 200 is formed on the surface of the drift layer 210 facing away from the semiconductor substrate layer 100, and a current spreading layer 220 is formed on the surface of the electric field shielding region 300 facing away from the semiconductor substrate layer 100.

[0094] In one embodiment, forming an electric field shielding region 300 in the current spreading layer 220 includes: forming an electric field shielding region 300 inside the current spreading layer 220, or forming an electric field shielding region 300 on the bottom surface of the current spreading layer 220 toward the drift layer 210.

[0095] refer to Figure 12 A drift layer 210 is formed on a semiconductor substrate 100; and an electric field shielding region 300 is formed on the surface of the drift layer 210; Reference Figure 13 A current spreading layer 220 is formed on the surface of the drift layer 210 and the electric field shielding region 300 on the side away from the semiconductor substrate layer 100.

[0096] In one embodiment, the doping concentration of the drift layer 210 is 1E14 atom / cm³. 3 ~5E16atom / cm 3 For example, 1E14 atom / cm 3 3E14atom / cm 3 5E14atom / cm 3 2E15atom / cm 3 5E15atom / cm 3 Or 5E16atom / cm 3 The doping concentration and thickness of the drift layer 210 need to be selected based on the voltage withstand capability of the semiconductor structure. No restrictions are imposed here.

[0097] In one embodiment, the doping concentration of the current spreading layer 220 is 1E16 atom / cm². 3 ~2E17atom / cm 3 For example, 1E16atom / cm 3 2E16atom / cm 3 Or 2E17atom / cm 3 .

[0098] In one embodiment, the thickness of the current spreading layer 220 is 0.5 μm to 2 μm, for example, 0.5 μm, 1 μm or 2 μm.

[0099] For the material descriptions of the drift layer 210 and the current spreading layer 220, please refer to the descriptions in the foregoing embodiments.

[0100] refer to Figure 14 A doped region 400 is formed on the side of the electric field shielding region 300 in the epitaxial layer 200 away from the semiconductor substrate layer 100, and the doped region 400 is exposed on the surface of the epitaxial layer 200 away from the semiconductor substrate layer 100.

[0101] Specifically, the step of forming a doped region 400 on the side of the electric field shielding region 300 in the epitaxial layer 200 away from the semiconductor substrate layer 100 includes: forming a doped region 400 on the side of the current spreading layer 220 away from the semiconductor substrate layer 100, and exposing the doped region 400 on the surface of the current spreading layer 220 on the side away from the semiconductor substrate layer 100.

[0102] In one embodiment, the step of forming a doped region 400 on the side of the current spreading layer 220 opposite to the semiconductor substrate layer 100 includes: performing ion implantation on the current spreading layer 220 using a mask. The pattern on the mask is transferred to the doped region 400 after ion implantation. Ion implantation of the current spreading layer 220 can be performed directly using a hard mask, or it can be performed by first transferring the pattern on the mask to the photoresist, and then using the photoresist as a mask to perform ion implantation on the current spreading layer 220.

[0103] The conductivity type of the doped region 400 is opposite to that of the current spreading layer 220.

[0104] It should be noted that the same mask is used for forming the doped region 400 and the electric field shielding region 300. This saves on manufacturing tooling costs and simplifies and facilitates the process.

[0105] In one embodiment, the doping concentration of the doped region 400 is greater than 1E18 atom / cm. 3 .

[0106] For material, structural, and shape descriptions of the doped regions, please refer to the descriptions in the foregoing embodiments.

[0107] refer to Figure 15 A metal layer 500 is formed on the surface of the epitaxial layer 200 away from the semiconductor substrate layer 100; an anode layer 600 is formed on the surface of the metal layer 500 away from the semiconductor substrate layer.

[0108] Specifically, a metal layer 500 is formed on the surface of the current spreading layer 220 and the doped region 400 away from the semiconductor substrate layer 100. The metal layer 500 and the current spreading layer 220 contact to form a metal-semiconductor junction.

[0109] In one embodiment, the metal layer 500 includes a Schottky metal layer; the metal semiconductor junction includes a Schottky junction.

[0110] The Schottky metal layer and the current spreading layer 220 are contacted to form a Schottky junction. In one embodiment, the height of the Schottky junction is 0.3 μm to 3 μm, for example, 0.3 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm or 2 μm.

[0111] In one embodiment, the process of forming the metal layer 500 includes a deposition process; the process of forming the anode layer 600 includes a deposition process.

[0112] For a description of the material of the anode layer 600, please refer to the description in the foregoing embodiments.

[0113] refer to Figure 16 A cathode layer 700 is formed on the side surface of the semiconductor substrate layer 100 opposite to the epitaxial layer.

[0114] In one embodiment, the process for forming the cathode layer 700 includes a sputtering process.

[0115] The material description of the cathode layer 700 is given in the description of the foregoing embodiments.

[0116] In one embodiment, an ohmic contact layer 800 is formed on the surface of the semiconductor substrate 100 opposite to the epitaxial layer 200 before the cathode layer 700 is formed. This improves the contact effect between the semiconductor substrate 100 and the subsequently formed cathode layer 700. In other embodiments, the ohmic contact layer may not be formed.

[0117] In one embodiment, the process for forming the ohmic contact layer 800 includes a sputtering process.

[0118] It should be understood that the terms "mechanism," "device," "component," etc., used in this application are merely one method of distinguishing different components, elements, parts, sections, or assemblies at different levels. However, if other terms can achieve the same purpose, they can be replaced by other expressions.

[0119] Those skilled in the art will understand that the above embodiments are specific examples of implementing the present invention. In practical applications, the technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification, and various changes can be made to them in form and detail without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor structure, characterized in that, include: Semiconductor substrate layer; An epitaxial layer located on the semiconductor substrate layer; An electric field shielding region and a doped region are located in the epitaxial layer, wherein the doped region is located on the side of the electric field shielding region away from the semiconductor substrate layer, and the doped region is exposed on the side of the epitaxial layer away from the semiconductor substrate layer; A metal layer located on the surface of the epitaxial layer away from the semiconductor substrate layer, wherein at least a portion of the area directly opposite the metal layer and the electric field shielding region does not overlap with the doped region; The electric field shielding region and the doped region have the same conductivity type, but the opposite conductivity type to that of the epitaxial layer.

2. The semiconductor structure according to claim 1, characterized in that, The orthographic projection of the electric field shielding region onto the semiconductor substrate and the orthographic projection of the doped region onto the semiconductor substrate do not overlap at least partially.

3. The semiconductor structure according to claim 1, characterized in that, The electric field shielding region includes multiple separately arranged electric field shielding sub-regions; the multiple electric field shielding sub-regions are arranged periodically along a first direction and a second direction; wherein the first direction and the second direction are both parallel to the surface of the semiconductor substrate layer, and the extension directions of the first direction and the second direction are different.

4. The semiconductor structure according to claim 3, characterized in that, The doped region includes multiple discretely arranged doped sub-regions; the multiple doped sub-regions are periodically arranged along a third direction and a fourth direction; wherein the third direction and the fourth direction are both parallel to the surface of the semiconductor substrate layer, and the third direction and the fourth direction extend in different directions.

5. The semiconductor structure according to claim 4, characterized in that, The first direction and the third direction are the same direction, and the second direction and the fourth direction are the same direction; The plurality of electric field shielding sub-regions and the plurality of doped sub-regions are staggered along the first direction and / or staggered along the second direction; Alternatively, the plurality of electric field shielding sub-regions and the plurality of doped sub-regions may be aligned along the first direction and / or aligned along the second direction.

6. The semiconductor structure according to claim 4, characterized in that, The first projection patterns of each of the electric field shielding sub-regions on the surface of the semiconductor substrate are the same, and the second projection patterns of each of the doped sub-regions on the surface of the semiconductor substrate are the same in shape. The first projection pattern and the second projection pattern may be the same or different.

7. The semiconductor structure according to claim 6, characterized in that, When the first projection pattern and the second projection pattern are the same, the first projection pattern is rotated by a first angle and / or translated on the surface of the semiconductor substrate to obtain the second projection pattern.

8. The semiconductor structure according to claim 7, characterized in that, The first angle is 90 degrees.

9. The semiconductor structure according to any one of claims 6-8, characterized in that, The shape of the first projected graphic includes one of the following: bar shape, circle shape, square shape, and regular hexagon shape; the shape of the second projected graphic includes one of the following: bar shape, circle shape, square shape, and regular hexagon shape.

10. The semiconductor structure according to claim 1, characterized in that, The doping concentration of the electric field shielding region is less than that of the doping region.

11. The semiconductor structure according to claim 1, characterized in that, The epitaxial layer includes a drift layer located on the semiconductor substrate and a current spreading layer located on the surface of the drift layer facing away from the semiconductor substrate. The electric field shielding region is located in the drift layer, or the electric field shielding region is located in the current spreading layer; The doped region is located in the current spreading layer, and the doped region is exposed on the side of the current spreading layer opposite to the semiconductor substrate. The drift layer and the current spreading layer have the same conductivity type; the doping concentration of the current spreading layer is greater than that of the drift layer.

12. The semiconductor structure according to claim 1, characterized in that, The metal layer is also located on the surface of the doped region away from the semiconductor substrate layer; The semiconductor structure further includes: an anode layer located on the surface of the metal layer opposite to the semiconductor substrate layer; A cathode layer located on the side of the semiconductor substrate layer opposite to the epitaxial layer.

13. The semiconductor structure according to claim 12, characterized in that, The metal layer includes a Schottky metal layer, and the semiconductor structure includes a junction barrier Schottky diode.

14. A method for fabricating a semiconductor structure, characterized in that, include: An epitaxial layer is formed on a semiconductor substrate; An electric field shielding region is formed in the epitaxial layer; A doped region is formed on the side of the electric field shielding region in the epitaxial layer away from the semiconductor substrate, and the doped region is exposed on the surface of the epitaxial layer away from the semiconductor substrate. A metal layer is formed on the surface of the epitaxial layer away from the semiconductor substrate layer, and at least a portion of the area directly opposite the metal layer and the electric field shielding region does not overlap with the doped region. The electric field shielding region and the doped region have the same conductivity type, but the opposite conductivity type to that of the epitaxial layer.

15. The method for preparing a semiconductor structure according to claim 14, characterized in that, The steps of forming an electric field shielding region in the epitaxial layer and forming a doped region on the side of the electric field shielding region in the epitaxial layer away from the semiconductor substrate include: performing ion implantation on the epitaxial layer using the same set of masks to make the electric field shielding region and the doped region have the same shape.

16. The method for preparing a semiconductor structure according to claim 14, characterized in that, The step of forming an epitaxial layer on the semiconductor substrate includes: forming a drift layer on the semiconductor substrate; and forming a current spreading layer on the surface of the drift layer opposite to the semiconductor substrate. The step of forming an electric field shielding region in the epitaxial layer includes: forming the electric field shielding region in the drift layer before forming a current spreading layer on the surface of the drift layer away from the semiconductor substrate layer, or forming the electric field shielding region in the current spreading layer; The step of forming a doped region on the side of the electric field shielding region in the epitaxial layer away from the semiconductor substrate includes: forming the doped region in the current spreading layer, wherein the doped region is exposed on the side surface of the current spreading layer away from the semiconductor substrate. The drift layer and the current spreading layer have the same conductivity type; the doping concentration of the current spreading layer is greater than that of the drift layer.

17. The method for preparing a semiconductor structure according to claim 14, characterized in that, During the process of forming a metal layer on the surface of the epitaxial layer away from the semiconductor substrate, the metal layer is formed on the surface of the doped region away from the semiconductor substrate. The method for fabricating a semiconductor structure further includes: forming an anode layer on the surface of the metal layer opposite to the semiconductor substrate layer; A cathode layer is formed on the side of the semiconductor substrate layer opposite to the epitaxial layer.

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