Compound semiconductor device and preparation method thereof

Abstract

The invention provides a compound semiconductor device and a preparation method thereof. The preparation method comprises the following steps: providing a multi-layer butt joint structure; wherein the multi-layer butt joint structure comprises a temporary substrate and a porous gallium nitride layer which are epitaxially grown along a first direction, and the first direction is a direction from a nitrogen polar surface to a gallium polar surface; sequentially epitaxially growing a barrier structure, a channel layer, a supporting layer, a heat conduction layer and a diamond substrate on the surface of the porous gallium nitride layer along a first direction to obtain a first structure; overturning the first structure, and stripping the multi-layer butt joint structure from the junction surface formed by the barrier structure and the porous gallium nitride layer; forming a plurality of mutually isolated electrodes on the surface of the barrier structure to prepare the compound semiconductor device; wherein the metal content in the barrier structure is gradually increased and then gradually reduced in the first direction. According to the invention, the preparation steps are simplified, and the performance and reliability of the compound semiconductor device are improved.

Description

Technical Field

[0001] This invention relates to the field of compound semiconductor device technology, and in particular to a compound semiconductor device and its preparation method. Background Technology

[0002] Compound semiconductor devices (e.g., gallium nitride semiconductor devices) have high electron mobility μe, high breakdown field strength BV, and lower on-resistance R compared to silicon-based semiconductor devices. DS(ON) Gallium nitride (GaN) substrates offer numerous advantages, including lower switching losses (Psw), resulting in smaller size and weight for compound semiconductor devices and faster switching speeds. GaN substrates have two polar orientations: Ga polar and N polar. Semiconductor devices grown along the N polar surface have advantages over those grown along the Ga polar surface in suppressing the short channel effect (SCE) and increasing electron mobility (μe).

[0003] Currently, methods for fabricating semiconductor devices grown along the N-polar plane include epitaxial growth and epitaxial layer transfer. Epitaxial growth utilizes methods such as MBE (molecular beam epitaxy) and MOCVD (metal-organic chemical vapor deposition) to directly grow N-polar GaN and fabricate semiconductor devices. Compared to semiconductor devices fabricated along the Ga polar plane, directly epitaxially growing N-polar plane semiconductor devices have certain disadvantages in terms of material growth difficulty, crystal quality control, and interface state density. Furthermore, fabricating compound semiconductor devices by epitaxial growth along the N-polar plane using the epitaxial layer transfer method requires multiple bonding and substrate transfer processes, resulting in a long process route and cumbersome fabrication steps. Additionally, the aforementioned compound semiconductor devices based on the epitaxial layer transfer method also suffer from difficulties in controlling bonding strength and controlling damage to functional layers (e.g., channel layers) during substrate removal.

[0004] In view of this, it is necessary to improve the existing compound semiconductor devices fabricated on gallium nitride substrates, which are grown along the N-polar plane and ultimately formed, to solve the aforementioned problems. It should be noted that the above description of the background art is only for the purpose of clearly and completely explaining the technical solutions of the present invention and facilitating understanding by those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because these solutions have been described in the background art section of the present invention. Summary of the Invention

[0005] The purpose of this invention is to disclose a compound semiconductor device and its fabrication method to solve the aforementioned technical problems. In particular, it aims to avoid the cumbersome fabrication steps and process damage caused by the use of bonding processes, and to avoid damage to the barrier layer and other functional layers caused by shear stress generated during the peeling process of the temporary substrate during the fabrication of compound semiconductor devices grown along the N-polar plane based on the flipping process, thereby improving the performance and reliability of the compound semiconductor device.

[0006] To achieve one of the above objectives, the present invention first provides a method for preparing a compound semiconductor device, comprising the following steps:

[0007] A multilayer docking structure is provided; wherein the multilayer docking structure includes a temporary substrate epitaxially grown along a first direction and a porous gallium nitride layer, the first direction being the direction from the nitrogen polar surface to the gallium polar surface;

[0008] A barrier structure, a channel layer, a support layer, a thermally conductive layer, and a diamond substrate are sequentially epitaxially grown on the surface of the porous gallium nitride layer along the first direction to obtain a first structure; wherein, the metal content in the barrier structure gradually increases and then gradually decreases along the first direction.

[0009] The first structure is flipped, and the multilayer docking structure is peeled off from the interface formed by the barrier structure and the porous gallium nitride layer.

[0010] A compound semiconductor device is fabricated by forming several mutually isolated electrodes on the surface of the barrier structure.

[0011] As a further improvement of the present invention, the barrier structure includes a transition layer and a barrier layer stacked along the first direction, wherein the metal content in the transition layer gradually increases along the first direction, and the metal content in the barrier layer gradually decreases along the first direction.

[0012] As a further improvement of the present invention, a transition layer and a barrier layer are epitaxially grown sequentially on the surface of the porous gallium nitride layer, including:

[0013] When a metal source is introduced into the deposition chamber, the flow rate of the metal source is gradually increased to form a transition layer in which the metal content gradually increases along the first direction.

[0014] When a metal source is introduced into the deposition chamber, the flow rate of the metal source is gradually reduced to form a barrier layer in which the metal content gradually decreases along the first direction.

[0015] As a further improvement of the present invention

[0016] The process conditions for the transition layer include: a temperature of 1080-1100℃ and a pressure of 60-80 Torr.

[0017] The process conditions for the barrier layer include a temperature of 1040-1060℃ and a pressure of 60-80 Torr.

[0018] As a further improvement of the present invention, the transition layer and the barrier layer include any one of AlGaN, InAlN, ScAlN, and BAlN;

[0019] When the transition layer and the barrier layer are AlGaN, the metal whose content changes along the first direction is Al; or, when the transition layer and the barrier layer are InAlN, the metal whose content changes along the first direction is In; or, when the transition layer and the barrier layer are ScAlN, the metal whose content changes along the first direction is Sc; or, when the transition layer and the barrier layer are BAlN, the metal whose content changes along the first direction is B.

[0020] And / or, the thickness of the transition layer is greater than the thickness of the barrier layer;

[0021] And / or, the thickness of the transition layer is 40-80 nm, and the thickness of the barrier layer is 30-50 nm;

[0022] And / or, the metal content in the barrier layer is greater than the metal content in the transition layer.

[0023] As a further improvement of the present invention, the multi-layer docking structure includes:

[0024] A temporary substrate is provided, and a buffer layer is epitaxially grown on the surface of the temporary substrate along the first direction;

[0025] The porous gallium nitride layer is epitaxially grown on the surface of the buffer layer along the first direction;

[0026] The temporary substrate includes a silicon-based substrate or a sapphire substrate, and the buffer layer includes gallium nitride.

[0027] The silicon substrate has a crystal plane index of (111) along the first direction, and the sapphire substrate has a crystal plane index of (0001) along the first direction.

[0028] The thickness of the buffer layer is 800-1000 nm, and the process conditions of the buffer layer include: temperature of 1100-1200℃, pressure of 30-50 Torr, ammonia flow rate of 1500-2500 sccm, gallium source flow rate of 150-200 sccm and hydrogen flow rate of 2500-3500 sccm.

[0029] The process conditions for the porous gallium nitride layer include: a temperature of 800-1100℃ and a pressure of 100-500 Pa, and the porosity density of the porous gallium nitride layer is 10. 7 -10 10 cm -3 The pore size is 50-150nm.

[0030] As a further improvement of the present invention, the epitaxial growth of the buffer layer on the temporary substrate along the first direction includes:

[0031] A nucleation layer is epitaxially grown on the surface of the temporary substrate along the first direction;

[0032] The buffer layer is epitaxially grown on the surface of the nucleation layer along the first direction;

[0033] The nucleation layer includes an aluminum nitride nucleation layer or a gallium nitride nucleation layer.

[0034] As a further improvement of the present invention

[0035] The process conditions for the channel layer include: a temperature of 1100-1150℃ and a pressure of 80-100 Torr.

[0036] The process conditions for the support layer include: a temperature of 1100-1150℃, a pressure of 40-60 Torr, a flow rate of 1500-2000 sccm for ammonia, a flow rate of 50-100 sccm for gallium source, and a flow rate of 2500-3500 sccm for hydrogen.

[0037] The process conditions for the thermal conductive layer include: sputtering temperature of 200-600℃ and radio frequency power of 100-150W;

[0038] The process conditions for the diamond substrate include: a temperature of 800-1000℃, a methane flow rate of 20-100 mL / min, a pressure of 100-200 Torr, a microwave power of 2-5 kW, a nitrogen flow rate of 20-100 μL / min, and a hydrogen flow rate of 500-1000 mL / min.

[0039] And / or, the thickness of the diamond substrate is 30-100 μm;

[0040] And / or, the thermally conductive layer comprises silicon carbide, and the thickness of the thermally conductive layer is 80-150 nm;

[0041] And / or, the thickness of the support layer is 3-20 μm;

[0042] And / or, the thickness of the channel layer is 500-3000 nm;

[0043] And / or, the support layer and the channel layer comprise gallium nitride.

[0044] As a further improvement of the present invention, the barrier structure includes a transition layer and a barrier layer stacked along the first direction, and the formation of a plurality of mutually isolated electrodes on the surface of the barrier structure includes:

[0045] A gate groove is formed inside the transition layer, penetrating the transition layer and extending along the first direction to the barrier layer;

[0046] A gate dielectric layer is formed on the surface of the gate recess, a passivation layer is formed on the surface of the transition layer, and a plurality of electrodes isolated by the passivation layer are formed above the gate dielectric layer.

[0047] The plurality of electrodes include a gate, a source and a drain that form an ohmic contact with the transition layer, the passivation layer isolates the source, the drain and the gate, the passivation layer includes silicon nitride or silicon oxide, the thickness of the passivation layer is 20-50 nm, and the source, drain and gate include elemental metals or alloys of titanium, aluminum, nickel, copper or gold.

[0048] The gate dielectric layer is a first gate dielectric layer formed on the surface of the gate recess, or a double gate dielectric layer composed of a first gate dielectric layer and a second gate dielectric layer formed sequentially from the surface of the gate recess.

[0049] The first gate dielectric layer includes aluminum oxide, and the second gate dielectric layer includes hafnium oxide. The thickness of the first gate dielectric layer is 3-10 nm, and the thickness of the second gate dielectric layer is 10-20 nm.

[0050] Based on the same inventive concept, the present invention also discloses a compound semiconductor device, comprising: a diamond substrate, a thermally conductive layer, a support layer, a channel layer and a barrier structure sequentially stacked along a second direction, wherein a plurality of mutually isolated electrodes are formed on the surface of the barrier structure.

[0051] The metal content in the barrier layer structure gradually increases and then gradually decreases along the second direction; the second direction is the direction from the gallium polar surface to the nitrogen polar surface.

[0052] Compared with the prior art, the beneficial effects of the present invention are as follows: First, a multilayer docking structure is provided; second, a barrier structure, a channel layer, a support layer, a thermally conductive layer, and a diamond substrate are sequentially epitaxially grown on the surface of the porous gallium nitride layer contained in the multilayer docking structure to obtain a first structure; then, the first structure is flipped, and the multilayer docking structure is peeled off from the interface formed by the barrier structure and the porous gallium nitride layer; finally, several mutually isolated electrodes are formed on the surface of the barrier structure to prepare a compound semiconductor device. Compared to existing technologies, the fabrication method disclosed in this invention eliminates the need for a bonding support substrate, thus avoiding potential risks to the thermal and chemical stability of the material system at high temperatures. In particular, existing bonding layers typically use metal materials, which introduce additional capacitance and resistance during compound semiconductor device operation, affecting high-frequency performance. Furthermore, during prolonged operation, the large coefficient of thermal expansion between the metal and semiconductor layers leads to significant thermal stress, easily causing delamination or cracking between the materials in the compound semiconductor device. Additionally, the stress resulting from differences in the bonding material system is uncontrollable and unevenly distributed. This invention, by eliminating the need for bonding, avoids the process difficulties and performance instability associated with bonding. Moreover, the support layer in this invention, in conjunction with a diamond substrate, provides support and heat dissipation, simplifying the fabrication process and improving the heat dissipation performance of the resulting compound semiconductor device. Attached Figure Description

[0053] Figure 1 This is a schematic diagram illustrating the steps of a method for fabricating a compound semiconductor device disclosed in this invention;

[0054] Figure 2 This is a cross-sectional view of a device in which a buffer layer and a porous gallium nitride layer are epitaxially grown sequentially along a first direction on the surface of a temporary substrate.

[0055] Figure 3 for Figure 2 A cross-sectional view of the device in which a transition layer is epitaxially grown along the first direction;

[0056] Figure 4 for Figure 3 A cross-sectional view of the device in which a barrier layer and a channel layer are epitaxially grown sequentially along the first direction.

[0057] Figure 5 for Figure 4 A cross-sectional view of the device in which a support layer and a thermally conductive layer are epitaxially grown sequentially along the first direction.

[0058] Figure 6 for Figure 5 A cross-sectional view of the device in which a diamond substrate is epitaxially grown along a first direction;

[0059] Figure 7 To flip Figure 6 The cross-sectional view of the device for peeling off the temporary substrate, the buffer layer and a part of the porous gallium nitride layer from the bonding surface formed by the barrier structure and the porous gallium nitride layer;

[0060] Figure 8 The cross-sectional view of the device for removing the remaining part of the porous gallium nitride layer;

[0061] Figure 9 For Figure 8 The cross-sectional view of the device for coating a photoresist layer on the surface of the transition layer along the first direction in the device in , and forming a photoresist layer after drying and curing;

[0062] Figure 10 The cross-sectional view of the device for etching the transition layer and the barrier layer on the exposed area below the photoresist layer with the photoresist layer as a mask to form a gate groove partially extending to the barrier layer;

[0063] Figure 11 For Figure 10 The cross-sectional view of the device for sequentially depositing a first gate dielectric layer and a second gate dielectric layer on the bottom surface and the side wall of the gate groove in , wherein the first gate dielectric layer and the second gate dielectric layer form a double-layer gate dielectric layer;

[0064] Figure 12 For Figure 11 The cross-sectional view of the device for forming a passivation layer, source electrodes, drain electrodes and gate electrodes on the surface of the device in . Specific embodiments

[0065] The present invention will be described in detail below in conjunction with the embodiments shown in the drawings. However, it should be noted that these embodiments are not limitations on the present invention. Any equivalent transformation or substitution in terms of function, method or structure made by those of ordinary skill in the art according to these embodiments shall fall within the protection scope of the present invention. The compound semiconductor device involved in the present invention refers to a semiconductor device formed on a gallium nitride substrate.

[0066] In particular, it should be noted that in the present invention, the first direction 1 refers to the direction in which the nitrogen-polarity surface points to the gallium-polarity surface, and the second direction 2 refers to the direction in which the gallium-polarity surface points to the nitrogen-polarity surface.

[0067] Refer Figures 1 to 12 As shown, the present invention provides a specific embodiment of a method for manufacturing a compound semiconductor device 100. This manufacturing method is used to manufacture the compound semiconductor device 100. The compound semiconductor device 100 may be, for example, a gallium nitride semiconductor device. This embodiment is not specifically limited thereto, and in the following description, the gallium nitride semiconductor device will be taken as an example for illustrative purposes. The manufacturing method of the compound semiconductor device 100 includes the following steps S1 to step S4.

[0068] like Figure 2 As shown, step S1 is to provide a multi-layer docking structure 10.

[0069] The multilayer docking structure 10 includes a temporary substrate 11 epitaxially grown along a first direction 1 and a porous gallium nitride layer 13.

[0070] In one implementation, the reference Figure 2 As shown, providing the multi-layer docking structure 10 includes the following steps S11 and S12.

[0071] Step S11: Provide a temporary substrate 11 and epitaxially grow a buffer layer 12 on the surface of the temporary substrate 11 along the first direction 1.

[0072] The temporary substrate 11 includes a silicon substrate or a sapphire substrate. The silicon substrate has a crystal plane index of (111) along the first direction 1, and the sapphire substrate has a crystal plane index of (0001) along the first direction 1. The buffer layer 12 includes gallium nitride. The thickness of the buffer layer 12 is 800-1000 nm. The process conditions of the buffer layer 12 include: a temperature of 1100-1200 °C, a pressure of 30-50 Torr, an ammonia flow rate of 1500-2500 sccm, a gallium source flow rate of 150-200 sccm, and a hydrogen flow rate of 2500-3500 sccm.

[0073] More specifically, the direction of upward growth along the temporary substrate 11 is determined to be the direction from the nitrogen polar surface to the gallium polar surface (i.e., the aforementioned first direction 1). If a silicon substrate is used as the temporary substrate 11, gallium polar surface growth of gallium nitride (here, gallium nitride refers to the buffer layer 12) can be achieved by controlling the growth conditions; if a sapphire substrate is used as the temporary substrate 11, it is beneficial for gallium atoms to occupy surface positions during the growth process, thereby forming a gallium polar surface.

[0074] For example, the buffer layer 12 may be formed using metal-organic chemical vapor deposition (MOCVD) technology in a reaction chamber at a temperature of 1100-1200°C (e.g., 1100°C, 1110°C, 1120°C, 1130°C, 1140°C, 1150°C, 1160°C, 1170°C, 1180°C, 1190°C, or 1200°C) and a pressure of 30-50 Torr (e.g., 30 Torr, 35 Torr, 40 Torr, 45 Torr, or 50 Torr), with an ammonia flow rate of 1500-2500 sccm (e.g., 1500 sccm, 1800 sccm, 1900 sccm, 2200 sccm). Under process conditions of 2400 sccm or 2500 sccm), gallium source flow rate of 150-200 sccm (e.g., 2150 sccm, 160 sccm, 170 sccm, 180 sccm, 190 sccm or 200 sccm), and hydrogen flow rate of 2500-3500 sccm (e.g., 2500 sccm, 2700 sccm, 2900 sccm, 3000 sccm, 3300 sccm or 3500 sccm), gallium nitride with a thickness of 800-1000 nm (e.g., 800 nm, 850 nm, 900 nm, 950 nm or 1000 nm) is formed as buffer layer 12.

[0075] In one embodiment, a buffer layer 12 is epitaxially grown on a temporary substrate 11 along a first direction 1, including the following steps S111 and S112.

[0076] Step S111: Epitaxially grow a nucleation layer on the surface of the temporary substrate 11 along the first direction 1.

[0077] Step S112: Epitaxially grow a buffer layer 12 on the surface of the nucleation layer along the first direction 1.

[0078] The nucleation layer (not shown) includes an aluminum nitride nucleation layer or a gallium nitride nucleation layer. By forming the nucleation layer before forming the buffer layer 12, the quality of the buffer layer 12 is improved and the formation of the buffer layer 12 is facilitated.

[0079] Step S12: Epitaxially grow a porous gallium nitride layer 13 on the surface of the buffer layer 12 along the first direction 1.

[0080] The process conditions for the porous gallium nitride layer 13 include a temperature of 800-1100℃ and a pressure of 100-500Pa, and the porosity density of the porous gallium nitride layer 13 is 10. 7 -10 10 cm -3 The pore size is 50-150nm.

[0081] For example, the porous gallium nitride layer 13 can be formed using metal-organic chemical vapor deposition (MOCVD) technology, using trimethylgallium (TMGa) as the gallium source and ammonia (NH3) as the nitrogen source, in a reaction chamber at a temperature of 800-1100°C (e.g., 800°C, 850°C, 900°C, 950°C, 1000°C, 1050°C, or 1100°C) and a pressure of 100-500 Pa (e.g., 100 Pa, 200 Pa, 300 Pa, 400 Pa, or 500 Pa). Laser annealing is then used to control the porosity and pore size of the gallium nitride layer, controlling the porosity density to be 10-1. 7 -10 10 cm -3 (For example, 10) 7 cm -3 10 8 cm -3、 10 9 cm -3 Or 10 10 cm -3 A porous gallium nitride layer 13 is formed with a pore size of 50-150 nm (e.g., 50 nm, 80 nm, 100 nm, 130 nm or 150 nm).

[0082] Because the porous gallium nitride layer 13 has a porous structure, it can absorb stress. When removing the temporary substrate 11, it can be peeled off from the interface formed by the porous gallium nitride layer 13 and the barrier structure 14, which is convenient for peeling off and will not affect the barrier structure 14.

[0083] like Figures 3 to 6 As shown, in step S2, a barrier structure 14, a channel layer 15, a support layer 16, a thermally conductive layer 17, and a diamond substrate 18 are epitaxially grown sequentially on the surface of the porous gallium nitride layer 13 along the first direction 1 to obtain the first structure.

[0084] (1) As Figure 3 and Figure 4 As shown, a barrier structure 14 is epitaxially grown sequentially along the first direction 1 on the surface of the porous gallium nitride layer 13.

[0085] The metal content in the barrier structure 14 gradually increases and then gradually decreases along the first direction 1.

[0086] In one implementation, the reference Figure 3 and Figure 4 As shown, the barrier structure 14 includes a transition layer 141 and a barrier layer 142 stacked along the first direction 1. The metal content in the transition layer 141 gradually increases along the first direction 1, and the metal content in the barrier layer 142 gradually decreases along the first direction 1.

[0087] Based on this, a transition layer 141 and a barrier layer 142 are epitaxially grown sequentially on the surface of the porous gallium nitride layer 13 along the first direction 1, including the following steps S21 and S22.

[0088] Step S21: When introducing a metal source into the deposition chamber, gradually increase the flow rate of the metal source to form a transition layer 141 in which the metal content gradually increases along the first direction 1.

[0089] The process conditions for the transition layer 141 include a temperature of 1080-1100℃ and a pressure of 60-80 Torr.

[0090] Step S22: When introducing a metal source into the deposition chamber, gradually reduce the flow rate of the metal source to form a barrier layer 142 in which the metal content gradually decreases along the first direction 1.

[0091] The process conditions for barrier layer 142 include a temperature of 1040-1060℃ and a pressure of 60-80 Torr.

[0092] In one embodiment, the transition layer 141 and the barrier layer 142 comprise any one of AlGaN, InAlN, ScAlN, and BAlN. When the transition layer 141 and the barrier layer 142 are AlGaN, the metal whose content changes along the first direction 1 is Al; or, when the transition layer 141 and the barrier layer 142 are InAlN, the metal whose content changes along the first direction 1 is In; or, when the transition layer 141 and the barrier layer 142 are ScAlN, the metal whose content changes along the first direction 1 is Sc; or, when the transition layer 141 and the barrier layer 142 are BAlN, the metal whose content changes along the first direction 1 is B.

[0093] In one embodiment, the thickness of the transition layer 141 is greater than the thickness of the barrier layer 142.

[0094] In one embodiment, the thickness of the transition layer 141 is 40-80 nm, and the thickness of the barrier layer 142 is 30-50 nm.

[0095] For example, both the transition layer 141 and the barrier layer 142 can be formed using metal-organic chemical vapor deposition (MOCVD), and the material of the transition layer 141 is Al. x Ga 1-x N, x ranges from (0, 0.3), for example, x is 0.05, 0.1, 0.15, 0.2 or 0.25, and the barrier layer 142 is Al. y Ga 1-y The range of N, y is (0.2, 0.4), for example, y is 0.22, 0.25, 0.3, 0.35 or 0.38.

[0096] Using triethylgallium, trimethylaluminum, and high-purity ammonia as gallium, aluminum, and ammonia sources, respectively, Al with a thickness of 40-80 nm (e.g., 1080°C, 1090°C, or 1100°C) is deposited on a porous gallium nitride layer 13 in a deposition chamber at a temperature of 1080-1100°C (e.g., 1080°C, 1090°C, or 1100°C) and a pressure of 60-80 Torr (e.g., 60 Torr, 65 Torr, 70 Torr, 75 Torr, or 80 Torr). x Ga 1-x N serves as the transition layer 141. During its formation, the amount of trimethylaluminum introduced is controlled to achieve a change in x from low to high. For example, at the beginning of growth, no or very little trimethylaluminum is introduced, and then the amount of trimethylaluminum introduced is gradually increased, starting from 5 sccm and gradually adjusted to 60 sccm, thereby forming a transition layer 141 in which the metal content gradually increases along the first direction 1.

[0097] Similarly, using triethylgallium, trimethylaluminum, and high-purity ammonia as gallium, aluminum, and ammonia sources, respectively, an Al layer with a thickness of 30-50 nm (e.g., 30 nm, 35 nm, 40 nm, 45 nm, or 50 nm) is deposited on the transition layer 141 in a deposition chamber at a temperature of 1040-1060 °C (e.g., 1040 °C, 1050 °C, or 1060 °C) and a pressure of 60-80 Torr (e.g., 60 Torr, 65 Torr, 70 Torr, 75 Torr, or 80 Torr). y Ga 1-y N serves as barrier layer 142. The amount of trimethylaluminum introduced is controlled to achieve a change in y from high to low. For example, a larger amount of trimethylaluminum is introduced at the beginning of growth, and then the amount of trimethylaluminum introduced is gradually reduced, from 80 sccm to 40 sccm, thereby forming barrier layer 142 with a metal content that gradually decreases along the first direction 1.

[0098] It should be noted that when the transition layer 141 and the barrier layer 142 are grown, the temperature of the transition layer 141 is higher than that of the barrier layer 142, thereby improving the crystal quality of the transition layer 141. The transition layer 141 is formed on the porous gallium nitride layer 13, and the metal content of the transition layer 141 gradually increases along the first direction 1, similar to the transition interface, thereby ensuring that there will be no large interface mutation between the porous gallium nitride layer 13 and the transition layer 141, and being able to better match the porous gallium nitride layer 13 to improve the crystal properties of the material formed by the transition layer 141 along the first direction 1. The barrier layer 142 is formed on the transition layer 141, and the metal content of the barrier layer 142 gradually decreases along the first direction 1, thereby ensuring that the metal content difference between the transition layer 141 and the barrier layer 142 is not large, being able to better match, and not generating excessive lattice mismatch, and ensuring that there will be no large interface mutation between the barrier layer 142 and the channel layer 15, which is beneficial to better lattice matching.

[0099] At the same time, during the growth process of the transition layer 141 and the barrier layer 142, only the flow rate of trimethylaluminum needs to be gradually adjusted to achieve a gradual change in the aluminum doping concentration, without the need to frequently switch different material sources or change the growth conditions, which is beneficial to improving the repeatability and stability of the process; and the gradual change in the metal content in the transition layer 141 and the barrier layer 142 is continuous. Compared with the abrupt interface, it can reduce the interface defects and stress concentration between different aluminum concentration layers, which is beneficial to growing a barrier layer 142 with better quality.

[0100] Preferably, the metal content in the barrier layer 142 is greater than that in the transition layer 141. Thus, after subsequent flipping treatment and preparation of the compound semiconductor device 100, the barrier layer 142 with a high metal content located in the lower layer can generate stronger spontaneous polarization and piezoelectric polarization effects, significantly enhancing the two-dimensional electron gas (2DEG) surface density at the heterointerface.

[0101] See Figure 4 As shown, at the bonding surface 140 formed by the transition layer 141 and the barrier layer 142, the metal content in the transition layer 141 and the metal content in the barrier layer 142 can be close to or equal, and the change rate formed by the metal content in the transition layer 141 increasing from low to high along the first direction 1 and the change rate formed by the metal content in the barrier layer 142 increasing from low to high along the second direction 2 opposite to the first direction 1 can be close to or equal. This embodiment does not make specific limitations on this.

[0102] In another embodiment, the transition layer 141 and the barrier layer 142 can be considered as an integral structure, namely, the barrier structure 14. During the growth process, the amount of metal source introduced is gradually increased first, and then gradually decreased, thereby forming a barrier structure 14 in which the metal content gradually increases and then gradually decreases along the first direction 1. This embodiment does not specifically limit this. Preferably, the barrier structure 14 is composed of the transition layer 141 and the barrier layer 142.

[0103] (2) Figure 4 As shown, a channel layer 15 is formed on the barrier layer 142.

[0104] The channel layer 15 includes gallium nitride; the thickness of the channel layer 15 is 500-3000 nm; the process conditions of the channel layer 15 include a temperature of 1100-1150 °C and a pressure of 80-100 Torr.

[0105] For example, the channel layer 15 can be formed using metal-organic chemical vapor deposition (MOCVD), with triethylgallium and high-purity ammonia as the gallium source and ammonia source, respectively. Gallium nitride with a thickness of 500-3000 nm (e.g., 500 nm, 600 nm, 800 nm, 1300 nm, 2000 nm, 2500 nm, or 3000 nm) is formed on the barrier structure 14 as the channel layer 15 within a deposition chamber at a temperature of 1100-1150°C (e.g., 1100°C, 1110°C, 1120°C, 1130°C, 1140°C, or 1150°C) and a pressure of 80-100 Torr (e.g., 80 Torr, 90 Torr, or 100 Torr). A higher temperature is required during the growth of the channel layer 15 to improve its quality.

[0106] Preferably, the barrier layer 142 and the channel layer 15 are grown in the same deposition chamber to avoid the time extension caused by changing the deposition chamber and possible contamination by water and oxygen impurities.

[0107] (3) Figure 5 As shown, a support layer 16 is formed on the channel layer 15.

[0108] The support layer 16 includes gallium nitride; the thickness of the support layer 16 is 3-20 μm; the process conditions of the support layer 16 include: temperature of 1100-1150℃, pressure of 40-60 Torr, ammonia flow rate of 1500-2000 sccm, gallium source flow rate of 50-100 sccm and hydrogen flow rate of 2500-3500 sccm.

[0109] For example, the support layer 16 may be formed using metal-organic chemical vapor deposition (MOCVD) technology in a reaction chamber at a temperature of 1100-1150°C (e.g., 1100°C, 1110°C, 1120°C, 1130°C, 1140°C, or 1150°C) and a pressure of 40-60 Torr (e.g., 40 Torr, 50 Torr, or 60 Torr), with an ammonia flow rate of 1500-2000 sccm (e.g., 1500 sccm, 1600 sccm, 1700 sccm, 1800 sccm, 1900 sccm, or 2...). Gallium nitride with a thickness of 3-20 μm (e.g., 3 μm, 6 μm, 9 μm, 13 μm, 15 μm, or 20 μm) is formed as a support layer 16 under process conditions of gallium source flow rate of 50-100 sccm (e.g., 50 sccm, 60 sccm, 70 sccm, 80 sccm, 90 sccm, or 100 sccm) and hydrogen flow rate of 2500-3500 sccm (e.g., 2500 sccm, 2800 sccm, 3000 sccm, 3200 sccm, or 3500 sccm) and hydrogen flow rate of 2500-3500 sccm (e.g., 2500 sccm, 2800 sccm, 3000 sccm, 3200 sccm, or 3500 sccm).

[0110] The support layer 16 provides support during the subsequent peeling of the multilayer docking structure 10 and has high thermal conductivity with the diamond substrate 18.

[0111] It is worth noting that the thickness of the support layer 16 does not need to be too thick; it only needs to serve as a transition and facilitate heat conduction.

[0112] (4) Figure 5 As shown, a heat-conducting layer 17 is formed on the support layer 16.

[0113] The thermal conductive layer 17 includes silicon carbide; the thickness of the thermal conductive layer 17 is 80-150nm; the process conditions of the thermal conductive layer 17 include: sputtering temperature of 200-600℃ and RF power of 100-150W.

[0114] For example, the thermal conductive layer 17 can be formed by magnetron sputtering. Under the process conditions of sputtering temperature of 200-600°C (e.g., 200°C, 300°C, 400°C, 500°C or 600°C) and RF power of 100-150W (e.g., 100W, 110W, 120W, 130W, 140W or 150W), silicon carbide with a thickness of 80-150nm (e.g., 80nm, 90nm, 100nm, 110nm, 120nm, 130nm, 140nm or 150nm) is formed on the support layer 16 as the thermal conductive layer 17.

[0115] Furthermore, if the target material for growing silicon carbide is a Si target, then the working gas is Ar and CH4; if the target material for growing silicon carbide is a SiC target, then the working gas is Ar.

[0116] It should be noted that the thermally conductive layer 17 is made of silicon carbide. Silicon carbide and the subsequently formed diamond substrate 18 share certain similarities in crystal structure, both being covalently bonded crystals. During the growth process, when the diamond substrate 18 is formed on the support layer 16, silicon carbide promotes the nucleation and epitaxial growth of the diamond crystals, resulting in better crystal quality of the diamond substrate 18 and further improving heat dissipation performance. Simultaneously, silicon carbide (i.e., the thermally conductive layer 17) has high thermal conductivity, which is close to that of diamond (i.e., the diamond substrate 18) and gallium nitride (i.e., the support layer 16). This allows for smoother heat transfer between gallium nitride, silicon carbide, and diamond, reducing thermal resistance caused by excessive differences in thermal conductivity and effectively improving heat dissipation performance.

[0117] (5) Figure 6 As shown, a diamond substrate 18 is formed on the thermally conductive layer 17.

[0118] The process conditions for the diamond substrate 18 include: a temperature of 800-1000℃, a methane flow rate of 20-100 mL / min, a pressure of 100-200 Torr, a microwave power of 2-5 kW, a nitrogen flow rate of 20-100 μL / min, and a hydrogen flow rate of 500-1000 mL / min. The thickness of the diamond substrate 18 is 30-100 μm.

[0119] Exemplarily, the diamond substrate 18 may be formed using microwave plasma chemical vapor deposition (MPCVD) in a reaction chamber at a temperature of 800-1000°C (e.g., 800°C, 900°C, or 1000°C), a pressure of 100-200 Torr (e.g., 100 Torr, 130 Torr, 170 Torr, 185 Torr, or 200 Torr), and a microwave power of 2-5 kW (e.g., 2 kW, 3 kW, 4 kW, or 5 kW), with a methane flow rate of 20-100 mL / min (e.g., 20 mL / min, 40 mL / min, 60 mL / min, 80 mL / min, or 10 mL / min). Under process conditions where the flow rate of nitrogen is 20-100 μL / min (e.g., 20 mL / min, 40 mL / min, 60 mL / min, 80 mL / min or 100 mL / min) and the flow rate of hydrogen is 500-1000 mL / min (e.g., 500 mL / min, 600 mL / min, 700 mL / min, 800 mL / min, 900 mL / min or 100 mL / min), a diamond substrate 18 with a thickness of 30-100 μm (e.g., 30 μm, 50 μm, 70 μm, 90 μm or 100 μm) is formed on the thermally conductive layer 17.

[0120] Preferably, the diamond substrate 18 is made of single-crystal diamond. The thermal conductivity of single-crystal diamond can theoretically reach 2000-2200 W / (m·K), which is one of the materials with the highest thermal conductivity in nature. Its crystal structure is complete, with few defects, less phonon scattering, and a long mean free path of phonons, so that heat can be conducted efficiently through lattice vibration.

[0121] Based on this, a temporary substrate 11, a buffer layer 12, a porous gallium nitride layer 13, a transition layer 141, a barrier layer 142, a channel layer 15, a support layer 16, a thermally conductive layer 17, and a diamond substrate 18 are sequentially formed from bottom to top along the first direction 1; and after subsequent reversal, the diamond substrate 18, the thermally conductive layer 17, the support layer 16, the channel layer 15, the barrier layer 142, the transition layer 141, the porous gallium nitride layer 13, the buffer layer 12, and the temporary substrate 11 are sequentially formed from bottom to top along the second direction 2 opposite to the first direction 1.

[0122] Step S3: The first structure is flipped, and the multilayer docking structure 10 is peeled off at the interface formed by the barrier structure 14 and the porous gallium nitride layer 13.

[0123] Flip the first structure (not labeled) so that the gallium polar face is downward and the nitrogen polar face is upward. Using the support layer 16, the thermal conduction layer 17, and the diamond substrate 18 together as the support substrate during peeling, peel off and remove the upper multi-layer docking structure 10 (i.e., including the temporary substrate 11, the buffer layer 12, and the porous gallium nitride layer 13), to obtain Figure 7 the structure shown. The peeling process can adopt a laser peeling process, and by controlling the power and angle of the laser, the bonding surface 131 between the porous gallium nitride layer 13 and the transition layer 141 contained in the barrier structure 14 can be accurately controlled. This embodiment does not make specific limitations on this.

[0124] Refer Figure 7 As shown, during actual peeling, there may be some residual porous gallium nitride 13a after the porous gallium nitride layer 13 is peeled off. The residual porous gallium nitride 13a can be removed through a cleaning process to complete the overall peeling of the multi-layer docking structure 10. The cleaning process includes wet etching or plasma cleaning, etc. This embodiment does not make specific limitations on this.

[0125] It should be noted that in the present invention, before the flipping process, a transition layer 141 is formed on the multi-layer docking structure 10. Since the quality of the film layer formed by the transition layer 141 is particularly important for the compound semiconductor device 100, and the transition layer 141 is close to the separated multi-layer docking structure 10. Compared with the laser peeling or chemical peeling in the prior art, the damage or stress during the peeling process is likely to cause damage or destruction to the transition layer 141; while in the present invention, the porous gallium nitride layer 13 is adopted. Since the porous gallium nitride layer 13 can release the interfacial bonding force, and the shear stress generated during the peeling process can be absorbed, it can prevent the damage to the underlying transition layer 141 and the barrier layer 142 during peeling.

[0126] Step S4, form a number of electrodes isolated from each other on the surface of the barrier structure 14 to prepare the compound semiconductor device 100.

[0127] The barrier structure 14 includes a transition layer 141 and a barrier layer 142 stacked in a first direction. Forming a number of electrodes isolated from each other on the surface of the barrier structure 14 includes the following steps S41 and step S42.

[0128] Refer Figure 9 and Figure 10 As shown, step S41, form a gate groove 21 penetrating through the transition layer 141 and extending along the first direction 1 to the barrier layer 142 inside the transition layer 141.

[0129] The formation method of the gate groove 21 can be by using photolithography and etching processes. First, a photoresist layer is coated on the surface of the transition layer 141 and dried and cured to form a photoresist layer 20. Secondly, the photoresist layer 20a corresponding to the gate region is removed through exposure and development processes, and a photoresist layer (not labeled) with an opening is formed on the surface of the transition layer 141. Finally, with the photoresist layer with an opening as a mask, the exposed areas of the underlying transition layer 141 and the barrier layer 142 are etched to form the gate groove 21 in the transition layer 141 and the barrier layer 142. Among them, the thickness of the photoresist layer 20 is 200 - 500 nm (for example, 200 nm, 300 nm, 400 nm or 500 nm), the photoresist layer can be a positive photoresist layer or a negative photoresist layer, the etching can be dry etching or wet etching, the depth of the gate groove 21 is 60 - 80 nm (that is, the sum of d1, d2 and d3, for example, 60 nm, 65 nm, 70 nm, 75 nm or 80 nm), and this embodiment does not make specific limitations on this.

[0130] Refer Figure 11 and Figure 12 As shown, in step S42, a gate dielectric layer 22 is formed on the surface of the gate groove 21, a passivation layer 23 is formed on the surface of the transition layer 141, and a plurality of electrodes isolated by the passivation layer 23 are formed above the gate dielectric layer 22.

[0131] Refer Figure 11 As shown, the gate dielectric layer 22 is a first gate dielectric layer 221 formed on the surface of the gate groove 21, or a double - layer gate dielectric layer composed of the first gate dielectric layer 221 or the second gate dielectric layer 222 formed in sequence from the surface of the gate groove 21. The first gate dielectric layer 221 includes alumina, the second gate dielectric layer 222 includes hafnium oxide, the thickness of the first gate dielectric layer 221 is 3 - 10 nm, and the thickness of the second gate dielectric layer 222 is 10 - 20 nm. The plurality of electrodes include a gate 26, a source 24 that forms an ohmic contact with the transition layer 141, and a drain 25. The passivation layer 23 isolates the source 24, the drain 25 and the gate 26. The passivation layer 23 includes silicon nitride or silicon oxide, the thickness of the passivation layer 23 is 20 - 50 nm, and the source 24, the drain 25 and the gate 26 include elemental metals or alloys of titanium, aluminum, nickel, copper or gold.

[0132] Exemplarily, refer Figures 10 to 11As shown, after etching to form the gate groove 21, the photoresist layer 20a is removed by ashing. Ozone can be used as the ashing process gas to achieve the ashing process. For example, ozone can be used as an oxidizing free radical to react with hydrocarbons (CH) in the photoresist to generate volatile substances, such as carbon dioxide (CO2) and water vapor (H2O), to remove the photoresist layer 20a. The ashing temperature for removing the photoresist layer 20a is 250-300℃. Because ozone has strong oxidizing properties, the sidewall surfaces of the exposed barrier layer 142 and transition layer 141 will also be oxidized when removing the photoresist layer 20a. Since both the barrier layer 142 and transition layer 141 are AlGaN materials, the oxides formed by sidewall oxidation are mainly aluminum oxide with a small amount of gallium oxide. However, since aluminum oxide is the material of the double gate dielectric layer, the presence of a small amount of gallium oxide will not affect the insulation properties of the double gate dielectric layer.

[0133] like Figure 11 As shown, after removing the photoresist layer 20a, aluminum oxide with a thickness of 3-10nm (e.g., 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm or 10nm) and hafnium oxide with a thickness of 10-20nm (e.g., 10nm, 13nm, 15nm, 18nm or 20nm) are formed in the gate recess 21, which serve as the first gate dielectric layer 221 and the second gate dielectric layer 222, respectively, and the first gate dielectric layer 221 and the second gate dielectric layer 222 form a double gate dielectric layer. The lower aluminum oxide layer can be formed using atomic layer deposition (ALD). Since aluminum oxide and gallium oxide, which may have been oxidized, may form inside the gate recess 21, aluminum oxide is first formed as the first gate dielectric layer 221 to facilitate better adhesion to the inner wall of the gate recess 21. ALD is used to improve the density of the deposited first gate dielectric layer 221. The upper hafnium oxide layer can be formed using sputtering or ALD. Hafnium oxide is a high dielectric constant material, which can improve the characteristics of the double gate dielectric layer and reduce gate leakage current. Therefore, the double gate dielectric layer can reduce gate leakage current and increase the threshold voltage.

[0134] The passivation layer 23 can be formed by sputtering or atomic layer deposition, forming a silicon nitride or silicon oxide layer with a thickness of 20-50 nm on the surface of the gate trench 21 as the passivation layer 23. After forming the passivation layer 23, it is patterned to expose the source and drain regions on the surface of the transition layer 141. Metal deposition is performed in the source, drain, and gate regions to form the source 24, drain 25, and gate 26. The patterning process includes photolithography and etching steps. The source 24, drain 25, and gate 26 can be multilayer metals such as Ti / Al / Ni / Au or their alloys; this embodiment does not specifically limit this. A compound semiconductor device 100 is thus fabricated.

[0135] In summary, the fabrication method disclosed in this invention, compared to existing technologies, eliminates the need for a bonding support substrate, thus avoiding potential risks to the thermal and chemical stability of the material system at high temperatures. In particular, existing technologies typically use metal bonding layers, which introduce additional capacitance and resistance during the operation of the compound semiconductor device 100, affecting high-frequency performance. Furthermore, during prolonged operation, the large coefficient of thermal expansion between the metal and semiconductor layers leads to significant thermal stress, easily causing delamination or cracking between the materials in the compound semiconductor device 100. Additionally, the stress resulting from differences in the bonding material system is uncontrollable and unevenly distributed. This invention, by eliminating the need for bonding, avoids the process difficulties and performance instability associated with bonding. Moreover, the support layer 16 in this invention, in conjunction with the diamond substrate 18, provides support and heat dissipation, simplifying the fabrication process and improving the heat dissipation performance of the resulting compound semiconductor device 100.

[0136] Simultaneously, before the flipping process, a transition layer 141 is formed on the multilayer docking structure 10. The quality of the transition layer 141 is particularly important for the compound semiconductor device 100, and the transition layer 141 is close to the separated multilayer docking structure 10. Compared to laser or chemical peeling in the prior art, damage or stress during the peeling process can easily damage or destroy the transition layer 141. In this invention, a porous gallium nitride layer 13 is used. Since the porous gallium nitride layer 13 can release interfacial bonding forces and absorb the shear stress generated during peeling, it can prevent damage to the underlying transition layer 141 and barrier layer 142 during peeling.

[0137] A transition layer 141 is disposed between the porous gallium nitride layer 13 and the barrier layer 142. The purpose of the transition layer 141 is to improve the quality of the barrier layer 142 formed above. The transition layer 141 is made of an aluminum-doped gallium nitride AlGaN material system, with the doping concentration gradually increasing along the first direction 1. The barrier layer 142 is also made of an AlGaN material system, with the doping concentration gradually decreasing along the first direction 1. The metal content of the transition layer 141 and the barrier layer 142 changes in the order of low-high-low during formation, and after subsequent flipping processing, the metal content changes in the order of low-high-low, thus forming a double-layer gradient barrier structure 14. In particular, the metal content of the transition layer 141 gradually increases along the first direction 1, similar to a transition interface, thereby ensuring that there is no large interface abruptness between the porous gallium nitride layer 13 and the transition layer 141.

[0138] After the flipping process, the metal content in the lower barrier layer 142 gradually increases along the second direction 2, resulting in a gradual decrease in the conduction band bottom energy. This better confines the two-dimensional electron gas in the gate groove 21, reducing electron scattering from impurities and thus improving electron mobility. The metal content in the upper transition layer 141 gradually decreases along the second direction 2, making the electric field change between the barrier layer 142 and the surface smoother, reducing the scattering of electrons by surface states, further improving electron mobility, and contributing to the performance improvement of the compound semiconductor device 100. Simultaneously, the gradual increase in metal content in the lower barrier layer 142 along the second direction 2 causes more electrons to be absorbed into the gate groove 21, increasing the electron concentration in the gate groove 21. Although the metal content in the upper transition layer 141 gradually decreases along the second direction 2, it still provides a certain amount of electron accumulation. The combination of these two (i.e., the transition layer 141 and the barrier layer 142) effectively improves the current driving capability of the compound semiconductor device 100, thereby enhancing its power performance.

[0139] Based on the same inventive concept, Figure 12 As shown, the present invention also discloses a compound semiconductor device 100, which is prepared by the above-described preparation method. For details, please refer to the previous description, which will not be repeated here.

[0140] The compound semiconductor device 100 includes a diamond substrate 18, a thermally conductive layer 17, a support layer 16, a channel layer 15, and a barrier structure 14, which are sequentially stacked along a second direction 2. A plurality of mutually isolated electrodes are formed on the surface of the barrier structure 14. The metal content in the barrier structure 14 gradually increases and then gradually decreases along the second direction 2, where the second direction 2 is the direction from the gallium polar surface to the nitrogen polar surface.

[0141] Furthermore, the barrier structure 14 includes a transition layer 141 and a barrier layer 142 stacked along a first direction 1. The metal content in the transition layer 141 gradually decreases along a second direction 2, and the metal content in the barrier layer 142 gradually increases along a second direction 2.

[0142] The compound semiconductor device 100 provided by this invention can be grown on a nitrogen-polarized surface and has high quality. The metal content in the lower barrier layer 142 gradually increases along the second direction 2, which gradually reduces the conduction band bottom energy, better confining the two-dimensional electron gas in the gate groove 21, reducing electron scattering with impurities, and thus improving electron mobility. The metal content in the upper transition layer 141 gradually decreases along the second direction 2, which makes the electric field change between the barrier layer 142 and the surface more gradual, reducing the scattering of electrons by surface states, further improving electron mobility, and helping to improve the performance of the compound semiconductor device 100. Moreover, the gradual increase in the metal content in the lower barrier layer 142 along the second direction 2 causes more electrons to be absorbed into the gate groove 21, increasing the electron concentration of the gate groove 21. Although the metal content in the upper transition layer 141 gradually decreases along the second direction 2, it can still provide a certain amount of electron accumulation. The combination of the two (i.e., the transition layer 141 and the barrier layer 142) can effectively improve the current driving capability of the compound semiconductor device 100, thereby improving the power performance of the compound semiconductor device 100.

[0143] The detailed descriptions listed above are merely specific descriptions of feasible embodiments of the present invention, and are not intended to limit the scope of protection of the present invention. All equivalent embodiments or modifications made without departing from the spirit of the present invention should be included within the scope of protection of the present invention.

[0144] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0145] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A method for fabricating a compound semiconductor device, characterized in that, Includes the following steps: A multilayer docking structure is provided; wherein the multilayer docking structure includes a temporary substrate epitaxially grown along a first direction and a porous gallium nitride layer, the first direction being the direction from the nitrogen polar surface to the gallium polar surface; A barrier structure, a channel layer, a support layer, a thermally conductive layer, and a diamond substrate are sequentially epitaxially grown on the surface of the porous gallium nitride layer along the first direction to obtain a first structure; wherein, the metal content in the barrier structure gradually increases and then gradually decreases along the first direction. The first structure is flipped, and the multilayer docking structure is peeled off from the interface formed by the barrier structure and the porous gallium nitride layer. A compound semiconductor device is fabricated by forming several mutually isolated electrodes on the surface of the barrier structure.

2. The preparation method according to claim 1, characterized in that, The barrier structure includes a transition layer and a barrier layer stacked along the first direction, wherein the metal content in the transition layer gradually increases along the first direction, and the metal content in the barrier layer gradually decreases along the first direction.

3. The preparation method according to claim 2, characterized in that, The porous gallium nitride layer is epitaxially grown with a transition layer and a barrier layer sequentially on its surface, including: When a metal source is introduced into the deposition chamber, the flow rate of the metal source is gradually increased to form a transition layer in which the metal content gradually increases along the first direction. When a metal source is introduced into the deposition chamber, the flow rate of the metal source is gradually reduced to form a barrier layer in which the metal content gradually decreases along the first direction.

4. The preparation method according to claim 3, characterized in that, The process conditions for the transition layer include: a temperature of 1080-1100℃ and a pressure of 60-80 Torr. The process conditions for the barrier layer include a temperature of 1040-1060℃ and a pressure of 60-80 Torr.

5. The preparation method according to claim 2, characterized in that, The transition layer and the barrier layer include any one of AlGaN, InAlN, ScAlN, and BAlN; When the transition layer and the barrier layer are AlGaN, the metal whose content changes along the first direction is Al; or, when the transition layer and the barrier layer are InAlN, the metal whose content changes along the first direction is In; or, when the transition layer and the barrier layer are ScAlN, the metal whose content changes along the first direction is Sc; or, when the transition layer and the barrier layer are BAlN, the metal whose content changes along the first direction is B. And / or, the thickness of the transition layer is greater than the thickness of the barrier layer; And / or, the thickness of the transition layer is 40-80 nm, and the thickness of the barrier layer is 30-50 nm; And / or, the metal content in the barrier layer is greater than the metal content in the transition layer.

6. The preparation method according to claim 1, characterized in that, The provided multi-layer docking structure includes: A temporary substrate is provided, and a buffer layer is epitaxially grown on the surface of the temporary substrate along the first direction; The porous gallium nitride layer is epitaxially grown on the surface of the buffer layer along the first direction; The temporary substrate includes a silicon-based substrate or a sapphire substrate, and the buffer layer includes gallium nitride. The silicon substrate has a crystal plane index of (111) along the first direction, and the sapphire substrate has a crystal plane index of (0001) along the first direction. The thickness of the buffer layer is 800-1000 nm, and the process conditions of the buffer layer include: temperature of 1100-1200℃, pressure of 30-50 Torr, ammonia flow rate of 1500-2500 sccm, gallium source flow rate of 150-200 sccm and hydrogen flow rate of 2500-3500 sccm. The process conditions for the porous gallium nitride layer include: a temperature of 800-1100℃ and a pressure of 100-500 Pa, and the porosity density of the porous gallium nitride layer is 10. 7 -10 10 cm -3 The pore size is 50-150nm.

7. The preparation method according to claim 6, characterized in that, The epitaxial growth of a buffer layer on the temporary substrate along the first direction includes: A nucleation layer is epitaxially grown on the surface of the temporary substrate along the first direction; The buffer layer is epitaxially grown on the surface of the nucleation layer along the first direction; The nucleation layer includes an aluminum nitride nucleation layer or a gallium nitride nucleation layer.

8. The preparation method according to claim 1, characterized in that, The process conditions for the channel layer include: a temperature of 1100-1150℃ and a pressure of 80-100 Torr. The process conditions for the support layer include: a temperature of 1100-1150℃, a pressure of 40-60 Torr, a flow rate of 1500-2000 sccm for ammonia, a flow rate of 50-100 sccm for gallium source, and a flow rate of 2500-3500 sccm for hydrogen. The process conditions for the thermal conductive layer include: sputtering temperature of 200-600℃ and radio frequency power of 100-150W; The process conditions for the diamond substrate include: a temperature of 800-1000℃, a methane flow rate of 20-100 mL / min, a pressure of 100-200 Torr, a microwave power of 2-5 kW, a nitrogen flow rate of 20-100 μL / min, and a hydrogen flow rate of 500-1000 mL / min. And / or, the thickness of the diamond substrate is 30-100 μm; And / or, the thermally conductive layer comprises silicon carbide, and the thickness of the thermally conductive layer is 80-150 nm; And / or, the thickness of the support layer is 3-20 μm; And / or, the thickness of the channel layer is 500-3000 nm; And / or, the support layer and the channel layer comprise gallium nitride.

9. The preparation method according to claim 1, characterized in that, The barrier structure includes a transition layer and a barrier layer stacked along the first direction, and the formation of a plurality of mutually isolated electrodes on the surface of the barrier structure includes: A gate groove is formed inside the transition layer, penetrating the transition layer and extending along the first direction to the barrier layer; A gate dielectric layer is formed on the surface of the gate recess, a passivation layer is formed on the surface of the transition layer, and a plurality of electrodes isolated by the passivation layer are formed above the gate dielectric layer. The plurality of electrodes include a gate, a source and a drain that form an ohmic contact with the transition layer, the passivation layer isolates the source, the drain and the gate, the passivation layer includes silicon nitride or silicon oxide, the thickness of the passivation layer is 20-50 nm, and the source, drain and gate include elemental metals or alloys of titanium, aluminum, nickel, copper or gold. The gate dielectric layer is a first gate dielectric layer formed on the surface of the gate recess, or a double gate dielectric layer composed of a first gate dielectric layer and a second gate dielectric layer formed sequentially from the surface of the gate recess. The first gate dielectric layer includes aluminum oxide, and the second gate dielectric layer includes hafnium oxide. The thickness of the first gate dielectric layer is 3-10 nm, and the thickness of the second gate dielectric layer is 10-20 nm.

10. A compound semiconductor device, characterized in that, include: A diamond substrate, a thermally conductive layer, a support layer, a channel layer, and a barrier structure are sequentially stacked along a second direction, and a plurality of mutually isolated electrodes are formed on the surface of the barrier structure. The metal content in the barrier layer structure gradually increases and then gradually decreases along the second direction; the second direction is the direction from the gallium polar surface to the nitrogen polar surface.

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