Asymmetric fin heat conduction enhanced GaN HEMT device and manufacturing method thereof

Abstract

The invention relates to an asymmetric fin heat conduction enhanced GaN HEMT device and a manufacturing method thereof, and belongs to the technical field of semiconductor devices, the asymmetric fin heat conduction enhanced GaN HEMT device comprises a substrate, a buffer layer, a channel layer, a barrier layer, a grid electrode, a source electrode and a drain electrode, a composite passivation layer is formed by embedding high heat conduction heat dissipation fins in a drain electrode side passivation layer, a heat conduction side wall is introduced, and a high heat conduction material and a composite structure are utilized to form a high heat conduction enhanced GaN HEMT device. The heat conduction bottleneck of a surface medium is effectively broken, the surface heat dissipation area is increased, a multi-dimensional heat dissipation path is constructed, the peak temperature in the device is remarkably reduced, parameter degradation and hot carrier injection damage under electrothermal coupling cooperation are relieved from the source, and therefore the overall electrical performance and reliability of the device are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to a gallium nitride (GaN) high electron mobility transistor (HEMT) based heat dissipation structure optimization and manufacturing method, belonging to the technical field of semiconductor devices. Specifically, the present application provides an asymmetric fin heat conduction enhanced GaN HEMT device and its manufacturing method, aiming to suppress the self-heating effect of the device under high power operation through the synergistic optimization of materials and processes, reduce the channel peak temperature by increasing the heat dissipation contact area and introducing a high thermal conductivity path, and improve the reliability of the device. The device can be widely used in high-frequency, high-power and high-temperature application fields such as power electronics and radio frequency power amplifiers. BACKGROUND

[0002] Wide bandgap GaN material has become the core material in high-frequency, high-power and high-temperature semiconductor application fields due to its high electron mobility, high saturation electron velocity and excellent critical breakdown field strength. Especially in the fields of 5G communication and power electronic conversion, GaN HEMT devices have shown great application potential. However, with the continuous increase of device power density, GaN HEMT faces extremely severe thermal management challenges in practical applications. Because the device generates extremely high Joule heat in the channel near the drain side of the gate, forming a local "hot spot" and causing significant self-heating effect, which leads to degradation of device performance and deterioration of long-term reliability.

[0003] In view of the thermal management needs of traditional enhancement mode GaN HEMT, various improvement methods have been proposed, such as thinning the substrate to shorten the heat conduction path, using high thermal conductivity substrates (such as SiC or diamond) or introducing micro-channel cooling technology. However, these methods often have the negative effects of significantly increasing process complexity, skyrocketing manufacturing cost or making the wafer brittle, and existing solutions focus more on backside heat dissipation, ignoring the heat dissipation path in the front channel region, resulting in limited heat dissipation efficiency due to material physical properties.

[0004] In addition, in the structure of traditional P-GaN gate GaN HEMT devices, there are the following main problems in heat dissipation and reliability: (1) heat accumulation near the channel: conventional devices generally use single SiO2 as the passivation layer. The thermal conductivity of SiO2 is extremely low (about 1.4 W / m*K), forming a serious high thermal resistance path on the surface of the device, which causes the Joule heat generated in the channel to be unable to dissipate efficiently through the surface. The heat accumulates in the near-channel region, causing severe phonon scattering and leading to a significant decrease in carrier mobility, which is manifested macroscopically as a decrease in drain saturation current and a drop in output power; (2) degradation of parameter stability under thermal excitation: the severe self-heating effect significantly accelerates the capture and release of charges by the trap states at the interface between the P-GaN gate and the passivation layer. This trap effect caused by thermal excitation leads to a significant shift of the threshold voltage V thSignificant drift occurs, and the dynamic on-resistance deteriorates, severely affecting the electrical stability of the device under high-speed switching conditions; (3) Hot carrier injection (HCl): Under the combined effect of high electric field and high temperature, the hot carrier injection effect is aggravated, and electrons are more likely to penetrate the barrier and enter the passivation layer, resulting in interface quality deterioration, which in turn leads to a long-term decline in device reliability. The above problems together limit the performance improvement and reliability of P-GaN HEMT.

[0005] In summary, existing technologies urgently require a new device structure and manufacturing process that can effectively dissipate surface heat, suppress thermally excited trap degradation, and enhance hot carrier injection protection capabilities, thereby improving the device's threshold voltage stability, power density, and reliability. To this end, this invention proposes an enhanced gallium nitride device with asymmetric fin thermal conductivity and its manufacturing method, providing an effective solution to the aforementioned problems. Summary of the Invention

[0006] To address the problems of near-channel heat buildup, threshold voltage drift, and significant hot carrier injection effects caused by self-heating in existing P-GaN enhancement-mode gallium nitride high electron mobility transistors (HEMTs), this invention proposes an asymmetric finned thermally enhanced gallium nitride device and its fabrication method. This invention forms a composite passivation layer by embedding high thermal conductivity heat dissipation fins into the drain-side passivation layer and introducing thermally conductive sidewalls. Utilizing high thermal conductivity materials and a composite structure, this effectively breaks through the thermal conduction bottleneck of the surface medium, increases the surface heat dissipation area, constructs multi-dimensional heat dissipation pathways, and significantly reduces the peak temperature inside the device. This fundamentally alleviates parameter degradation and hot carrier injection damage under electrothermal coupling, thereby improving the overall electrical performance and reliability of the device.

[0007] The technical solution of the present invention is as follows:

[0008] An asymmetric fin thermally enhanced GaN HEMT device comprises, from bottom to top, a substrate, a GaN buffer layer, a GaN channel layer, and an AlGaN barrier layer. A source metal is disposed above the GaN buffer layer on one side of the GaN channel layer and the AlGaN barrier layer, and a drain metal is disposed above the GaN buffer layer on the other side of the GaN channel layer and the AlGaN barrier layer. An AlN sidewall is disposed above the substrate outside the drain metal.

[0009] A P-GaN cap layer is provided above the AlGaN barrier layer, and a gate metal is provided above the P-GaN cap layer;

[0010] A single passivation layer is provided between the P-GaN cap layer and the source metal, and above the AlGaN barrier layer; a composite passivation layer is provided between the P-GaN cap layer and the AlN sidewall.

[0011] Preferably, the single passivation layer is a SiO2 passivation layer, and the composite passivation layer includes a lower layer and an upper layer, the lower layer being SiO2 and the upper layer being AlN. Both the lower and upper layers are fin-shaped and are interlocked by a tooth-shaped interlocking mechanism.

[0012] In a further preferred embodiment, the highest point of the lower layer is not higher than the P-GaN cap layer and the drain metal, the AlN sidewall is higher than the drain metal, and the upper layer covers the drain metal and is flush with the AlN sidewall; the height of the single passivation layer on both sides of the P-GaN cap layer is the same as the height of the lower layer.

[0013] More preferably, the thickness of the SiO2 passivation layer is 10-2000 nm, and even more preferably, the thickness of the SiO2 passivation layer is 260 nm.

[0014] More preferably, the thickness of the upper AlN passivation layer is 5-2000 nm, and even more preferably, the thickness of the AlN passivation layer is 600 nm.

[0015] Further preferably, the depth of the upper and lower toothed fins is 2-500nm, preferably 190nm, the toothed fin width is 1μm, the spacing between two adjacent toothed fins is 1μm, and the number of lower toothed fins is 5.

[0016] According to a preferred embodiment of the present invention, the substrate material is silicon carbide, silicon, or sapphire; more preferably, the substrate material is silicon.

[0017] According to a preferred embodiment of the present invention, the thickness of the GaN buffer layer is 0.1-50 μm, and more preferably, the thickness of the GaN buffer layer is 5.2 μm.

[0018] According to a preferred embodiment of the present invention, the thickness of the GaN channel layer is 5-500 nm, and more preferably, the thickness of the GaN channel layer is 200 nm.

[0019] According to a preferred embodiment of the present invention, the thickness of the AlGaN barrier layer is 5-50 nm and the molar ratio of Al is 5-35%. More preferably, the thickness of the AlGaN barrier layer is 18 nm and the molar ratio of Al is 20%.

[0020] According to a preferred embodiment of the present invention, the thickness of the P-GaN cap layer is 1-500 nm, and more preferably, the thickness of the P-GaN cap layer is 100 nm.

[0021] According to a preferred embodiment of the present invention, the doping concentration of the P-GaN cap layer is 1×10⁻⁶. 17 -1×10 20 cm -3 More preferably, the doping concentration of the P-GaN cap layer is 3×10⁻⁶. 17 cm-3 The doping source is magnesium or boron.

[0022] According to a preferred embodiment of the present invention, the AlN sidewall has a width of 0.1-10 μm and a depth of 0.1-10 μm; more preferably, the AlN sidewall has a width of 1.5 μm and a depth of 5.2 μm.

[0023] According to a preferred embodiment of the present invention, the device has a gate-source pitch of 4 μm, a gate length of 4 μm, a gate-drain pitch of 12 μm, and a gate width of 100 μm; the gate-source pitch is the distance from the left side of the P-GaN cap layer to the source metal electrode, the gate length is the length from the left end to the right end of the P-GaN cap layer, the gate-drain pitch is the distance from the right side of the P-GaN cap layer to the drain metal electrode, and the gate width is the width of the gate metal extending into the paper.

[0024] Preferably, the source metal and drain metal are Ti / Al / Ni / Au, Ti / Al / Ti / Au, or Ti / Al / Mo / Au metal stacks. More preferably, the source metal and drain metal are Ti / Al / Ni / Au metal stacks, and the gate metal is Ni / Au metal stack.

[0025] A method for fabricating an asymmetric finned thermally enhanced GaN HEMT device includes the following steps:

[0026] S1. A GaN buffer layer, a GaN channel layer, an AlGaN barrier layer, and a P-GaN cap layer are sequentially grown on a Si substrate.

[0027] S2. Dry etching removes the P-GaN cap layer except for the area below the gate;

[0028] S3. Remove the GaN channel layer and AlGaN barrier layer outside the device by dry etching, and etch down to the GaN buffer layer to form a mesa;

[0029] S4. Source metal and drain metal are deposited on top of the GaN buffer layers on both sides of the mesa, respectively.

[0030] S5. Annealing in the drain metal and source metal regions to form an ohmic contact;

[0031] S6. Deposit the first passivation layer SiO2 on the entire surface of the device;

[0032] S7. In the SiO2 passivation layer on the drain side, several vertical micro-deep trenches are formed by dry etching, which are rectangular teeth, as filling skeletons for heat dissipation fins.

[0033] S8. On the side of the drain metal away from the gate, dry etching is used to remove part of the dielectric, creating a sidewall heat dissipation space that reaches the substrate area.

[0034] S9. Deposit a second passivation layer AlN with high thermal conductivity, fill the micro-deep trench in SiO2 to form embedded heat dissipation fins, and simultaneously fill the heat dissipation space of the sidewall to form AlN sidewalls.

[0035] S10. Deposit gate metal in the gate region;

[0036] S11, the passivation layer of the source and drain regions is opened by dry etching, exposing the source and drain metals on the surface.

[0037] According to a preferred embodiment of the present invention, the growth method of the GaN buffer layer, GaN channel layer, AlGaN barrier layer and P-GaN cap layer in step S1 is a high-quality film formation method such as metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). More preferably, the growth method is metal-organic chemical vapor deposition (MOCVD).

[0038] According to a preferred embodiment of the present invention, the etching method in steps S2, S3, S7, S8, and S11 is inductively coupled plasma etching (ICP) or reactive ion etching (RIE), and more preferably, the etching method is inductively coupled plasma etching (ICP).

[0039] According to a preferred embodiment of the present invention, the method for depositing the first passivation layer SiO2 in step S6 is plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD), and more preferably, the deposition method is low-pressure chemical vapor deposition (LPCVD).

[0040] According to a preferred embodiment of the present invention, the method for depositing the second passivation layer AlN in step S9 is metal-organic chemical vapor deposition (MOCVD) or atomic layer deposition (ALD), and more preferably, the deposition method is atomic layer deposition (ALD).

[0041] According to a preferred embodiment of the present invention, the annealing treatment of the source metal and drain metal in step S5 is laser selective annealing.

[0042] Where this invention does not cover all aspects, existing practices in the field can be employed.

[0043] The beneficial effects of this invention are as follows:

[0044] 1. Significantly Enhanced Surface Heat Dissipation Capacity: By embedding high thermal conductivity AlN heat dissipation fins in the SiO2 passivation layer on the drain side, the thermal conductivity of AlN, which is much higher than that of SiO2, is greatly increased, significantly improving the heat dissipation contact area and efficiency in the near-channel region. This embedded structure allows the Joule heat generated in the channel to be rapidly dissipated through the surface composite passivation layer, effectively mitigating heat accumulation near the channel.

[0045] 2. Constructing a Multi-Dimensional, High-Efficiency Heat Dissipation Pathway: This invention simultaneously introduces AlN thermally conductive sidewalls that extend directly to the substrate, working in conjunction with the surface fin structure to construct a multi-dimensional heat dissipation network on the surface and laterally, rather than being limited to traditional vertical heat dissipation. Simulation results show that, compared to conventional devices, the lattice temperature distribution of the composite structure device is significantly smoother, the area of ​​high-temperature "hot spots" is significantly reduced, achieving an effective temperature reduction of approximately 10K (peak temperature reduced from 388K to 378K), significantly improving thermal management efficiency.

[0046] 3. Enhanced Device Power Density: By leveraging the synergistic optimization of the asymmetric composite passivation layer and thermally conductive sidewalls, the device exhibits stronger power handling capability under the same thermal environment. According to simulation data comparison, under the same junction temperature constraint (e.g., 360K), the power density of conventional devices is only about 1.0 W / mm², while the composite structure device of this invention can achieve approximately 1.2 W / mm². This means that under the same temperature rise conditions, the device can withstand higher power.

[0047] 4. Suppressing parameter stability degradation under thermal excitation: By effectively reducing the channel peak temperature, this scheme significantly mitigates the charge trapping and release process of interface traps under thermal excitation. This improvement in thermal stability helps suppress the threshold voltage V. th The drift and the mitigation of dynamic on-resistance R on The degradation of the device ensures the stability of its electrical performance in high-frequency, high-power switching applications.

[0048] 5. Increased Device Reliability: High-quality electrothermal coupling design not only mitigates high-temperature-induced hot carrier injection (HCI) damage but also reduces the accumulation of thermomechanical stress between the passivation layer and the substrate. Multi-dimensional heat dissipation pathways and physical cooling work together to slow down the device aging process, thereby significantly improving device lifespan and reliability. Attached Figure Description

[0049] Figure 1 This is a structural diagram of an asymmetric finned heat-conducting device;

[0050] Figure 2 This is a diagram of a conventional device structure;

[0051] Figure 3 This is a lattice temperature distribution diagram for a conventional device;

[0052] Figure 4 This is a lattice temperature distribution diagram for an asymmetric finned thermal conductive device.

[0053] Figure 5 A temperature-distance comparison chart of asymmetric finned thermal conductive devices;

[0054] Figure 6 A comparison of power density and peak temperature for asymmetric finned thermal conductive devices;

[0055] in:

[0056] 1. Substrate; 2. GaN buffer layer; 3. GaN channel layer; 4. AlGaN barrier layer; 5. P-GaN cap layer; 6. SiO2 passivation layer; 7. Source metal; 8. Drain metal; 9. AlN sidewall; 10. AlN passivation layer; 11. Gate metal. Detailed Implementation

[0057] The present invention will be further described below with reference to the embodiments and accompanying drawings, but is not limited thereto.

[0058] Example 1

[0059] An asymmetric finned thermally enhanced GaN HEMT device, such as Figure 1 As shown, from bottom to top, it includes a substrate, a GaN buffer layer, a GaN channel layer, and an AlGaN barrier layer. A source metal is provided above the GaN buffer layer on one side of the GaN channel layer and the AlGaN barrier layer, and a drain metal is provided above the GaN buffer layer on the other side of the GaN channel layer and the AlGaN barrier layer. An AlN sidewall is provided above the substrate outside the drain metal.

[0060] A P-GaN cap layer is disposed above the AlGaN barrier layer, and a gate metal is disposed above the P-GaN cap layer.

[0061] A single passivation layer is provided between the P-GaN cap layer and the source metal, and above the AlGaN barrier layer; a composite passivation layer is provided between the P-GaN cap layer and the AlN sidewall.

[0062] The single passivation layer is a SiO2 passivation layer, and the composite passivation layer includes a lower layer and an upper layer. The lower layer is SiO2 and the upper layer is AlN. Both the lower and upper layers are fin-shaped and are interlocked by a tooth-shaped interlocking mechanism.

[0063] The highest point of the lower layer is no higher than the P-GaN cap layer and the drain metal, the AlN sidewall is higher than the drain metal, and the upper layer covers the drain metal and is flush with the AlN sidewall; the height of the single passivation layer on both sides of the P-GaN cap layer is the same as the height of the lower layer.

[0064] The SiO2 passivation layer has a thickness of 260 nm, and the AlN passivation layer has a thickness of 600 nm. The upper and lower toothed fins have a depth of 190 nm, a tooth width of 1 μm, a spacing of 1 μm between two adjacent toothed fins, and 5 toothed fins in the lower layer.

[0065] The substrate material is silicon. The GaN buffer layer has a thickness of 5.2 μm, the GaN channel layer has a thickness of 200 nm, the AlGaN barrier layer has a thickness of 18 nm, the Al molar ratio is 20%, the P-GaN cap layer has a thickness of 100 nm, and the doping concentration of the P-GaN cap layer is 3 × 10⁻⁶. 17 cm -3 The doping source is magnesium or boron, and the AlN sidewall width is 1.5 μm and the depth is 5.2 μm. The device has a gate-source pitch of 4 μm, a gate length of 4 μm, a gate-drain pitch of 12 μm, and a gate width of 100 μm. The gate-source pitch is the distance from the left side of the P-GaN cap layer to the source metal electrode, the gate length is the length from the left end to the right end of the P-GaN cap layer, the gate-drain pitch is the distance from the right side of the P-GaN cap layer to the drain metal electrode, and the gate width is the distance from the gate metal to the source metal electrode. Figure 1 The width of the extension within the plane shown.

[0066] The source and drain metals are made of Ti / Al / Ni / Au metal stacks, and the gate metal is made of Ni / Au metal stacks.

[0067] The effect of the asymmetric fin composite passivation layer and thermally conductive sidewall structure on improving the heat dissipation performance of the device was verified in Sentaurus TCAD simulation. Specifically, this invention introduces a fin-shaped high thermal conductivity composite passivation layer on the drain side of the device and introduces a thermally conductive sidewall on the outer side, breaking the high thermal resistance limitation of the surface medium and constructing a multi-dimensional heat dissipation path. It was found that this structure can significantly reduce the peak temperature of the device.

[0068] (1) Simulation model construction: A two-dimensional structural model of GaN HEMT was constructed in Sentaurus TCAD software.

[0069] (2) Simulation parameter settings: Set appropriate electrothermal boundary conditions and initial conditions, including voltage and current. Enable the thermodynamic transport model in the simulation to achieve self-consistent solution of the lattice heat flow equation and the carrier transport equation. For the output curve, first apply a gate voltage of 5V, and then continuously apply the drain voltage from 0V to 20V.

[0070] (3) Simulation process: Perform electrothermal coupling simulation to observe the change in heat dissipation performance of asymmetric finned thermally conductive P-GaN HEMT compared with conventional P-GaNHEMT.

[0071] (4) Results Analysis: Comparing the lattice temperature distributions in Figures 3 and 4, it can be seen that conventional devices have severe hot spots at the gate-drain edge, while the novel asymmetric finned device optimizes the near-channel thermal resistance through AlN / SiO2 composite passivation and sidewall heat dissipation, significantly smoothing the temperature and reducing the area of ​​the high-temperature region. As shown in Figure 5, the overall temperature of the asymmetric finned thermally conductive device is significantly lower than that of the conventional device, with the peak temperature decreasing from 388 K to 378 K, an effective cooling of 10 K. Figure 6 further confirms that, under the junction temperature limit of 360 K, the power density of this structure increases from 1.0 W / mm² to 1.2 W / mm². This indicates that, with the synergistic optimization of the asymmetric composite passivation layer and the thermally conductive sidewall, the novel enhanced device can not only achieve significant physical cooling but also withstand higher power density under the same thermal environment, significantly improving the heat dissipation performance and reliability of the device.

[0072] Example 2

[0073] An asymmetric finned thermally enhanced GaN HEMT device is disclosed, with the structure described in Example 1, except that the SiO2 passivation layer is 10 nm thick, the upper AlN passivation layer is 5 nm thick, and the tooth profile depth is 2 nm. The substrate material is silicon carbide. The GaN buffer layer is 0.1 μm thick, the GaN channel layer is 5 nm thick, the AlGaN barrier layer is 5 nm thick, the Al molar ratio is 5%, the P-GaN cap layer is 1 nm thick, and the doping concentration of the P-GaN cap layer is 1 × 10⁻⁶. 17 cm -3 The AlN sidewalls are 0.1 μm wide and 0.1 μm deep, and the source and drain metals are made of Ti / Al / Ti / Au metal stacks.

[0074] Example 3

[0075] An asymmetric finned thermally enhanced GaN HEMT device is disclosed, with the structure described in Example 1, except that the SiO2 passivation layer is 2000 nm thick, the upper AlN passivation layer is 2000 nm thick, and the tooth profile depth is 500 nm. The substrate material is sapphire. The GaN buffer layer is 50 μm thick, the GaN channel layer is 500 nm thick, the AlGaN barrier layer is 50 nm thick, the Al molar ratio is 35%, the P-GaN cap layer is 500 nm thick, and the doping concentration of the P-GaN cap layer is 1 × 10⁻⁶. 20 cm -3 The AlN sidewalls are 10 μm wide and 10 μm deep, and the source and drain metals are made of Ti / Al / Mo / Au metal stacks.

[0076] Example 4

[0077] A method for fabricating an asymmetric finned thermally enhanced GaN HEMT device includes the following steps:

[0078] S1. A GaN buffer layer, a GaN channel layer, an AlGaN barrier layer, and a P-GaN cap layer are sequentially grown on a Si substrate. The GaN buffer layer, GaN channel layer, AlGaN barrier layer, and P-GaN cap layer are grown using metal-organic chemical vapor deposition (MOCVD).

[0079] S2. Dry etching removes the P-GaN cap layer except for the area below the gate.

[0080] S3. The GaN channel layer and AlGaN barrier layer outside the device are removed by dry etching, and the etching extends to the GaN buffer layer to form a mesa.

[0081] S4. Source metal and drain metal are deposited on top of the GaN buffer layers on both sides of the mesa.

[0082] S5. Annealing is performed on the drain and source metal regions to form ohmic contacts. The annealing process for the source and drain metals is selective laser annealing.

[0083] S6. Deposit the first passivation layer SiO2 on the entire surface of the device. The method for depositing the first passivation layer SiO2 is low-pressure chemical vapor deposition (LPCVD).

[0084] S7. In the SiO2 passivation layer on the drain side, several vertical micro-deep trenches are formed by dry etching, which are rectangular teeth, as filling skeletons for heat dissipation fins.

[0085] S8. On the side of the drain metal away from the gate, a portion of the dielectric is removed by dry etching to create a sidewall heat dissipation space that extends directly to the substrate region.

[0086] S9. A second passivation layer of AlN with high thermal conductivity is deposited, which fills the micro-deep trenches in SiO2 to form embedded heat dissipation fins, and simultaneously fills the sidewall heat dissipation space to form AlN sidewalls. The method for depositing the second passivation layer AlN is atomic layer deposition (ALD).

[0087] S10, Deposit gate metal in the gate region.

[0088] S11, the passivation layer of the source and drain regions is opened by dry etching, exposing the source and drain metals on the surface.

[0089] The etching method for steps S2, S3, S7, S8, and S11 is inductively coupled plasma etching (ICP).

Claims

1. An asymmetric finned thermally enhanced GaN HEMT device, characterized in that, From bottom to top, the structure includes a substrate, a GaN buffer layer, a GaN channel layer, and an AlGaN barrier layer. A source metal is disposed above the GaN buffer layer on one side of the GaN channel layer and the AlGaN barrier layer, and a drain metal is disposed above the GaN buffer layer on the other side of the GaN channel layer and the AlGaN barrier layer. An AlN sidewall is disposed above the substrate outside the drain metal. A P-GaN cap layer is disposed above the AlGaN barrier layer, and a gate metal is disposed above the P-GaN cap layer. A single passivation layer is provided between the P-GaN cap layer and the source metal, and above the AlGaN barrier layer. A composite passivation layer is provided between the P-GaN cap layer and the AlN sidewall. The single passivation layer is a SiO2 passivation layer, and the composite passivation layer includes a lower layer and an upper layer. The lower layer is a SiO2 passivation layer, and the upper layer is an AlN passivation layer. Both the lower and upper layers are fin-shaped and are interlocked by a tooth-shaped interlocking mechanism.

2. The asymmetric finned thermally enhanced GaN HEMT device according to claim 1, characterized in that, The highest point of the lower layer is no higher than the P-GaN cap layer and the drain metal, the AlN sidewall is higher than the drain metal, and the upper layer covers the drain metal and is flush with the AlN sidewall; the height of the single passivation layer on both sides of the P-GaN cap layer is the same as the height of the lower layer.

3. The asymmetric finned thermally enhanced GaN HEMT device according to claim 1, characterized in that, The thickness of the SiO2 passivation layer is 10-2000 nm, and the thickness of the upper AlN passivation layer is 5-2000 nm.

4. The asymmetric finned thermally enhanced GaN HEMT device according to claim 3, characterized in that, The SiO2 passivation layer has a thickness of 260 nm, and the AlN passivation layer has a thickness of 600 nm.

5. The asymmetric finned thermally enhanced GaN HEMT device according to claim 1, characterized in that, The depth of the upper and lower toothed fins is 2-500nm, the width of the toothed fins is 1μm, the distance between two adjacent toothed fins is 1μm, and the number of toothed fins in the lower layer is 5.

6. The asymmetric finned thermally enhanced GaN HEMT device according to claim 5, characterized in that, The depth of the upper and lower tooth profiles is 190nm.

7. The asymmetric finned thermally enhanced GaN HEMT device according to claim 1, characterized in that, The device includes any of the following solutions: 1) The substrate material is silicon carbide, silicon, or sapphire; 2) The thickness of the GaN buffer layer is 0.1-50 μm; 3) The thickness of the GaN channel layer is 5-500 nm; 4) The thickness of the AlGaN barrier layer is 5-50 nm, and the molar ratio of Al is 5-35%; 5) The thickness of the P-GaN cap layer is 1-500 nm; 6) The doping concentration of the P-GaN cap layer is 1×10⁻⁶. 17 -1×10 20 cm -3 The doping source is magnesium or boron; 7) The AlN sidewall has a width of 0.1-10 μm and a depth of 0.1-10 μm; 8) The device has a gate-source pitch of 4μm, a gate length of 4μm, a gate-drain pitch of 12μm, and a gate width of 100μm; 9) The source metal and drain metal are made of Ti / Al / Ni / Au, Ti / Al / Ti / Au or Ti / Al / Mo / Au metal stacks, and the gate metal is made of Ni / Au metal stacks.

8. The asymmetric finned thermally enhanced GaN HEMT device according to claim 7, characterized in that, 1) The substrate material is silicon; 2) The thickness of the GaN buffer layer is 5.2 μm; 3) The thickness of the GaN channel layer is 200 nm; 4) The AlGaN barrier layer has a thickness of 18 nm and an Al molar ratio of 20%. 5) The thickness of the P-GaN cap layer is 100 nm; 6) The doping concentration of the P-GaN cap layer is 3×10⁻⁶. 17 cm -3 ; 7) The AlN sidewall has a width of 1.5 μm and a depth of 5.2 μm.

9. A method for manufacturing an asymmetric finned thermally enhanced GaN HEMT device, characterized in that, The steps include the following: S1. A GaN buffer layer, a GaN channel layer, an AlGaN barrier layer, and a P-GaN cap layer are sequentially grown on a Si substrate. S2. Dry etching removes the P-GaN cap layer except for the area below the gate; S3. Remove the GaN channel layer and AlGaN barrier layer outside the device by dry etching, and etch down to the GaN buffer layer to form a mesa; S4. Source metal and drain metal are deposited on top of the GaN buffer layers on both sides of the mesa, respectively. S5. Annealing in the drain metal and source metal regions to form an ohmic contact; S6. Deposit the first passivation layer SiO2 on the entire surface of the device; S7. In the SiO2 passivation layer on the drain side, several vertical grooves are formed by dry etching, which are rectangular teeth, as filling skeletons for heat dissipation fins. S8. On the side of the drain metal away from the gate, dry etching is used to remove part of the dielectric, creating a sidewall heat dissipation space that reaches the substrate area. S9. Deposit a second passivation layer AlN with high thermal conductivity, fill the micro-deep trench in SiO2 to form embedded heat dissipation fins, and simultaneously fill the heat dissipation space of the sidewall to form AlN sidewalls. S10. Deposit gate metal in the gate region; S11, the passivation layer of the source and drain regions is opened by dry etching.

10. The method for manufacturing the asymmetric finned thermally enhanced GaN HEMT device according to claim 9, characterized in that, The GaN buffer layer, GaN channel layer, AlGaN barrier layer, and P-GaN cap layer in step S1 are grown by metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). The etching methods for steps S2, S3, S7, S8, and S11 are inductively coupled plasma etching (ICP) or reactive ion etching (RIE). The method for depositing the first passivation layer SiO2 in step S6 is plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD). The method for depositing the second passivation layer AlN in step S9 is metal-organic chemical vapor deposition (MOCVD) or atomic layer deposition (ALD). The annealing process for the source metal and drain metal in step S5 is laser selective annealing.

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