Semiconductor device and forming method thereof

Abstract

The method includes forming a conductive feature proximate the source / drain region; exposing a first surface of the conductive feature and a first surface of the source / drain region; forming a metal oxide layer on the conductive feature and forming a silicon oxide layer on the source / drain region; removing the silicon oxide layer, wherein the second surface of the source / drain region is exposed by removing the silicon oxide layer; forming a silicide region on the second surface of the source / drain region; removing the metal oxide layer, wherein removing the metal oxide layer exposes the second surface of the conductive feature; and depositing a first conductive material on the silicide region and on the second surface of the conductive feature. The embodiment of the invention also relates to a semiconductor device and a forming method thereof.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor devices and methods of forming the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor layer on a semiconductor substrate, and then using photolithography to pattern the individual material layers to form circuit components and elements on them.

[0003] The semiconductor industry increases the integration density of individual electronic components (such as transistors, diodes, resistors, capacitors, etc.) by continuously reducing the size of the smallest component, allowing more components to be integrated into a given area. However, as the size of the smallest component decreases, additional problems arise and need to be addressed. Summary of the Invention

[0004] Some embodiments of this application provide a method for forming a semiconductor device, comprising: forming a source / drain region; forming a contact etch stop layer over the source / drain region; forming an interlayer dielectric layer over the contact etch stop layer; forming a first contact plug in the interlayer dielectric layer and the contact etch stop layer; performing a first etching process to form an opening in the interlayer dielectric layer and the contact etch stop layer, wherein the opening exposes the surface of the source / drain region and the surface of the first contact plug, wherein a metal oxide layer on the first contact plug is exposed through the opening; performing a silicide formation process to form a silicide region on the surface of the source / drain region; performing a second etching process to remove the metal oxide layer; and forming a second contact plug in the opening, the second contact plug being electrically connected to the silicide region and the first contact plug, the conductivity of the silicide region being between the conductivity of the source / drain region and the conductivity of the second contact plug.

[0005] Other embodiments of this application provide a method for forming a semiconductor device, comprising: forming a conductive component near a source / drain region; exposing a first surface of the conductive component and the first surface of the source / drain region; forming a metal oxide layer on the conductive component and a silicon oxide layer on the source / drain region; removing the silicon oxide layer, wherein the removal of the silicon oxide layer exposes a second surface of the source / drain region; forming a silicide region on the second surface of the source / drain region; removing the metal oxide layer, wherein the removal of the metal oxide layer exposes the second surface of the conductive component; and depositing a first conductive material on the silicide region and the second surface of the conductive component.

[0006] Further embodiments of this application provide a semiconductor device including: a lower transistor including a lower source / drain region; an upper transistor including an upper source / drain region; a vertical interconnect extending near the lower source / drain region and near the upper source / drain region; a silicide region located on the upper source / drain region; a first metal overlay material located on the silicide region; a second metal overlay material located on the vertical interconnect; and a metal filler layer covering the first metal overlay material and the second metal overlay material. Attached Figure Description

[0007] The following detailed description, taken in conjunction with the accompanying drawings, will best provide a comprehensive understanding of all aspects of this disclosure. It should be noted that, in accordance with industry standard practice, the components are not drawn to scale. In fact, the dimensions of the components may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1A , Figure 1B , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 and Figure 9 This is a view of an intermediate stage in the formation of a contact plug of a stacked transistor structure according to some embodiments.

[0009] Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 and Figure 16 This is a view of an intermediate stage in the formation of a contact plug of a stacked transistor structure according to some embodiments.

[0010] Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 and Figure 23 This is a view of an intermediate stage in the formation of a contact plug of a stacked transistor structure according to some embodiments.

[0011] Figure 24 , Figure 25 , Figure 26 and Figure 27 This is a view of an intermediate stage in the formation of a contact plug of a stacked transistor structure according to some embodiments.

[0012] Figure 28 , Figure 29 , Figure 30 , Figure 31 and Figure 32 This is a view of an intermediate stage in the formation of a contact plug of a stacked transistor structure according to some embodiments.

[0013] Figure 33 , Figure 34 , Figure 35 , Figure 36 and Figure 37 This is a view of an intermediate stage in the formation of a contact plug of a stacked transistor structure according to some embodiments.

[0014] Figure 38 , Figure 39 and Figure 40 This is a view of an intermediate stage in the formation of a contact plug of a stacked transistor structure according to some embodiments. Detailed Implementation

[0015] The following disclosure provides numerous different embodiments or examples for implementing various components of the invention. To simplify this disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on top of a second component may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components may not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various examples. Repetition is for the purpose of brevity and clarity and does not in itself establish a relationship between the various embodiments and / or configurations discussed.

[0016] Furthermore, spatial relative terms (such as "below," "under," "lower," "above," "upper," etc.) may be used herein to describe the relationship between one element or component and another shown in the figures. Spatial relative terms are intended to cover different orientations of the device during use or operation, as well as orientations other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0017] Various representative embodiments are described with respect to contact plugs within a stacked transistor structure. Complementary field-effect transistors (CFETs), silicide regions, contact plugs, and methods for forming them are provided. According to some embodiments of this disclosure, the interface between two contact plugs is formed with minimal or no silicide or nitride residues. Reducing or eliminating residues between contact plugs can lower resistance and improve electrical connection. Furthermore, the interface between contact plugs is formed to be substantially free of metal oxides, which also reduces resistance and improves electrical connection.

[0018] It should be understood that although the discussion herein is set in the context of the formation of stacked transistors, including gate-all-around (GAA) transistors (e.g., nanostructured field-effect transistors), the concepts of this disclosure can also be applied to the formation of other types of transistors (e.g., planar transistors, FinFETs, etc.). Throughout the description, the terms "FET" and "transistor" are used interchangeably.

[0019] The embodiments discussed herein are intended to provide examples for making or using the subject matter of this disclosure, and modifications that may be made within the intended scope of the different embodiments will be readily understood by those skilled in the art. In the various views and exemplary embodiments, the same reference numerals are used to designate the same elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0020] According to some embodiments, Figure 1A-Figure 1B to Figure 9 A cross-sectional view is shown at an intermediate stage in the formation of a stacked transistor structure. Specifically, according to some embodiments, Figures 1B to 9 The contact plug 140 of the stacked transistor structure is shown (see Figure 9 This is an intermediate stage in the formation of the stacked transistor structure. In some cases, the stacked transistor structure can be a complementary field-effect transistor (CFET) structure. According to some embodiments, Figure 1A-Figure 1B An exemplary stacked transistor 10 is illustrated. The stacked transistor 10 includes a plurality of vertically stacked field-effect transistors. For example, the stacked transistor may include a lower nanostructure field-effect transistor 10L of a first device type (e.g., n-type / p-type) and an upper nanostructure field-effect transistor 10U of a second device type (e.g., p-type / n-type). When the stacked transistor is a CFET, the second device type of the upper nanostructure field-effect transistor 10U is opposite to the first device type of the lower nanostructure field-effect transistor 10L. The nanostructure field-effect transistors 10U and 10L include a semiconductor nanostructure 26 (including a lower semiconductor nanostructure 26L and an upper semiconductor nanostructure 26U), wherein the semiconductor nanostructure 26 serves as the channel region of the nanostructure field-effect transistor. The lower semiconductor nanostructure 26L is used for the lower nanostructure field-effect transistor 10L, and the upper semiconductor nanostructure 26U is used for the upper nanostructure field-effect transistor 10U. In other embodiments, the stacked transistor may also be applied to other types of transistors (e.g., fin field-effect transistors, etc.).

[0021] According to some embodiments, stacked transistors 10 are formed on a wafer, which may include a substrate 20. The substrate 20 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., and may be doped (e.g., doped with p-type or n-type dopants) or undoped. The SOI substrate may include a semiconductor material layer formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate (e.g., a silicon or glass substrate). Other substrates may also be used, such as multilayer substrates or gradient substrates. According to some embodiments, the semiconductor material of the substrate 20 may include silicon, germanium, carbon-doped silicon, III-V compound semiconductors, etc., or combinations thereof.

[0022] A gate dielectric layer 78 surrounds the corresponding semiconductor nanostructure 26. Gate electrodes 80 (including a lower gate electrode 80L and an upper gate electrode 80U) are located above the gate dielectric layer 78. The gate dielectric layer 78 and the gate electrodes 80 form a "gate stack" or "gate structure" between the semiconductor nanostructure 26. The upper gate stack includes the gate dielectric layer 78 and the upper gate electrode 80U. The lower gate stack includes the gate dielectric layer 78 and the lower gate electrode 80L.

[0023] A dielectric isolation layer 56 is formed to isolate the gate stack of the upper field-effect transistor 10U from the gate stack of the lower field-effect transistor 10L. According to some embodiments, the adjacent semiconductor layers above and below the dielectric isolation layer 56 may be pseudo-semiconductor layers (e.g., pseudo-nanostructures).

[0024] Source / drain regions 62 (including lower source / drain region 62L and upper source / drain region 62U) are arranged on opposite sides of the gate stack (e.g., gate dielectric 78 and corresponding gate electrode 80). Source / drain regions 62 may refer to either the source or the drain, individually or collectively, depending on the context. Isolation members (not shown) may be formed to separate the desired source / drain regions 62 and / or the desired gate electrode 80.

[0025] Internal spacers 54, which are dielectric spacers, are formed on opposite sides of portions of the gate stack, with portions of internal spacers 54 located between semiconductor layers 26. Internal spacers 54 electrically insulate the source / drain regions 62L and 62U from their corresponding portions of the gate stack to prevent and reduce leakage. Gate spacers 44 are formed over the multilayer stack and on the sidewalls of the gate stack 90. ​​Gate spacers 44 can be formed by conformally forming one or more dielectric layers and subsequently anisotropically etching the dielectric layers. Suitable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc., which can be formed by deposition processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.

[0026] Source / drain regions 62L and 62U are laterally formed between a multilayer stack including a channel region (e.g., semiconductor nanostructure 26) and a gate stack (e.g., gate dielectric 78 and gate electrode 80). A lower source / drain region 62L is formed above and in contact with a substrate (which includes substrate 20). The lower source / drain region 62L further contacts the lower semiconductor nanostructure 26L but not the upper semiconductor nanostructure 26U.

[0027] The lower source / drain region 62L is epitaxially grown and has a conductivity type suitable for the type of lower nanostructure field-effect transistor device (p-type or n-type). When the lower source / drain region 62L is an n-type source / drain region, the corresponding material may include silicon or carbon-doped silicon doped with n-type dopants such as phosphorus or arsenic. When the lower source / drain region 62L is a p-type source / drain region, the corresponding material may include silicon or silicon-germanium doped with p-type dopants such as boron or indium. The lower source / drain region 62L may be in-situ doped and may or may not be implanted with the corresponding p-type or n-type dopants.

[0028] A first contact etch stop layer (CESL) 66 and a first interlayer dielectric layer (ILD) 68 are formed above the lower source / drain region 62L. Suitable dielectric materials for the first interlayer dielectric layer 68 may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), silicon oxide, etc. The first contact etch stop layer 66 may be formed from a dielectric material that exhibits high selectivity for etching the first interlayer dielectric layer 68. For example, the first contact etch stop layer 66 may include silicon nitride, silicon oxide, silicon oxynitride, etc., and can be formed by any suitable deposition process (e.g., chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.).

[0029] The upper source / drain region 62U is formed to overlap with the first contact etch stop layer 66 and the first interlayer dielectric layer 68, and also overlaps with the lower source / drain region 62L. The material of the upper source / drain region 62U can be selected from the same group of candidate materials used to form the lower source / drain region 62L, depending on the desired conductivity type of the upper source / drain region 62U. The conductivity type of the upper source / drain region 62U can be opposite to that of the lower source / drain region 62L. In other words, the doping of the upper source / drain region 62U can be opposite to that of the lower source / drain region 62L. The upper source / drain region 62U can be in-situ doped and / or implanted with n-type or p-type dopants.

[0030] The second contact etch stop layer 70 and the second interlayer dielectric layer 72 are formed above the upper source / drain region 62U. The materials may be similar to, and may be the same as or different from, the materials and formation methods of the first contact etch stop layer 66 and the first interlayer dielectric layer 68, which will not be discussed in detail herein.

[0031] Figure 1B It shows Figure 1A The cross-sectional view of the structure shown is shown. The cross-section shown can be similar to... Figure 1A The cross section B-B' is indicated in the diagram. A dielectric isolation region 32 (sometimes also called a shallow trench isolation (STI) region 32) is formed over the substrate 20. Semiconductor strip 20' (see also...) Figure 1A The semiconductor strip 20' is formed between the shallow trench isolation regions 32. In some cases, the semiconductor strip 20' can be regarded as a semiconductor fin. The fin spacer 45 can be formed on the sidewall of the top portion of the semiconductor strip 20'. Figure 1B The lower source / drain region 62L, the first contact etch stop layer 66, the first interlayer dielectric layer 68, the upper source / drain region 62U, the second contact etch stop layer 70, and the second interlayer dielectric layer 72 are also shown.

[0032] Figure 1B The formation of contact plug 116 is further illustrated. In some cases, contact plug 116 may be considered as a vertical local interconnect (VLI), via, interconnect structure, etc. According to some embodiments, the formation of contact plug 116 includes etching a second interlayer dielectric layer 72, a second contact etch stop layer 70, a first interlayer dielectric layer 68, and a first contact etch stop layer 66 to form a trench. The trench may extend to an intermediate level between the top and bottom surfaces of the isolation region 32. A dielectric liner 114 is formed in the trench. According to some embodiments, the formation of dielectric liner 114 includes conformal deposition processes (e.g., chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), etc.). According to some embodiments, the material of dielectric liner 114 may include silicon nitride, metal oxides of metals, or metal nitrides (metals such as hafnium, titanium, aluminum, tungsten, niobium, rhenium, etc., or combinations thereof). For example, according to some embodiments, dielectric liner 114 comprises titanium nitride or tantalum nitride, but other materials are also possible.

[0033] The conductive material of the contact plug 116 is then deposited on the dielectric substrate 114. According to some embodiments, the conductive material of the contact plug 116 includes metals (e.g., tungsten, cobalt, copper, nickel, molybdenum, ruthenium, iridium, etc.), alloys thereof, or combinations thereof. According to some embodiments, the contact plug 116 has a single-layer structure, and the entire contact plug 116 is formed of a homogeneous material.

[0034] After depositing the material used to form the contact plug 116, a planarization process (e.g., chemical mechanical polishing (CMP) or mechanical grinding) is performed to remove excess material, wherein the remaining material forms the contact plug 116. The contact plug 116 is coplanar with the top surface of the dielectric liner 114, and in some embodiments, may further be coplanar with the top surface of the second interlayer dielectric layer 72. In this manner, the contact plug 116 is surrounded by the dielectric liner 114.

[0035] like Figure 1B As shown, an etch stop layer (ESL) 118 is formed. The etch stop layer 118 may include aluminum nitride, aluminum oxide, silicon oxynitride, or a multilayer structure thereof. A dielectric layer 120 is deposited above the etch stop layer 118. The dielectric layer 120 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, etc. According to some embodiments, a patterned etch mask 121 is formed above the dielectric layer 120. The patterned etch mask 121 may include photoresist, a hard mask, etc.

[0036] According to some embodiments, in Figure 2 In the process, a patterned etch stop layer 118 and a dielectric layer 120 are used to form an opening 122. The opening 122 exposes a dielectric substrate 114 and a contact plug 116. The opening 122 also extends into a second interlayer dielectric layer 72 and through a second contact etch stop layer 70 to expose an upper source / drain region 62U. The opening 122 can be formed using one or more etching processes, which may employ a patterned etch mask 121 as the etching mask. The opening exposes the top surface of the upper source / drain region 62U. After exposing the upper source / drain region 62U and the contact plug 116, the patterned etch mask 121 can be removed by a suitable process (e.g., ashing or etching).

[0037] According to some embodiments, in Figure 3 In this process, a dielectric liner 124 is formed on some sidewall surfaces of the opening 122. According to some embodiments, the dielectric liner 124 is deposited as a conformal layer using a suitable conformal deposition process. For example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc., can be used to deposit the dielectric liner 124. An anisotropic etching process is then performed to remove the conformal layer portion on the horizontal surface, leaving the remaining vertical portion as the dielectric liner 124. During the anisotropic etching process, the exposed portions of the dielectric liner 114 can also be recessed. For example, a portion of the dielectric liner 114 can be removed to expose the sidewalls of the contact plug 116, such as... Figure 3 As shown. The material of dielectric liner 124 may be selected from the same group of candidate materials as those forming dielectric liner 114, and may be the same as or different from the material of dielectric liner 114. For example, dielectric liner 124 may be formed of and / or include silicon nitride. Other materials or forming techniques are also possible.

[0038] See Figure 4 In some cases, oxide layers may be formed on the upper source / drain region 62U and the contact plug 116. The oxide layers may be formed due to vacuum disruption during structure transfer between process steps. For example, a silicon oxide layer 126 may be formed on the upper source / drain region 62U due to oxidation of the exposed surface, and a metal oxide layer 128 may be formed on the contact plug 116 due to oxidation of the exposed surface. Therefore, the metal oxide layer 128 contains an oxide of the metal in the contact plug 116. For example, when the contact plug 116 contains tungsten, the metal oxide layer 128 contains tungsten oxide (e.g., WOx). The shape and size of the metal oxide layer 128 may differ from... Figure 4 As shown.

[0039] According to some embodiments, in Figure 5 In this process, a first pre-cleaning process is performed to remove the silicon oxide layer 126. The first pre-cleaning process may include, for example, a process gas mixture of HF and NH3, but other processes are also possible. After performing the first pre-cleaning process, the silicon oxide layer 126 is removed, and the underlying upper source / drain region 62U is exposed. According to some embodiments, such as... Figure 5 As shown, the first pre-cleaning process does not remove the metal oxide layer 128.

[0040] According to some embodiments, in Figure 6 In this embodiment, a silicide region 130 is formed on the upper source / drain region 62U. According to some embodiments, the silicide region 130 can be formed by exposing the structure to a metal-containing precursor. The metal-containing precursor reacts with the surface of the upper source / drain region 62U to form the silicide region 130, and can be deposited on other surfaces to form a residue layer 132 (also referred to as residue 132), which will be described in detail below. The metal of the silicide region 130 may include titanium, vanadium, zinc, niobium, aluminum, or other suitable metals. According to some embodiments, a nitride layer (not shown separately) is formed over the silicide region 130 to reduce oxidation. The nitride layer may be deposited as a separate layer on the silicide region 130, or a nitriding process (e.g., nitriding treatment or nitrogen treatment process) may be performed on the silicide region 130 to form a nitride layer at or near the top surface of the silicide region 130. For example, for a silicide region 130 that is titanium silicide (e.g., TiSi). x In some embodiments, the nitride layer may include titanium nitride (e.g., TiN) and / or titanium silicide nitride (e.g., TiSiN). Other materials are also possible. In some cases, the conductivity of the silicide region 130 is higher than that of the upper source / drain region 62U.

[0041] In some cases, the formation of the silicide region 130 may also form a residue layer 132 within the opening 122. For example, the residue layer 132 may extend onto the surface of the silicide region 130, the dielectric liner 124, the metal oxide layer 128, and / or the contact plug 116. The residue layer 132 may comprise a material similar to that of the metal precursor, the silicide region 130, and / or the nitride layer. For example, in embodiments where the silicide region 130 is titanium silicide, the residue layer 132 may comprise titanium and / or titanium nitride. Other materials are also possible.

[0042] According to some embodiments, further in Figure 6 A metal filler 134 is deposited to fill the opening 122. The metal filler 134 is deposited on the residue layer 132 and thus over the silicide region 130 and the contact plug 116. According to some embodiments, the metal filler 134 and the contact plug 116 are the same metal. In other embodiments, the metal filler 134 and the contact plug 116 are different conductive materials. For example, the metal filler 134 may be a metal (e.g., tungsten, molybdenum, ruthenium, iridium, etc.). The metal filler 134 may be deposited using suitable techniques, which may be similar to those used to deposit the material of the contact plug 116. In some cases, the contact plug 116 and the metal filler 134 are spaced apart by the residue layer 132. In some cases, the metal filler 134 may be considered a "sacrificial metal" that is at least partially removed in subsequent process steps described below.

[0043] According to some embodiments, Figure 7 An etching process is performed to recess the metal filler 134. The etching process removes the upper portion of the metal filler 134 and may also remove the upper portion of the residual layer 132. The etching process can be considered as a "pull-back etching" or similar process and may include any suitable etching process. In some cases, the etching process may oxidize a portion of the metal filler 134, such that a metal oxide layer 136 remains on or near the top surface of the remaining metal filler 134 after the etching process. The metal oxide layer 136 may contain oxides of the metal in the metal filler 134. For example, when the metal filler 134 contains tungsten, the metal oxide layer 136 contains tungsten oxide. Therefore, for embodiments where the metal filler 134 and the contact plug 116 are the same metal, the metal oxide layer 136 and the metal oxide layer 128 may be similar metal oxides. The shape and size of the metal oxide layer 136 may differ from... Figure 4 As shown. For example, according to some embodiments, such as Figure 7As shown, the portion of the metal fill 134 beneath the metal oxide layer 136 is not oxidized. In other embodiments, all remaining metal fill 134 has been oxidized by an etching process (e.g., only the metal oxide layer 136 remains). After the etching process, the top surface of the remaining metal fill 134 and / or the metal oxide layer 136 may be higher than, lower than, or substantially equal to the top surface of the contact plug 116 and / or the metal oxide layer 128. Figure 7 As shown, the metal oxide layer 136 and the metal oxide layer 128 may be separated by the residue layer 132. The metal filler 134 is recessed to form an opening 123, which may partially overlap with the previously formed opening 122.

[0044] According to some embodiments, Figure 8 A second pre-cleaning process is performed to remove metal oxide layers 128 and 136. This second pre-cleaning process differs from the first pre-cleaning process. The second pre-cleaning process may also remove portions of the residual layer 132 adjacent to metal oxide layers 128 and / or 136. After the second pre-cleaning process, at least a portion of the metal oxide layer 128 is removed, and the contact plug 116 is exposed. According to some embodiments, such as... Figure 8 As shown, some metal filler 134 remains after the removal of metal oxide layer 136. In other embodiments, metal filler 134 is completely removed after the second pre-cleaning process. In some cases, some residual layer 132 may remain above silicide region 130. According to some embodiments, the second pre-cleaning process can remove metal oxide layers 128 and 136 regardless of whether metal oxide layers 128 and 136 are similar metal oxides.

[0045] According to some embodiments, Figure 9Metal filler is deposited into opening 123 to form contact plug 140. Contact plug 140 is electrically connected to upper source / drain region 62U via silicide region 130 and residual layer 132 (if present), and therefore contact plug 140 may also be referred to as upper source / drain contact plug. Metal filler physically contacts the exposed surface of contact plug 116, and therefore contact plug 140 is physically and electrically connected to contact plug 116. Metal filler can be a material similar to those of metal filler 134 and / or contact plug 116. For example, according to some embodiments, metal filler is a conductive material (e.g., tungsten, molybdenum, ruthenium, iridium, etc., or alloys thereof). According to some embodiments, metal filler may completely fill opening 123. After depositing the metal filler for forming contact plug 140, a planarization process (e.g., chemical mechanical polishing (CMP) or mechanical polishing) is performed to remove excess metal filler, the remaining portion of which forms contact plug 140. After planarization, the top surfaces of contact plug 140, dielectric liner 124, and dielectric layer 120 may be flush or coplanar. Contact plug 140 is at least partially surrounded by dielectric liner 124. In some cases, the conductivity of silicide region 130 is lower than that of contact plug 140 and / or contact plug 116. In some cases, the conductivity of silicide region 130 is between that of the upper source / drain region 62U and that of contact plug 140.

[0046] In some cases, the residual layer 132 may have a relatively high resistance (e.g., higher than that of contact plugs 116 and / or 140). Therefore, removing the residual layer 132 from contact plug 116 as described herein can reduce the resistance between contact plug 140 and contact plug 116, which can improve device performance. For example, in some cases, it may be difficult to remove portions of the residue without damaging or removing the silicide region. The techniques described herein allow for partial removal of the residue without the risk of damaging the silicide region. Furthermore, removing the metal oxide layer 128 from contact plug 116 can also reduce resistance, improve the electrical connection between contact plug 116 and contact plug 140, and improve the electrical performance of the device. In this way, the electrical connection between conductive components (e.g., source / drain contact plugs and vertical local interconnects (VLI)) can be improved.

[0047] Additional processing can be performed on the structure. For example, additional conductive components (not shown separately), such as redistribution lines, vias, or contact plugs, can be formed on the front or back side of the structure. The back-side conductive components may include contact plugs electrically connected to the lower source / drain region 62L and / or contact plug 116. These back-side contact plugs can use similar methods as those used for... Figures 1A-9Those techniques described herein or similar to those described in other parts of this disclosure are used for forming. For example, a "front-side" contact plug 140 may be connected to the upper source / drain region 62U and contact plug 116, while a "back-side" contact plug may be connected to the lower source / drain region 62L and may also be connected to the same contact plug 116. In this case, the back-side contact plug may be formed using techniques similar to those described herein for forming contact plug 140 or contact plugs in other embodiments. Other conductive components or other additional process steps are also possible.

[0048] According to some embodiments, Figures 10 to 16 The contact plug 140 of the stacked transistor structure is shown (see Figure 16 The intermediate stage of formation. Contact plug 140 is similar to... Figure 9 The difference with respect to the contact plug is that a self-assembling material (SAM) is used during the formation of the contact plug 140 to provide an improved connection between the contact plug 140 and the contact plug 116. Figures 10-15 Some of the materials and techniques used are similar to those previously used. Figures 1A-9 Those mentioned above, and therefore some details may not be repeated. Figure 10 It shows something similar to the previous one. Figure 4 The structure shown can be used in a manner similar to Figures 1A-4 The materials and techniques described above are used to form this. For example, Figure 10 The diagram shows the structure after oxidation of the upper source / drain region 62U and the contact plug 116, forming a silicon oxide layer 126 and a metal oxide layer 128, respectively.

[0049] According to some embodiments, Figure 11 Self-assembled material (SAM) 150 is selectively formed on the metal oxide layer 128. The SAM 150 can be a material selectively formed on a metal-containing surface, thus the SAM 150 can be deposited on the surfaces of the metal oxide layer 128 and / or the contact plug 116. Very little or no SAM 150 is deposited on the dielectric substrate 124, the silicon oxide layer 126, or the upper source / drain region 62U. The SAM 150 can completely or partially cover the exposed surfaces of the metal oxide layer 128 and / or the contact plug 116.

[0050] The self-assembly material 150 may include suitable self-assembly materials, and in some cases may form a monolayer. The self-assembly material 150 may be deposited using suitable techniques, such as exposing a surface to a self-assembly material precursor. For example, according to some embodiments, the self-assembly material precursor may be a thiol (e.g., 16-mercaptohexadecanoic acid, 11-mercaptoundecanoic acid, lipoic acid, etc.) having an R group containing 3 to 20 carbon chains; a phosphonic acid (e.g., NDPA, HDPA, PUA, PHA, etc.) having an R group containing 3 to 20 carbon chains; a carboxylic acid (e.g., stearic acid, oleic acid, dodecanoic acid, etc.) having an R group containing 3 to 20 carbon chains; or a silane (e.g., dodecyltrichlorosilane, n-octadecyltrichlorosilane, (tetrafluoro-1,1,2,2-tetrahydrooctyl)trichlorosilane, dodecenyltriethoxysilane, etc.) having an R group containing 3 to 20 carbon chains. These are examples; other self-assembly material precursors or self-assembly materials can be used to form self-assembly material 150.

[0051] According to some embodiments, Figure 12 A pre-cleaning process is performed to remove the silicon oxide layer 126. The pre-cleaning process can be similar to the previous one. Figure 5 The first pre-cleaning process is described above. After the pre-cleaning process, the silicon oxide layer 126 is removed, and the underlying upper source / drain region 62U is exposed. According to some embodiments, the pre-cleaning process does not remove the self-assembled material 150 or the underlying metal oxide layer 128.

[0052] According to some embodiments, Figure 13 A silicide region 130 is formed on the upper source / drain region 62U. The silicide region 130 can use a similar design as previously described. Figure 6 The materials or techniques described above are used to form the silicide region 130. For example, according to some embodiments, the silicide region 130 can be formed by exposing the structure to a metal-containing precursor, which reacts with the surface of the upper source / drain region 62U to form the silicide region 130. In some cases, a nitride layer can be formed on the silicide region 130. For example, in which the silicide region 130 is titanium silicide (e.g., TiSi). x In some embodiments, the nitride layer may include titanium nitride (e.g., TiN) and / or titanium silicon nitride (e.g., TiSiN). Other materials are also possible.

[0053] In some cases, a residue layer 132 may be formed within the opening 122, which may be similar to the previous one. Figure 6The residue layer 132 is described above. According to some embodiments, the formation rate of residue 132 on the self-assembly material 150 is lower than the formation rate on other surfaces of the structure. In this way, very little or no residue 132 can be formed on the self-assembly material 150, and very little or no residue 132 can be formed on the metal oxide layer 128. Due to the presence of the self-assembly material 150, according to some embodiments, the metal oxide layer 128 may be free of residue layer 132. In some cases, residue 132 may be deposited on some portions of the metal oxide layer 128, such as portions not completely or adequately covered by the self-assembly material 150.

[0054] According to some embodiments, Figure 14 The self-assembled material 150 is removed. The self-assembled material 150 can be removed using a suitable process, such as etching, ashing, chemical rinsing, or other processes. After removal of the self-assembled material 150, the surfaces of the metal oxide layer 128 and / or the contact plug 116 are exposed. According to some embodiments, after removal of the self-assembled material 150, the metal oxide layer 128 may be free of a residue layer 132. In some cases, residue 132 may remain on the surface of the metal oxide layer 128 after removal of the self-assembled material 150.

[0055] According to some embodiments, Figure 15 A pre-cleaning process is performed to remove the metal oxide layer 128. The pre-cleaning process can be similar to the previous one. Figure 8 The second pre-cleaning process. After performing the pre-cleaning process, at least a portion of the metal oxide layer 128 is removed, and the contact plug 116 is exposed. In some cases, a portion of the residual layer 132 may remain above the silicide region 130.

[0056] According to some embodiments, Figure 16 Metal filler is deposited into opening 122 to form contact plug 140. The metal filler and contact plug 140 can be similar to those previously... Figure 9 Those described above. For example, contact plug 140 is electrically connected to the upper source / drain region 62U and physically and electrically connected to contact plug 116. According to some embodiments, a metal filler may completely fill the opening 122. The metal filler may be a similar material to those of metal filler 134 and / or contact plug 116. In this way, the interface between contact plug 140 and contact plug 116 may be free of residue 132, which can reduce resistance and improve device performance.

[0057] According to some embodiments, Figures 17 to 23 The contact plug 140 of the stacked transistor structure is shown (see Figure 23 The intermediate stage of formation. Figures 17-23 The process is similar to Figures 10-16The process differs in that the self-assembled material 150 is deposited after the removal of the metal oxide layer 128, rather than before the removal of the metal oxide layer 128. Figures 17-23 Some of the materials and techniques used are similar to those previously used. Figures 1A-16 The aforementioned details, and therefore some corresponding details, may not be repeated. Figure 17 It shows something similar to the previous one. Figure 4 and Figure 10 The structure shown can be used in a manner similar to... Figures 1A-4 The materials and techniques described above are used to form [the product / technology]. For example, Figure 17 The diagram shows the structure after oxidation on the upper source / drain region 62U and the contact plug 116, thereby forming a silicon oxide layer 126 and a metal oxide layer 128, respectively.

[0058] According to some embodiments, Figure 18 A pre-cleaning process is performed to remove the metal oxide layer 128. The pre-cleaning process can be similar to the previous one. Figure 8 The second pre-cleaning process described above. After performing the pre-cleaning process, at least a portion of the metal oxide layer 128 is removed, and the contact plug 116 is exposed. According to some embodiments, the pre-cleaning process does not remove the silicon oxide layer 126, thereby leaving the silicon oxide layer 126 on the upper source / drain region 62U after the pre-cleaning process has been performed.

[0059] According to some embodiments, Figure 19 In this process, a self-assembly material 150 is selectively formed on the contact plug 116. The self-assembly material 150 can be similar to the previously... Figure 11 The material described herein may be formed using similar techniques or precursors. For example, the self-assembly material 150 may be a material selectively formed on a metal-containing surface, and thus the self-assembly material 150 is deposited on the surface of the contact plug 116 exposed by a previous pre-cleaning process. Minimal or no self-assembly material 150 is deposited on the dielectric liner 124, the silicon oxide layer 126, or the upper source / drain region 62U. The self-assembly material 150 may completely or partially cover the exposed surface of the contact plug 116.

[0060] According to some embodiments, Figure 20 A pre-cleaning process is performed to remove the silicon oxide layer 126. The pre-cleaning process can be similar to the previous one. Figure 5 The first pre-cleaning process is described above. After the pre-cleaning process, the silicon oxide layer 126 is removed, and the underlying upper source / drain region 62U is exposed. According to some embodiments, the pre-cleaning process does not remove the self-assembled material 150.

[0061] According to some embodiments, Figure 21A silicide region 130 is formed on the upper source / drain region 62U. The silicide region 130 can use a similar design as previously described. Figure 6 The materials or techniques described above are used to form the silicide region 130. For example, according to some embodiments, the silicide region 130 can be formed by exposing the structure to a metal-containing precursor, which reacts with the surface of the upper source / drain region 62U to form the silicide region 130. In some cases, a nitriding process can be performed. For example, in cases where the silicide region 130 is titanium silicide (e.g., TiSi), the silicide region 130 is formed. x In some embodiments, the nitride layer may include titanium nitride (e.g., TiN) and / or titanium silicon nitride (e.g., TiSiN). Other materials are also possible.

[0062] In some cases, a residue layer 132 may be formed within the opening 122, which may be similar to the previous one. Figure 6 The residue layer 132 is described above. According to some embodiments, the formation rate of residue 132 on the self-assembly material 150 is lower than the formation rate on other surfaces of the structure. In this way, very little or no residue 132 can be formed on the self-assembly material 150, and very little or no residue 132 can be formed on the contact plug 116. Due to the presence of the self-assembly material 150, according to some embodiments, the contact plug 116 may be without a residue layer 132. In some cases, residue 132 may be deposited on some portions of the contact plug 116, such as portions not completely or adequately covered by the self-assembly material 150.

[0063] According to some embodiments, Figure 22 Remove self-assembly material 150. Self-assembly material 150 can be used similarly to the previous... Figure 14 The aforementioned techniques are used to remove the self-assembly material 150. After removing the self-assembly material 150, the surface of the contact plug 116 is exposed. According to some embodiments, after removing the self-assembly material 150, the contact plug 116 may be free of a residue layer 132. In some cases, residue 132 may remain on the surface of the contact plug 116 after removing the self-assembly material 150.

[0064] According to some embodiments, Figure 23 Metal filler is deposited into opening 122 to form contact plug 140. The metal filler and contact plug 140 can be similar to those previously... Figure 9 Those described above. For example, contact plug 140 is electrically connected to the upper source / drain region 62U and physically and electrically connected to contact plug 116. According to some embodiments, a metal filler may completely fill the opening 122. The metal filler may be a similar material to those of metal filler 134 and / or contact plug 116. In this way, the interface between contact plug 140 and contact plug 116 may be free of residue 132, which can reduce resistance and improve device performance.

[0065] According to some embodiments, Figures 24 to 27 The contact plug 160 of the stacked transistor structure is shown (see Figure 27 The intermediate stage of formation. The contact plug 160 is similar to the previously described contact plug 140, except that the contact plug 160 includes a metal filler 142 and a metal cover layer 154. Figures 24-27 Some of the materials and techniques used are similar to those previously used. Figure 1A-Figure 23 Those have been mentioned, and therefore some details may not be repeated. Figure 24 It shows something similar to the previous one. Figure 4 The structure shown can be used in a manner similar to... Figures 1A-4 The materials and techniques described above are used to form [the product / technology]. For example, Figure 24 The diagram shows the structure after oxidation of the upper source / drain region 62U and the contact plug 116, thereby forming a silicon oxide layer 126 and a metal oxide layer 128, respectively.

[0066] According to some embodiments, Figure 25 A selective silicide region 152 is formed on the upper source / drain region 62U. Prior to forming the selective silicide region 152, a first pre-cleaning process is performed to remove the silicon oxide layer 126. This first pre-cleaning process may be similar to previous processes. Figure 5 The first pre-cleaning process is described above. After performing the first pre-cleaning process, the silicon oxide layer 126 is removed, and the underlying upper source / drain region 62U is exposed.

[0067] After removing the silicon oxide layer 126, a selective silicide region 152 is formed on the upper source / drain region 62U. The selective silicide region 152 is deposited using materials and techniques that selectively form silicide materials on the material of the upper source / drain region 62U rather than on other materials (e.g., dielectric layers, metals, or metal oxides). For example, the selective silicide region 152 can be formed by exposing the upper source / drain region 62U to a suitable precursor. According to some embodiments, the selective silicide region 152 can be formed using suitable techniques (e.g., chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), etc.). The selective silicide region 152 may contain titanium silicide, but other silicides are also possible.

[0068] According to some embodiments, Figure 26A metal capping layer 154 is formed on the selective silicide region 152 and the contact plug 116. The metal capping layer 154 forms physical and electrical contacts with the selective silicide region 152 and the contact plug 116. The metal capping layer 154 protects the selective silicide region 152 and the contact plug 116 during subsequent process steps and allows a low-resistance electrical connection to be formed between the contact plug 160 and the contact plug 116. The metal capping layer 154 may be formed as multiple metal regions (e.g., Figure 26 As shown), it may form a continuous metal region.

[0069] The metal capping layer 154 may be a suitable metal deposited using a suitable technique. For example, according to some embodiments, the metal capping layer 154 comprises a metal (e.g., tungsten, molybdenum, ruthenium, iridium, cobalt, tantalum, rhenium, palladium, platinum, etc., or combinations thereof). According to some embodiments, the metal capping layer 154 and the contact plug 116 may be the same metal, but in other embodiments the metal capping layer 154 and the contact plug 116 may be different metals. According to some embodiments, the metal capping layer 154 may be formed using a deposition technique that deposits on a metal-containing surface (e.g., the surface of the selective silicide region 152 and the contact plug 116). In this way, the metal capping layer 154 may be deposited using a "bottom-up" deposition technique. According to some embodiments, the metal capping layer 154 may be deposited using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc. According to some embodiments, the precursor used to deposit the metal capping layer 154 also removes the metal oxide layer 128. Examples of precursors that also remove the metal oxide layer 128 include WCl5, MoCl5, etc. Therefore, the metal oxide layer 128 can be removed without performing a separate pre-cleaning process, allowing the metal capping layer 154 to be deposited directly onto the contact plug 116. Other precursor or deposition techniques are also possible. According to some embodiments, the selective silicide region 152 and the metal capping layer 154 can be deposited in the same process chamber (e.g., in situ).

[0070] According to some embodiments, Figure 27 Metal filler 142 is deposited into opening 122 to form contact plug 160. Metal filler 142, together with metal capping layer 154, forms contact plug 160. Metal filler 142 may be similar to previously... Figure 9 The metal filler 142 may, for example, comprise a metal similar to or different from that of the metal capping layer 154 and / or the contact plug 116. The contact plug 160 is electrically connected to the upper source / drain region 62U and is physically and electrically connected to the contact plug 116. Forming the selective silicide region 152 and the metal capping layer 154, as described herein, ensures a silicide-free interface between the contact plug 160 and the contact plug 116, which reduces resistance and improves device performance.

[0071] According to some embodiments, Figures 28 to 32 The contact plug 160 of the stacked transistor structure is shown (see Figure 32 The intermediate stage of formation. Contact plug 160 uses a similar... Figures 24-27 The process steps described above differ in that the silicide is not formed using a selective deposition process. Figures 28-32 Some of the materials and techniques used are similar to those previously used. Figures 1A-27 Those have been mentioned, and therefore some details may not be repeated. Figure 28 It shows something similar to the previous one. Figure 4 The structure shown can be used in a manner similar to... Figures 1A-4 The materials and techniques described above are used to form [the product / technology]. For example, Figure 28 The diagram shows the structure after oxidation on the upper source / drain region 62U and the contact plug 116, thereby forming a silicon oxide layer 126 and a metal oxide layer 128, respectively.

[0072] According to some embodiments, Figure 29 A silicide region 130 is formed on the upper source / drain region 62U. Prior to forming the silicide region 130, a first pre-cleaning process is performed to remove the silicon oxide layer 126. This first pre-cleaning process may be similar to previous processes. Figure 5 The first pre-cleaning process is described above. After performing the first pre-cleaning process, the silicon oxide layer 126 is removed, and the underlying upper source / drain region 62U is exposed. The silicide region 130 can be used similarly to the previously described process. Figure 6 The materials or techniques described above are used to form the silicide region 130. For example, according to some embodiments, the silicide region 130 can be formed by exposing the structure to a metal-containing precursor, which reacts with the surface of the upper source / drain region 62U to form the silicide region 130. In some cases, a nitriding process can be performed. For example, in cases where the silicide region 130 is titanium silicide (e.g., TiSi), the silicide region 130 is formed. x In embodiments of the invention, the nitride layer may comprise titanium nitride (e.g., TiN) and / or titanium silicon nitride (e.g., TiSiN). Other materials are also possible. In some cases, a residual layer 132 may be formed within the opening 122, which may be similar to the previously described layer. Figure 6 The aforementioned residue layer 132.

[0073] According to some embodiments, Figure 30 An etching process is performed to remove residual layer 132. In some cases, the etching process may be considered as a "pull-back etching" or similar process. The etching process may expose silicide regions 130 and / or metal oxide layers 128. In some cases, the etching process may not completely remove residual layer 132. The etching process may include wet etching and / or dry etching processes.

[0074] According to some embodiments, Figure 26 A metal capping layer 154 is formed on the selective silicide region 152 and the contact plug 116. The metal capping layer 154 may be similar to the previous Figure 26 Those described above can be formed using similar techniques. For example, according to some embodiments, the precursor used for depositing the metal capping layer 154 also removes the metal oxide layer 128. The metal capping layer 154 forms physical and electrical contacts with the selective silicide region 152 and the contact plug 116. The metal capping layer 154 protects the selective silicide region 152 and the contact plug 116 during subsequent process steps, while simultaneously allowing a low-resistance electrical connection to be formed between the contact plug 160 and the contact plug 116. The metal capping layer 154 can be formed as multiple metal regions (e.g., Figure 26 As shown), it may form a continuous metal region. According to some embodiments, the etching of the residue layer 132 and the deposition of the metal capping layer 154 may be performed in the same process chamber (e.g., in situ).

[0075] According to some embodiments, Figure 32 Metal filler 142 is deposited into opening 122 to form contact plug 160. Metal filler 142, together with metal capping layer 154, forms contact plug 160. Metal filler 142 may be similar to previously... Figure 9 The metal filler and / or Figure 27 The metal filler 142. For example, the metal filler 142 may contain a metal similar to or different from the metal capping layer 154 and / or the contact plug 116. The contact plug 160 is electrically connected to the upper source / drain region 62U and is physically and electrically connected to the contact plug 116. According to some embodiments, excess metal filler 142 may be removed using a planarization process.

[0076] According to some embodiments, Figures 33 to 37 The contact plug 170 of the stacked transistor structure is shown (see Figure 37 The intermediate stage of formation. Contact plug 170 uses a similar... Figures 24-27 The contact plug 160 is formed in a process that differs in that the metal oxide layer 128 is also removed during the formation of the silicide. For example, the contact plug 170 includes a metal capping layer 164 and a metal filler 142. Figures 33-37 Some of the materials and techniques used are similar to those previously used. Figure 1A-Figure 32 Those have been mentioned, and therefore some details may not be repeated. Figure 33 It shows something similar to the previous one. Figure 4 The structure shown can be used in a manner similar to... Figures 1A-4 The materials and techniques described above are used to form [the product / technology]. For example, Figure 33The diagram shows the structure after oxidation on the upper source / drain region 62U and the contact plug 116, thereby forming a silicon oxide layer 126 and a metal oxide layer 128, respectively.

[0077] According to some embodiments, Figure 34 A pre-cleaning process is performed to remove the silicon oxide layer 126. The pre-cleaning process can be similar to the previous one. Figure 5 The first pre-cleaning process is described above. After the pre-cleaning process, the silicon oxide layer 126 is removed, and the underlying upper source / drain region 62U is exposed. According to some embodiments, the pre-cleaning process does not remove the metal oxide layer 128.

[0078] According to some embodiments, Figure 35 A silicide region 162 is formed on the upper source / drain region 62U. The silicide region 162 can be formed by exposing the structure to a silicide precursor (e.g., a metal-containing precursor). According to some embodiments, the silicide precursor also removes the metal oxide layer 128. Other silicide precursors are also possible. Therefore, the metal oxide layer 128 can be removed without performing a separate pre-cleaning process. According to some embodiments, the silicide precursor is also deposited on other surfaces (e.g., the surface of the contact plug 116). The metal of the silicide region 162 may include titanium, vanadium, zinc, niobium, aluminum, zirconium, ruthenium, molybdenum, or other suitable metals. In some cases, the silicide region 162 may extend beyond... Figure 37 More surfaces or different surfaces are shown.

[0079] According to some embodiments, Figure 36 A metal capping layer 164 is formed in the opening 122. The metal capping layer 164 may cover the silicide region 162 and may partially fill the opening 122. The metal capping layer 164 may be a suitable metal deposited using a suitable technique. For example, according to some embodiments, the metal capping layer 164 comprises a metal (e.g., tungsten, molybdenum, ruthenium, iridium, cobalt, tantalum, rhenium, palladium, platinum, zirconium, etc., or combinations thereof). According to some embodiments, the metal capping layer 164 and the contact plug 116 may be the same metal, but in other embodiments the metal capping layer 164 and the contact plug 116 may be different metals. According to some embodiments, the metal capping layer 164 may be deposited using a bottom-up deposition technique.

[0080] The metal capping layer 164 protects the silicide region 162 during subsequent process steps and allows for a low-resistance electrical connection between the contact plug 170 and the contact plug 116. According to some embodiments, the deposition of the silicide region 162 and the deposition of the metal capping layer 164 can be performed in the same process chamber (e.g., in situ). Therefore, a nitride layer may not be formed on the silicide region 162, as the silicide region 162 is protected by the metal capping layer 164. In this way, omitting the relatively high-resistance nitride layer improves the electrical connection between the contact plug 170 and the contact plug 116 and enhances device performance.

[0081] According to some embodiments, Figure 37 Metal filler 142 is deposited into opening 122 to form contact plug 170. Metal filler 142, together with metal capping layer 164, forms contact plug 170. Metal filler 142 may be similar to previously... Figure 9 The metal filler and / or Figure 27 The metal filler 142 may, for example, comprise a metal similar to or different from the metal capping layer 164 and / or the contact plug 116. The contact plug 170 is electrically connected to the upper source / drain region 62U and is physically and electrically connected to the contact plug 116. According to some embodiments, a planarization process can be used to remove excess metal filler 142. In this way, by omitting the nitride layer above the silicide region 162 and removing the metal oxide layer 128, the electrical connection between the source / drain contact plug and the vertical local interconnect can be improved.

[0082] According to some embodiments, Figures 38 to 40 The contact plug 170 of the stacked transistor structure is shown (see Figure 40 The intermediate stage of formation. Contact plug 170 uses a similar... Figures 33-37 The contact plug 170 is formed using the same process steps as those described above, except that the silicide is selectively formed on the upper source / drain region 62U. For example, the contact plug 170 includes a metal capping layer 164 and a metal filler 142, and the metal oxide layer 128 is also removed during silicide formation. Figures 38-40 Some of the materials and techniques used are similar to those previously used. Figures 1A-37 Those have been mentioned, and therefore some details may not be repeated. Figure 38 It shows something similar to the previous one. Figure 34 The structure shown is structurally sound. For example... Figure 38 The structure after the silicon oxide layer 126 has been removed by a pre-cleaning process is shown.

[0083] According to some embodiments, Figure 39A selective silicide region 166 is formed on the upper source / drain region 62U. The selective silicide region 166 is deposited using materials and techniques that selectively form on the upper source / drain region 62U material while simultaneously removing the metal oxide layer 128. For example, this can be achieved by exposing the upper source / drain region 62U to a suitable precursor for removing the metal oxide layer 128 (e.g., Mo(CO)6, MoO2(thd)2, MoCl5, MoO2Cl2, [C2H5Ru(CO)2]2, Ru(CO)H2[P(C6H5)3]3, Ru(TMM)(CO)3, Ru3(CO). 12 Selective silicide regions 166 can be formed using precursors such as TDMAZ, ZrCl4, TEMAZr, and Zr(OEt)4. Other precursors are also possible. Therefore, the metal oxide layer 128 can be removed without performing a separate pre-cleaning process. According to some embodiments, the selective silicide regions 166 can be formed using suitable techniques such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), etc. The selective silicide regions 166 may contain, for example, molybdenum silicide, zirconium silicide, ruthenium silicide, etc., but other silicides are also possible. In some cases, the selective silicide regions 166 can use precursors similar to those previously described. Figure 25 The selective silicide region 152 is formed using materials or techniques. Depositing selective silicide on the upper source / drain region 62U avoids depositing silicide material or residue on the contact plug 116, which reduces resistance.

[0084] According to some embodiments, Figure 40 A metal capping layer 164 and a metal filler 142 are deposited into the opening 122 to form a contact plug 170. The metal filler 142, together with the metal capping layer 164, forms the contact plug 170. The metal capping layer 164 may be deposited on the selective silicide region 166 and the contact plug 116. The metal capping layer 164 may be a suitable metal deposited using a suitable technique and may be similar to previously... Figure 36 The metal capping layer 164 is described above. For example, according to some embodiments, the metal capping layer 164 comprises a metal (e.g., tungsten, molybdenum, ruthenium, iridium, cobalt, tantalum, rhenium, palladium, platinum, zirconium, etc., or combinations thereof). According to some embodiments, the metal capping layer 164 and the contact plug 116 may be the same metal, but in other embodiments the metal capping layer 164 and the contact plug 116 may be different metals. According to some embodiments, the metal capping layer 164 may be deposited using a bottom-up deposition technique.

[0085] Metal filler 142 can be similar to the previous Figure 9 The metal filling and / or previous Figure 27The metal filler 142 may, for example, comprise a metal similar to or different from the metal capping layer 164 and / or the contact plug 116. The contact plug 170 is electrically connected to the upper source / drain region 62U and is physically and electrically connected to the contact plug 116. According to some embodiments, a planarization process can be used to remove excess metal filler 142. This improves the electrical connection between the source / drain contact plug and the vertical local interconnect.

[0086] The embodiments of this disclosure have several advantages. By removing the resistive metal oxide formed on the contact plug, the resistance at the interface between one contact plug and another can be reduced. The techniques described herein also allow the interface between the two contact plugs to form with very little or no resistive silicide residue. According to some embodiments, silicide residue is removed from the contact plug. In other embodiments, silicide residue is prevented from forming on the contact plug. According to some embodiments, a metal overlay is used to enhance the electrical connection between the two contact plugs. The techniques described herein can reduce the resistance between the two contact plugs, which can improve the electrical connection and enhance device performance.

[0087] According to some embodiments of this disclosure, a method includes: forming a source / drain region; forming a contact etch stop layer over the source / drain region; forming an interlayer dielectric layer over the contact etch stop layer; forming a first contact plug in the interlayer dielectric layer and the contact etch stop layer; performing a first etching process to form an opening in the interlayer dielectric layer and the contact etch stop layer, wherein the opening exposes the surface of the source / drain region and the surface of the first contact plug, wherein a metal oxide layer on the first contact plug is exposed by the opening; performing a silicide formation process to form a silicide region on the surface of the source / drain region; performing a second etching process to remove the metal oxide layer; and forming a second contact plug in the opening, wherein the second contact plug is electrically connected to the silicide region and the first contact plug, wherein the conductivity of the silicide region is between the conductivity of the source / drain region and the conductivity of the second contact plug. In an embodiment, the silicide formation process includes forming a nitride layer over the silicide region. In one embodiment, the method includes depositing a sacrificial metal layer over a silicide region and a metal oxide layer after performing a silicide formation process; and recessing the sacrificial metal layer. In another embodiment, a second etching process further removes the metal oxide on the sacrificial metal layer. In yet another embodiment, the method includes depositing a self-assembled material (SAM) over a first contact plug before performing a silicide formation process. In yet another embodiment, a second etching process is performed before the silicide formation process. In yet another embodiment, the silicide formation process is a selective process that selectively deposits silicide material on the source / drain regions. In yet another embodiment, the silicide formation process includes a second etching process that removes the metal oxide layer.

[0088] According to some embodiments of this disclosure, a method includes: forming a conductive component near a source / drain region; exposing a first surface of the conductive component and the first surface of the source / drain region; forming a metal oxide layer on the conductive component and a silicon oxide layer on the source / drain region; removing the silicon oxide layer, wherein removing the silicon oxide layer exposes a second surface of the source / drain region; forming a silicide region on the second surface of the source / drain region; removing the metal oxide layer, wherein removing the metal oxide layer exposes the second surface of the conductive component; and depositing a first conductive material on the silicide region and the second surface of the conductive component. In embodiments, the conductive component includes the first conductive material. In embodiments, the method includes depositing a second conductive material on the first conductive material, wherein the conductive component includes the second conductive material. In embodiments, forming the silicide region also removes the metal oxide layer. In embodiments, depositing the first conductive material also removes the metal oxide layer. In embodiments, forming the silicide region also forms a residual layer over the metal oxide layer. In embodiments, the metal oxide layer is tungsten oxide.

[0089] According to some embodiments of this disclosure, a device includes: a lower transistor including a lower source / drain region; an upper transistor including an upper source / drain region; a vertical interconnect extending adjacent to both the lower and upper source / drain regions; a silicide region on the upper source / drain region; a first metal overlay material on the silicide region; a second metal overlay material on the vertical interconnect; and a metal filler layer covering the first and second metal overlay materials. In embodiments, the metal filler material is different from the metal overlay material. In embodiments, the first and second metal filler materials are continuous. In embodiments, the interface between the second metal overlay material and the vertical interconnect is free of metal oxide. In embodiments, the silicide region extends between the second metal overlay material and the vertical interconnect.

[0090] Some embodiments of this application provide a method for forming a semiconductor device, comprising: forming a source / drain region; forming a contact etch stop layer over the source / drain region; forming an interlayer dielectric layer over the contact etch stop layer; forming a first contact plug in the interlayer dielectric layer and the contact etch stop layer; performing a first etching process to form an opening in the interlayer dielectric layer and the contact etch stop layer, wherein the opening exposes the surface of the source / drain region and the surface of the first contact plug, wherein a metal oxide layer on the first contact plug is exposed through the opening; performing a silicide formation process to form a silicide region on the surface of the source / drain region; performing a second etching process to remove the metal oxide layer; and forming a second contact plug in the opening, the second contact plug being electrically connected to the silicide region and the first contact plug, the conductivity of the silicide region being between the conductivity of the source / drain region and the conductivity of the second contact plug.

[0091] In some embodiments, the silicide formation process includes forming a nitride layer over a silicide region. In some embodiments, the method further includes: depositing a sacrificial metal layer over the silicide region and depositing a sacrificial metal layer over the metal oxide layer after performing the silicide formation process; and recessing the sacrificial metal layer. In some embodiments, the second etching process further removes the metal oxide from the sacrificial metal layer. In some embodiments, the method further includes depositing a self-assembled material (SAM) over the first contact plug before performing the silicide formation process. In some embodiments, the second etching process is performed before the silicide formation process. In some embodiments, the silicide formation process is a selective process that selectively deposits silicide material on the source / drain regions. In some embodiments, the silicide formation process includes the second etching process that removes the metal oxide layer.

[0092] Other embodiments of this application provide a method for forming a semiconductor device, comprising: forming a conductive component near a source / drain region; exposing a first surface of the conductive component and the first surface of the source / drain region; forming a metal oxide layer on the conductive component and a silicon oxide layer on the source / drain region; removing the silicon oxide layer, wherein the removal of the silicon oxide layer exposes a second surface of the source / drain region; forming a silicide region on the second surface of the source / drain region; removing the metal oxide layer, wherein the removal of the metal oxide layer exposes the second surface of the conductive component; and depositing a first conductive material on the silicide region and the second surface of the conductive component.

[0093] In some embodiments, the conductive component includes the first conductive material. In some embodiments, the method further includes depositing a second conductive material on the first conductive material, wherein the conductive component includes the second conductive material. In some embodiments, forming the silicide region also removes the metal oxide layer. In some embodiments, depositing the first conductive material also removes the metal oxide layer. In some embodiments, forming the silicide region also forms a residual layer over the metal oxide layer. In some embodiments, the metal oxide layer is tungsten oxide.

[0094] Further embodiments of this application provide a semiconductor device including: a lower transistor including a lower source / drain region; an upper transistor including an upper source / drain region; a vertical interconnect extending near the lower source / drain region and near the upper source / drain region; a silicide region located on the upper source / drain region; a first metal overlay material located on the silicide region; a second metal overlay material located on the vertical interconnect; and a metal filler layer covering the first metal overlay material and the second metal overlay material.

[0095] In some embodiments, the metal filler material is different from the metal overlay material. In some embodiments, the first metal filler layer and the second metal filler layer are continuous. In some embodiments, the interface between the second metal overlay material and the vertical interconnect component is free of metal oxide. In some embodiments, the silicide region extends between the second metal overlay material and the vertical interconnect component.

[0096] The foregoing has outlined components of several embodiments, enabling those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis to design or modify other processes and structures to achieve the same purpose and / or the same advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a semiconductor device, comprising: Forming source / drain regions; A contact etch stop layer is formed above the source / drain region; An interlayer dielectric layer is formed above the contact etch stop layer; A first contact plug is formed in the interlayer dielectric layer and the contact etch stop layer; A first etching process is performed to form an opening in the interlayer dielectric layer and the contact etch stop layer, wherein the opening exposes the surface of the source / drain region and the surface of the first contact plug, wherein the metal oxide layer on the first contact plug is exposed through the opening; Perform a silicide formation process to form silicide regions on the surface of the source / drain regions; Perform a second etching process to remove the metal oxide layer; and A second contact plug is formed in the opening, the second contact plug being electrically connected to the silicide region and the first contact plug, the conductivity of the silicide region being between the conductivity of the source / drain region and the conductivity of the second contact plug.

2. The method of claim 1, wherein the silicide formation process includes forming a nitride layer over the silicide region.

3. The method according to claim 1, further comprising: After performing the silicide formation process, a sacrificial metal layer is deposited over the silicide region and a sacrificial metal layer is deposited over the metal oxide layer; as well as This causes the sacrificial metal layer to be recessed.

4. The method of claim 3, wherein the second etching process further removes metal oxides from the sacrificial metal layer.

5. The method of claim 1, further comprising depositing a self-assembled material (SAM) over the first contact plug prior to performing the silicide formation process.

6. The method of claim 1, wherein the second etching process is performed prior to the silicide formation process.

7. The method of claim 1, wherein the silicide formation process is a selective process that selectively deposits silicide material on the source / drain regions.

8. The method of claim 1, wherein the silicide formation process includes the second etching process for removing the metal oxide layer.

9. A method for forming a semiconductor device, comprising: Conductive components are formed near the source / drain regions; The first surface of the conductive component and the first surface of the source / drain region are exposed; A metal oxide layer is formed on the conductive component and a silicon oxide layer is formed on the source / drain region; Remove the silicon oxide layer, wherein the removed silicon oxide layer exposes the second surface of the source / drain region; A silicide region is formed on the second surface of the source / drain region; Remove the metal oxide layer, wherein the removal of the metal oxide layer exposes the second surface of the conductive component; as well as A first conductive material is deposited on the silicide region and on the second surface of the conductive component.

10. A semiconductor device, comprising: The lower transistor includes the lower source / drain region; Upper transistor, including upper source / drain regions; Vertical interconnect components extend near the lower source / drain region and near the upper source / drain region; The silicide region is located on the upper source / drain region; A first layer of metallic covering material is located on the silicide region; A second layer of metallic covering material is located on the vertical interconnect component; and A metal filler layer covers the first metal cover material and the second metal cover material.

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