Stacked transistor and preparation method thereof, semiconductor device and electronic equipment
By constructing oriented strip-shaped vias aligned with the power rails in stacked transistors, the parasitic resistance problem caused by high aspect ratio vias is solved, resulting in lower interconnect resistance and higher integration density, thus optimizing circuit performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-24
- Publication Date
- 2026-04-10
Smart Images
Figure CN121843225A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor device manufacturing, in particular to a stacked transistor, a preparation method thereof, a semiconductor device and an electronic equipment. BACKGROUND
[0002] With the continuous evolution of Moore's Law, how to further realize the miniaturization of transistors after entering the gate all around (GAA) transistor technology node has become a key problem in the industry. The stacked transistor technology can greatly improve the device density in a unit area by integrating two or more layers of transistors in the vertical direction, and is also conducive to optimizing the performance and power consumption of the circuit. Therefore, this technology is considered as one of the important paths to continue the miniaturization trend of integrated circuits and promote the continuous growth of computing power. However, the stacking of stacked transistors in the vertical direction requires the use of high aspect ratio vias for interconnection, which can cause large parasitic resistance inside the transistor. SUMMARY
[0003] The embodiments of the present application provide a stacked transistor, a preparation method thereof, a semiconductor device and an electronic equipment, which can reduce the interconnection resistance inside the stacked transistor and reduce the voltage drop.
[0004] The technical solutions of the embodiments of the present application are implemented as follows:
[0005] The embodiments of the present application provide a preparation method of a stacked transistor, comprising: forming a first active structure and a second active structure stacked in a first direction on a substrate; based on the first active structure, forming a first front-end layer of a first transistor; the first front-end layer comprises a first gate structure, a first source-drain structure and a first interlayer dielectric layer; wherein the first source-drain structure comprises a first source structure and a first drain structure; etching a part of the first source structure or a part of the first drain structure; depositing a dielectric material on the first front-end layer to form a first dielectric layer; forming a first strip-shaped via in the first dielectric layer; the first strip-shaped via extends along a second direction, and the second direction is perpendicular to the first direction; the orthographic projection of the first strip-shaped via in the first direction does not overlap with the orthographic projection of the etched first source structure or first drain structure in the first direction, and the first strip-shaped via is connected to the unetched first drain structure or first source structure; performing a back-end interconnection process on the first dielectric layer to form a first back-end interconnection layer; a first power rail in the first back-end interconnection layer is connected to the first strip-shaped via; the orthographic projection of the first strip-shaped via in the first direction is located inside the orthographic projection of the first power rail in the first direction; reversing and thinning the substrate; and based on the second active structure, forming a second transistor.
[0006] In some possible implementation manners, the first strip-shaped via hole is formed in the first dielectric layer, including: forming a first groove in the first dielectric layer by photolithography; depositing a conductive material in the first groove, and performing thinning processing to form the first strip-shaped via hole.
[0007] In some possible implementation manners, a back-end interconnection process is performed on the first dielectric layer to form a first back-end interconnection layer, including: depositing a dielectric material on the first dielectric layer to form a second dielectric layer; forming a first power supply rail and a plurality of first signal lines in the second dielectric layer; and wherein the first strip-shaped via hole is connected to the first power supply rail or one of the plurality of first signal lines.
[0008] In some possible implementation manners, the second transistor is formed based on the second active structure, including: forming a second front-end layer of the second transistor based on the second active structure; the second front-end layer includes a second gate structure, a second source-drain structure, and a second interlayer dielectric layer; wherein the second source-drain structure includes a second source structure and a second drain structure; etching a part of the second source structure or a part of the second drain structure; depositing a dielectric material on the second front-end layer to form a third dielectric layer; forming a second strip-shaped via hole in the third dielectric layer; the second strip-shaped via hole extends along a second direction, a projection of the second strip-shaped via hole in a first direction does not overlap a projection of the etched second source structure or second drain structure in the first direction, and the second strip-shaped via hole is connected to the unetched second drain structure or second source structure; performing a back-end interconnection process on the third dielectric layer to form a second back-end interconnection layer; a second power supply rail in the second back-end interconnection layer is connected to the second strip-shaped via hole; and a projection of the second strip-shaped via hole in the first direction is located inside a projection of the second power supply rail in the first direction.
[0009] In some possible implementation manners, the second strip-shaped via hole is formed in the third dielectric layer, including: forming a second groove in the third dielectric layer by photolithography; depositing a conductive material in the second groove, and performing thinning processing to form the second strip-shaped via hole.
[0010] In some possible implementation manners, the first power supply rail and the second power supply rail are symmetrically arranged in the first direction.
[0011] In some possible implementation manners, the first power supply rail and the second power supply rail are asymmetrically arranged in the first direction.
[0012] The embodiment of the present application provides a stacked transistor, which is prepared by the method described above, and the stacked transistor comprises: a first transistor; a first source-drain structure of the first transistor and a first power rail of the first transistor are connected through a first strip-shaped via; a projection of the first strip-shaped via in a first direction is located in a projection of the first power rail in the first direction; a second transistor; a second source-drain structure of the second transistor and a second power rail of the second transistor are connected through a second strip-shaped via; a projection of the second strip-shaped via in the first direction is located in a projection of the second power rail in the first direction.
[0013] The embodiment of the present application provides a semiconductor device, comprising: a plurality of stacked transistors as described above; wherein the plurality of semiconductor structures are electrically connected through a back-end interconnection layer, and the plurality of semiconductor structures form a functional circuit.
[0014] The embodiment of the present application provides an electronic device, comprising: a circuit board; a semiconductor device as described above; and the semiconductor device is mounted on the circuit board and electrically connected with the circuit board.
[0015] The technical scheme provided by the embodiment of the present application can have the following beneficial effects:
[0016] By constructing the first strip-shaped via extending along a specific direction (i.e. the second direction) in the first dielectric layer, and aligning the first strip-shaped via with the first power rail in the first back-end interconnection layer, the projection of the first strip-shaped via in the first direction is located in the projection of the first power rail in the first direction, thereby forming a relatively continuous electrical contact, so as to reduce the interconnection resistance in the stacked transistor and reduce the voltage drop.
[0017] Further, the second transistor has the same structure as the first transistor, and in the high-density integrated stacked transistor, the integration density can be further increased, and the wiring scheme can be optimized.
[0018] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF DRAWINGS
[0019] The drawings herein are incorporated into the specification and form a part of the specification, show embodiments consistent with the present application, and together with the specification, serve to explain the principles of the present application.
[0020] Figure 1 An implementation flowchart of a preparation method of a stacked transistor in the embodiment of the present application;
[0021] Figure 2 A first design layout of a stacked transistor in the embodiment of the present application;
[0022] Figures 3 to 5A flow chart of a preparation method of the stacked transistor in the embodiment of the present application;
[0023] Figure 6 A first structure diagram of the stacked transistor in the embodiment of the present application;
[0024] Figure 7 A second design layout of the stacked transistor in the embodiment of the present application;
[0025] Figure 8 A second structure diagram of the stacked transistor in the embodiment of the present application.
[0026] The reference signs and names in the figures are as follows:
[0027] 11-first transistor; 111-first active structure; 112-first gate structure; 113-first source / drain epitaxy; 114-first interlayer dielectric layer; 115-first source / drain metal; 1151-first drain metal; 116-second interconnection layer; 1161-first power supply rail; 12-second transistor; 121-second active structure; 122-second gate structure; 123-second source / drain epitaxy; 124-second interlayer dielectric layer; 125-second source / drain metal; 1251-second drain metal; 126-second interconnection layer; 1261-second power supply rail; 13-first strip-shaped via; 14-second strip-shaped via; 15-insulating layer; 16-carrier wafer; 21-substrate; 22-shallow trench isolation structure; 31-first dielectric layer; 32-third dielectric layer. DETAILED DESCRIPTION
[0028] In order to make the purpose, technical scheme and advantages of the present application more clear, the present application will be described in further detail below with reference to the drawings, and the described embodiments should not be regarded as limiting the present application, all other embodiments obtained by those skilled in the art without making creative efforts fall within the scope of protection of the present application.
[0029] In the following description, "some embodiments" are referred to, which describe a subset of all possible embodiments, but it can be understood that "some embodiments" can be the same subset or different subset of all possible embodiments, and can be combined with each other without conflict.
[0030] In the following description, the terms "first\second\third" are only to distinguish similar objects, and do not represent a specific order of the objects, and it can be understood that "first\second\third" can be interchanged in a specific order or sequence as allowed, so that the embodiments of the present application described here can be implemented in an order other than that illustrated or described here.
[0031] Unless otherwise defined, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the embodiments of this application is for the purpose of describing the embodiments of this application only and is not intended to limit this application.
[0032] The following description involves several key terms and concepts, which are explained below:
[0033] Stacked field-effect transistor (stacked FET): refers to a device that integrates two or more transistor structures in the vertical direction, often used to improve chip integration density and circuit performance.
[0034] Back end of line (BEOL) technology refers to the process steps such as power rail and via filling performed after the front-end structure of the transistor is completed. It is mainly responsible for the interconnection between transistors or functional modules in the circuit.
[0035] Wafer bonding: a process that physically binds two wafers together, typically used to realize three-dimensional integrated circuit structures, such as flip-chip stacked transistors.
[0036] Flip wafer: After wafer bonding, one of the wafers is flipped and thinned to allow for the subsequent processing of the transistor structure on the other side.
[0037] As integrated circuit technology continues to advance towards higher integration levels, stacked transistor structures have become an important means of perpetuating Moore's Law. By integrating multiple transistor layers in the vertical direction, higher device density and circuit performance can be achieved within a limited chip area. Stacked transistor technology is particularly valuable in complementary field-effect transistor (CFET) structures.
[0038] Currently, in stacked transistors, back-side power delivery network (BSPDN) technology is commonly used to connect power lines to the source and drain regions of transistors, i.e., interconnecting the power lines with the source and drain metals through vias. However, in CFET structures, due to the different transistor types on the upper and lower layers (such as NMOS and PMOS), the corresponding via depths differ significantly, making the implementation of high aspect ratio power vias difficult and affecting interconnect reliability and manufacturing yield. Furthermore, the power via structure is difficult to ideally match with the upper-layer power rails during routing, easily leading to increased parasitic resistance, signal delay, and other problems, thus limiting the overall performance improvement of stacked transistors.
[0039] To solve the above technical problems, the embodiment of the present application provides a preparation method of a stacked transistor, which can reduce the interconnection resistance in the stacked transistor and reduce the voltage drop.
[0040] Figure 1 For an implementation flowchart of the preparation method of the stacked transistor in the embodiment of the present application, refer to Figure 1 The preparation method of the stacked transistor includes the following steps:
[0041] In step 101, a first active structure and a second active structure stacked in a first direction are formed on a substrate.
[0042] In some embodiments, a substrate is provided; and a process such as photolithography, etching, etc. is performed on the substrate to form an active structure; the active structure includes a first active structure and a second active structure. The first active structure is used to prepare a first transistor, and the second active structure is used to prepare a second transistor, and the first transistor and the second transistor constitute a stacked transistor.
[0043] In some embodiments, the first direction is the direction in which the active region in the transistor extends, which can also be referred to as the vertical direction.
[0044] In some embodiments, the types of the first transistor and the second transistor in the stacked transistor can include, but are not limited to, fin field effect transistors (fin FETs), gate-all-around field effect transistors (GAA FETs), and planar field effect transistors.
[0045] In some embodiments, the active structure is different in different types of transistors. For example, in a fin field effect transistor, the active structure is a fin structure; in a gate-all-around field effect transistor, the active structure is a nanosheet structure; and in a planar field effect transistor, the active structure is a block structure.
[0046] In some embodiments, a silicon substrate or a silicon-on-insulator (SOI) substrate can be selected according to actual conditions, and the embodiment of the present application does not make specific limitations.
[0047] In step 102, a first front-end layer of the first transistor is formed based on the first active structure. The first front-end layer includes a first gate structure, a first source-drain structure, and a first interlayer dielectric layer; the first source-drain structure includes a first source structure and a first drain structure.
[0048] In some embodiments, after forming the active structure, an insulating material is deposited on the active structure and the substrate, and the insulating material is etched back so that the insulating material wraps the second active structure and the first active structure is exposed, forming a shallow trench isolation (STI) structure; based on the exposed first active structure, a front end of line (FEOL) process is performed to form a first FEOL layer.
[0049] In some embodiments, the first FEOL layer refers to a process layer in which the basic structure of the first transistor is completed, but has not yet entered the metal interconnection stage.
[0050] In some embodiments, the first source-drain structure includes a doped region and a metallization structure, such as a first source-drain epitaxy and a first source-drain metal, which can realize the input and output of current.
[0051] It should be noted that in the embodiments of the present application, "source-drain" is a short form of "source and / or drain".
[0052] In some embodiments, the first inter layer dielectric (ILD) layer is an insulating material, typically silicon oxide, silicon nitride or other low dielectric constant material, which can isolate the electric field between the first gate structure and the first source-drain structure.
[0053] In step 103, a portion of the first source structure or a portion of the first drain structure is etched.
[0054] In some embodiments, etching a portion of the first source structure or a portion of the first drain structure means etching a portion of the first source metal or a portion of the first drain metal.
[0055] In some embodiments, if a power connection point needs to be formed on one side, the first source metal or the first drain metal on this side can be reserved, and the first drain metal and the first source metal on the other side can be cut or etched to reduce the length of the first drain metal and the first source metal. In this way, it can be ensured that the power rail or the signal line can be stably connected to the above-mentioned reserved first source metal or first drain metal through the metal via hole.
[0056] In the embodiments of the present application, etching a portion of the first source structure or a portion of the first drain structure plays a key role in the accurate alignment of the subsequent first strip-shaped via hole, ensuring that the first power rail or the first signal line can be stably connected to the first source-drain structure of the first transistor.
[0057] In step 104, a dielectric material is deposited on the first FEOL layer to form a first dielectric layer.
[0058] It can be understood that the step 104 and the step 105 are middle of line (MOL) processes in the transistor.
[0059] In some embodiments, the first dielectric layer is a layer of insulating material deposited on the first front-end layer. The commonly used dielectric material for preparing the first dielectric layer can include SiO2, SiN, Low-K, etc.
[0060] In the step 105, a first strip-shaped via is formed in the first dielectric layer.
[0061] In some embodiments, the first strip-shaped via extends along a second direction, the second direction being perpendicular to the first direction; a projection of the first strip-shaped via in the first direction does not overlap a projection of the first source structure or the first drain structure in the first direction after the etching, and the first strip-shaped via connects the first source structure or the first drain structure that is not etched.
[0062] In some embodiments, the first strip-shaped via is a long strip-shaped conductive structure for connecting the first power rail or the first signal line to the first source / drain structure of the first transistor. The extension direction (the second direction) of the first strip-shaped via is perpendicular to the extension direction (the first direction) of the first active structure.
[0063] In some embodiments, the position of the projection of the first strip-shaped via should be staggered with the first source structure or the first drain structure that is not etched, so as to avoid the risk of short circuit. For example, in the first direction, if the first source structure is partially etched, the position of the first strip-shaped via should avoid the unetched part and only connect to the first drain structure that is not etched.
[0064] In the step 106, a back-end interconnection process is performed on the first dielectric layer to form a first back-end interconnection layer. In the first back-end interconnection layer, the first power rail is connected to the first strip-shaped via; the projection of the first strip-shaped via in the first direction is located inside the projection of the first power rail in the first direction.
[0065] In some embodiments, the back-end interconnection process includes steps such as metal wiring, via filling, interlayer dielectric deposition, etc., which can realize the electrical connection between the first transistors. The first power rail belongs to the metal wiring in the transistor, which is usually made of copper or aluminum as the conductor material and is formed by photolithography and electroplating process.
[0066] In some embodiments, the first strip-shaped via needs to be precisely aligned with the first power rail, so as to ensure that the first strip-shaped via has good electrical contact with the power rail. For example, the orthographic projection of the first strip-shaped via is completely contained in the orthographic projection of the first power rail, so as to ensure that the first strip-shaped via has continuous electrical contact with the first power rail, so that the interconnection contact resistance is smaller.
[0067] In step 107, the substrate is flipped and thinned.
[0068] In some embodiments, flipping refers to turning over the wafer after the preparation of the first transistor on the front side, and then thinning the substrate on the back side to expose the shallow trench isolation structure, so as to subsequently prepare the second transistor on the back side. The thinning process is usually achieved by means of grinding, polishing, etc.
[0069] In some embodiments, before step 107, the preparation method of the stacked transistor can further include: depositing an insulating material on the first back-end interconnection layer to form an insulating layer; and bonding a carrier wafer with the insulating layer. The carrier wafer and the insulating layer can avoid the first transistor from being damaged due to external force during the preparation of the second transistor after the first transistor is turned over.
[0070] In step 108, a second transistor is formed based on a second active structure.
[0071] It can be understood that the preparation method of the second transistor is the same as that of the first transistor.
[0072] In the embodiments of the present application, by constructing the first strip-shaped via extending along a specific direction (i.e., the second direction) in the first dielectric layer, and aligning the first strip-shaped via with the first power rail in the first back-end interconnection layer, so that the orthographic projection of the first strip-shaped via in the first direction is located inside the orthographic projection of the first power rail in the first direction, a more continuous electrical contact is formed; thereby reducing the interconnection resistance inside the stacked transistor, and reducing the voltage drop.
[0073] Further, the second transistor has the same structure as the first transistor, and in the high-density integrated stacked transistor, the integration density can be further increased, and the wiring scheme can be optimized.
[0074] In some possible implementation manners, step 108 can include: based on the second active structure, forming a second front-end layer of the second transistor; the second front-end layer includes a second gate structure, a second source-drain structure, and a second interlayer dielectric layer; the second source-drain structure includes a second source structure and a second drain structure; etching a part of the second source structure or a part of the second drain structure; depositing a dielectric material on the second front-end layer to form a third dielectric layer; forming a second strip-shaped via in the third dielectric layer; the second strip-shaped via extends along a second direction, a projection of the second strip-shaped via on a first direction does not overlap with a projection of the etched second source structure or the second drain structure on the first direction, and the second strip-shaped via is connected to the unetched second drain structure or the second source structure; performing a back-end interconnection process on the third dielectric layer to form a second back-end interconnection layer; a second power supply rail in the second back-end interconnection layer is connected to the second strip-shaped via; and a projection of the second strip-shaped via on the first direction is located inside a projection of the second power supply rail on the first direction.
[0075] In some embodiments, the projection of the second strip-shaped via is staggered (i.e., not overlapped) with the unetched second source structure or the second drain structure.
[0076] In some embodiments, the second strip-shaped via needs to be precisely aligned with the second power supply rail, so as to ensure good electrical contact between the second strip-shaped via and the power supply rail. For example, the projection of the second strip-shaped via is completely contained in the projection range of the second power supply rail, so as to ensure continuous electrical contact between the second strip-shaped via and the second power supply rail, so that the interconnection contact resistance is smaller.
[0077] In some embodiments, there is a direct electrical connection relationship between the power supply rail and its corresponding strip-shaped via (such as the first power supply rail and the first strip-shaped via). The design of the strip-shaped via makes the power supply rail cover the entire strip-shaped via area, so as to ensure the continuity and uniformity of power transmission. Compared with the point-to-point connection mode, this continuous contact mode can reduce the resistance and increase the electrical contact area, which helps to improve the power consumption performance and thermal management performance of the chip.
[0078] In some possible implementation manners, forming the second strip-shaped via in the third dielectric layer includes: forming a second groove in the third dielectric layer by photolithography; depositing a conductive material in the second groove and performing thinning processing to form the second strip-shaped via.
[0079] In some embodiments, the second groove refers to a cavity or a groove formed in the dielectric layer of the second transistor, and the purpose of forming the second groove is to accommodate the subsequent filled conductive material.
[0080] In some embodiments, the second trench is a strip structure extending in a specific direction, and the length of the second trench is consistent with the length of the second active structure in the second direction. By setting the length of the second trench to be the same as the length of the second active structure in the second direction, a good match between the via and the transistor structure can be ensured.
[0081] In some embodiments, a conductive material (such as copper, aluminum, tungsten, etc.) or other material with good conductivity is deposited in the second trench to form a conductive path (i.e., the second strip-shaped via).
[0082] In some possible implementations, the above step 105 can include: forming a first trench in the first dielectric layer by photolithography; depositing a conductive material in the first trench and performing a thinning process to form a first strip-shaped via.
[0083] In some embodiments, the first trench refers to a cavity or groove formed in the dielectric layer of the first transistor, and the purpose of forming the first trench is to accommodate the subsequently filled conductive material.
[0084] In some embodiments, the first trench is a strip structure extending in a specific direction, and the length of the first trench is consistent with the length of the first active structure in the second direction. By setting the length of the first trench to be the same as the length of the first active structure in the first direction, a good match between the via and the transistor structure can be ensured.
[0085] In some embodiments, the position and shape of the trench can be accurately defined on the first dielectric layer by photolithography technology, thereby achieving control of the via position. Photolithography can ensure that the trench has high precision and consistency, which helps to improve the yield of subsequent processes.
[0086] In some embodiments, a conductive material (such as copper, aluminum, tungsten, etc.) or other material with good conductivity is deposited in the first trench to form a conductive path (i.e., the first strip-shaped via).
[0087] In some embodiments, the process of depositing a conductive material can be carried out by physical vapor deposition (PVD), chemical vapor deposition (CVD), or electroplating, etc., and the specific choice depends on the material and process conditions used.
[0088] In some embodiments, the thinning process is a process for removing excess material and planarizing the surface, which usually adopts chemical mechanical polishing (CMP) technology. Through the thinning process, the conductive material in the trench can be made to have the same height as the surrounding first dielectric layer, thereby forming a flat surface for subsequent interconnection processes. In addition, the thinning process can also improve the uniformity and electrical performance of the via.
[0089] In the embodiments of the present application, the first strip-shaped via hole has a narrow width and a long length, and is suitable for large-area connection between the first power supply rail and the first source-drain structure. Compared with the point-shaped via hole, the first strip-shaped via hole can provide smaller resistance and lower IR drop, and these characteristics of the first strip-shaped via hole are beneficial to improve the overall performance of the circuit. In addition, the long strip-shaped structure of the first strip-shaped via hole can reduce the number of masks, simplify the process flow, and improve the production efficiency.
[0090] In some possible implementations, the step 106 can include: depositing a dielectric material on the first dielectric layer to form a second dielectric layer; and forming the first power supply rail and the plurality of first signal lines in the second dielectric layer; and the first strip-shaped via hole is connected to the first power supply rail.
[0091] In some embodiments, the main role of the second dielectric layer is to provide a planarized surface for subsequent wiring and serve as an insulating substrate for the first power supply rail and the first signal lines.
[0092] In some embodiments, the first signal line refers to a metal line formed in a subsequent interconnection process and used for transmitting an electrical signal. The first signal line is mainly responsible for the transmission of data or control signals of the first transistor, and usually has a lower current load requirement and a higher frequency response characteristic.
[0093] It should be noted that in the subsequent process, the first subsequent interconnection layer can include a plurality of dielectric layers, and each dielectric layer has metal wiring. In the embodiments of the present application, the second dielectric layer belongs to the M0 (metal 0) layer in the first subsequent interconnection layer, and other dielectric layers can also be arranged on the M0 layer, which is not limited in the embodiments of the present application.
[0094] In some embodiments, the first power supply rail is a metal line used for transmitting a power supply voltage, and is usually located in the first subsequent interconnection layer close to the first source-drain structure to provide stable power supply connection for the first transistor. The first signal line is a metal line used for transmitting data or control signals.
[0095] In some embodiments, the process of forming the first power supply rail and the plurality of first signal lines in the second dielectric layer includes steps such as photolithography, etching, and metal deposition. Through accurate patterning process, the layout of the first power supply rail and the first signal line is realized in the same dielectric layer at the same time, thereby improving the overall interconnection efficiency and space utilization.
[0096] In some embodiments, the first strip-shaped via hole can be connected to the first power supply rail to realize direct connection between the first power supply rail and the first source-drain structure.
[0097] In some possible implementations, the first power supply rail and the second power supply rail are symmetrically arranged in the first direction.
[0098] In some embodiments, the first power rail corresponds to a power supply path of the first transistor, and the second power rail corresponds to a power supply path of the second transistor.
[0099] In some embodiments, the symmetric arrangement refers to the first power rail and the second power rail having the same width, length and position distribution in the first direction, which helps to achieve uniform current distribution, reduce voltage drop, and simplify wiring design.
[0100] In some possible implementations, the first power rail and the second power rail are asymmetrically arranged in the first direction.
[0101] In some embodiments, the asymmetric arrangement allows the first power rail and the second power rail to have different sizes and positions, which is suitable for scenarios where space is limited or local performance needs to be optimized, and improves wiring flexibility.
[0102] In the embodiments of the present application, by selecting symmetric or asymmetric arrangement of the first power rail and the second power rail in the first direction, the layout of the power supply network can be optimized without increasing the process complexity, and the overall performance of the stacked transistor structure can be improved. In addition, in the asymmetric scenario, the position and shape of the first power rail and the second power rail can also be adjusted according to the specific application scenario to meet the power consumption and signal integrity requirements of different circuit modules, thereby enhancing the functional diversity and scalability of the chip.
[0103] In an example, taking a fin field effect transistor as an example, the preparation method of the stacked transistor described in the embodiments of the present application is explained, Figure 2 is a first design layout of the stacked transistor in the embodiments of the present application; Figures 3 to 5 is a flowchart of the preparation method of the stacked transistor in the embodiments of the present application. In combination with Figure 2 and Figures 3 to 5 , the preparation method of the stacked transistor can include:
[0104] Step 1: Forming a first active structure 111 and a second active structure 121 on a substrate 21; forming a shallow trench isolation structure 22; based on the first active structure 111, forming a first gate structure 112, a first source / drain epitaxial layer 113, a first interlayer dielectric layer 114 and a first source / drain metal 115 in the first transistor 11. Among them, the first source metal in the first source / drain metal 115 is etched by a part, and the first drain metal 1151 is not etched (see Figure 3 ).
[0105] Step 2: Depositing a dielectric material on the first front layer to form a first dielectric layer 31; performing photolithography on the first dielectric layer 31 to form a first trench, and depositing a conductive material in the first trench and on the first dielectric layer (see Figure 4 ).
[0106] Step 3: Thin the conductive material until it reaches the same height as the first dielectric layer 31, forming the first strip-shaped via 13; perform subsequent processing on the first dielectric layer 31 to form the first subsequent interconnect layer 116. The first strip-shaped via 13 is connected to the first power rail 1161 in the first subsequent interconnect layer 116 (see...). Figure 5 ).
[0107] Step 4: Deposit an insulating material on the first back-end interconnect layer 116 to form an insulating layer 15, and bond the wafer 16 to the insulating layer 15; flip the wafer, and then thin the substrate 21 to expose the shallow trench isolation structure 22; etch the shallow trench isolation structure 22 to a preset height until the second active structure 121 is exposed; based on the second active structure 121, form the second gate structure 122, the second source / drain epitaxial layer 123, the second interlayer dielectric layer 124, and the second source / drain metal 125 in the second transistor 12. In this process, a portion of the second source metal in the second source / drain metal 125 is etched away, while the second drain metal 1251 remains unetched. A dielectric material is deposited on the second front-end layer to form a third dielectric layer 32. Photolithography is performed on the third dielectric layer 32 to form a second trench. Conductive material is deposited in the second trench and on the second dielectric layer. The conductive material is thinned until it reaches the same height as the third dielectric layer 32, forming a second via 14. Back-end processing is performed on the third dielectric layer 32 to form a second back-end interconnect layer 126. The second via 14 is connected to the second power rail 1261 in the second back-end interconnect layer 126 (see [reference]). Figure 6 ).
[0108] This completes the stacking of transistors.
[0109] This application provides a stacked transistor, which is prepared by the above method. The stacked transistor includes: a first transistor; a first source-drain structure of the first transistor and a first power rail of the first transistor are connected through a first strip-shaped via; the orthographic projection of the first strip-shaped via in a first direction is located inside the orthographic projection of the first power rail in the first direction; a second transistor; a second source-drain structure of the second transistor and a second power rail of the second transistor are connected through a second strip-shaped via; the orthographic projection of the second strip-shaped via in a first direction is located inside the orthographic projection of the second power rail in the first direction.
[0110] In some embodiments, Figure 6 This is a schematic diagram of a first structure of stacked transistors in an embodiment of this application. See also... Figure 6 As shown, the first transistor 11 and the second transistor 12 are stacked in a first direction. The first power rail 1161 and the second power rail 1261 are symmetrically arranged.
[0111] In some embodiments, the first transistor and the second transistor need to use different design layouts respectively in the case of asymmetric arrangement of the first power rail and the second power rail. Figure 7 A second design layout of a stacked transistor in an embodiment of the present application; Figure 8 A second structural schematic diagram of a stacked transistor in an embodiment of the present application. It should be noted that, Figure 8 The preparation process of the first transistor in the stacked transistor shown uses Figure 6 The layout shown, and the preparation process of the second transistor uses Figure 7 The layout shown. Referring to Figure 8 As shown, the first transistor 11 and the second transistor 12 are arranged in a stacked manner in the first direction. The first power rail 1161 and the second power rail 1261 are asymmetrically arranged.
[0112] In an embodiment of the present application, the asymmetric arrangement of the first power rail and the second power rail makes the metal wiring inside the transistor more flexible.
[0113] The stacked transistor provided in an embodiment of the present application can be detected by detection analysis instruments, such as a scanning electron microscope (SEM), a transmission electron microscope (TEM), a scanning transmission electron microscope (STEM), etc. For example, taking the TEM as an example, it can be observed in the TEM section that the stacked transistor has a first strip-shaped via hole and a second strip-shaped via hole in a long groove shape.
[0114] An embodiment of the present application provides a semiconductor device, which can include a plurality of stacked transistors as shown in Figure 6 or Figure 8 The plurality of stacked transistors are electrically connected through a back-end interconnection layer, signal transmission is performed through the back-end interconnection layer, and a functional circuit is constructed.
[0115] An embodiment of the present application provides an electronic device, which includes a circuit board and a semiconductor device as described above, the semiconductor device being mounted on the circuit board and electrically connected to the circuit board.
[0116] In some embodiments, the electronic device refers to a device combined by various electronic elements, which can complete a specific function. After the semiconductor device is arranged on the circuit board, it can be used as a main memory or a cache, and can support high-speed data reading and writing and complex computing tasks.
[0117] In some embodiments, the electronic device can include, but is not limited to: mobile communication devices such as mobile phones, tablets, 5G / 6G base stations; computing devices such as personal computers, laptops, servers, data center computing units; consumer electronics such as smart wearable devices, digital cameras, game consoles; Internet of Things devices or automotive electronic systems.
[0118] The above merely illustrates the embodiments of the present application, but should not be used to limit the protection scope of the present application. Any modification, equivalent replacement and improvement made within the spirit and scope of the present application shall be included in the protection scope of the present application.
Claims
1. A method for fabricating stacked transistors, characterized in that, include: A first active structure and a second active structure are formed on a substrate stacked in a first direction; Based on the first active structure, a first front-end layer of the first transistor is formed; The first front-end layer includes a first gate structure, a first source / drain structure, and a first interlayer dielectric layer; wherein the first source / drain structure includes a first source structure and a first drain structure; Etch a portion of the first source structure or a portion of the first drain structure; A dielectric material is deposited on the first front layer to form a first dielectric layer; A first strip-shaped via is formed in the first dielectric layer; the first strip-shaped via extends along a second direction, which is perpendicular to the first direction; the orthographic projection of the first strip-shaped via in the first direction does not coincide with the orthographic projection of the etched first source structure or the etched first drain structure in the first direction; the first strip-shaped via connects to the unetched first drain structure or the first source structure. A back-end interconnect process is performed on the first dielectric layer to form a first back-end interconnect layer; a first power rail in the first back-end interconnect layer is connected to the first strip via; the orthographic projection of the first strip via in the first direction is located inside the orthographic projection of the first power rail in the first direction. The substrate is then poured and thinned. A second transistor is formed based on the second active structure.
2. The method according to claim 1, characterized in that, The process of forming a first strip-shaped through-hole in the first dielectric layer includes: A first trench is formed in the first dielectric layer by photolithography; Conductive material is deposited in the first trench and then thinned to form the first strip-shaped through hole.
3. The method according to claim 1, characterized in that, The step of performing a back-end interconnect process on the first dielectric layer to form a first back-end interconnect layer includes: A dielectric material is deposited on the first dielectric layer to form a second dielectric layer; The first power rail and a plurality of first signal lines are formed in the second dielectric layer.
4. The method according to claim 1, characterized in that, The formation of the second transistor based on the second active structure includes: Based on the second active structure, a second front-end layer is formed for the second transistor; the second front-end layer includes a second gate structure, a second source / drain structure, and a second interlayer dielectric layer; wherein the second source / drain structure includes a second source structure and a second drain structure; Etch a portion of the second source structure or a portion of the second drain structure; A dielectric material is deposited on the second front layer to form a third dielectric layer; A second strip-shaped via is formed in the third dielectric layer; the second strip-shaped via extends along the second direction, and the orthographic projection of the second strip-shaped via in the first direction does not coincide with the orthographic projection of the etched second source structure or the etched second drain structure in the first direction; the second strip-shaped via connects to the unetched second drain structure or the second source structure. A back-end interconnect process is performed on the third dielectric layer to form a second back-end interconnect layer; the second power rail in the second back-end interconnect layer is connected to the second strip via; the orthographic projection of the second strip via in the first direction is located inside the orthographic projection of the second power rail in the first direction.
5. The method according to claim 4, characterized in that, The formation of the second strip-shaped through-hole in the third dielectric layer includes: A second trench is formed in the third dielectric layer by photolithography; Conductive material is deposited in the second trench and then thinned to form the second strip-shaped through hole.
6. The method according to claim 1, characterized in that, The first power rail and the second power rail of the second transistor are symmetrically arranged in the first direction.
7. The method according to claim 1, characterized in that, The first power rail and the second power rail of the second transistor are asymmetrically arranged in the first direction.
8. A stacked transistor, characterized in that, The stacked transistor is fabricated using the method described in any one of claims 1 to 7, wherein the stacked transistor comprises: A first transistor; the first source-drain structure of the first transistor and the first power rail of the first transistor are connected through a first strip-shaped through-hole; the orthographic projection of the first strip-shaped through-hole in a first direction is located inside the orthographic projection of the first power rail in the first direction; The second transistor; the second source-drain structure of the second transistor and the second power rail of the second transistor are connected through a second strip-shaped via; the orthographic projection of the second strip-shaped via in the first direction is located inside the orthographic projection of the second power rail in the first direction.
9. A semiconductor device, characterized in that, include: Multiple stacked transistors as described in claim 8; Multiple stacked transistors are electrically connected through a back-end interconnect layer to form a functional circuit.
10. An electronic device, characterized in that, include: Circuit board; The semiconductor device as claimed in claim 9; the semiconductor device is mounted on the circuit board and electrically connected to the circuit board.