Semiconductor device including stressor layer and method of forming same

Abstract

Semiconductor devices including stressor layers and methods of forming the same are provided. The semiconductor device includes a substrate, a source / drain region on the substrate, a channel structure on the substrate and electrically connected to the source / drain region, a gate structure on the substrate and at least partially surrounding the channel structure, and a stressor layer in contact with an upper surface of the source / drain region and configured to apply a compressive stress or a tensile stress to the source / drain region.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to the field of semiconductor devices, and more particularly, to semiconductor devices including a stressor layer and methods of forming the same. BACKGROUND

[0002] Integrated circuit (IC) devices, chips, and / or dies can receive power and data signals from one or more external sources (e.g., power sources and data sources). Some IC devices can receive power and data signals via front-side conductive structures, which can provide a power distribution network (PDN). For example, an IC device can include a front-side power distribution network (FSPDN) having one or more components formed during a back-end-of-line (BEOL) process, and conductive structures for data signals can be located on the same side of the IC device as the FSPDN. IC devices can include various transistor structures, including, for example, two-dimensional (2D) planar structures, fin field effect transistors (FinFETs), gate-all-around transistors, multi-bridge-channel FETs (MBCFETs), and stacked transistors (e.g., three-dimensional (3D) stacked transistors).

[0003] More recently, backside PDNs (BSPDNs) have also been developed, in which the backside of an IC device is used as a PDN. In BSPDN structures, power rails can be formed on the backside of a semiconductor chip, IC device, or wafer (generally referred to herein as a semiconductor device), rather than on the frontside thereof. As such, power rails can be on the side of the semiconductor structure opposite active components (e.g., transistors) of the IC device (e.g., one side of a substrate of the IC device). Moreover, conductive structures for data signals can be on the frontside of the semiconductor device, so the BSPDN and conductive structures for data signals can be on opposite sides of the semiconductor device. BSPDN structures can improve power rail effectiveness, voltage drop (i.e., IR drop), high power delivery performance, and further scaling of standard cell height.

[0004] During fabrication of an IC device, source / drain regions and channel structures can undergo various processes, which can cause variations in strain within the source / drain regions and channel structures. These variations can cause carrier mobility in the channel structures to degrade, which can negatively impact performance of the IC device. Accordingly, methods of improving carrier mobility in IC devices are being investigated. SUMMARY

[0005] According to some embodiments, a semiconductor device includes a substrate, a source / drain region on the substrate, a channel structure on the substrate and electrically connected to the source / drain region, a gate structure on the substrate and at least partially surrounding the channel structure, and a stressor layer in contact with an upper surface of the source / drain region and configured to apply compressive or tensile stress to the source / drain region.

[0006] In some embodiments, the stressor layer extends into the upper surface of the source / drain region.

[0007] In some embodiments, a first distance between a lower surface of the stressor layer and an upper surface of the substrate is greater than a second distance between an upper surface of the channel structure and the upper surface of the substrate.

[0008] In some embodiments, the stressor layer includes a first portion in the source / drain region and a second portion on the upper surface of the source / drain region, a first width of the first portion of the stressor layer in a direction parallel to the upper surface of the substrate is less than a second width of the second portion of the stressor layer in the direction.

[0009] In some embodiments, the stressor layer does not overlap the gate structure in a direction perpendicular to the upper surface of the substrate.

[0010] In some embodiments, the stressor layer overlaps the gate structure and the channel structure in a direction perpendicular to the upper surface of the substrate.

[0011] In some embodiments, the semiconductor device further includes a backside contact structure extending in the substrate and electrically connected to the source / drain region, and the stressor layer overlaps the backside contact structure in a direction perpendicular to the upper surface of the substrate.

[0012] In some embodiments, the source / drain region is a first source / drain region, the stressor layer is a first stressor layer, and the semiconductor device further includes a second source / drain region adjacent to the first source / drain region, the channel structure between the second source / drain region and the first source / drain region, and a second stressor layer in contact with an upper surface of the second source / drain region and configured to apply compressive or tensile stress to the second source / drain region.

[0013] In some embodiments, the second stressor layer is spaced apart from the first stressor layer, the gate structure between the second stressor layer and the first stressor layer.

[0014] In some embodiments, the source / drain region is a first source / drain region, the semiconductor device further includes a second source / drain region adjacent to the first source / drain region, the channel structure is between the second source / drain region and the first source / drain region, and the stressor layer is in contact with an upper surface of the second source / drain region and is configured to apply a compressive stress or a tensile stress to the second source / drain region.

[0015] In some embodiments, the stressor layer continuously extends from an upper surface of the first source / drain region to an upper surface of the second source / drain region.

[0016] In some embodiments, there is no stressor layer on an outer lateral surface of the source / drain region.

[0017] In some embodiments, the stressor layer is configured to apply a compressive stress to the source / drain region when the source / drain region includes n-type impurities, and the stressor layer is configured to apply a tensile stress to the source / drain region when the source / drain region includes p-type impurities.

[0018] According to some embodiments, a semiconductor device includes a substrate, a first source / drain region and a second source / drain region spaced apart from each other on the substrate, a channel structure between the first source / drain region and the second source / drain region, a gate structure on the substrate and at least partially surrounding the channel structure, a backside contact structure extending in the substrate and electrically connected to the first source / drain region or the second source / drain region, and a stressor layer extending into an upper surface of the first source / drain region and configured to apply a compressive stress or a tensile stress to the first source / drain region, the channel structure including a plurality of channel regions spaced apart from each other in a direction perpendicular to an upper surface of the substrate.

[0019] In some embodiments, the stressor layer is a first stressor layer, and the semiconductor device further includes a second stressor layer extending into an upper surface of the second source / drain region and spaced apart from the first stressor layer, the second stressor layer configured to apply a compressive stress or a tensile stress to the second source / drain region.

[0020] In some embodiments, the stressor layer extends into an upper surface of the second source / drain region and is configured to apply a compressive stress or a tensile stress to the second source / drain region.

[0021] In some embodiments, the stressor layer overlaps the backside contact structure in the direction.

[0022] According to some embodiments, a method of forming a semiconductor device includes forming a stressor layer on an upper surface of a source / drain region and in contact with the source / drain region, wherein the stressor layer applies a compressive stress or a tensile stress to the source / drain region.

[0023] In some embodiments, forming the stressor layer includes forming a recess in an upper surface of the source / drain region, and forming the stressor layer in the recess.

[0024] In some embodiments, forming the stressor layer includes epitaxially growing the stressor layer on the source / drain region.

[0025] In some embodiments, forming the stressor layer includes depositing the stressor layer on an upper surface of the source / drain region using a deposition process.

[0026] In some embodiments, the method further includes forming a placeholder layer, removing the placeholder layer using an etching process, and forming the backside contact structure on a lower surface of the source / drain region in a space left after removing the placeholder layer.

[0027] Other devices, apparatuses, and / or methods according to example embodiments will become readily apparent from the following drawings and detailed description, some of which will be described in conjunction with the provided flow charts. All these additional embodiments are intended to be included within the scope of this specification, are within the scope of the disclosure, and are protected by the following claims. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1A is a plan view or layout view showing a semiconductor device according to some embodiments.

[0029] Figure 1B and Figure 1C is a cross-sectional view taken along line A-A' of Figure 1A according to some embodiments.

[0030] Figure 2A and Figure 2B are simplified schematic diagrams showing a source / drain region and a channel structure of a semiconductor device according to some embodiments.

[0031] Figure 3 is a flow chart showing a method of forming a semiconductor device according to some embodiments.

[0032] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H and Figure 4I are cross-sectional views showing a method of forming a semiconductor device according to some embodiments.

[0033] Figure 5 is a cross-sectional view showing a method of forming a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0034] The BSPDN structure can include a power delivery network that includes one or more power rails on (in) the backside of the semiconductor device. Different ways of connecting from the frontside to the backside can include, for example, front via backside power rails (FV-BPR) and direct backside contact (DBC). DBC can be more efficient than other ways of connecting the frontside to the backside in terms of process capability and size limitations.

[0035] Channel stress can help improve carrier mobility in a channel structure of a semiconductor device, and thus can provide performance advantages for the semiconductor device. For example, improved carrier mobility in the channel structure can improve switching speed and / or reduce power consumption of the semiconductor device. By introducing stress to the channel structure of the semiconductor device, the strain within the channel structure can be altered to optimize carrier mobility. For example, in a semiconductor device that includes one or more n-type transistors (e.g., n-type MOSFETs (NMOS)), tensile stress introduced in the channel structure can help improve electron mobility. In a semiconductor device that includes one or more p-type transistors (e.g., p-type MOSFETs (PMOS)), compressive stress introduced in the channel structure can help improve hole mobility.

[0036] During fabrication of a semiconductor device, the source / drain regions and channel structure can undergo various processes that can cause changes in the strain within the source / drain regions and channel structure. These changes can be exacerbated in semiconductor devices that include BSPDN structures and / or channel structures implemented as nanosheets or nanowires due to the additional processes associated therewith. As a result, carrier mobility in the channel structure can deteriorate, thereby negatively impacting performance of the semiconductor device. The orientation of the substrate (i.e., wafer) and channel structure can be controlled during fabrication to help improve carrier mobility, but these techniques can not be sufficient to offset the negative impact on carrier mobility caused by changes in the strain within the source / drain regions and channel structure.

[0037] According to example implementations herein, a semiconductor (e.g., integrated circuit) device is provided that includes one or more stressor layers on an upper surface of a source / drain region (i.e., on the frontside) to induce stress in a channel structure. As a result, the strain within the channel structure can be better controlled to improve carrier mobility. In some implementations, the stressor layers can extend into the upper surface of the source / drain region, thereby allowing the stressor layers to induce a greater degree of stress on the channel structure. Some examples of implementations of the present disclosure are described in greater detail with reference to the accompanying drawings.

[0038] Figure 1A is a plan view or layout view showing a semiconductor device according to some implementations. Figure 1B andFigure 1C It is based on some implementation methods Figure 1A A cross-sectional view taken by line A-A'. Figure 1A The middle part is omitted Figure 1B and Figure 1C Some layers / structures are shown to help illustrate the example implementation.

[0039] refer to Figure 1A and Figure 1B The semiconductor device 100 may include a substrate 101 (also referred to as a back-side insulating layer) and a transistor structure TS (also referred to as a transistor) on the upper surface (or front side) S1 of the substrate 101. The substrate 101 may extend in a first direction D1 (also referred to as a first horizontal direction or X direction) and a second direction D2 (also referred to as a second horizontal direction or Y direction). The first direction D1 and the second direction D2 may be parallel to the surface of the substrate 101 (e.g., the upper surface S1). In some embodiments, the first direction D1 may be perpendicular to the second direction D2.

[0040] In some embodiments, substrate 101 may include or be formed of an insulating material, such as silicon oxide, silicon oxide nitride, silicon nitride, silicon carbon nitride, silicon boron nitride, and / or a low-k dielectric material. Low-k dielectric materials may include, for example, fluorine-doped silicon oxide, organosilicon glass, carbon-doped oxide, porous silica, porous organosilicon glass, spin-on organic polymer dielectrics, and / or spin-on silicon-based polymer dielectrics. In some embodiments, substrate 101 may include or be a semiconductor material, such as Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, and / or InP. For example, substrate 101 may be an insulating layer, a bulk substrate (e.g., a bulk silicon wafer), and / or a semiconductor-on-insulator (SOI) substrate. The thickness of substrate 101 in the third direction D3 (also referred to as the vertical direction or Z direction) may be, for example, in the range of (about) 50 nanometers (nm) to 100 nm, but is not limited thereto. In some implementations, the third direction D3 may be perpendicular to the first direction D1 and / or the second direction D2. The third direction D3 may be perpendicular to the surface of the substrate 101 (e.g., the upper surface S1).

[0041] A first interlayer 122 may be provided on the upper surface S1 of the substrate 101. In some embodiments, the first interlayer 122 may extend between the substrate 101 and the transistor structure TS and may contact the upper surface S1 of the substrate 101 and the transistor structure TS. For example, the first interlayer 122 may include an insulating material (e.g., silicon oxide, silicon oxide nitride, silicon nitride, silicon carbon nitride, and / or a low-k material).

[0042] Each of the transistor structures TS can include a gate structure 102 and a channel structure 104 extending between source / drain regions 108 (in a first direction D1). The gate structure 102 can be over the channel structure 104 and can overlap the channel structure 104 in a third direction D3. As used herein, “element A overlaps element B in direction X” (or similar language) means that there is at least one straight line extending in direction X and intersecting both elements A and B. For example, the gate structure 102 can at least partially surround the channel structure 104. In some embodiments, the channel structure 104 can extend in the first direction D1 and the gate structure 102 can extend in a second direction D2.

[0043] In some embodiments, each of the channel structures 104 can include a plurality of channel regions 110 stacked in the third direction D3, which can be spaced apart from each other in the third direction D3. For example, in some embodiments, the transistor structures TS can be nanosheet transistors including a stack of nanosheet layers in each channel structure 104. Although Figure 1B Although each channel structure 104 is shown to include three channel regions 110, the present disclosure is not limited thereto. In some embodiments, each channel structure 104 can include fewer than three channel regions 110 or more than three channel regions 110.

[0044] The semiconductor device 100 can include a plurality of gate structures 102 extending in the second direction D2 (i.e., longitudinally) and spaced apart from each other in the first direction D1. Each gate structure 102 can include a gate electrode 112, a gate insulator 114, and a gate cap layer 116.

[0045] The gate electrode 112 can include a single layer or multiple layers. In some embodiments, the gate electrode 112 can include a metal layer or a material including, for example, tungsten (W), aluminum (Al), copper (Cu), molybdenum (Mo), cobalt (Co), and / or ruthenium (Ru), and can additionally include a work function layer (e.g., a TiN layer, a TaN layer, a TiAl layer, a TiC layer, a TiAlC layer, a TiAlN layer, and / or a WN layer). For example, the work function layer can separate the metal layer from the gate insulator 114. In some embodiments, the gate electrodes 112 included in different gate structures 102 can include the same material.

[0046] A gate insulator 114 may extend between the gate electrode 112 and the channel structure 104. More specifically, the gate insulator 114 may contact and physically separate the gate electrode 112 and the channel structure 104 (including the channel region 110). The gate insulator 114 may comprise a single layer or multiple layers (e.g., a silicon oxide layer and / or a high-k dielectric material layer). For example, the high-k dielectric material layer may comprise Al2O3, HfO2, ZrO2, HfZrO4, TiO2, Sc2O3, Y2O3, La2O3, Lu2O3, Nb2O5, and / or Ta2O5.

[0047] The gate cap layer 116 may be located on the upper surface of the gate electrode 112. That is, the gate cap layer 116 may be located on the uppermost portion of the gate electrode 112. The gate cap layer 116 may comprise, for example, silicon oxide, silicon nitride, silicon carbon nitride, and / or a low-k material. In some embodiments, the gate cap layer 116 may comprise a material different from the upper gate insulating spacer 118 and / or the lower gate insulating spacer 120, but this disclosure is not limited thereto.

[0048] In some embodiments, the gate dicing layer 132 (see Figure 1A A portion of each gate electrode 112 can be separated in the second direction D2. For example, a gate cleaving layer 132 can extend in the first direction D1 to separate a portion of each gate electrode 112 in the second direction D2. The gate cleaving layer 132 may include an insulating material (e.g., silicon oxide, silicon nitride, silicon carbon nitride, silicon boron nitride, and / or a low-k material). In some embodiments, the gate cleaving layer 132 may be omitted.

[0049] Each of the transistor structures TS may further include a pair of source / drain regions 108 spaced apart from each other in the first direction D1. Each transistor structure TS may include a gate structure 102 and a channel structure 104 provided between the pair of source / drain regions 108. The source / drain regions 108 may contact opposite side surfaces of the channel structure 104 spaced apart from each other in the first direction D1.

[0050] The channel structure 104 can include a semiconductor material (e.g., Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, and / or InP). That is, each of the channel regions 110 can include a semiconductor material (e.g., Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, and / or InP). In some implementations, the channel regions 110 can be nanosheets that can have a thickness in the third direction D3 of, for example, in the range of (about) 1 nm to 100 nm, or can be nanowires that can have a circular cross-section with a diameter of, for example, in the range of (about) 1 nm to 100 nm. When the channel structure 104 includes a nanosheet or a nanowire, the gate structure 102 can extend around the channel structure 104 on multiple sides of the channel structure 104 (i.e., can at least partially surround the channel structure 104).

[0051] Each of the source / drain regions 108 can include a semiconductor layer (e.g., a silicon (Si) layer and / or a silicon germanium (SiGe) layer), and can additionally include a dopant in the semiconductor layer. For example, each of the source / drain regions 108 can include an epitaxial semiconductor layer with a dopant (i.e., an impurity) therein.

[0052] In some implementations, the transistor structure TS can be a three-dimensional (3D) field effect transistor (FET), such as a multi-bridge channel FET (MBCFET). In some implementations, the transistor structure TS can have a different structure than the illustrated structure. For example, the transistor structure TS can be a gate-all-around FET (GAAFET) or a fin FET that includes a single channel structure.

[0053] Stressor layers 134 can be provided on upper surfaces of source / drain regions 108, respectively, and can be in contact with source / drain regions 108. Stressor layers 134 can apply compressive or tensile stress to respective ones of source / drain regions 108, and thus stressor layers 134 can also be referred to as mechanical stressor layers. In some embodiments, stressor layers 134 can include a different material than source / drain regions 108. For example, stressor layers 134 can include a dielectric material (e.g., SiOC, SiON, SiCN, SiN, TOSZ, TEOS, ALD oxide, FCVD oxide, HDP oxide, and / or PEOX oxide), a metallic material (e.g., tungsten (W) and / or molybdenum (Mo)), or a combination thereof. In some embodiments, stressor layers 134 can include an epitaxial semiconductor layer. For example, stressor layers 134 can include an epitaxial semiconductor layer having a higher Ge concentration than source / drain regions 108 (e.g., in the range of (about) 75 to 100 atomic percent (at%) of Ge), although the present disclosure is not limited thereto. Although each stressor layer 134 is shown as a single layer, in some embodiments, each stressor layer 134 can include multiple layers. Figure 1B Although each stressor layer 134 is shown as a single layer, in some embodiments, each stressor layer 134 can include multiple layers.

[0054] In some embodiments, each stressor layer 134 can extend into an upper surface of a respective source / drain region 108, which can allow stressor layers 134 to exert a greater degree of stress on source / drain regions 108. Thus, a lower portion of each stressor layer 134 can be in source / drain regions 108.

[0055] The stressor layers 134 can not overlap the channel structures 104 in the first direction Dl. For example, a first distance between a lower surface of each stressor layer 134 and the upper surface SI of the substrate 101 can be greater than a second distance between an upper surface 104U of each channel structure 104 and the upper surface SI of the substrate 101. In other words, the stressor layers 134 can extend into the source / drain regions 108 in the third direction D3 to a depth above the upper surface 104U of each channel structure 104 relative to the upper surface SI of the substrate 101. If the stressor layers 134 extend too deep into the source / drain regions 108, they can significantly reduce the volume (or area) of the source / drain regions 108, thereby negatively impacting carrier mobility and / or compromising the integrity of the electrical connection between the source / drain regions 108 and the channel structures 104. By providing each stressor layer 134 such that it extends into the upper surface of the respective source / drain region 108 without overlapping the channel structure 104 in the horizontal direction (i.e., the first direction Dl), the stressor layers 134 can exert a greater degree of stress on the source / drain regions 108 without substantially reducing their volume (or area).

[0056] Each stressor layer 134 can include a first portion in the source / drain region 108 and a second portion on the upper surface of the source / drain region 108. A first width of the first portion (in the first direction Dl) of each stressor layer 134 can be less than a second width of the second portion (in the first direction Dl) of each stressor layer 134. For example, each stressor layer 134 can have a 'T' shape in cross-section, although the present disclosure is not limited thereto. In some embodiments, each stressor layer 134 can extend over (e.g., can cover and / or overlap) the entire upper surface of the respective source / drain region 108. For example, each stressor layer 134 can extend across the entire upper surface of the respective source / drain region 108 in the first direction Dl and / or the second direction D2, although embodiments are not limited thereto. By providing the stressor layers 134 such that the first portion of the stressor layers 134 in the source / drain region 108 is narrower than the second portion of the stressor layers 134 on the upper surface of the source / drain region 108, the stressor layers 134 can exert a greater degree of stress on the source / drain regions 108 without substantially reducing their volume (or area).

[0057] The outer lateral surfaces of the source / drain regions 108 can be free of the stressor layers 134 thereon. By providing the stressor layers 134 such that the stressor layers 134 extend into the source / drain regions 108 without extending over their outer lateral surfaces, the stressor layers 134 can exert a greater degree of stress on the source / drain regions 108 without negatively impacting the electrical connection between the source / drain regions 108 and the channel structures 104.

[0058] The stressor layers 134 can be spaced apart from each other (e.g., in the first direction Dl) over the source / drain regions 108. For example, the stressor layers 134 can be spaced apart from each other with at least one gate structure 102 therebetween. The stressor layers 134 can overlap the gate structures 102 in the first direction Dl. The stressor layers 134 can not overlap the gate structures 102 in the third direction D3. In other words, the stressor layers 134 can not extend onto the upper surfaces of the gate structures 102. The upper surfaces of the stressor layers 134 can be substantially coplanar with each other. In some embodiments, the upper surfaces of the stressor layers 134 can be substantially coplanar with the upper surfaces of the gate structures 102 (e.g., with the upper surfaces of the gate cap layers 116).

[0059] When the transistor structure TS is an n-type transistor (e.g., NMOS), the stressor layers 134 can apply compressive stress to the source / drain regions 108, and thus the stressor layers 134 can be referred to as compressive stressor layers. In other words, when the source / drain regions 108 include n-type impurities (e.g., phosphorus (P), arsenic (As), antimony (Sb), etc.), the stressor layers 134 can apply compressive stress to the source / drain regions 108. When the transistor structure TS is a p-type transistor (e.g., PMOS), the stressor layers 134 can apply tensile stress to the source / drain regions 108, and thus the stressor layers 134 can be referred to as tensile stressor layers. In other words, when the source / drain regions 108 include p-type impurities (e.g., boron (B), gallium (Ga), indium (In), etc.), the stressor layers 134 can apply tensile stress to the source / drain regions 108. As will be discussed in more detail below, the application of stress to the source / drain regions 108 can change the strain within the source / drain regions 108, which in turn can result in inducing a desired stress in the channel structure 104, thereby enhancing the desired stress in the channel structure 104. As a result, the carrier mobility in the channel structure 104 can be improved. Figure 2A and Figure 2B As discussed in more detail below, the application of stress to the source / drain regions 108 can change the strain within the source / drain regions 108, which in turn can result in inducing a desired stress in the channel structure 104, thereby enhancing the desired stress in the channel structure 104. As a result, the carrier mobility in the channel structure 104 can be improved.

[0060] The semiconductor device 100 can further include an upper gate insulating spacer 118 and a lower gate insulating spacer 120. The upper gate insulating spacer 118 can be between the gate electrode 112 and the source / drain regions 108 (in the first direction Dl), and can also be between the gate electrode 112 and the stressor layers 134 (in the first direction Dl). For example, the upper gate insulating spacer 118 can be between the upper portion of the gate electrode 112 and the upper portion of the source / drain regions 108. The upper gate insulating spacer 118 can extend over the side surfaces of the gate electrode 112, the gate insulator 114, the gate cap layer 116, the source / drain regions 108, and the stressor layers 134.

[0061] The lower gate insulating spacers 120 can be between the gate electrodes 112 and the source / drain regions 108 (in the first direction Dl). For example, the lower gate insulating spacers 120 can be between lower portions of the gate electrodes 112 and lower portions of the source / drain regions 108. The lower gate insulating spacers 120 can extend on side surfaces of the gate electrodes 112, the gate insulators 114, and the source / drain regions 108. Portions of the lower gate insulating spacers 120 can be between adjacent ones of the channel regions 110 (in the third direction D3) and can also be between a lowermost one of the channel regions 110 and the substrate 101.

[0062] In some implementations, the upper gate insulating spacers 118 and the lower gate insulating spacers 120 can include the same material, although the present disclosure is not limited to this. Each of the upper gate insulating spacers 118 and the lower gate insulating spacers 120 can include, for example, silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, and / or a low-k material. In some implementations, the upper gate insulating spacers 118 and / or the lower gate insulating spacers 120 can be omitted.

[0063] The semiconductor device 100 can further include a second interlayer 136 on an upper surface of the gate structure 102 (e.g., an upper surface of the gate cap layer 116), an upper surface of the upper gate insulating spacers 118, and an upper surface of the stressor layer 134. For example, the second interlayer 136 can be in contact with the upper surface of the stressor layer 134. Although the second interlayer 136 is shown as a single layer, in some implementations, the second interlayer 136 can include multiple layers. Figure 1B The second interlayer 136 is shown as a single layer, although in some implementations, the second interlayer 136 can include multiple layers. The second interlayer 136 can include, for example, silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, and / or a low-k material.

[0064] The semiconductor device 100 can further include an upper structure 138 on the second interlayer 136. The upper structure 138 can include elements formed by a middle-of-line (MOL) portion and / or a back-end-of-line (BEOL) portion of a device fabrication. As used herein, the upper structure 138 can also be referred to as a BEOL structure. The upper structure 138 can include conductive elements (e.g., conductive lines and / or via plugs) and insulating elements (e.g., interlayers and / or spacers). For example, the upper structure 138 can include an interlayer insulating layer, conductive lines (e.g., metal lines) provided in the interlayer insulating layer and stacked in the third direction D3, and conductive via plugs (e.g., metal via plugs), each of which can be electrically connected to two conductive lines spaced apart from each other in the third direction D3. The conductive elements of the upper structure 138 can be electrically connected to, for example, the source / drain regions 108 and / or the gate structure 102.

[0065] The gate structures 102, the channel structures 104, and the source / drain regions 108 can be provided on an upper surface SI of the substrate 101. The semiconductor device 100 can further include backside contact structures 106 (shown by dashed lines in Figure 1A FIG. 1) electrically connected to the source / drain regions 108. The backside contact structures 106 can extend through the substrate 101 from a lower surface (or backside) S2 of the substrate 101 to electrically connect to the source / drain regions 108 on the upper surface (or frontside) SI of the substrate 101. In some embodiments, a lower portion (in the first direction DI) of the backside contact structures 106 can be wider than an upper portion of the backside contact structures 106. Respective ones of the source / drain regions 108 can overlap respective ones of the backside contact structures 106 in a third direction D3. Respective ones of the stressor layers 134 can also overlap respective ones of the backside contact structures 106 in the third direction D3.

[0066] The backside contact structures 106 (which can also be referred to herein as backside source / drain contacts) can be on a lower portion (e.g., a bottom) or a lower surface (e.g., a bottom surface) of the source / drain regions 108, respectively. In some embodiments, a conductive layer 124 can be provided between each backside contact structure 106 and a respective source / drain region 108. The conductive layer 124 can be provided in the first interlayer 122. For example, a lower surface and an upper surface of the conductive layer 124 can be substantially coplanar with a lower surface and an upper surface of the first interlayer 122, respectively. In some embodiments, the conductive layer 124 can include a metal silicide layer (e.g., tungsten silicide, aluminum silicide, and / or copper silicide), a metal nitride layer (e.g., titanium nitride, tantalum nitride, and / or tungsten nitride), or a combination thereof. The conductive layer 124 can contact a lower surface of the source / drain region 108 and an upper surface of the backside contact structure 106, respectively. Each backside contact structure 106 can be electrically connected to the source / drain region 108 through the conductive layer 124. In some embodiments, the conductive layer 124 can be omitted, and the backside contact structure 106 can be in contact with the lower surface of the source / drain region 108.

[0067] In some embodiments, as shown in Figure 1A FIG. 1, backside gate contact structures 126 (shown by dashed lines) can be provided on a lower surface of the gate structures 102 and can be electrically connected to the gate structures 102 (e.g., to the gate electrodes 112). The backside gate contact structures 126 can provide control signals (e.g., gate voltages) to the gate structures 102. The backside contact structures 106 and / or the backside gate contact structures 126 can include a metal layer or a material including, for example, W, Al, Cu, Mo, Co, and / or Ru.

[0068] In some embodiments, as shown in Figure 1AAs shown in the middle, the semiconductor device 100 can further include a front-side contact structure 128 and a front-side gate contact structure 130. At least one of the source / drain regions 108 can be electrically connected to the front-side contact structure 128 and can not overlap the back-side contact structure 106 in the third direction D3. The front-side contact structure 128 can be provided in the second interlayer 136. The front-side contact structure 128 can be on an upper surface of the source / drain regions 108 and can extend through the second interlayer 136 in the third direction D3. The front-side contact structure 128 can electrically connect the source / drain regions 108 to a conductive element (e.g., a conductive line and / or a conductive via plug) of the upper structure 138. In some embodiments, the front-side contact structure 128 can be omitted and all of the source / drain regions 108 can be electrically connected to the back-side contact structure 106.

[0069] At least one of the gate structures 102 (e.g., at least one of the gate electrodes 112) can be electrically connected to the front-side gate contact structure 130 and can not overlap the back-side gate contact structure 126 in the third direction D3. The front-side gate contact structure 130 can be provided in the second interlayer 136. The front-side gate contact structure 130 can be on an upper surface of the gate structures 102 and can extend through the second interlayer 136 in the third direction D3. The front-side gate contact structure 130 can electrically connect the gate structures 102 (e.g., the gate electrodes 112) to a conductive element (e.g., a conductive line and / or a conductive via plug) of the upper structure 138. In some embodiments, the front-side gate contact structure 130 can be omitted and all of the gate structures 102 can be electrically connected to the back-side gate contact structure 126. The front-side contact structure 128 and / or the front-side gate contact structure 130 can include a metal layer or a material including, for example, W, Al, Cu, Mo, Co, and / or Ru.

[0070] The semiconductor device 100 can further include a back-side power distribution network (BSPDN) structure 140 on a lower surface (or backside) S2 of the substrate 101. The back-side contact structure 106 can electrically connect the BSPDN structure 140 to the source / drain regions 108. The BSPDN structure 140 can be provided on a lower surface of the back-side contact structure 106 and the lower surface S2 of the substrate 101. The BSPDN structure 140 can include a back-side insulator 142 and one or more back-side power rails 144 provided in the back-side insulator 142. The back-side power rails 144 can be electrically connected to the back-side contact structure 106. The back-side power rails 144 can include a metal layer or a material including, for example, W, Al, Cu, Mo, Co, and / or Ru, and the back-side insulator 142 can include, for example, silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, and / or a low-k material, although embodiments are not limited thereto.

[0071] The back-side power rail 144 can be electrically connected to a power source having a predetermined voltage (e.g., drain voltage (VDD) or source voltage (VSS)). For example, the BSPDN structure 140 may include a power delivery network. The power delivery network may include a wiring network for delivering power (e.g., gate voltage and / or source / drain voltage) to the back-side power rail 144. The source / drain region 108 can be electrically connected to the power source via the back-side contact structure 106 and the back-side power rail 144. The back-side contact structure 106 may be located on a third direction D3 between the back-side power rail 144 and the source / drain region 108. In some embodiments, one or more conductive plugs may be provided between the back-side contact structure 106 and the back-side power rail 144. The back-side contact structure 106 and the conductive plugs may comprise the same material. For example, the back contact structure 106 and the conductive plug can be integrated into a monolithic or unitary structure, that is, a structure formed by the same process or the same series of processes, with no structurally or visibly separated interface between them.

[0072] As used herein, back-side power rail 144 may refer to one or more conductive elements included in the BSPDN structure 140. For example, back-side power rail 144 may include power rails, conductive path plugs, and / or conductive lines included in the BSPDN structure 140. That is, although shown as including back-side power rail 144 and back-side insulator 142, it should be understood that the BSPDN structure 140 may include one or more conductive layers (e.g., metal layers) stacked on the third direction D3 to provide back-side power delivery to the transistor structure TS. The conductive layers may be included in the insulating layers, and conductive path plugs (e.g., metal path plugs) may electrically connect the conductive layers to each other on the third direction D3. For example, although back-side insulator 142 is shown as a single layer, in some embodiments, back-side insulator 142 may include multiple layers stacked on the lower surface S2 of substrate 101. The conductive layers may include one or more conductive lines (e.g., metal lines). In some embodiments, an intermediate structure may be provided between the substrate 101 and the BSPDN structure 140, and the intermediate structure may separate the substrate 101 from the BSPDN structure 140. The BSPDN structure 140 may improve the power delivery efficiency in the semiconductor device 100, reduce the area of ​​the semiconductor device 100 used for power delivery, and / or improve the voltage drop (i.e., IR drop) in the semiconductor device 100.

[0073] Figure 1C It is based on some implementation methods Figure 1A The cross-sectional view taken by line A-A'. For example... Figure 1CAs shown in FIG. 1, the stressor layer 134' can extend over the upper surfaces of the source / drain regions 108 and the upper surface of the gate structure 102. That is, the stressor layer 134' can extend continuously over the gate structure 102, the channel structure 104, and the pair of source / drain regions 108 included in the respective transistor structure TS. For example, the stressor layer 134' can extend continuously from the upper surface of a first source / drain region 108 of the pair of source / drain regions 108 to the upper surface of a second source / drain region of the pair of source / drain regions 108. The stressor layer 134' can extend into the upper surfaces of the pair of source / drain regions 108. The stressor layer 134' can overlap the gate structure 102 and the channel structure 104 in the third direction D3. For example, the stressor layer 134' can be in contact with the upper surface of the gate structure 102 (e.g., the upper surface of the gate cap layer 116) and the upper surface of the upper gate insulating spacer 118. At least a portion of the stressor layer 134' can be between the gate structure 102 and the second interlayer 136 (in the third direction D3). Although not shown in FIG. 1, the stressor layer 134' can be in contact with the upper surface of the channel structure 104 (e.g., the upper surface of the channel cap layer 114). In some embodiments, the stressor layer 134' can be in contact with the upper surface of the channel structure 104 and the upper surface of the gate structure 102. In some embodiments, the stressor layer 134' can be in contact with the upper surface of the channel structure 104 and the upper surface of the gate structure 102, and can not be in contact with the upper surface of the source / drain regions 108. Figure 1C Although the stressor layer 134' is shown as a single layer, in some embodiments, the stressor layer 134' can include multiple layers. Figure 1C Embodiments of the semiconductor device 100 are otherwise similar to Figure 1B Embodiments of the semiconductor device 100 are otherwise similar to

[0074] According to example embodiments, the semiconductor device 100 can include a stressor layer 134 (134') on the upper surfaces of the source / drain regions 108 and in contact with the source / drain regions 108. The stressor layer 134 (134') can apply compressive or tensile stress to the source / drain regions 108 to change the strain within the source / drain regions 108, which in turn can cause a desired stress to be induced in the channel structure 104. As a result, the carrier mobility in the channel structure 104 can be improved, and thus the performance and reliability of the semiconductor device 100 can be improved. In some embodiments, the stressor layer 134 (134') can extend into the upper surfaces of the source / drain regions 108, which can allow the stressor layer 134 (134') to exert a greater degree of stress on the source / drain regions 108 without substantially reducing its volume (or area).

[0075] Figure 2A and Figure 2B are simplified diagrams showing source / drain regions and channel structures of semiconductor devices according to some embodiments. Specifically, Figure 2A and Figure 2B schematically show the effect of the stressor layer 134 (134') on the source / drain regions 108 and the channel structure 104. In Figure 2A and Figure 2BStress source layer 134 (134') is omitted to aid in illustrating the example implementation.

[0076] refer to Figure 1B , Figure 1C , Figure 2A and Figure 2B The stress source layer 134 (134') can apply compressive or tensile stress to the source / drain region 108. For example... Figure 2A As shown, when the stress source layer 134 (134') is a compressive stress source layer, compressive stress is applied to the source / drain region 108 (indicated by the inward arrow). The compressive stress applied to the source / drain region 108 can compress the lattice structure of the source / drain region 108, thus altering the strain within the source / drain region 108. The strain (i.e., internal pressure) within the source / drain region 108 caused by the compression of its lattice structure can then introduce tensile stress into the channel structure 104 (indicated by the outward arrow). In other words, the stress source layer 134 (134') can apply compressive stress to the source / drain region 108, which can then induce tensile stress in the source / drain region 108 within the channel structure 104. The tensile stress induced in the channel structure 104 can increase the carrier mobility (e.g., electron mobility) therein. For example, when the source / drain region 108 includes n-type impurities, the stress source layer 134 (134') can be designed to apply compressive stress to the source / drain region 108, which in turn can induce tensile stress in the channel structure 104.

[0077] like Figure 2B As shown, when the stress source layer 134 (134') is a tensile stress source layer, tensile stress (indicated by the outward arrow) is applied to the source / drain region 108. The tensile stress applied to the source / drain region 108 can stretch (or expand) the lattice structure of the source / drain region 108, thus altering the strain within the source / drain region 108. The strain (i.e., internal pressure) within the source / drain region 108 caused by the expansion of its lattice structure can then introduce compressive stress (indicated by the inward arrow) into the channel structure 104. In other words, the stress source layer 134 (134') can apply tensile stress to the source / drain region 108, which in turn can cause the source / drain region 108 to induce compressive stress in the channel structure 104. The compressive stress induced in the channel structure 104 can increase the carrier mobility (e.g., hole mobility) therein. For example, when the source / drain region 108 includes p-type impurities, the stress source layer 134 (134') can be designed to apply tensile stress to the source / drain region 108, which in turn can induce compressive stress in the channel structure 104.

[0078] Figure 3 This is a flowchart illustrating a method for forming a semiconductor device according to some embodiments. Figure 4A , Figure 4B ,Figure 4C 、 Figure 4D 、 Figure 4E 、 Figure 4F 、 Figure 4G 、 Figure 4H and Figure 4I are cross-sectional views illustrating a method of forming a semiconductor device according to some embodiments. Specifically, Figure 4A 、 Figure 4B 、 Figure 4C 、 Figure 4D 、 Figure 4E 、 Figure 4F 、 Figure 4G 、 Figure 4H and Figure 4I are cross-sectional views corresponding to line A-A' of Figure 1A .

[0079] As shown in Figure 4A , an etch stop layer 456 and an epitaxial layer 458 can be formed on a preliminary substrate 454. The preliminary substrate 454, the etch stop layer 456, and the epitaxial layer 458 can be sequentially stacked in a third direction D3. The first interlayer 122 can be provided on the epitaxial layer 458.

[0080] The preliminary substrate 454 can include a semiconductor material (e.g., Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, and / or InP), or can include an insulating material (e.g., silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, and / or a low-k material), but embodiments are not limited thereto. The etch stop layer 456 can include, for example, silicon germanium (SiGe). The epitaxial layer 458 can include one or more semiconductor materials, such as silicon (Si). The epitaxial layer 458 can be doped with an impurity (e.g., boron (B), phosphorus (P), etc.) to change a conductivity type (e.g., n-type or p-type) of the epitaxial layer 458. For example, the epitaxial layer 458 can be formed by an epitaxial growth process using the etch stop layer 456 as a seed layer. A doping concentration of the epitaxial layer 458 can be different from a doping concentration of the preliminary substrate 454.

[0081] The channel structures 104 can be provided on the preliminary substrate 454. Each of the channel structures 104 can include a plurality of channel regions 110 stacked in the third direction D3. In some embodiments, the channel regions 110 can be nanosheets or nanowires.

[0082] The sacrificial gate layers 462 can be provided on the preliminary substrate 454. The sacrificial gate layers 462 can be alternately stacked with the channel regions 110 in the third direction D3. The sacrificial gate layers 462 can include, for example, silicon germanium (SiGe). The sacrificial gate layers 462 can have an etch selectivity with respect to the channel regions 110.

[0083] A dummy gate layer 446 can be formed on the channel structure 104. For example, a material of the dummy gate layer 446 can be formed (e.g., can be epitaxially grown or deposited) on the channel structure 104, which can then be etched. The dummy gate layer 446 can include insulating material(s) and / or semiconductor material(s). A hard mask 464 can be formed on an upper surface of the dummy gate layer 446. The hard mask 464 can include, for example, insulating material (e.g., silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, and / or low-k material). Insulating spacers 466 can be formed on opposite side surfaces of the dummy gate layer 446 and the hard mask 464. The insulating spacers 466 can include, for example, silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, and / or low-k material.

[0084] The dummy gate layer 446, the hard mask 464, and the insulating spacers 466 can form a dummy gate structure. A first trench (i.e., opening) 452 can be provided between adjacent dummy gate structures. The first trench 452 can extend through the channel structure 104 in the third direction D3. For example, the first trench 452 can expose an upper surface of the first interlayer 122. Opposite sidewalls of the first trench 452 can expose respective insulating spacers 466 of adjacent dummy gate structures. The sidewalls of the first trench 452 can also expose side surfaces of the channel region 110 and the sacrificial gate layer 462. The first trench 452 can be formed, for example, using an anisotropic etching process such as reactive ion etching (RIE), wet etching, or the like, although embodiments are not limited thereto.

[0085] A lower gate insulating spacer 120 can be provided on opposite side surfaces of the sacrificial gate layer 462. For example, portions of the sacrificial gate layer 462 can be etched in a horizontal direction (e.g., the first direction D1) through the first trench 452 to reduce a width of the sacrificial gate layer 462. The lower gate insulating spacer 120 can be formed in spaces left after etching the sacrificial gate layer 462.

[0086] After forming the lower gate insulating spacer 120, a gate liner 448 can be formed in the first trench 452. The gate liner 448 can include, for example, a layer containing nitrogen (e.g., SiN, SiON, SiBCN, SiOCN, SiBN, and / or SiCN), and can have a thickness in a range of (about) 1 nm to 5 nm, for example. In some embodiments, the gate liner 448 extends conformally on sidewalls and a bottom surface of each first trench 452. For example, the gate liner 448 can be formed on side surfaces of the dummy gate structure and an upper surface of the first interlayer 122.

[0087] As shown in FIG. 4B, a placeholder layer 468 can be formed on the gate liner 448 and the lower gate insulating spacer 120. The placeholder layer 468 can include, for example, a layer containing nitrogen (e.g., SiN, SiON, SiBCN, SiOCN, SiBN, and / or SiCN), and can have a thickness in a range of (about) 1 nm to 5 nm, for example. In some embodiments, the placeholder layer 468 extends conformally on sidewalls and a bottom surface of each first trench 452. For example, the placeholder layer 468 can be formed on side surfaces of the dummy gate structure and an upper surface of the first interlayer 122. Figure 4B Figure 3 ​(See box 350 in the image). For example, a placeholder layer 468 can be formed in the epitaxial layer 458.

[0088] More in detail, such as Figure 4A and Figure 4B As shown, the upper surface of the epitaxial layer 458 can be etched to form a first recess 472 in the epitaxial layer 458. In some embodiments, a self-aligned etching process can be used to form the first recess 472, wherein the hard mask 464, the insulating spacer 466, and / or the gate pad 448 are used as etching masks. For example, the portion of the epitaxial layer 458 overlapping the first trench 452 in the third direction D3 can be etched to form the first recess 472 in the epitaxial layer 458. The portion of the first interlayer 122 overlapping the first trench 452 in the third direction D3 can also be etched. The bottom surface of the first recess 472 in the epitaxial layer 458 may not extend to the etch stop layer 456.

[0089] A vacancy layer 468 may be formed in the first recess 472. In some embodiments, the vacancy layer 468 may be epitaxially grown. For example, the vacancy layer 468 may be formed by performing an epitaxial growth process using an epitaxial layer 458 as a seed layer. In some other embodiments, the vacancy layer 468 may be formed by performing a deposition process on the first recess 472 and then removing the top portion of the vacancy layer 468 (e.g., using an etching process). In some further embodiments, the first recess 472 may not be formed, and the vacancy layer 468 may be formed by implanting impurities into the epitaxial layer 458 via the first trench 452.

[0090] The occupant layer 468 may include, for example, semiconductor materials and / or insulating materials (e.g., SiGe, SiN, and / or SiBCN). In some embodiments, the occupant layer 468 may include a SiGe layer having a germanium concentration in the range of (about) 15 atomic% to 25 atomic% . The upper surface of the occupant layer 468 may be substantially coplanar with the upper surface of the epitaxial layer 458.

[0091] like Figure 4A and Figure 4B As shown, the sacrificial gate layer 462 can be removed and replaced with gate electrode 112 and gate insulator 114. The dummy gate layer 446 can also be removed and replaced with gate electrode 112 and gate insulator 114. Gate electrode 112 may comprise a material different from that of the sacrificial gate layer 462 and dummy gate layer 446. In some embodiments, a replacement metal gate (RMG) process can be used to form gate electrode 112.

[0092] The hard mask 464 can be removed, and the insulating spacer 466 can be thinned vertically (in the third direction D3). In some embodiments, a planarization process, such as, for example, a chemical mechanical polishing / planarization (CMP) process, lapping, etc., can be performed to remove the hard mask 464. In some embodiments, the planarization process can reduce the thickness of the insulating spacer 466 (in the third direction D3), thereby forming the upper gate insulating spacer 118. The gate cap layer 116 can be formed on the upper surface of the gate electrode 112. In some embodiments, only the upper portion of the hard mask 464 can be removed by the planarization process, and the lower portion thereof can be retained, thereby forming the gate cap layer 116. In some other embodiments, the hard mask 464 can be completely removed by the planarization process, and the gate cap layer 116 can be formed thereafter (e.g., using a deposition process). The gate liner 448 can also be removed after the first recess 472 is formed.

[0093] The source / drain regions 108 can be formed on the preliminary substrate 454. For example, the source / drain regions 108 can be formed in the first trenches 452, respectively. In some embodiments, the source / drain regions 108 can be epitaxially grown. For example, the source / drain regions 108 can be formed by performing an epitaxial growth process using the channel regions 110 as seed layers. The source / drain regions 108 can be epitaxially grown from opposite side surfaces of the channel regions 110. The conductive layers 124 can be formed in the first interlayers 122. For example, each conductive layer 124 can be formed on the corresponding placeholder layer 468 before the source / drain regions 108 are formed. In some embodiments, the source / drain regions 108 and the placeholder layers 468 can each include a SiGe layer, and the germanium concentration of the source / drain regions 108 can be higher than the germanium concentration of the placeholder layers 468, although the present disclosure is not limited thereto.

[0094] In some embodiments, the gate structure (see the gate structure 102 in Figure 1B and Figure 1C ), the channel structure 104, and the source / drain regions 108 can be formed by a front-end-of-line (FEOL) process.

[0095] As shown in Figure 4C , the stressor layer 134 can be formed on the upper surface of the source / drain regions 108 (block 360 in Figure 3 ). For example, the stressor layer 134 can be in contact with the source / drain regions 108.

[0096] In some embodiments, each stressor layer 134 can be epitaxially grown on a respective source / drain region 108. For example, the stressor layers 134 can be formed by performing an epitaxial growth process (e.g., a selective epitaxial growth (SEG) process) using the source / drain regions 108 as seed layers. When using an epitaxial growth process to form the stressor layers 134, the source / drain regions 108 can undergo less processing, which can help reduce variations in strain within the source / drain regions 108. The epitaxial growth process can also allow for better control of the lattice structure of the source / drain regions 108. In some other embodiments, the stressor layers 134 can be formed by depositing the stressor layers 134 (i.e., depositing the material of the stressor layers 134) using a deposition process and then removing an upper portion of the stressor layers 134 (e.g., using an etching process and / or a planarization process) such that the stressor layers 134 are spaced apart from each other in the first direction Dl and are respectively provided on the source / drain regions 108.

[0097] In some embodiments, each stressor layer 134 can include an epitaxial layer having a higher Ge concentration than the source / drain regions 108. For example, in some embodiments, each stressor layer 134 can have a Ge concentration in the range of (about) 75 to 100 at%. In some other embodiments, the stressor layers 134 can include a dielectric material (e.g., SiOC, SiON, SiCN, SiN, TOSZ, TEOS, ALD oxide, FCVD oxide, HDP oxide, and / or PEOX oxide), a metallic material (e.g., tungsten (W) and / or molybdenum (Mo)), or a combination thereof.

[0098] In some embodiments, forming the stressor layers 134 can include forming second recesses 474 in upper surfaces of each source / drain region 108 and then forming the stressor layers 134 in the second recesses 474. For example, an upper portion of each source / drain region 108 can be removed to form the second recesses 474. In some embodiments, an etching process such as, for example, a wet etching process and / or a dry etching process (e.g., plasma etching) can be used to remove the upper portion of each source / drain region 108 to form the second recesses 474. The stressor layers 134 can be respectively formed in the second recesses 474 using, for example, an epitaxial growth process (e.g., a SEG process) and / or a deposition process (e.g., a CVD process, a PVD process, an ALD process, etc.). By forming the stressor layers 134 in the second recesses 474, each stressor layer 134 can extend into the upper surface of the respective source / drain region 108, which can allow the stressor layers 134 to exert a greater degree of stress on the source / drain regions 108.

[0099] As shown in Figure 4D , a second interlayer 136 can be formed, and an upper structure 138 can be formed on the second interlayer 136. For example, an upper surface of the gate cap layer 116 and / or an upper surface of the stressor layer 134 can be substantially coplanar with a lower surface of the second interlayer 136. In some embodiments, a carrier wafer (not shown) can be provided on the upper structure 138, and can serve as a temporary support structure for performing subsequent backside processing. Although not shown, the frontside contact structures 128 and the frontside gate contact structures 130 (see Figure 1A ) can be formed in the second interlayer 136 prior to forming the upper structure 138.

[0100] As shown in Figure 4D and Figure 4E , the preliminary substrate 454 can be removed, e.g., by a CMP process or the like, to expose the etch stop layer 456. Although not shown in Figure 4E , in some embodiments, Figure 4D the structures shown in may be flipped upside down (i.e., can be inverted) during backside processing, and can be supported on the carrier wafer (not shown) discussed above.

[0101] Figure 4E As shown in Figure 4F and , the etch stop layer 456 and the epitaxial layer 458 can be removed, e.g., by selective etching, without removing the placeholder layer 468. The first interlayer 122 and the placeholder layer 468 can be exposed after removing the etch stop layer 456 and the epitaxial layer 458. The placeholder layer 468 can comprise a different material than the epitaxial layer 458, and thus can have etch selectivity with respect to the epitaxial layer 458. In some embodiments, the placeholder layer 468 can comprise silicon germanium (SiGe), and the epitaxial layer 458 can comprise silicon (Si), although the present disclosure is not limited thereto.

[0102] Figure 4G As shown in and

[0103] , the substrate 101 can be formed on the placeholder layer 468 and the first interlayer 122. The substrate 101 can be formed, e.g., using a deposition process. Figure 4G Figure 4H As shown in Figure 3The etching process can be selective to the material of the placeholder layer 468. Portions of the substrate 101 can also be removed by the etching process. After the placeholder layer 468 is removed, the surrounding substrate 101 that is not etched will remain, forming second trenches 476 (i.e., openings) having a profile similar to that of the placeholder layer 468 (i.e., the border shape). In other words, each second trench 476 can be a space left after the placeholder layer 468 is removed. In some embodiments, the etching process can result in a lower portion (in the first direction D1) of each second trench 476 being wider than an upper portion thereof. For example, the etching process can include a first etch to remove the placeholder layer 468 and a second etch to widen the lower portion of each second trench 476. By forming each second trench 476 to have a shape that widens away from the source / drain region 108, the backside contact structure 106, which will be described in more detail below, can have a reduced resistance and / or improved electrical connection to the BSPDN structure 140.

[0104] As shown in Figure 4H and Figure 4I , the backside contact structure 106 can be formed on the lower surface of the source / drain region 108 in the space left after the placeholder layer 468 is removed (block 380 in Figure 3 ). In other words, the backside contact structure 106 can be formed in the second trench 476, respectively. For example, a conductive material (e.g., a metallic material) can be deposited in each second trench 476 to form the backside contact structure 106. The backside contact structure 106 can be electrically connected to the source / drain region 108, respectively. For example, the backside contact structure 106 can be electrically connected to the source / drain region 108 through the conductive layer 124, respectively.

[0105] Referring back to Figure 1B , the BSPDN structure 140 can be formed on the backside contact structure 106. The backside contact structure 106 can be electrically connected to the BSPDN structure 140 and the source / drain region 108. The backside contact structure 106 can be between the BSPDN structure 140 and the source / drain region 108 in the third direction D3. The BSPDN structure 140 can include a backside insulator 142 and one or more backside power rails 144 provided in the backside insulator 142. Thus, the semiconductor device 100 can be formed.

[0106] Figure 5 is a cross-sectional view illustrating a method of forming a semiconductor device according to some embodiments. Specifically, Figure 5 is a cross-sectional view corresponding to line A-A' of Figure 1A .

[0107] As shown in Figure 5 , the backside contact structure 106 can be formed on the lower surface of the source / drain region 108 in the space left after the placeholder layer 468 is removed (block 380 in Figure 4A andFigure 4B Following the described operation, a stress source layer 134' can be formed on the upper surface of the source / drain region 108. Figure 3 (See box 360 in the image). For example, stress source layer 134' can contact source / drain region 108.

[0108] In some embodiments, the stress source layer 134' can be formed by depositing a stress source layer 134' (i.e., the material on which the stress source layer 134' is deposited) on the upper surface of the source / drain region 108 using a deposition process (e.g., CVD, PVD, ALD, etc.). For example, the deposition process used to form the stress source layer 134' can be more cost-effective and / or faster than an epitaxial growth process. The stress source layer 134' can be deposited on the corresponding transistor structure (see [reference]). Figure 1C The gate structure in the transistor structure TS (see Figure 1C The stress source layer 134' can extend continuously on the gate structure 102 (which includes a gate electrode 112, a gate insulator 114, and a gate capping layer 116), the channel structure 104, and the source / drain region 108. In some embodiments, the stress source layer 134' may include a dielectric material (e.g., SiOC, SiON, SiCN, SiN, TOSZ, tetraethyl orthosilicate (TEOS), atomic layer deposition (ALD) oxide, flowable chemical vapor deposition (FCVD) oxide, high-density plasma (HDP) oxide, and / or plasma-enhanced oxide (PEOX) oxide), a metallic material (e.g., tungsten (W) and / or molybdenum (Mo)), or combinations thereof, but this disclosure is not limited thereto.

[0109] In some embodiments, forming the stress source layer 134' may include forming a second recess 474 in the upper surface of each source / drain region 108, and then forming the stress source layer 134' in the second recess 474. For example, the upper portion of each source / drain region 108 may be removed to form the second recess 474. In some embodiments, the upper portion of each source / drain region 108 may be removed using an etching process (such as, for example, wet etching and / or dry etching (e.g., plasma etching)) to form the second recess 474. The stress source layer 134' may be formed in the second recess 474 using, for example, a deposition process (e.g., CVD, PVD, ALD, etc.). By forming the stress source layer 134' in the second recess 474, the stress source layer 134' may extend into the upper surface of each source / drain region 108, which may allow the stress source layer 134' to apply a greater degree of stress to the source / drain region 108.

[0110] After the stress source layer 134' is formed, the above reference can be performed.Figure 4D 、 Figure 4E 、 Figure 4F 、 Figure 4G 、 Figure 4H 、 Figure 4I and Figure 1B the operations described. Thus, the semiconductor device 100 shown in Figure 1C may be formed.

[0111] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Furthermore, all terms are to be interpreted in the same manner as they would be by a person skilled in the art and in the context of this disclosure, and are not to be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0112] In the above description, example embodiments can be described with reference to regions of a particular conductivity type. It will be appreciated that devices of the opposite conductivity type can be formed by simply reversing the conductivity of the n-type and p-type layers in each of the above embodiments. Thus, it will be appreciated that the present disclosure encompasses both n-channel and p-channel devices for each different device structure.

[0113] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of embodiments. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises," "comprising," "includes," and / or "including," specify the presence of stated features, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof.

[0114] It will be understood that, although the terms "first," "second," etc. can be used herein to describe various elements, these elements should not be limited by these terms. Rather, these terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0115] As used herein, the term "surrounding" or "covering" or "filling" can not require complete surrounding or covering or filling of the described element or layer, but may, for example, refer to partially surrounding or covering or filling the described element or layer. Components or layers described with reference to "overlapping" in a particular direction can be at least partially obstructed from each other when viewed along a line extending in the particular direction or in a plane perpendicular to the particular direction.

[0116] It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements can also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. The term "connected" can include physical and / or electrical connections.

[0117] Spatially relative terms such as "beneath", "below", "lower", "above", "upper" and the like can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if the device described herein is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features.

[0118] Example implementations are described herein with reference to the accompanying drawings, which can be schematic or drawing illustrations of idealized implementations (and intermediate structures) in which many specific details are shown. Many different forms and implementations are possible. The disclosure should not be construed as limited to the example implementations set forth herein; rather, these example implementations are provided for illustrative purposes. Accordingly, one of ordinary skill in the art will recognize that many modifications and variations are possible while remaining within the scope of the present disclosure, as defined by the appended claims. In the drawings, the size and relative sizes of layers and regions can be exaggerated for clarity. Also, it is to be understood that changes in the shape and / or arrangement of the illustrated shapes can be made without departing from the scope of the present disclosure.

[0119] Implementations of the disclosure are also described with reference to manufacturing operations and flowcharts. It will be understood that the steps shown in the manufacturing operations and flowcharts need not be performed in the order shown.

[0120] The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other implementations falling within the scope of the present disclosure. Thus, to the maximum extent possible, the scope of the claims shall not be limited to the expressly disclosed implementations and the specific examples shown and described herein. Rather, the scope of the claims shall be governed by the claims and their equivalents, and the full breadth of the claims, and is intended to cover all changes, enhancements, and other implementations falling within the scope of the present disclosure.

[0121] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 705,228, filed October 9, 2024, entitled “INTEGRATED CIRCUIT DEVICES HAVING STRESSOR STRUCTURE AND METHODS OF MANUFACTURING THE SAME,” the disclosure of which is incorporated by reference herein in its entirety.

Claims

1. A semiconductor device, comprising: Substrate; Source / drain regions on the substrate; A channel structure is present on the substrate and electrically connected to the source / drain regions; A gate structure, on the substrate and at least partially surrounding the channel structure; as well as A stress source layer is in contact with the upper surface of the source / drain region and is configured to apply compressive or tensile stress to the source / drain region.

2. The semiconductor device of claim 1, wherein the stress source layer extends into the upper surface of the source / drain region.

3. The semiconductor device according to claim 2, wherein, The first distance between the lower surface of the stress source layer and the upper surface of the substrate is greater than the second distance between the upper surface of the channel structure and the upper surface of the substrate.

4. The semiconductor device of claim 2, wherein the stress source layer comprises a first portion in the source / drain region and a second portion on the upper surface of the source / drain region, and in, The first width of the first portion of the stress source layer in a direction parallel to the upper surface of the substrate is smaller than the second width of the second portion of the stress source layer in that direction.

5. The semiconductor device according to claim 1, wherein, The stress source layer does not overlap with the gate structure in a direction perpendicular to the upper surface of the substrate.

6. The semiconductor device according to claim 1, wherein, The stress source layer overlaps with the gate structure and the channel structure in a direction perpendicular to the upper surface of the substrate.

7. The semiconductor device of claim 1, further comprising a back-side contact structure extending in the substrate and electrically connected to the source / drain region. in, The stress source layer overlaps with the back contact structure in a direction perpendicular to the upper surface of the substrate.

8. The semiconductor device according to claim 1, wherein, The source / drain region is the first source / drain region. Wherein, the stress source layer is the first stress source layer, and The semiconductor device further includes: A second source / drain region is adjacent to the first source / drain region, and the channel structure is located between the second source / drain region and the first source / drain region; and The second stress source layer is in contact with the upper surface of the second source / drain region and is configured to apply compressive or tensile stress to the second source / drain region.

9. The semiconductor device according to claim 8, wherein, The second stress source layer is spaced apart from the first stress source layer, and the gate structure is located between the second stress source layer and the first stress source layer.

10. The semiconductor device according to claim 1, wherein, The source / drain region is the first source / drain region. The semiconductor device further includes a second source / drain region adjacent to the first source / drain region, and the channel structure is located between the second source / drain region and the first source / drain region. The stress source layer is in contact with the upper surface of the second source / drain region and is configured to apply compressive or tensile stress to the second source / drain region.

11. The semiconductor device according to claim 10, wherein, The stress source layer extends continuously from the upper surface of the first source / drain region to the upper surface of the second source / drain region.

12. The semiconductor device according to claim 1, wherein, The stress source layer is not present on the outer surface of the source / drain region.

13. The semiconductor device according to claim 1, wherein, The stress source layer is configured to apply compressive stress to the source / drain region when the source / drain region includes an n-type impurity, and The stress source layer is configured to apply tensile stress to the source / drain region when the source / drain region includes p-type impurities.

14. A semiconductor device, comprising: Substrate; The first source / drain region and the second source / drain region are spaced apart from each other on the substrate. A channel structure, between the first source / drain region and the second source / drain region, the channel structure includes a plurality of channel regions spaced apart from each other in a direction perpendicular to the upper surface of the substrate; A gate structure, on the substrate and at least partially surrounding the channel structure; A back-side contact structure extends in the substrate and is electrically connected to the first source / drain region or the second source / drain region; as well as A stress source layer extends into the upper surface of the first source / drain region and is configured to apply compressive or tensile stress to the first source / drain region.

15. The semiconductor device according to claim 14, wherein, The stress source layer is the first stress source layer, and The semiconductor device further includes a second stress source layer that extends into the upper surface of the second source / drain region and is spaced apart from the first stress source layer. The second stress source layer is configured to apply compressive or tensile stress to the second source / drain region.

16. The semiconductor device according to claim 14, wherein, The stress source layer extends into the upper surface of the second source / drain region and is configured to apply compressive or tensile stress to the second source / drain region.

17. The semiconductor device according to claim 14, wherein, The stress source layer overlaps with the back contact structure in the direction stated therein.

18. A method of forming a semiconductor device, comprising: A stress source layer is formed on the upper surface of the source / drain region and in contact with the source / drain region. The stress source layer applies compressive or tensile stress to the source / drain region.

19. The method according to claim 18, wherein, The formation of the stress source layer includes: A recess is formed in the upper surface of the source / drain region; and The stress source layer is formed in the depression.

20. The method according to claim 18, wherein, Forming the stress source layer includes epitaxially growing the stress source layer on the source / drain region.

21. The method according to claim 18, wherein, Forming the stress source layer includes depositing the stress source layer on the upper surface of the source / drain region using a deposition process.

22. The method of claim 18, further comprising: Forming a placeholder layer; The placeholder layer is removed using an etching process; as well as In the space left after removing the placeholder layer, a back-side contact structure is formed on the lower surface of the source / drain region.

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