Semiconductor device and method of forming semiconductor device

Abstract

A semiconductor device and a method of forming a semiconductor device. The semiconductor device includes a first source / drain region; a first silicide region on the first source / drain region; a first nanostructure adjacent to the first source / drain region; a second source / drain region overlapping the first source / drain region; and a second silicide region on the second source / drain region. The first silicide region includes a first metal that is different from a second metal included in the second silicide region.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device having stacked transistors and a method for forming the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Manufacturing semiconductor devices typically involves sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and using photolithography to pattern the individual material layers to form multiple circuit components and multiple elements thereon.

[0003] The semiconductor industry is continuously increasing the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated within a given area. As the semiconductor industry further moves towards increasing device density, higher performance, and lower cost, challenges in manufacturing and design have led to stacked device configurations, such as stacked multiple transistors including complementary field-effect transistors (CFETs). However, with the reduction in the minimum feature size, additional features are introduced. Summary of the Invention

[0004] Some embodiments of this disclosure provide a semiconductor device comprising: a first source / drain region, a first silicide region, a plurality of first nanostructures, a second source / drain region, a second silicide region, a plurality of second nanostructures, a first gate structure, and a second gate structure. The first silicide region is on the first source / drain region. The plurality of first nanostructures are adjacent to the first source / drain region. The second source / drain region overlaps with the first source / drain region. The second silicide region is on the second source / drain region, wherein the first silicide region includes a first metal, the first metal being different from a second metal included in the second silicide region. The plurality of second nanostructures are adjacent to the second source / drain region. The first gate structure surrounds the plurality of first nanostructures. The second gate structure overlaps with the first gate structure and surrounds the plurality of second nanostructures.

[0005] Other embodiments of this disclosure provide a method for forming a semiconductor device, comprising: patterning a first opening through one or more dielectric layers to expose a first source / drain region and a second source / drain region, wherein the second source / drain region overlaps with the first source / drain region; forming a first silicide region on the first source / drain region in the first opening, and forming a second silicide region on the second source / drain region; forming a first [missing information - likely a slurry] in the first opening above the first silicide region and the second silicide region. Source / drain contacts; etching the first source / drain contacts to define a second opening, the second opening exposing the second silicide region; replacing the second silicide region with a third silicide region in the second opening on the second source / drain region; and forming a second source / drain contact in the second opening, wherein the first source / drain contact is electrically coupled to the first source / drain region through the first silicide region, and wherein the second source / drain contact is electrically coupled to the second source / drain region through the second silicide region.

[0006] Other embodiments of this disclosure provide a method for forming a semiconductor device, comprising: patterning a first opening through one or more dielectric layers to expose a first source / drain region and a second source / drain region, wherein the second source / drain region overlaps with the first source / drain region and has a conductivity type opposite to that of the first source / drain region; forming a first silicide region on the first source / drain region in the first opening, the first silicide region comprising a first metal; forming a first source / drain contact in the first opening and extending to the first silicide region; etching the first source / drain contact to define a second opening; forming a second silicide region on a second source / drain region in the second opening; and forming a second source / drain contact in the second opening and extending to the second silicide region. Attached Figure Description

[0007] Several aspects of this disclosure can be described in detail below and in conjunction with the appended... Figure One For best understanding, please read carefully. Note that, according to industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features can be increased or decreased arbitrarily for clarity of discussion.

[0008] Figure 1 A perspective view of multiple transistors stacked according to embodiments of some implementations is shown;

[0009] Figures 2 to 5 , Figure 6A , Figure 6B ,Figures 7 to 14 , Figure 15A , Figure 15B and Figure 16 This is a view of several intermediate stages in the fabrication of stacked transistors according to some implementation methods;

[0010] Figure 17A and Figure 17B This is a cross-sectional view of stacked transistors according to some implementation embodiments.

[0011] [Symbol Explanation]

[0012] 10: Stacked transistors

[0013] 10L: Lower nanostructure field-effect transistor (transistor)

[0014] 10U: Top-mounted nanostructure field-effect transistor (transistor)

[0015] 104: Etching Stop Layer

[0016] 106: Third interlayer dielectric

[0017] 108: Gate contact

[0018] 108L: Lower source / drain contact opening (lower contact opening)

[0019] 108U: Upper source / drain contact opening (upper contact opening)

[0020] 110: Contact spacer

[0021] 112L: Lower silicide region

[0022] 112U: Upper silicide region

[0023] 114: Source / Drain Contact

[0024] 116: Source / Drain contact opening

[0025] 118: Upper silicide region

[0026] 120: Upper source / drain contact (source / drain contact)

[0027] 122: Device Layer

[0028] 124: Dielectric layer

[0029] 126: Electrical conductivity characteristics

[0030] 128: Front-side interconnect structure

[0031] 130: Contact guide hole

[0032] 132: Contact spacer

[0033] 134: Backside interconnect structure

[0034] 20:Substrate

[0035] 20': Semiconductor strip (fin)

[0036] 22: Multi-layer stacking

[0037] 24: Feigning a nanostructure

[0038] 24A: Virtual Nanostructure (Virtual Semiconductor Nanostructure)

[0039] 24B: Virtual Nanostructure (Virtual Semiconductor Nanostructure)

[0040] 26: Semiconductor Nanostructures

[0041] 26L: Lower semiconductor nanostructure

[0042] 26U: Upper semiconductor nanostructure

[0043] 28: Semiconductor strips

[0044] 32: Shallow trench isolation area (isolation area)

[0045] 36: Dummy dielectric layer

[0046] 38: Dummy Gate Layer (Dummy Gate)

[0047] 40: Masking layer (mask)

[0048] 42: Dummy Gate Stack (Gate Stack)

[0049] 44: Gate spacer

[0050] 45: Fin spacers

[0051] 46: Source / drain recess

[0052] 54: Internal spacers

[0053] 56: Dielectric isolation layer

[0054] 62: Source / Drain region; 62L: Lower epitaxial source / drain region

[0055] 62U: Upper epitaxial source / drain region

[0056] 66: First contact etch stop layer

[0057] 68: First interlayer dielectric

[0058] 70: Second contact etch stop layer

[0059] 72: Second interlayer dielectric

[0060] 78: Gate Dielectric

[0061] 80: Gate electrode; 80L: Lower gate electrode (lower gate stack)

[0062] 80U: Upper gate electrode (gate electrode)

[0063] 90: Gate structure (gate stacking)

[0064] 90L: Lower gate structure

[0065] 90U: Upper gate structure

[0066] 92: Gate mask A-A': Cross section B-B': Cross section Detailed Implementation

[0067] The following disclosure provides many different implementations or embodiments to carry out different features of this disclosure. Specific embodiments of components and arrangements are described below to simplify this disclosure. Of course, these are merely embodiments and not limiting. For example, in the following description, forming a first feature above or on a second feature may include implementations where the first and second features are formed in direct contact, and may also include implementations where additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, reference numerals and / or letters may be repeated in various embodiments of this disclosure. This repetition is for the purpose of simplicity and clarity, and does not in itself imply a relationship between the various implementations and / or configurations discussed.

[0068] Furthermore, to facilitate the description of the relationship between one element or feature and another, as illustrated in the accompanying drawings, spatially relative terms may be used herein, such as "below," "lower," "slightly below," "above," "slightly above," and similar terms. In addition to the directions illustrated in the accompanying drawings, the spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0069] Methods for forming stacked transistor structures, such as multiple complementary field-effect transistors (CFETs), are provided. The stacked transistor structures include two transistors of opposite types stacked vertically (e.g., an n-type transistor and a p-type transistor stacked vertically). In various embodiments, the silicide region of the n-type transistor is made of a different material than the silicide region of the p-type transistor. Specifically, the material of the silicide region can be selected to provide a lower barrier height to each of the n-type and p-type source / drain regions. As a result, the source / drain contact resistance in the resulting stacked transistors can be reduced, and device performance can be improved. Furthermore, various methods utilize stacked configurations of n-type and p-type transistors to form silicide regions of different materials without significantly complicating the fabrication process.

[0070] Figure 1 An embodiment of a stacked transistor 10 according to some implementations is illustrated, the stacked transistor 10 including a plurality of field-effect transistors (transistors) 10U and 10L. Figure 1 This is a 3D view; for clarity, some features of the stacked transistors have been omitted.

[0071] The stacked transistors comprise a plurality of vertically stacked field-effect transistors (FETs). For example, the stacked transistors may include a lower nanostructure FET 10L of a first device type (e.g., n-type / p-type) and an upper nanostructure FET 10U of a second device type (e.g., p-type / n-type). When the stacked transistors are complementary field-effect transistors (CFETs), the second device type of the upper nanostructure FET 10U is the opposite of the first device type of the lower nanostructure FET 10L. The nanostructure FETs 10U and 10L include semiconductor nanostructures 26 (including a lower semiconductor nanostructure 26L and an upper semiconductor nanostructure 26U), wherein the semiconductor nanostructure 26 acts as a channel region for the nanostructure FET. The lower semiconductor nanostructure 26L is used for the lower nanostructure FET 10L, and the upper semiconductor nanostructure 26U is used for the upper nanostructure FET 10U. In other embodiments, the stacked transistors may also be applied to other types of transistors (e.g., fin field-effect transistors, or similar).

[0072] A gate dielectric 78 surrounds the corresponding semiconductor nanostructure 26. Gate electrodes 80 (including a lower gate electrode 80L and an upper gate electrode 80U) are located above the gate dielectric 78. Source / drain regions 62 (including a lower epitaxial source / drain region 62L and an upper epitaxial source / drain region 62U) are disposed on opposite sides of the gate dielectric 78 and the corresponding gate electrodes 80. Each of the source / drain regions 62 may refer to either a source or a drain, individually or collectively depending on the context. Multiple isolation features (not shown) may be formed to separate the desired source / drain regions 62 and / or the desired gate electrodes 80.

[0073] Figure 1 Reference cross sections used in subsequent figures are also illustrated. Cross section A-A' is a vertical cross section parallel to the longitudinal axis of the semiconductor nanostructure 26 of the stacked transistors and in one direction of current flow, for example, between the multiple source / drain regions 62 of the stacked transistors. Cross section B-B' is a vertical cross section perpendicular to cross section A-A' and extends through the source / drain regions 62 of the stacked transistors. For clarity, reference can be made to these reference cross sections in the following figures.

[0074] Figures 2 to 15B The illustration depicts stacked transistors (such as in...) according to some implementation methods. Figure 1 Perspective and section views illustrating multiple intermediate stages in the formation of (the diagram is shown in the image). In the following discussion, Figure 3 , Figure 4 , Figure 5 , Figure 6A and Figure 16 Multiple vertical section views are drawn along and in Figure 1 The section is similar to the vertical reference section A-A' in the diagram. Figure 6B , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15A and Figure 15B Multiple cross-sectional views are drawn along and in Figure 1 The section is similar to the vertical reference section B-B' in the diagram.

[0075] exist Figure 2The image provides a perspective view of a wafer, which includes a substrate 20. The substrate 20 may be a semiconductor substrate, such as a bulk semiconductor, and may be doped (e.g., p-type or n-type dopant) or undoped. Other substrates may also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 20 may include silicon, germanium, carbon-doped silicon, III-V compound semiconductors; or similar materials, or combinations thereof.

[0076] Multiple semiconductor strips 28 are formed extending upward from a semiconductor substrate 20. Each semiconductor strip 28 includes a semiconductor strip 20' (a patterned portion of the semiconductor substrate 20, also referred to as a semiconductor fin 20') and a multilayer stack 22. The stacked components of the multilayer stack 22 are referred to hereinafter as nanostructures. Specifically, the multilayer stack 22 includes dummy nanostructures 24A and dummy nanostructures 24B, a lower semiconductor nanostructure 26L, and an upper semiconductor nanostructure 26U. Dummy nanostructures 24A and dummy nanostructures 24B can be further collectively referred to as dummy nanostructure 24, and the lower semiconductor nanostructure 26L and upper semiconductor nanostructure 26U can be further collectively referred to as semiconductor nanostructure 26.

[0077] The dummy nanostructure 24A is formed of a first semiconductor material, and the dummy nanostructure 24B is formed of a second semiconductor material different from the first semiconductor material. In some embodiments, the first semiconductor material of the dummy nanostructure 24A and the second semiconductor material of the dummy nanostructure 24B may be made of the same semiconductor material with different compositions of multiple elements. For example, both the first semiconductor material of the dummy nanostructure 24A and the second semiconductor material of the dummy nanostructure 24B may be made of silicon-germanium with different germanium concentrations. The first and second semiconductor materials may be selected from candidate semiconductor materials of the substrate 20. The first and second semiconductor materials have high etch selectivity for each other. Thus, in subsequent processes, the dummy semiconductor nanostructure 24B can be removed at a faster rate than the dummy semiconductor nanostructure 24A.

[0078] Semiconductor nanostructure 26 (including lower semiconductor nanostructure 26L and upper semiconductor nanostructure 26U) is formed of one or more third semiconductor materials. The third semiconductor material can be selected from candidate semiconductor materials of the substrate 20. The lower semiconductor nanostructure 26L and upper semiconductor nanostructure 26U can be formed of the same semiconductor material or different semiconductor materials. Furthermore, the first and second semiconductor materials of the dummy nanostructure 24 have high etch selectivity relative to the third semiconductor material of the semiconductor nanostructure 26. Thus, the dummy nanostructure 24 can be selectively removed in subsequent process steps without significantly removing the semiconductor nanostructure 26. In some embodiments, the dummy nanostructure 24A is formed of silicon-germanium, the semiconductor nanostructure 26 is formed of silicon, and the dummy nanostructure 24B can be formed of germanium or silicon-germanium (with a higher percentage of germanium atoms than the semiconductor nanostructure 24A).

[0079] The lower semiconductor nanostructure 26L will provide a channel region for the lower nanostructure field-effect transistor (CFET) of the complementary field-effect transistor (CFET). The upper semiconductor nanostructure 26U will provide a channel region for the upper nanostructure field-effect transistor (CFET) of the CFET. The semiconductor nanostructure 26 immediately above / below (e.g., in contact with) the dummy nanostructure 24B can be used for isolation and may or may not serve as a channel region for the CFET. The dummy nanostructure 24B will then be replaced by an isolation structure that defines the boundary between the lower and upper nanostructure field-effect transistors.

[0080] To form the semiconductor strip 28, multiple layers of first, second, and third semiconductor materials (as illustrated and described above) can be deposited over the semiconductor substrate 20. The multiple layers of the first, second, and third semiconductor materials can be grown via processes such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), or deposited via processes such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), or similar processes. Then, a patterning process can be applied to the multiple layers of the first, second, and third semiconductor materials and the semiconductor substrate 20 to define the semiconductor strip 28, which includes a semiconductor strip 20', a dummy nanostructure 24, and a semiconductor nanostructure 26.

[0081] Semiconductor fins and nanostructures can be patterned using any suitable method. For example, the patterning process may include one or more photolithography processes, including dual or multiple patterning processes. Generally, dual or multiple patterning processes combine photolithography and self-aligned processes, allowing the pattern to be created to have, for example, a smaller pitch than that obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate, and the sacrificial layer is patterned using a photolithography process. A plurality of spacers are formed along the sides of the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used as an etch mask for the patterning process to etch multiple layers of first, second, and third semiconductor materials and the semiconductor substrate 20. Etching can be performed via any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), the like, or combinations thereof. The etching may be anisotropic.

[0082] like Figure 2 As illustrated, a shallow trench isolation region 32 is formed over a substrate 20 and between a plurality of adjacent semiconductor strips 28. The shallow trench isolation region 32 may include a dielectric pad and a dielectric material above the dielectric pad. Both the dielectric pad and the dielectric material may include, for example, an oxide of silicon oxide, a nitride of silicon nitride, the like, or a combination thereof. Forming the shallow trench isolation region 32 may include depositing a dielectric layer and performing a planarization process, such as chemical mechanical polishing (CMP), mechanical polishing, or the like, to remove excess dielectric material. Deposition processes may include atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD), the like, or a combination thereof. In some embodiments, the shallow trench isolation region 32 includes silicon oxide formed via a flowable chemical vapor deposition process, followed by an annealing process. The dielectric layer is then recessed to define the shallow trench isolation region 32. The dielectric layer can be recessed so that the upper portion of the semiconductor strip 28 (including the multilayer stack 22) protrudes above the remaining shallow trench isolation region 32.

[0083] After forming the shallow trench isolation region 32, a dummy gate stack 42 may be formed over the upper portion of the semiconductor strip 28 (the portion protruding above the shallow trench isolation region 32) and along the sidewalls of this upper portion. Forming the dummy gate stack 42 may include forming a dummy dielectric layer 36 on the semiconductor strip 28. The dummy dielectric layer 36 may be formed, for example, by silicon oxide, silicon nitride, combinations thereof, or the like, or may contain silicon oxide, silicon nitride, combinations thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 38 is formed over the dummy dielectric layer 36. The dummy gate layer 38 may be deposited, for example, by physical vapor deposition (PVD), chemical vapor deposition, or other techniques, and then planarized, for example, by a chemical mechanical polishing process. The material of the dummy gate layer 38 may be conductive or non-conductive and may be selected from the group including amorphous silicon, polycrystalline silicon, poly-SiGe, or the like. A mask layer 40 is formed over a planarized dummy gate layer 38 and may include, for example, silicon nitride, silicon oxynitride, or the like. Next, the mask layer 40 may be patterned using photolithography and etching processes to form a mask, which is then used to etch and pattern the dummy gate layer 38, and possibly the dummy dielectric layer 36. Multiple remaining portions of the mask layer 40, the dummy gate layer 38, and the dummy dielectric layer 36 form a dummy gate stack 42.

[0084] exist Figure 3 In this process, gate spacers 44 and source / drain recesses 46 are formed. First, gate spacers 44 are formed over the multilayer stack 22 and on the exposed sidewalls of the dummy gate stack 42. The gate spacers 44 can be formed by conformally forming one or more dielectric layers and subsequently anisotropically etching the dielectric layers. Applicable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or the like, and can be formed via deposition processes such as chemical vapor deposition, atomic layer deposition, or the like. Fin spacers 45 (see...) Figure 6B It can also be formed as part of the formation of gate spacer 44.

[0085] Subsequently, source / drain recesses 46 are formed in semiconductor strip 28. Formation of the source / drain recesses 46 is achieved through etching and can extend through the multilayer stack 22 and into the semiconductor strip 20'. The bottom surface of the source / drain recesses 46 may be higher, lower, or the same level as the top surface of the isolation region 32. During the etching process, the gate spacers 44 and the dummy gate stack 42 cover portions of the semiconductor strip 28. Etching may include a single etching process or multiple etching processes. A timed etching process can be used, stopping the etching of the source / drain recesses 46 when the desired depth is reached.

[0086] exist Figure 4In this process, internal spacers 54 and dielectric isolation layers 56 are formed. Forming the internal spacers 54 and dielectric isolation layers 56 may include an etching process that laterally etches the dummy nanostructures 24A and removes the dummy nanostructures 24B. The etching process may be isotropic and selective for the material of the dummy nanostructures 24, allowing the dummy nanostructures 24 to be etched at a faster rate than the semiconductor nanostructures 26. The etching process may also be selective for the material of the dummy nanostructures 24B, allowing the dummy nanostructures 24B to be etched at a faster rate than the dummy nanostructures 24A. In this way, the dummy nanostructures 24B can be completely removed from between the plurality of lower semiconductor nanostructures 26L (commonly) and the plurality of upper semiconductor nanostructures 26U (commonly), without completely removing the dummy nanostructures 24A. In some embodiments, removing the dummy nanostructure 24B can etch the exposed surface of the semiconductor nanostructure 26 and can further widen the space between the plurality of lower semiconductor nanostructures 26L (commonly) and the plurality of upper semiconductor nanostructures 26U (commonly). In some embodiments, wherein the dummy nanostructure 24B is formed of germanium or silicon-germanium with a high percentage of germanium atoms, the dummy nanostructure 24A is formed of silicon-germanium with a low percentage of germanium atoms, and the semiconductor nanostructure 26 is formed of germanium-free silicon, the etching process may include a dry etching process using chlorine gas, with or without plasma. Because the dummy gate stack 42 surrounds the sidewalls of the semiconductor nanostructure 26 (see...), Figure 2 Therefore, the dummy gate stack 42 can support the upper semiconductor nanostructure 26U, so that the upper semiconductor nanostructure 26U will not collapse when the dummy nanostructure 24B is removed. In addition, although the sidewalls of the dummy nanostructure 24A are shown as straight after etching, the sidewalls can be concave or convex.

[0087] An internal spacer 54 is formed on the sidewalls of the recessed dummy nanostructure 24A, and a dielectric isolation layer 56 is formed between the plurality of upper semiconductor nanostructures 26U (commonly) and the plurality of lower semiconductor nanostructures 26L (commonly). As will be described in more detail later, source / drain regions will subsequently be formed in the source / drain recess 46, and the dummy nanostructure 24A will be replaced by the corresponding gate structure. The internal spacer 54 serves as an isolation feature between the subsequently formed source / drain regions and the subsequently formed gate structure. Furthermore, the internal spacer 54 can be used to prevent damage to the subsequently formed source / drain regions by subsequent etching processes (e.g., etching processes for forming the gate structure). On the other hand, the dielectric isolation layer 56 is used to isolate the plurality of upper semiconductor nanostructures 26U (commonly) from the plurality of lower semiconductor nanostructures 26L (commonly). Furthermore, the intermediate semiconductor nanostructures (a number of the plurality of semiconductor nanostructures 26 in contact with the dielectric isolation layer 56) and the dielectric isolation layer 56 define the boundaries between the lower nanostructure field-effect transistor and the upper nanostructure field-effect transistor. Because removing the dummy nanostructure 24B etches and widens a space between the plurality of intermediate semiconductor nanostructures, the dielectric isolation layer 56 can be wider than the removed dummy nanostructure 24B.

[0088] The internal spacer 54 and dielectric isolation layer 56 can be formed by conformally depositing an insulating material in the source / drain recess 46, on the sidewalls of the dummy nanostructure 24, and between the upper semiconductor nanostructure 26U and the lower semiconductor nanostructure 26L, followed by etching the insulating material. The insulating material can be a hard dielectric material, such as a carbon-containing dielectric material, such as silicon oxynitride, silicon carbide, silicon oxynitride, or the like. Other low-k materials with a dielectric constant (k-value) less than about 3.5 can be used. The insulating material can be formed via a deposition process, such as atomic layer deposition, chemical vapor deposition, or the like. The etching of the insulating material can be anisotropic or isotropic. When etched, the insulating material has portions remaining in the sidewalls of the dummy nanostructure 24A (thus forming the internal spacer 54) and portions remaining between the upper semiconductor nanostructure 26U and the lower semiconductor nanostructure 26L (thus forming the dielectric isolation layer 56).

[0089] As also Figure 4As illustrated, a lower epitaxial source / drain region 62L and an upper epitaxial source / drain region 62U are formed. The lower epitaxial source / drain region 62L is formed in the lower portion of the source / drain recess 46. The lower epitaxial source / drain region 62L is in contact with the lower semiconductor nanostructure 26L, but not with the upper semiconductor nanostructure 26U. An internal spacer 54 electrically insulates the lower epitaxial source / drain region 62L from the dummy nanostructure 24A, which will be replaced by a gate in a subsequent process.

[0090] The lower epitaxial source / drain region 62L is epitaxially grown and has a conductivity type suitable for the device type (p-type or n-type) of the lower nanostructure field-effect transistor. When the lower epitaxial source / drain region 62L is an n-type source / drain region, the corresponding material may include silicon or carbon-doped silicon doped with n-type dopants, such as phosphorus, arsenic, or the like. When the lower epitaxial source / drain region 62L is a p-type source / drain region, the corresponding material may include silicon or silicon-germanium doped with p-type dopants, such as boron, indium, or the like. The lower epitaxial source / drain region 62L may be in-situ doped and may or may not have the corresponding p-type or n-type dopants implanted. During the epitaxy of the lower epitaxial source / drain region 62L, the exposed surfaces (e.g., sidewalls) of the upper semiconductor nanostructure 26U can be masked to prevent undesirable epitaxial growth on the upper semiconductor nanostructure 26U. After the lower epitaxial source / drain region 62L has grown, the mask on the upper semiconductor nanostructure 26U can then be removed.

[0091] As a result of the epitaxial process used to form the lower epitaxial source / drain regions 62L, the upper surface of the lower epitaxial source / drain regions 62L has multiple crystal planes that extend laterally outward beyond the sidewalls of the multilayer stack 22. In some embodiments, adjacent lower epitaxial source / drain regions 62L remain separated after the epitaxial process is completed. In other embodiments, these crystal planes result in the merging of adjacent lower epitaxial source / drain regions 62L of an identical field-effect transistor.

[0092] A first contact etch stop layer (CESL) 66 and a first interlayer dielectric 68 are formed above the lower epitaxial source / drain region 62L. The first contact etch stop layer 66 may be formed of a dielectric material with high etch selectivity compared to the etching of the first interlayer dielectric 68, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, and may be formed by any suitable deposition process, such as chemical vapor deposition, atomic layer deposition, or the like. The first interlayer dielectric 68 may be formed of a dielectric material, and the deposited dielectric material may be deposited by any suitable method, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition (PECVD), or flowable chemical vapor deposition. Applicable dielectric materials for the first interlayer dielectric 68 may include silicon oxide, phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or similar materials.

[0093] The formation process may include depositing a conformal contact etch stop layer, depositing material for the first interlayer dielectric 68, followed by a planarization process, and then an etch-back process. In some embodiments, the first interlayer dielectric 68 is first etched, leaving the first contact etch stop layer 66 unetched. An anisotropic etch process is then performed to remove portions of the first contact etch stop layer 66 above the recessed first interlayer dielectric 68. After recessing, the sidewalls of the upper semiconductor nanostructure 26U are exposed.

[0094] Then, an upper epitaxial source / drain region 62U is formed on the upper portion of the source / drain recess 46. The upper epitaxial source / drain region 62U can be epitaxially grown from the exposed surface of the upper semiconductor nanostructure 26U. Depending on the desired conductivity type of the upper epitaxial source / drain region 62U, the material of the upper epitaxial source / drain region 62U can be selected from the same candidate group of materials used to form the lower epitaxial source / drain region 62L. In embodiments where the stacked transistors are complementary field-effect transistors, the conductivity type of the upper epitaxial source / drain region 62U can be opposite to that of the lower epitaxial source / drain region 62L. For example, the upper epitaxial source / drain region 62U can be doped in the opposite way to the lower epitaxial source / drain region 62L. For example, the upper epitaxial source / drain region 62U can be n-type, and the lower epitaxial source / drain region 62L can be p-type. Alternatively, the upper epitaxial source / drain region 62U can be p-type, and the lower epitaxial source / drain region 62L can be n-type. The upper epitaxial source / drain region 62U can be in-situ doped and / or implanted with n-type or p-type dopants. Multiple adjacent upper epitaxial source / drain regions 62U can remain separated after the epitaxial process, or they can be merged.

[0095] After forming the upper epitaxial source / drain region 62U, a second contact etch stop layer 70 and a second interlayer dielectric 72 are formed. The materials and formation methods may be similar to those of the first contact etch stop layer 66 and the first interlayer dielectric 68, respectively, and will not be discussed in detail here. This formation process may include depositing multiple layers for the second contact etch stop layer 70 and the second interlayer dielectric 72, and performing a planarization process to remove excess portions of the corresponding multiple layers. After the planarization process, the multiple top surfaces of the second interlayer dielectric 72, the gate spacer 44, and the mask 40 (if present) or dummy gate 38 are substantially coplanar (within process variations). Accordingly, the top surface of the mask 40 (if present) or dummy gate 38 is exposed through the second interlayer dielectric 72. In the illustrated embodiment, the mask 40 is retained after the removal process. In other embodiments, the mask 40 is removed such that the top surface of the dummy gate 38 is exposed through the second interlayer dielectric 72.

[0096] Figure 5A gate replacement process is illustrated to replace a dummy gate stack 42 and a dummy nanostructure 24A with a gate stack 90. ​​The gate replacement process includes first removing the remaining portions of the dummy gate stack 42 and the dummy nanostructure 24A. The dummy gate stack 42 is removed in one or more etching processes, thereby defining a recess between a plurality of gate spacers 44 and exposing the upper portion of a semiconductor strip 28. The remaining portions of the dummy nanostructure 24A are then removed by etching, such that the recess extends between a plurality of semiconductor nanostructures 26. In the etching process, the dummy nanostructure 24A is etched at a faster rate than the semiconductor nanostructures 26, the dielectric isolation layer 56, and the internal spacers 54. The etching can be isotropic. For example, when the dummy nanostructure 24A is formed of silicon germanium and the semiconductor nanostructure 26 is formed of silicon, the etching process may include a wet etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like.

[0097] Then, gate dielectric 78 is deposited in the recesses between the plurality of gate spacers 44 and on the exposed semiconductor nanostructure 26. Gate dielectric 78 is conformally formed on the exposed surface of the recesses (removed gate stack 42 and dummy nanostructure 24A) including the semiconductor nanostructure 26 and the gate spacers 44. In some embodiments, gate dielectric 78 surrounds all (e.g., four) sides of the semiconductor nanostructure 26. Specifically, gate dielectric 78 may be formed on the top surface of fin 20'; on the top surface, sidewalls, and bottom surface of the semiconductor nanostructure 26; and on the sidewalls of the gate spacers 44. Gate dielectric 78 may include, for example, oxides of silicon oxide or metal oxides, silicates such as metal silicates, combinations thereof, multilayers thereof, or the like. The gate dielectric 78 may comprise a high-k material having a k-value greater than about 7.0, such as a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, or combinations thereof. Methods for forming the gate dielectric 78 may include molecular beam deposition (MBD), atomic layer deposition, plasma-enhanced chemical vapor deposition, or similar processes, followed by a planarization process (e.g., chemical mechanical polishing) to remove portions of the gate dielectric 78 above the second interlayer dielectric 72. Although a single-layer gate dielectric 78 is illustrated, the gate dielectric 78 may comprise multiple layers, such as an interface layer and an overlying high-k dielectric layer.

[0098] A lower gate electrode 80L is formed on a gate dielectric 78 surrounding the lower semiconductor nanostructure 26L. For example, the lower gate electrode 80L surrounds the lower semiconductor nanostructure 26L. The lower gate electrode 80L can be formed of a metal-containing material, such as tungsten, titanium, titanium nitride, tantalum, tantalum nitride, tantalum carbide, aluminum, ruthenium, cobalt, combinations thereof, multilayers thereof, or similar materials. Although a single-layer gate electrode is illustrated, the lower gate electrode 80L may include any number of work function tuning layers, any number of barrier layers, any number of adhesive layers, and filler materials.

[0099] The lower gate electrode 80L is formed of a material suitable for the device type of a lower nanostructure field-effect transistor. For example, the lower gate electrode 80L may include one or more work function tuning layers formed of a material suitable for the device type of a lower nanostructure field-effect transistor. In some embodiments, the lower gate electrode 80L includes an n-type work function tuning layer, which may be formed of titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum carbide, combinations thereof, or the like. In some embodiments, the lower gate electrode 80L includes a p-type work function tuning layer, which may be formed of titanium nitride, tantalum nitride, combinations thereof, or the like. Additionally or alternatively, the lower gate electrode 80L may include a dipole inducing element suitable for the device type of a lower nanostructure field-effect transistor. Acceptable dipole inducing elements include lanthanum, aluminum, scandium, ruthenium, zirconium, erbium, magnesium, strontium, or combinations thereof.

[0100] The lower gate electrode 80L can be formed by conformally depositing one or more gate electrode layers and recessing the gate electrode layers. Any acceptable etching process, such as dry etching, wet etching, similar, or combinations thereof, can be performed to recess the gate electrode layers. The etching can be isotropic. Etching the lower gate electrode 80L exposes the upper semiconductor nanostructure 26U.

[0101] In some embodiments, an isolation layer (not explicitly shown) may optionally be formed on the lower gate electrode 80L. The isolation layer acts as an isolation feature between the lower gate electrode 80L and the subsequently formed upper gate electrode 80U. The isolation layer may be formed by conformally depositing a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, combinations thereof, or the like) and subsequently recessing the dielectric material to expose the upper semiconductor nanostructure 26U.

[0102] Then, an upper gate electrode 80U is formed on the isolation layer (if present) or lower gate electrode 80L described above. The upper gate electrode 80U is disposed between a plurality of upper semiconductor nanostructures 26U. In some embodiments, the upper gate electrode 80U surrounds the upper semiconductor nanostructures 26U. The upper gate electrode 80U may be formed from the same candidate materials and candidate processes used to form the lower gate electrode 80L. The upper gate electrode 80U is formed from a material suitable for the device type of the upper nanostructure field-effect transistor. For example, the upper gate electrode 80U may include one or more work function calibration layers (e.g., n-type work function calibration layers and / or p-type work function calibration layers) formed from a material suitable for the device type of the upper nanostructure field-effect transistor. Although a single-layer gate electrode 80U is illustrated, the upper gate electrode 80U may include any number of work function calibration layers, any number of barrier layers, any number of adhesive layers, and filler materials.

[0103] In addition, a removal process is performed to planarize the multiple top surfaces of the upper gate electrode 80U and the second interlayer dielectric 72. The removal process used to form the gate dielectric 78 can be the same as the removal process used to form the upper gate electrode 80U. In some embodiments, planarization processes, such as chemical mechanical polishing (CMP), etch-back processes, combinations thereof, or similar processes, can be utilized. After the planarization process, the multiple top surfaces of the upper gate electrode 80U, the gate dielectric 78, the second interlayer dielectric 72, and the gate spacer 44 are substantially coplanar (within process variations). The respective pairs of gate dielectrics 78 and gate electrodes 80 (including the upper gate electrode 80U and / or the lower gate electrode 80L) can be collectively referred to as “gate structures” 90 (including the upper gate structure 90U and the lower gate structure 90L). Each gate structure 90 extends along three sides (e.g., top surface, sidewall, and bottom surface) of the channel region of the semiconductor nanostructure 26 (see Figure 1 The lower gate structure 90L may also extend along the sidewalls and / or top surface of the semiconductor fin 20'.

[0104] As also Figure 5 As shown, a gate mask 92 is formed over a gate stack 42. This formation process may include recessing the gate stack 90, filling the resulting recess with a dielectric material such as silicon nitride, silicon carbonitride, silicon oxynitride, silicon carbonitride, or the like, and performing a planarization process to remove excess dielectric material over the second interlayer dielectric 72.

[0105] Figures 6A to 15B Cross-sectional views are shown illustrating the intermediate steps in forming the source / drain contacts leading to the upper epitaxial source / drain region 62U and the lower epitaxial source / drain region 62L. First, refer to...Figure 6A and Figure 6B An etch stop layer 104 and a third interlayer dielectric 106 are formed. In some embodiments, the etch stop layer 104 may comprise a dielectric material with high etch selectivity compared to the etch of the third interlayer dielectric 106, such as alumina, aluminum nitride, silicon carbide, or the like. The third interlayer dielectric 106 may be formed using flowable chemical vapor deposition, atomic layer deposition, or the like, and the material may include phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, undoped silicate glass, or the like, which may be deposited via any suitable method, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, or the like. The etch stop layer 104 and the third interlayer dielectric 106 may be used to help define the shape of the subsequently formed source / drain contacts.

[0106] exist Figure 7 and Figure 8 In the middle, an upper source / drain contact opening 108U and a lower source / drain contact opening 108L are formed to expose (and optionally extend to) the upper epitaxial source / drain region 62U and / or the lower epitaxial source / drain region 62L. Specifically, the lower source / drain contact opening 108L extends through the third interlayer dielectric 106, the etch stop layer 104, the second interlayer dielectric 72, the second contact etch stop layer 70, the upper epitaxial source / drain region 62U, the first interlayer dielectric 68, and / or the first contact etch stop layer 66 to expose and partially extend into the lower epitaxial source / drain region 62L, and the upper source / drain contact opening 108U extends through the third interlayer dielectric 106, the etch stop layer 104, the second interlayer dielectric 72, and the second contact etch stop layer 70 to expose and partially extend into the upper epitaxial source / drain region 62U. Each of the plurality of upper source / drain contact openings 108U may be connected to or not connected to one of the plurality of lower source / drain contact openings 108L. In the region where the upper source / drain contact opening 108U and the lower source / drain contact opening 108L are connected, the exposed upper epitaxial source / drain region 62U and the lower epitaxial source / drain region 62L can be electrically connected together via source / drain contacts subsequently formed in the connected upper source / drain contact opening 108U and lower source / drain contact opening 108L (see [reference]). Figure 15A and Figure 15BThe upper source / drain contact opening 108U and the lower source / drain contact opening 108L can be formed via a combination of sequential photolithography and etching processes. In the illustrated embodiment, the lower source / drain contact opening 108L is formed before the upper source / drain contact opening 108U. Alternatively, this order can be reversed, and the upper source / drain contact opening 108U can be formed before the lower source / drain contact opening 108L.

[0107] exist Figure 9 In this process, contact spacers 110 can be formed on the sidewalls of the upper and lower source / drain contact openings 108U / 108L. The contact spacers 110 can be formed of a low-dielectric-constant dielectric material. For example, the contact spacers 110 can comprise silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, combinations thereof, or similar materials. The contact spacers 110 can be formed by conformally depositing an insulating material layer (not explicitly shown), via chemical vapor deposition, atomic layer deposition, or similar methods. Lateral portions of the insulating material layer can then be etched away via an anisotropic etching process, such as plasma-based dry etching, to form the contact spacers 110. The contact spacers 110 help protect the materials of the first interlayer dielectric 68, the second interlayer dielectric 72, and / or the third interlayer dielectric 106 during subsequent processing steps. Furthermore, the contact spacers 110 can be used to improve the isolation between the subsequently formed source / drain contacts and adjacent features. In some implementations, the contact spacer 110 may be omitted.

[0108] exist Figure 10 In the middle, a lower silicide region 112L and an upper silicide region 112U are formed on the exposed surfaces of the lower epitaxial source / drain region 62L and the upper epitaxial source / drain region 62U, respectively. Although referred to as silicide, the upper silicide region 112U and the lower silicide region 112L can be any metal-semiconductor alloy region formed by metal silicides (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), a germanium region formed by metal germanides (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), a silicon-germanium region formed by both metal silicides and metal germanides, or similar.

[0109] Forming the upper silicide region 112U and the lower silicide region 112L can be achieved by depositing metal in the upper source / drain contact opening 108U and the lower source / drain contact opening 108L, followed by a thermal annealing process to react the metal with the semiconductor material of the upper epitaxial source / drain region 62U and the lower epitaxial source / drain region 62L. The resulting upper silicide region 112U and lower silicide region 112L may contain the deposited metal. The upper silicide region 112U and the lower silicide region 112L can be formed simultaneously (e.g., during the same process), and each contains the same metal element. The metal can be selected based on the conductivity type of the lower epitaxial source / drain region 62L to provide a relatively low barrier height to the lower epitaxial source / drain region 62L. For example, in an embodiment where the lower epitaxial source / drain region 62L is a p-type region, the metals of the upper silicide region 112U and the lower silicide region 112L can be cobalt, vanadium, niobium, nickel, tungsten, magnesium, iron, cobalt, rhodium, palladium, ruthenium, rhenium, platinum, iridium, or osmium. Alternatively, in an embodiment where the lower epitaxial source / drain region 62L is an n-type region, the metals of the upper silicide region 112U and the lower silicide region 112L can be titanium, chromium, tantalum, molybdenum, zirconium, hafnium, scandium, yttrium, holmium, terbium, gadolinium, lutetium, dysprosium, erbium, or ytterbium. In various embodiments, the barrier height difference between the lower silicide region 112L and the lower epitaxial source / drain region 62L can be less than 0.4 electron volts (eV), which advantageously allows for a reduction in the source / drain contact resistance and an improvement in device performance. The deposited metal can be deposited via deposition processes such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, or similar methods. After thermal annealing, a cleaning process, such as wet cleaning, can be performed to remove any residual metal from the upper contact opening 108U and the lower contact opening 108L (e.g., from multiple surfaces of the upper silicide region 112U and the lower silicide region 112L). In subsequent process steps, the upper silicide region 112U can be removed and replaced with another material. Thus, the upper silicide region 112U can also be referred to as a sacrificial silicide region.

[0110] Next, in Figure 11In this embodiment, source / drain contacts 114 are formed in the upper source / drain contact opening 108U and the lower source / drain contact opening 108L to electrically couple with the upper epitaxial source / drain region 62U and the lower epitaxial source / drain region 62L. As an embodiment of forming the source / drain contacts 114, a gasket (e.g., a diffusion barrier layer, an adhesive layer, or the like) (not shown separately) and conductive material are formed in the upper source / drain contact opening 108U and the lower source / drain contact opening 108L. The gasket may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be cobalt, ruthenium, molybdenum, tungsten, copper, copper alloys, silver, gold, aluminum, nickel, or the like, formed via plating processes, physical vapor deposition, chemical vapor deposition, atomic layer deposition, or the like. A removal process can be performed to remove excess material from the top surface of the third interlayer dielectric 106. The remaining pads and conductive material form source / drain contacts 114 in the upper source / drain contact opening 108U and the lower source / drain contact opening 108L. In some embodiments, a planarization process, such as chemical mechanical polishing, etch-back, a combination thereof, or similar, is utilized. After the planarization process, the multiple top surfaces of the source / drain contacts 114, the contact spacers 110, and the third interlayer dielectric 106 are substantially coplanar (within process variations). Furthermore, in embodiments where the contact spacers 110 are omitted, the source / drain contacts 114 (e.g., the pads of the source / drain contacts 114) may be formed to directly contact the sidewalls of the third interlayer dielectric 106, the etch stop layer 104, the second interlayer dielectric 72, and / or the second contact etch stop layer 70.

[0111] exist Figures 12 to 14 In the middle, the upper silicide region 112U is replaced by an upper silicide region 118, which contains a different metal element than the lower silicide region 112L. First, refer to... Figure 12An etching process is performed to recess the source / drain contacts 114 and remove the upper silicide region 112U, exposing the upper epitaxial source / drain region 62U. Recessing the source / drain contacts 114 can be performed via an etching process that selectively etches the source / drain contacts 114 at a faster rate than etching the third interlayer dielectric 106, the contact spacer 110, and the upper epitaxial source / drain region 62U. Subsequently, the upper silicide region 112U is removed from the source / drain contact opening 116, for example, via a timed etching process. The timed etching process can be a selective process that selectively etches the upper silicide region 112U at a faster rate than etching the third interlayer dielectric 106, the contact spacer 110, and the source / drain contacts 114. In some embodiments, removing the upper silicide region 112U may also involve etching the upper portion of the upper epitaxial source / drain region 62U exposed by the source / drain contact opening 116. After removing the upper silicide region 112U, the lower portion of the source / drain contact 114 remains and is electrically connected to the lower epitaxial source / drain region 62L through the lower silicide region 112L, and the source / drain contact 114 may be referred to hereinafter as the lower source / drain contact 114.

[0112] exist Figure 13 In this process, an optional epitaxial re-growth process can be performed to re-grow the material of the upper epitaxial source / drain region 62U. The epitaxial re-growth process can be similar to those processes discussed above regarding the upper epitaxial source / drain region 62U, and the re-grown material can be the same as the upper epitaxial source / drain region 62U. In some embodiments, the epitaxial re-growth process is a low-temperature process (e.g., performed at temperatures below 400°C) to avoid thermal damage to the upper epitaxial source / drain region 62U and the lower epitaxial source / drain region 62L. The epitaxial re-growth process can be selective or non-selective for the material of the upper epitaxial source / drain region 62U. The epitaxial re-growth process can compensate for unintentional over-etching of the upper epitaxial source / drain region 62U due to the removal of the upper silicide region 112U. As a result of the epitaxial re-growth process, the upper epitaxial source / drain region 62U may overlap with the contact spacer 110 and / or the lower source / drain contact 114. The re-growth process is optional and can be omitted in embodiments where the remaining volume of the upper epitaxial source / drain region 62U is sufficient after removing the upper silicide region 112U (see, for example...). Figure 15B ).

[0113] exist Figure 14In the upper epitaxial region 118, an upper silicide region 118 is formed on the exposed surface of the upper epitaxial source / drain region 62U. Although referred to as a silicide, the upper silicide region 118 can be any metal-semiconductor alloy region formed by metal silicides (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), a germanium region formed by metal germanides (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), a silicon-germanium region formed by metal silicides and metal germanides, or similar.

[0114] The upper silicide region 118 can be formed by depositing metal in the source / drain contact opening 116 followed by a thermal annealing process. The thermal annealing process reacts the metal with the semiconductor material of the upper epitaxial source / drain region 62U. The upper silicide region 118 can be made of different metal elements and has a different composition than the lower silicide region 112L. Specifically, the metal can be selected based on the conductivity type of the upper epitaxial source / drain region 62U to provide a relatively low barrier height for the upper epitaxial source / drain region 62U. For example, in embodiments where the upper epitaxial source / drain region 62U is a p-type region, the metal of the upper silicide region 118 can be cobalt, vanadium, niobium, nickel, tungsten, magnesium, iron, cobalt, rhodium, palladium, ruthenium, rhenium, platinum, iridium, or osmium. Alternatively, in embodiments where the upper epitaxial source / drain region 62U is an n-type region, the metal of the upper silicide region 118 can be titanium, chromium, tantalum, molybdenum, zirconium, hafnium, scandium, yttrium, holmium, terbium, gadolinium, lutetium, dysprosium, erbium, or ytterbium. In various embodiments, the barrier height difference between the upper silicide region 118 and the upper epitaxial source / drain region 62U can be less than 0.4, which advantageously allows for a reduction in the source / drain contact resistance and an improvement in device performance. The deposited metal can be deposited via deposition processes such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, or the like. After the thermal annealing process, a cleaning process, such as wet cleaning, can be performed to remove any residual metal from the source / drain contact opening 116 (e.g., from the surface of the upper silicide region 118). Because the upper silicide region 118 and the lower silicide region 112L are formed from separate materials in separate steps, each of the upper silicide region 118 and the lower silicide region 112L can be formed to have a reduced barrier height for the corresponding one of the upper epitaxial source / drain region 62U and the lower epitaxial source / drain region 62L. This allows for an effective reduction in the source / drain contact resistance of each of the upper epitaxial source / drain region 62U and the lower epitaxial source / drain region 62L in the resulting device. Furthermore, the described method uses a stacked configuration of stacked transistors to form the upper silicide region 118 and the lower silicide region 112L separately without adding an additional masking step to the overall process.

[0115] As illustrated, the upper silicide region 118 may contact and connect different portions of the contact spacer 110. For example, the upper silicide region 118 may be positioned from the bottom of the upper contact spacer 110 (e.g., in the second interlayer dielectric 72 and surrounding the subsequently formed upper source / drain contact 120, see [reference]). Figure 15A and Figure 15B The upper silicide regions extend to the top of the lower contact spacer 110 (e.g., in the first interlayer dielectric 68 and surrounding the lower source / drain contact 114). Furthermore, several adjacent upper silicide regions 118 may have different bottom surface profiles. The profile of each of the multiple upper silicide regions 118 may depend on the profile of the corresponding upper epitaxial source / drain region 62U formed therein. For example, in... Figure 14 In the middle, the upper right silicide region 118 has a convex, curved bottom profile, while the upper left silicide region 118 has a linear bottom profile. Similarly, the bottom widths of the adjacent plurality of upper silicide regions 118 may also differ, depending on the width of the corresponding upper epitaxial source / drain region 62U of the upper silicide region 118 in which it is formed.

[0116] Next, in Figure 15A and Figure 15B In the middle, an upper source / drain contact 120 is formed in the source / drain contact opening 116 to electrically couple with the upper epitaxial source / drain region 62U through the upper silicide region 118. Figure 15A An embodiment is illustrated in which an epitaxial re-growth process is performed after the removal of the upper silicide region 112U and before the formation of the upper silicide region 118 to re-grow a portion of the source / drain region 62U of the upper epitaxial layer. Figure 15B An implementation method omitting the epitaxial growth process is illustrated. The upper silicide region 118 can cover the entire bottom surface of the upper source / drain contacts 120 (see [reference needed]). Figure 15A and Figure 15B The upper left source / drain contact 120 in the middle) or only partially covers the bottom surface of the upper source / drain contact (see in Figure 15A and Figure 15B (See the upper right source / drain contact 120 in the image). In the case where the upper silicide region 118 only partially covers the bottom surface of the upper source / drain contact, the width of the upper silicide region 118 may be smaller than the width of the bottom surface of the upper source / drain contact (see in...). Figure 15A and Figure 15B (Source / drain contact 120 on the upper right side).

[0117] In one embodiment of forming the upper source / drain contact 120, a pad (not shown separately) (e.g., a diffusion barrier layer, an adhesion layer, or the like) and a conductive material are formed in the source / drain contact opening 116. The pad may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be cobalt, ruthenium, molybdenum, tungsten, copper, copper alloys, silver, gold, aluminum, nickel, or the like, formed via plating processes, physical vapor deposition, chemical vapor deposition, or atomic layer deposition. A removal process may be performed to remove excess material from the top surface of the third interlayer dielectric 106. The remaining pad and conductive material form the upper source / drain contact 120 in the source / drain contact opening 116. In some embodiments, planarization processes, such as chemical mechanical planarization, etch-back processes, combinations thereof, or the like, are utilized. After the planarization process, the multiple top surfaces of the upper source / drain contacts 120, contact spacers 110, and the third interlayer dielectric 106 are substantially coplanar (within process variations).

[0118] The upper source / drain contact 120 can also be electrically coupled to the lower epitaxial source / drain region 62L via the lower source / drain contact 114. For example, the upper source / drain contact 120 and the lower source / drain contact 114 can be physically contacted at a shared interface, and the upper source / drain contact 120 and the lower source / drain contact 114 can jointly electrically couple the vertically stacked upper epitaxial source / drain region 62U and lower epitaxial source / drain region 62L together. The upper source / drain contact 120 and the lower source / drain contact 114 can be formed of the same material or different materials. In some embodiments, even when the same material is used to form the upper source / drain contact 120 and the lower source / drain contact 114, an interface exists between the materials of the upper source / drain contact 120 and the lower source / drain contact 114. This interface between the materials of the upper source / drain contact 120 and the lower source / drain contact 114 can be generated by the upper source / drain contact 120 and the lower source / drain contact 114 in separate processes, with a vacuum interruption occurring between the formation of the upper source / drain contact 120 and the formation of the lower source / drain contact 114. The interface between the upper source / drain contact 120 and the lower source / drain contact 114 can be disposed within the upper epitaxial source / drain region 62U, for example, at a level below the top surface and above the bottom surface of the upper epitaxial source / drain region 62U. In some embodiments, the material of the lower source / drain contact 114 may have relatively low resistance, such as ruthenium, molybdenum, or the like, while the upper source / drain contact 120 may be formed of a material with improved gap-filling properties, such as tungsten, or the like. Other combinations of materials are possible for the upper source / drain contact 120 and the lower source / drain contact 114.

[0119] Because the lower source / drain contact 114 partially extends through some of the upper epitaxial source / drain regions, the volume of some of the upper epitaxial source / drain regions (e.g., the upper left epitaxial source / drain region 62U) may be larger than that of other upper epitaxial source / drain regions (e.g., the upper right epitaxial source / drain region 62U). For example, in a cross-sectional view, the width of some of the upper epitaxial source / drain regions (e.g., the upper left epitaxial source / drain region 62U) may be greater than that of other upper epitaxial source / drain regions (e.g., the upper right epitaxial source / drain region 62U). Furthermore, the effective volume and / or cross-sectional width of the upper epitaxial source / drain regions 62U may differ from (e.g., be greater than or less than) the effective volume and / or cross-sectional width of the lower epitaxial source / drain regions 62L. Specifically, the effective volume of each of the upper epitaxial source / drain region 62U and / or the lower epitaxial source / drain region 62L can be configured based on the desired device type of the upper transistor and / or the lower transistor.

[0120] exist Figure 16 In this process, gate contacts 108 are formed to contact the upper gate electrode 80U. The formation of gate contacts 108 can occur before or after the formation of source / drain contacts 114 / 120. As one embodiment of the formation of gate contacts 108, an opening for the gate contacts 108 extends through the third interlayer dielectric 106 and the etch stop layer 104. Multiple openings can be formed using acceptable photolithography and etching techniques. Pads (not shown separately) (e.g., diffusion barrier layers, adhesion layers, or the like) and conductive material are formed within the openings. Pads may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. Conductive material may be cobalt, tungsten, copper, copper alloys, silver, gold, aluminum, nickel, or the like. A planarization process, such as chemical mechanical polishing, can be performed to remove excess material from the top surface of the third interlayer dielectric 106. The remaining pads and conductive material form the gate contacts 108 within the openings.

[0121] A front interconnect structure 128 is formed on a device layer 122 (a layer containing stacked transistors, gate contacts 108, upper source / drain contacts 120, and lower source / drain contacts 114). The front interconnect structure 128 includes a dielectric layer 124 and conductive features 126 of multiple layers within the dielectric layer 124. The dielectric layer 124 may include a low-dielectric-constant dielectric layer formed of a low-dielectric-constant dielectric material. The dielectric layer 124 may also include a passivation layer formed of a non-low-dielectric-constant and dense dielectric material, such as undoped silicate glass (USG), silicon oxide, silicon nitride, or similar materials or combinations thereof over a low-dielectric-constant dielectric material. The dielectric layer 124 may also include a polymer layer.

[0122] Conductive feature 126 may include wires and vias, and may be formed using an inlay process. Conductive feature 126 may include metal wires and metal vias, which include a diffusion barrier layer and a copper-containing material above the diffusion barrier layer. An aluminum pad may also be present above the metal wires and vias and electrically connected to them.

[0123] In some embodiments, the lower gate stack 90L and the lower epitaxial source / drain region 62L can be contacted via the back side of device layer 122 (e.g., the side opposite to the front interconnect structure 128). For example, Figure 17A and Figure 17B A device layer 122 is illustrated between the front interconnect structure 128 and the back interconnect structure 134. The back interconnect structure 134 may be substantially similar to the front interconnect structure 128 as described above. Figure 17A and Figure 17B In the text, the same reference numerals respectively indicate the components of the system and... Figure 15A and Figure 15B The same components are formed using the same process described above. Figure 17A An embodiment is illustrated in which an epitaxial re-growth process is performed after the removal of the upper silicide region 112U and before the formation of the upper silicide region 118 to re-grow a portion of the source / drain region 62U of the upper epitaxial layer. Figure 17B The implementation method omitting the epitaxial regeneration process is illustrated.

[0124] A contact via 130 (with contact spacers 132 disposed on its sidewalls) is formed to extend through at least partially through the device layer 122. The contact via 130 may be formed from a similar material and using a similar process to that described above for the upper source / drain contact 120 and the lower source / drain contact 114, and the contact spacers 132 may be formed from a similar material and using a similar process to that described above for the contact spacers 110. The contact via 130 and contact spacers 132 may be formed through the first contact etch stop layer 66, the first interlayer dielectric 68, the second contact etch stop layer 70, and the second interlayer dielectric 72 before the formation of the etch stop layer 104 and the third interlayer dielectric 106. The contact via 130 may be electrically connected to the back-side interconnect structure 134, and may also be electrically connected to the front-side interconnect structure 128 (e.g., through the upper source / drain contact 120). In this way, interconnection between the front interconnect structure 128 and the back interconnect structure 134 can be achieved.

[0125] Although the various embodiments are described using a front-side source / drain contact 120 that electrically connects the upper epitaxial source / drain region 62U to the lower epitaxial source / drain region 62L, the various embodiments can be applied to a back-side source / drain contact instead of a front-side source / drain contact. For example, the above-mentioned contact can be applied from the back side of the device layer 122. Figures 6A to 15B The various process steps described herein are used to provide back-side source / drain contacts that electrically connect the lower epitaxial source / drain region 62L to the upper epitaxial source / drain region 62U. Silicide regions of different materials can also be selectively formed to the lower epitaxial source / drain region 62L and the upper epitaxial source / drain region 62U through the contact openings of the back-side source / drain contacts. Furthermore, the back-side source / drain contacts can be formed before or after the front-side source / drain contacts.

[0126] In various embodiments, n-type and p-type transistors use different materials for the silicide regions, which are specifically selected to reduce the barrier height of their respective source / drain regions. This reduces the source / drain contact resistance in the stacked transistors, thereby improving overall device performance. The configuration of these stacked transistors allows for the formation of silicide regions with different materials without significantly complicating the fabrication process.

[0127] In some embodiments, the semiconductor device includes a first source / drain region; a first silicide region on the first source / drain region; a first nanostructure adjacent to the first source / drain region; a second source / drain region overlapping the first source / drain region; a second silicide region on the second source / drain region, wherein the first silicide region comprises a first metal, the first metal being different from a second metal comprised in the second silicide region; a second nanostructure adjacent to the second source / drain region; a first gate structure surrounding the first nanostructure; and a second gate structure overlapping the first gate structure and surrounding the second nanostructure. In some embodiments, the first source / drain region has a conductivity type opposite to that of the second source / drain region. In some embodiments, the barrier height difference between the first silicide region and the first source / drain region is less than 0.4 eV. In some embodiments, the barrier height difference between the second silicide region and the second source / drain region is less than 0.4 eV. In some embodiments, the device further includes a lower source / drain contact connected to a first source / drain region via a first silicide region; and an upper source / drain contact connected to a second source / drain region via a second silicide region, wherein the upper source / drain contact overlaps with the lower source / drain contact. In some embodiments, an interface between the upper and lower source / drain contacts is disposed within the second source / drain region. In some embodiments, the lower source / drain contact is made of a third metal, while the upper source / drain contact is made of a fourth metal, the fourth metal having a different composition from the third metal. In some embodiments, the lower source / drain contact is made of a third metal, while the upper source / drain contact is made of a fourth metal, the fourth metal having the same composition as the third metal.

[0128] In some embodiments, a method includes patterning a first opening that extends through one or more dielectric layers to expose a first source / drain region and a second source / drain region, wherein the second source / drain region overlaps with the first source / drain region; forming a first silicide region on the first source / drain region in the first opening, and forming a second silicide region on the second source / drain region; forming a first source / drain contact in the first opening over the first and second silicide regions; etching the first source / drain contact to define a second opening that exposes the second silicide region; replacing the second silicide region on the second source / drain region in the second opening with a third silicide region; and forming a second source / drain contact in the second opening, wherein the first source / drain contact is electrically coupled to the first source / drain region through the first silicide region, and wherein the second source / drain contact is electrically coupled to the second source / drain region through the second silicide region. In some embodiments, each of the first and second silicide regions comprises a first metal, which is different from the second metal comprised in the third silicide region. In some embodiments, the first metal is selected based on the conductivity type of the first source / drain region, and the second metal is selected based on the conductivity type of the second source / drain region. In some embodiments, the first source / drain contacts are electrically coupled to the second source / drain contacts. In some embodiments, replacing the second silicide region with the third silicide region comprises: removing the second silicide region using an etching process, wherein the etching process further comprises etching the second source / drain region; and forming the third silicide region on the second source / drain region after the etching process. In some embodiments, this method further comprises performing an epitaxial regeneration process on the second source / drain region before forming the third silicide region. In some embodiments, the first source / drain contacts are made of a third metal, and the second source / drain contacts are made of a fourth metal, the fourth metal having a different composition from the third metal. In some embodiments, the first source / drain contact is made of a third metal, while the second source / drain contact is made of a fourth metal having the same composition as the third metal.

[0129] In some embodiments, a method includes patterning a first opening that extends through one or more dielectric layers to expose a first source / drain region and a second source / drain region, wherein the second source / drain region overlaps with the first source / drain region and has a conductivity type opposite to that of the first source / drain region; forming a first silicide region on the first source / drain region in the first opening, the first silicide region comprising a first metal; forming a first source / drain contact in the first opening and extending to the first silicide region; etching the first source / drain contact to define a second opening; forming a second silicide region on the second source / drain region in the second opening; and forming a second source / drain contact in the second opening and extending to the second silicide region. In some embodiments, the method further includes forming a third silicide region on a second source / drain region in a first opening, wherein etching the first source / drain contacts exposes the third silicide region, and the third silicide region comprises a first metal; and performing an etching process to remove the third silicide region from the second opening prior to forming the second silicide region. In some embodiments, the etching process removes an upper portion of the second source / drain region, and wherein this method further includes performing an epitaxial process to regrow material of the second source / drain region. In some embodiments, the second silicide region comprises a second metal, which is different from the first metal.

[0130] The foregoing outlines several features of various embodiments, enabling those skilled in the art to better understand the multiple variations of this disclosure. Those skilled in the art should understand that they may readily use this disclosure as the basis for the design or modification of other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also understand that equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, Include: First source / drain region; A first silicide region on the first source / drain region; Multiple first nanostructures are located adjacent to the first source / drain region; A second source / drain region overlaps with the first source / drain region; A second silicide region on the second source / drain region, wherein the first silicide region contains a first metal, the first metal being different from a second metal contained in the second silicide region; Multiple second nanostructures are located adjacent to the second source / drain region; A first gate structure, surrounding the plurality of first nanostructures; and A second gate structure overlaps with the first gate structure and surrounds the plurality of second nanostructures.

2. The semiconductor device as claimed in claim 1, characterized in that, The first source / drain region has a conductivity type that is opposite to that of the second source / drain region.

3. The semiconductor device as claimed in claim 1, characterized in that, The barrier height difference between the first silicide region and the first source / drain region is less than 0.4 eV.

4. The semiconductor device as claimed in claim 1, characterized in that, Also includes: A lower source / drain contact is connected to the first source / drain region through the first silicide region; and An upper source / drain contact is connected to the second source / drain region through the second silicide region, wherein the upper source / drain contact overlaps with the lower source / drain contact.

5. A method for forming a semiconductor device, characterized in that, Include: A first opening is patterned through one or more dielectric layers to expose a first source / drain region and a second source / drain region, wherein the second source / drain region overlaps with the first source / drain region. A first silicide region is formed on a first source / drain region in the first opening, and a second silicide region is formed on the second source / drain region; A first source / drain contact is formed in a first opening above the first silicide region and the second silicide region; The first source / drain contact is etched to define a second opening that exposes the second silicide region. The second silicide region is replaced by a third silicide region in the second opening on the second source / drain region; as well as A second source / drain contact is formed in the second opening, wherein the first source / drain contact is electrically coupled to the first source / drain region through the first silicide region, and wherein the second source / drain contact is electrically coupled to the second source / drain region through the second silicide region.

6. The method for forming a semiconductor device as described in claim 5, characterized in that, The first silicide region and the second silicide region each contain a first metal, which is different from a second metal contained in the third silicide region.

7. The method for forming a semiconductor device as described in claim 5, characterized in that, The first source / drain contact is electrically coupled to the second source / drain contact.

8. The method for forming a semiconductor device as described in claim 5, characterized in that, Replacing the second silicide region with the third silicide region includes: The second silicide region is removed using an etching process, wherein the etching process further includes etching the second source / drain region; and Following the etching process, the third silicide region is formed on the second source / drain region.

9. A method for forming a semiconductor device, characterized in that, Include: A first opening is patterned through one or more dielectric layers to expose a first source / drain region and a second source / drain region, wherein the second source / drain region overlaps with the first source / drain region and has a conductivity type opposite to that of the first source / drain region. A first silicide region is formed on the first source / drain region in the first opening, and the first silicide region contains a first metal; A first source / drain contact is formed in the first opening and extends into the first silicide region; The first source / drain contact is etched to define a second opening; A second silicide region is formed on a second source / drain region in the second opening; as well as A second source / drain contact is formed in the second opening and extends into the second silicide region.

10. The method of forming a semiconductor device as claimed in claim 9, characterized in that, Also includes: A third silicide region is formed on the second source / drain region in the first opening, wherein the first source / drain contacts are etched to expose the third silicide region, and the third silicide region contains the first metal; and Before the second silicide region is formed, an etching process is performed to remove the third silicide region from the second opening.

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