Epitaxial structure for improving antistatic capability of Micro LED and growth method

Abstract

The invention discloses an epitaxial structure for improving the antistatic capability of a Micro LED and a growth method. The epitaxial structure sequentially comprises a substrate, a buffer layer, a non-doped GaN layer, an n-type GaN layer, a stress release layer, a multi-quantum well light-emitting layer, a low-temperature p-type GaN layer, an electron blocking layer and a P-type GaN layer in the growth direction. Wherein the crystal island growth layer adopts a three-section growth process to block an electric leakage channel; the stress release layer is constructed into a V-shaped pit regulation and control layer and is used for accurately controlling the opening size of a V-shaped pit to be 240-300nm; and the P-type GaN layer adopts a double-section structure of low-temperature V-shaped pit filling and high-temperature flat growth. Through the synergistic effect of bottom-layer crystal quality optimization, middle-layer V-shaped pit regulation and control and top-layer P layer leveling, the anti-static capacity of the Micro LED under the miniature size is remarkably improved, and meanwhile excellent photoelectric performance and surface flatness are considered.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor optoelectronics, in particular to an epitaxial structure for improving the anti-static capability of Micro LED and a growth method. BACKGROUND

[0002] GaN materials are widely used in the fields of LED light-emitting diodes and power electronic devices. In recent years, Micro LED full-color display is considered as the ultimate goal of future display, from large-size cinema screens to small watches, the market has extremely high requirements for pixel density and display effect. This also promotes the continuous miniaturization of Micro LED chip size, from 200 microns to 100 microns, 50 microns or even 30 microns.

[0003] However, with the miniaturization of chip size, the anti-static capability (ESD) of Micro LED is dramatically weakened. During the processing, the chip is prone to failure due to static breakdown, resulting in a decrease in yield; more seriously, some chips have a "dead point" after being made into finished products, causing frequent complaints.

[0004] The prior art usually adopts the following ways to improve the ESD capability: 1. Bottom layer optimization: improve the crystal quality of the bottom layer to reduce defects, but this often leads to an increase in voltage or insufficient V-pit density, affecting the light efficiency.

[0005] 2. Increase the carrier concentration: increase the carrier concentration in the depletion region, but this will introduce more non-radiative recombination centers, reducing the internal quantum efficiency.

[0006] 3. Increase the thickness of the P layer: although it can significantly improve the ESD, but if the growth control is not proper, the P layer will be easy to cause surface roughness, leakage, and the P-type GaN layer will absorb a large number of photons, reducing the external quantum efficiency.

[0007] Therefore, there is an urgent need for a new epitaxial structure design that can significantly improve the anti-static capability while considering the voltage, brightness and surface flatness in the case of Micro LED size miniaturization. SUMMARY

[0008] The purpose of the present application is to provide an epitaxial structure for improving the anti-static capability of Micro LED and a growth method, which solves the problem of sacrificing photoelectric performance when improving the ESD capability of the prior art by synergistically optimizing the growth of the bottom layer crystal island, the regulation of the middle layer stress and V-pit, and the growth of the top P layer.

[0009] To achieve the above purpose, the present application provides the following technical solutions: An epitaxial structure for improving the anti-static capability of a Micro LED, comprising, in sequence along a growth direction: a substrate, a buffer layer, a non-doped GaN layer, an n-type GaN layer, a stress release layer, a multi-quantum well light emitting layer, a low-temperature p-type GaN layer, an electron blocking layer, and a p-type GaN layer; The non-doped GaN layer is a controllable defect density crystal island growth layer, comprising, in sequence along a growth direction: a crystal island merging growth sublayer, a crystal island longitudinal growth sublayer, and a gap filling sublayer. The stress release layer is configured as a V-shaped pit control layer for controlling the opening size of the V-shaped pit on the surface of the epitaxial layer within a range of 240nm to 300nm, and the stress release layer comprises, in sequence: an opening consistency control sublayer, an opening size adjustment cycle sublayer, and an opening size adjustment doped sublayer. The p-type GaN layer is of a double-section structure, comprising a low-temperature V-shaped pit filling sublayer and a high-temperature flattening sublayer.

[0010] The crystal island merging growth sublayer is configured to promote the merging of crystal islands on a C-plane platform; the longitudinal growth rate of the crystal island longitudinal growth sublayer is greater than the transverse growth rate, and the height thereof matches the height of the substrate patterning structure; and the gap filling sublayer is used to fill the gap between the crystal islands and the substrate patterning structure.

[0011] The opening consistency control sublayer in the stress release layer is a low-temperature low-growth-rate Si-doped GaN layer; the opening size adjustment cycle sublayer comprises alternatingly grown Si-doped GaN layers and In-doped GaN layers; and the opening size adjustment doped sublayer comprises a first-stage Si-doped GaN layer and a second-stage Si-In co-doped GaN layer.

[0012] The low-temperature V-shaped pit filling sublayer in the p-type GaN layer is a Mg-doped GaN layer grown in a high-hydrogen atmosphere; and the high-temperature flattening sublayer is a Mg-doped GaN layer, and the growth temperature of the high-temperature flattening sublayer is higher than that of the low-temperature V-shaped pit filling sublayer.

[0013] A growth method of the above-mentioned epitaxial structure, comprising the following steps: S1: growing a buffer layer on a substrate; S2: growing a non-doped GaN layer, which comprises growing a controllable defect density crystal island growth layer by using a three-section variable-temperature variable-pressure process; S3: growing an n-type GaN layer; S4: growing a stress release layer, which comprises growing an opening consistency control sublayer, an opening size adjustment cycle sublayer, and an opening size adjustment doped sublayer by adjusting the growth temperature and the doping flow rate, so as to control the opening size and consistency of the V-shaped pit; S5: growing a multi-quantum well light emitting layer; S6: growing a low-temperature p-type GaN layer; S7: Growth of electron blocking layer; S8: Growth of P-type GaN layer. This step includes first growing a V-shaped pit-filled sublayer under low temperature and high hydrogen atmosphere, and then growing a high temperature smooth sublayer.

[0014] In step S2, the three-stage growth process of the crystal island growth layer is specifically as follows: First stage of growth: At 1030℃~1050℃ and 150 torr~250 torr pressure, H2 and NH3 are introduced to carry out lateral merging growth; Second stage growth: At 1070℃~1090℃, N2 is cut off, and only H2 and NH3 are introduced, with the V / III ratio lower than in the first stage, to carry out longitudinal dominant growth; The third stage of growth: at 1110℃~1130℃, N2 is cut off, NH3 flow is increased, and gap-filling growth is carried out.

[0015] In step S4, the growth temperature of the opening consistency control sublayer is 850℃~870℃, and the growth rate is controlled at 0.3μm / h~0.5μm / h; the opening size adjustment cycle sublayer consists of 3~6 cycles of alternating growth of Si-doped GaN / In-doped GaN.

[0016] In step S7, the growth temperature of the low-temperature V-shaped pit filling sublayer is 930℃~950℃, and the flow ratio of H2 to NH3 is 7:3 to 2.5:1 to accelerate the filling of the V-shaped pit.

[0017] The growth method is applied to the fabrication of Micro LED epitaxial wafers, wherein the chip size of the Micro LED is less than or equal to 100 micrometers.

[0018] The beneficial effects of this invention are as follows: 1. Significantly improved anti-static capability: By optimizing the bottom crystal island to block leakage channels, combined with the effective wrapping of dislocations by the middle V-shaped pit, and the current spread protection of the top P-type GaN layer, the three work together to significantly improve the ESD yield of Micro LEDs in extremely small sizes.

[0019] 2. Maintaining high luminous efficiency and excellent electrical properties: Precise control of the V-shaped pit size avoids the loss of effective light-emitting area due to excessively large V-pits; the dual-segment P-layer design reduces photon absorption. Tests show that this structure improves ESD while maintaining or even optimizing the device's brightness and voltage performance.

[0020] 3. Excellent surface quality: The two-segment P-layer growth method effectively solves the surface roughness problem that is easily generated by traditional P-type GaN layers, and improves the yield of subsequent chip manufacturing processes. Attached Figure Description

[0021] Figure 1 This is a detailed structural diagram of each key functional layer in an embodiment of the present invention.

[0022] Figure 2 This is a schematic diagram of the crystal island merging and growth stage.

[0023] Figure 3 This is a schematic diagram of the vertical growth and expansion stages of a crystal island.

[0024] Figure 4 This is a schematic diagram of the crystal island gap filling stage.

[0025] Figure 5 This is a schematic diagram of the structural cross-section after the growth of the V-shaped pit control layer. Detailed Implementation

[0026] The following is in conjunction with the appendix Figures 1 to 5 The specific embodiments of the present invention will be described in detail below.

[0027] Example 1

[0028] like Figure 1 As shown, this invention provides an epitaxial structure for improving the antistatic capability of blue-green Micro LEDs. The structure, along the growth direction, sequentially includes: a substrate 100, a buffer layer 200, an undoped GaN layer 300, an n-type GaN layer 400, a stress relief layer 500, an MQW (Multi-Level Wave) emitting layer 600, a low-temperature p-type GaN layer 700, an electron blocking layer 800, and a p-type GaN layer 900. The undoped GaN layer 300 includes an island merging growth sublayer 301, an island longitudinal growth strengthening sublayer 302, and a gap-filling sublayer 303. The stress relief layer 500 consists of an opening consistency control layer 501, an opening size adjustment circulation layer 502, and an opening size adjustment doped layer 503. The p-type GaN layer 900 consists of a low-temperature V-shaped pit filling sublayer 901 and a high-temperature flattening sublayer 902.

[0029] The preparation method and specific structure of each layer in this embodiment are as follows: 1. Substrate and bottom layer growth First, a substrate 100 is provided, in this embodiment a patterned sapphire substrate (PSS). A buffer layer 200 is deposited on the substrate 100, followed by the growth of an undoped GaN layer 300.

[0030] 2. Fabrication of undoped GaN layer 300 To reduce the density of through dislocations and improve antistatic properties, the undoped GaN layer 300 is grown using a three-stage process, corresponding to... Figure 2 , Figure 3 andFigure 4 The growth stages shown: First section (crystal island merging to grow sublayer 301): as follows Figure 2 As shown, the growth pressure was controlled at 150 torr to 250 torr, the growth speed at 700 rpm to 900 rpm, and the growth temperature at 1030℃ to 1050℃. N2, H2, and NH3 were introduced in a flow ratio of 8:2:1, with the NH3 flow rate ranging from 55 to 75 L / min. Growth was carried out for 30 seconds to 5 minutes, causing GaN islands to coalesce on the 100 mm C-Plane platform of the substrate and grow longitudinally.

[0031] Second section (vertical growth of crystal islands to strengthen sublayer 302): For example... Figure 3 As shown, while maintaining constant pressure and rotation speed, the growth temperature was increased to 1070℃~1090℃. N2 was cut off, and the H2:NH3 ratio was adjusted to between 8:1 and 6:1, with the NH3 flow rate reduced to 45~60 L / min. Growth was continued for 2~4 minutes. During this stage, the longitudinal growth rate was greater than the transverse growth rate, allowing the GaN layer height to reach a level comparable to the PSS height.

[0032] Third section (gap filling sub-layer 303): As... Figure 4 As shown, while maintaining constant pressure and rotation speed, the growth temperature was further increased to 1110℃~1130℃. With N2 at 0, the H2:NH3 ratio was adjusted to between 7:1 and 5:1, and the NH3 flow rate was increased to 95~115 L / min. Growth was continued for 7~10 minutes to quickly fill the gap between the GaN layer and the PSS.

[0033] 3. Fabrication of n-type GaN layer 400 and stress relief layer 500 An n-type GaN layer 400 is grown on top of the island growth layer 300, followed by a stress relief layer 500. The stress relief layer 500 is configured as a V-pit control layer to control the opening size of the V-pits within the range of 240 nm to 300 nm. Figure 5 As shown, the morphology of the V-shaped pits in this layer is controlled by specific growth conditions, including: Opening consistency control layer 501: Growth pressure 200 torr~250 torr, rotation speed 500 rpm~600 rpm, temperature 850℃~870℃. H2 shut off, N2:NH3 ratio 3:2, NH3 flow rate 100~140 L / min. TMGa is used as the gallium source, doped with Si (concentration 1.0×10⁻⁶). 18 ~1.5×10 18 cm -3The growth thickness was 50 nm, and the growth rate was controlled at 0.3–0.5 μm / h. This layer utilizes low temperature and low growth rate conditions to induce through-dislocations to open into a V-shape with better depth uniformity.

[0034] Crop layer 502 with adjustable aperture size: Growth temperature 880℃~900℃, consisting of 3~6 cycles. Each cycle includes: a Si-doped GaN layer (using TMGa, thickness 25nm~30nm, Si concentration 1.0×10⁻⁶). 18 ~1.5×10 18 cm -3 The system consists of an In-doped GaN layer (using TEGa, 2.5 nm thick). This layer is used to adjust the opening of the V-shaped pits.

[0035] The aperture size adjustment of the 503 doped layer: It is grown in two parts. The first part is a high-concentration Si-doped GaN (Si concentration 5.0 × 10⁻⁶). 18 ~8.0×10 18 cm -3 The first part is 25nm~33nm thick; the second part is Si and In co-doped GaN (In flux 50~100 sccm). This layer further precisely determines the final opening size of the V-shaped pit.

[0036] 4. Growth of the luminescent region and P-side structure An MQW light-emitting layer 600, a low-temperature p-type GaN layer 700, and an electron blocking layer 800 are sequentially grown on top of the stress relief layer 500.

[0037] MQW emitting layer 600: After the stress relief layer 500 is grown, the growth pressure is adjusted to 200 torr~400 torr, and 9~12 cycles of InGaN / GaN multiple quantum wells are grown. Each cycle includes: first, a 2.5nm~3nm thick InGaN well layer is grown by introducing TEGa and TMI at 720℃~750℃; then, the temperature is raised to 840℃~870℃, and a 10nm~13nm thick Si-doped GaN barrier layer is grown by introducing TEGa and Si, with a Si concentration of 3.0×10⁻⁶. 17 ~4.0×10 17 cm -3 .

[0038] Low-temperature p-type GaN layer 700: After quantum well growth is completed, the pressure is kept constant, and the temperature is controlled at 710℃~760℃. TEGa and Cp2Mg are introduced to grow a p-type GaN layer with a thickness of 10nm~20nm. This layer serves as a protective layer, preventing the volatilization of In components within the quantum well during subsequent heating, and also acting as a buffer to prevent high-concentration Mg from directly diffusing into the active region.

[0039] Electron blocking layer 800: The temperature was then raised to 960℃~980℃, and TMA, TEGa, and Cp2Mg were introduced to grow a p-type AlGaN layer. The Al composition was controlled at 15%~20%, the thickness at 25nm~35nm, and the Mg doping concentration at 2.0×10⁻⁶. 18 cm -3 ~ 4.0×10 18 cm -3 The large bandgap of this layer effectively prevents electrons from overflowing into the P layer, while simultaneously improving hole injection efficiency.

[0040] 5. Fabrication of p-type GaN layer 900 Finally, a P-type GaN layer 900 is grown. This layer is designed with a two-segment structure to balance V-crater filling and surface smoothness. Low-temperature V-pit filling sublayer 901: Growth pressure 200 torr~250 torr, rotation speed 1000 rpm~1200 rpm, temperature 930℃~950℃. Gas ratio N2:H2:NH3=1:7:3 (high H2 environment), N2 flow rate 55~75 L / min. Mg-doped GaN was grown using TEGa, with a thickness of 100~150 nm. The low-temperature conditions reduced the thermal baking of the active region, and the high H2 ratio facilitated rapid filling of the V-pits.

[0041] High-temperature flattened sublayer 902: The growth conditions are similar to those of the low-temperature V-pit filled sublayer 901, with a temperature of 960℃, but process parameters suitable for flat surface growth are used. The thickness is also 100~150nm, and the Mg doping concentration is 3.5×10⁻⁶. 19 ~6.5×10 19 cm -3 This layer provides a flat surface for chip fabrication while also improving current spread.

[0042] Through the above structure, especially the synergistic effect of the crystal island growth layer 300, the stress relief layer 500 and the P-type GaN layer 900, the Micro LED chip achieves a dual improvement in antistatic capability and photoelectric performance while miniaturizing its size.

[0043] Example 2

[0044] Based on Example 1, this embodiment adapts the growth parameters of the stress relief layer 500 to meet the specific requirements of antistatic capabilities for Micro LED chips with slightly larger dimensions (e.g., 80μm-100μm). Any parts not mentioned in this embodiment are the same as in Example 1.

[0045] In preparing the stress relief layer 500, to obtain a stronger stress-blocking effect to accommodate the current distribution over a larger light-emitting area: Regarding the V-shaped pit opening size: By adjusting the growth parameters, the opening size of the V-shaped pit was controlled between 280nm and 300nm. Compared to Example 1, the larger V-shaped pit can accommodate more dislocations, but requires more precise control to avoid brightness loss.

[0046] Regarding the aperture size adjustment cycle layer 502: The number of InGaN / GaN cycles is adjusted to 6 pairs. The increased number of cycles provides stronger stress relief capabilities, helping to reduce crack formation during large-size chip fabrication. In this step, the In doping flux is set to 800~1500 sccm to slightly increase the In composition and enhance the stress relaxation effect caused by lattice mismatch.

[0047] Regarding the island growth layer 300: In the first section (island merging growth sublayer 301), the growth pressure is adjusted to 250 torr. Higher pressure helps increase nucleation density, thus accommodating the subsequent larger V-shaped pit density distribution.

[0048] Example 3

[0049] This embodiment focuses on optimizing the doping process of the p-type GaN layer 900, aiming to improve antistatic capability while further reducing contact voltage. Structures not mentioned in this embodiment are consistent with those in Embodiment 1.

[0050] During the growth of the p-type GaN layer 900, in addition to employing a two-stage temperature control, a Mg doping concentration gradient was also introduced: Low-temperature V-shaped pit filled sublayer 901: During growth at 940℃, the Mg doping concentration was set to a low level, specifically 2.0 × 10⁻⁶. 19 cm -3 ~ 4.0×10 19 cm -3 Lower doping concentrations help reduce lattice defects, ensure crystal quality in V-pit filling regions, and prevent the formation of leakage channels.

[0051] High-temperature planarization sublayer 902: When growing the planarization layer at 960℃, the Mg doping concentration is increased to 6.0 × 10⁻⁶. 19 cm -3 ~ 8.0×10 19 cm -3 The high concentration of Mg doping on the surface facilitates the formation of a good ohmic contact with the transparent conductive electrode (ITO), reducing the forward voltage (Vf).

[0052] Thickness ratio adjustment: To balance the pit filling effect and light absorption, in this embodiment, the thickness of the low-temperature V-shaped pit filling sublayer 901 is adjusted to 80nm, while the thickness of the high-temperature leveling sublayer 902 is increased to 180nm. This "thin filling, thick cap" structural design, while ensuring complete closure of the V-pit, utilizes a high-quality high-temperature layer to provide a better current expansion path, further enhancing the device's ability to resist instantaneous electrostatic discharge (ESD).

[0053] Performance Verification and Comparative Analysis To verify the actual effect of the epitaxial structure and growth method provided by the present invention, the inventors prepared a Micro LED epitaxial wafer with the structure of Example 1 of the present invention (referred to as "experimental group") and a Micro LED epitaxial wafer with conventional epitaxial growth method (referred to as "comparative example / Base").

[0054] The structural difference of the comparative example is that it does not include the three-segment crystal island growth layer described in this invention (using conventional u-GaN growth), the V-shaped pits are not precisely controlled (natural growth), and the P layer uses conventional single-segment growth.

[0055] Antistatic Discharge (ESD) Test The anti-static capability of the wafers in the experimental group and the comparative example was tested in human body mode (HBM). The chip yield (pass rate) was calculated at voltages of 2000V (2K), 3000V (3K), and 4000V (4K). The test results are shown in Table 1.

[0056] Table 1: Comparison of Antistatic (ESD) Yield Rate Group 2K ESD Yield 3K ESD Yield 4K ESD Yield Base 99% 95% 0% Experimental group (the present invention) 100% 100% 98% Results Analysis: As shown in Table 1, the resistance of the existing technology (comparative example) decreases sharply with increasing electrostatic discharge (ESD) voltage, especially under a 4000V high-voltage impact, where the yield drops to 0%, completely failing to meet the reliability requirements of Micro LED miniaturization. In contrast, the experimental group using the structure of this invention maintained a high yield of 98% under 4000V. This indicates that the synergistic effect of this invention—reducing leakage channels through the crystal island layer, regulating the V-pit morphology through the stress relief layer, and optimizing current spread through the P-type GaN layer—significantly improves the device's ESD robustness.

[0057] Photoelectric performance testing Under standard current injection, the forward voltage (Vf) and luminance (Iv) of the blue and green Micro LED chips in the experimental group and the comparative example were tested. The test results are shown in Table 2.

[0058] Table 2: Comparison of Photoelectric Performance Group Blue light brightness (mcd) Blue light voltage (V) Green light brightness (mcd) Green light voltage (V) Base 12.2 2.71 110 2.46 Experimental group (the present invention) 12.3 2.69 112 2.45 Results Analysis: As shown in Table 2, compared to the comparative example, the present invention (experimental group) significantly improved antistatic capabilities without sacrificing photoelectric performance. On the contrary, the brightness of both blue and green light was slightly improved, and the operating voltage was slightly reduced. This indicates that the V-shaped pit size control (240-300nm) of the present invention effectively blocked dislocations while retaining sufficient effective light-emitting area; at the same time, the two-segment P-layer growth effectively improved surface smoothness and ohmic contact, and reduced the voltage.

Claims

1. A epitaxial structure for improving the anti-static capability of Micro LED, characterized in that, The substrate, the buffer layer, the non-doped GaN layer, the n-type GaN layer, the stress release layer, the multi-quantum well light emitting layer, the low-temperature p-type GaN layer, the electron blocking layer and the P-type GaN layer are sequentially arranged along the growth direction; The non-doped GaN layer is a controllable defect density island growth layer, sequentially comprising an island merging growth sublayer, an island longitudinal growth sublayer and a gap filling sublayer along the growth direction; The stress release layer is configured as a V-shaped pit control layer, used for controlling the opening size of the V-shaped pit on the surface of the epitaxial layer within the range of 240nm to 300nm, and the stress release layer comprises an opening consistency control sublayer, an opening size adjustment cycle sublayer and an opening size adjustment doped sublayer grown in sequence; The P-type GaN layer is a double-section structure, comprising a low-temperature V-shaped pit filling sublayer and a high-temperature flat sublayer.

2. The epitaxial structure of claim 1, wherein, The island merging growth sublayer is configured to promote the merging of the islands on the C-plane platform; the longitudinal growth rate of the island longitudinal growth sublayer is greater than the lateral growth rate, and the height thereof matches the height of the substrate patterning structure; and the gap filling sublayer is used to fill the gap between the islands and the substrate patterning structure.

3. The epitaxial structure of claim 1, wherein, The opening consistency control sublayer in the stress release layer is a low-temperature low-growth-rate Si-doped GaN layer; the opening size adjustment cycle sublayer comprises alternatingly grown Si-doped GaN layers and In-doped GaN layers; and the opening size adjustment doped sublayer comprises a first-stage Si-doped GaN layer and a second-stage Si-In co-doped GaN layer.

4. The epitaxial structure of claim 1, wherein, The low-temperature V-shaped pit filling sublayer in the P-type GaN layer is a Mg-doped GaN layer grown in a high-hydrogen atmosphere; and the high-temperature flat sublayer is a Mg-doped GaN layer, and the growth temperature of the high-temperature flat sublayer is higher than that of the low-temperature V-shaped pit filling sublayer.

5. A method of growing an epitaxial structure as claimed in any one of claims 1 to 4, characterised in that, The method comprises the following steps: S1: growing a buffer layer on a substrate; S2: growing a non-doped GaN layer, which comprises growing a controllable defect density island growth layer by using a three-section variable-temperature and variable-pressure process; S3: growing an n-type GaN layer; S4: growing a stress release layer, which comprises growing an opening consistency control sublayer, an opening size adjustment cycle sublayer and an opening size adjustment doped sublayer by adjusting the growth temperature and the doping flow to control the opening size and consistency of the V-shaped pit; S5: growing a multi-quantum well light emitting layer; S6: growing a low-temperature p-type GaN layer; S7: growing an electron blocking layer; S8: growing a P-type GaN layer, which comprises growing a V-shaped pit filling sublayer at a low temperature under a high-hydrogen atmosphere, and then growing a high-temperature flat sublayer.

6. The growth method of claim 5, wherein, In step S2, the three-section growth process of the island growth layer is as follows: First section growth: side merging growth is performed by inputting H2 and NH3 at 1030-1050℃ and 150-250torr pressure; Second section growth: longitudinal dominant growth is performed by cutting off N2 and only inputting H2 and NH3 at 1070-1090℃, and the V / III ratio is lower than that in the first section; Third section growth: gap filling growth is performed by cutting off N2 and increasing the NH3 flow at 1110-1130℃.

7. The growth method of claim 5, wherein, In step S4, the growth temperature of the opening consistency control sublayer is 850-870 °C, and the growth rate is controlled at 0.3-0.5 μm / h; the opening size adjustment cycle sublayer comprises 3-6 periods of Si-doped GaN / In-doped GaN alternative growth.

8. The growth method of claim 5, wherein, In step S8, the growth temperature of the low-temperature V-shaped pit filling sublayer is 930-950 °C, and the flow ratio of H2 to NH3 is 7:3 to 2.5:1, so as to accelerate the filling of the V-shaped pit.

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