Integrated preparation method of wafer-level silicon substrate transfer-free Micro-LED driving unit and Micro-LED device

Abstract

The invention discloses an integrated preparation method of a transfer-free Micro-LED driving unit of a wafer-level silicon substrate and a Micro-LED device. The integrated preparation method comprises the following steps: depositing a passivation insulating layer on a Micro-LED array; bottom gate electrodes are sequentially arranged on the passivation insulating layer; a gate dielectric layer and patterning; performing through hole etching on the passivation insulating layer; preparing a channel material based on a liquid phase method, and patterning; and pattern electrodes are evaporated on the Micro-LED array and the channel material, and the Micro-LED pixel unit and the MOS driving unit are connected in series, so that the Micro-LED array and MOS driving integration is realized. According to the preparation method, transfer and alignment bonding are not needed, the technological process is greatly simplified, higher pixel density can be achieved on the wafer level, meanwhile, the whole technological process is prepared on the basis of the silicon substrate from bottom to top, and the preparation method is completely compatible with a traditional silicon semiconductor manufacturing process.

Description

Technical Field

[0001] This invention relates to the field of semiconductor optoelectronic integration technology, and in particular to an integrated manufacturing method and a Micro-LED device for a wafer-level silicon substrate transfer-free Micro-LED driving unit. Background Technology

[0002] Micro-LED devices boast advantages such as high brightness, high contrast, high resolution, long lifespan, fast response speed, and low power consumption, showing promising application prospects in near-eye displays, visible light communication, automotive head-up displays, and biomedicine. For Micro-LED devices, the key to their manufacturing process lies in the preparation of the epitaxial layer. Currently, the mainstream epitaxial layer fabrication method uses silicon, sapphire, or silicon carbide substrates via metal-organic chemical vapor deposition (MOCVD), requiring temperatures above 900℃. Meanwhile, the current mainstream display device driver backplane is based on crystalline silicon CMOS integration technology, with manufacturing temperatures generally above 1000℃. Epitaxially growing LED epitaxial layers on crystalline silicon CMOS driver backplanes, or fabricating crystalline silicon CMOS devices from LED epitaxial layers, presents significant negative impacts on the other device due to the different manufacturing processes. This makes bottom-up manufacturing impossible, and traditionally, LED display device manufacturing and driver circuit manufacturing are separate processes. Subsequently, interconnecting the Micro-LED and driver circuits requires complex transfer, alignment, and bonding processes, significantly increasing technical challenges and manufacturing costs. Currently, there are also some new thin-film transistor (TFT) driving circuits, which are manufactured at temperatures below 400°C and can be deposited normally on the LED epitaxial layer for driving Micro-LEDs, realizing monolithic integration of Micro-LED devices and driving circuits. However, mass production is affected by problems such as low mobility, poor uniformity, or deposition difficulties, and the degree of commercialization is not high.

[0003] Chinese patent "CN114300501" introduces a method for fabricating a Micro-LED in-situ driving unit and a Micro-LED device. This invention uses non-degenerate oxide semiconductor as the channel material of MOS to fabricate an in-situ integration of MOS structure and Micro-LED. However, the deposition of non-degenerate oxide semiconductor requires expensive equipment such as chemical vapor deposition, magnetron sputtering or pulsed laser deposition, and the oxide semiconductor material used is prone to hydrolysis and degradation in atmospheric environment, which poses problems in terms of reliability.

[0004] US Patent “US 2016 / 0329378” describes a carbon nanotube control circuit and fabrication method for an active matrix LED display module. The scheme uses screen printing process to use coated single-walled carbon nanotubes as channel material. However, screen printing coating method is not easy to achieve high-resolution LED display modules. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the first objective of the present invention is to provide an integrated fabrication method for Micro-LED driving units on wafer-level silicon substrates without transfer.

[0006] A second objective of this invention is to provide a Micro-LED device.

[0007] To achieve the above objectives, the present invention adopts the following technical solution:

[0008] This invention discloses an integrated fabrication method for a transfer-free Micro-LED driving unit on a wafer-level silicon substrate. The method involves covering the Micro-LED array on a wafer containing the Micro-LED array with a passivation insulating layer. A patterned bottom gate electrode is deposited on the passivation insulating layer. A gate dielectric layer is deposited on the bottom gate electrode, and the gate dielectric layer is patterned and etched. Through-hole etching is performed on the passivation insulating layer to form P-vias located in the P-type layer region of the Micro-LED pixel unit and N-vias located outside the Micro-LED pixel unit. A dispersion containing a semiconductor channel material is placed on the surface of the wafer. After drying, a channel material film is obtained on the wafer surface. The channel material film is patterned and etched. Then, N-electrodes are deposited at the N-via locations, P-electrodes are deposited at the P-via locations, and source and drain electrodes are deposited on the channel material film. All Micro-LED pixel units in a Micro-LED array share a single N-electrode. The Micro-LED units and MOS driving units are connected in series using the interconnection of the P-vias and drain electrodes.

[0009] The integrated fabrication method provided by this invention first involves covering the Micro-LED array on the wafer with a passivation insulating layer to isolate the Micro-LED pixel units from short-circuit interference with the subsequent MOS driving units. This passivation insulating layer isolates the Micro-LED pixel units, allowing MOS driving units to be fabricated directly on the Micro-LED pixel units or in areas outside the Micro-LED pixel units. During the integrated fabrication of the MOS driving units, a patterned bottom gate electrode is first deposited on the passivation insulating layer to isolate the bottom gate electrode from short circuits with the channel material or source and drain electrodes, while also enabling the bottom gate electrode to control the channel current. Next, a gate dielectric is deposited on the bottom gate electrode, and the gate dielectric is patterned and etched. To reduce the impact of subsequent channel sequences on the connection window, the patterning of the gate dielectric is further refined. After etching, the passivation insulating layer is then etched with vias to form P-vias located in the P-type layer region of the Micro-LED pixel unit and N-vias located outside the Micro-LED pixel unit. Then, a channel material thin film is prepared based on the liquid phase method, and the channel material is patterned and etched. Finally, patterned electrodes are deposited on the Micro-LED array and the channel material thin film. The Micro-LED unit and the MOS driving unit are connected in series by the interconnection of the P-vias and the drain electrode to realize a device integrating the Micro-LED array and the MOS driving unit. This invention can realize the in-situ integration of Micro-LED pixel units and MOS driving units. Compared with the traditional process of transferring, aligning and bonding Micro-LED devices and driving circuit backplanes, this invention uses the liquid phase method to prepare the channel material, which greatly simplifies the process and reduces costs.

[0010] In a preferred embodiment, the method for obtaining the wafer containing the Micro-LED array is as follows: an LED epitaxial layer is epitaxially grown on a silicon substrate, the LED epitaxial layer including a buffer layer, an N-type layer, a multiple quantum well layer and a P-type layer from bottom to top, the LED epitaxial layer is patterned to form a Micro-LED array, the Micro-LED array containing two or more individually controllable Micro-LED pixel units.

[0011] In practice, forming a Micro-LED array on an LED epitaxial layer on a silicon substrate can be achieved by using an etching process to remove the P-type layer and multiple quantum well layer in the non-light-emitting area, or by using an ion implantation process to destroy the structure of the P-type layer and multiple quantum well layer in the non-light-emitting area.

[0012] In a preferred embodiment, the material of the passivation insulating layer is selected from SiO2, Al2O3, HfO2, AlN, and SiN. x At least one of the following, preferably Al2O3.

[0013] In a preferred embodiment, the thickness of the passivation insulating layer is 100nm-250nm, preferably 200nm.

[0014] The preferred embodiment employs one of the following deposition methods: ALD deposition, PECVD deposition, or magnetron sputtering. Preferably, ALD is deposited on a wafer containing a Micro-LED array, covering the Micro-LED array with a passivation insulating layer.

[0015] In a preferred embodiment, the bottom gate electrode is disposed in an area outside the Micro-LED pixel unit or in the Micro-LED pixel unit area, and the bottom gate electrode is connected to the gate power supply pad through a bottom gate power supply line.

[0016] In a further preferred embodiment, when the bottom gate electrode is disposed in a region outside the Micro-LED pixel unit, the material of the bottom gate electrode is selected from one of Ti, Au, Pd, and Ni.

[0017] When the bottom gate electrode is disposed in the Micro-LED pixel unit region, the bottom gate electrode material is selected from transparent conductive oxide.

[0018] In a preferred embodiment, when depositing the gate dielectric layer on the bottom gate electrode, the gate dielectric layer is controlled to completely cover the bottom gate electrode, and the interconnection between the bottom gate electrode power supply line and the source electrode, drain electrode and their power supply lines is isolated.

[0019] In actual operation, the method for depositing the gate dielectric layer can be ALD.

[0020] In a preferred embodiment, the material of the gate dielectric layer is selected from AlO. x HfO x One of Y2O3, preferably HfO2.

[0021] In a preferred embodiment, the thickness of the gate dielectric layer is 10nm-50nm, preferably 25nm.

[0022] In a preferred embodiment, before applying the dispersion containing the semiconductor channel material to the surface of the wafer, the wafer is first placed in an HMDS atmosphere and baked at 130°C to 150°C for 15 to 30 minutes.

[0023] In this invention, before depositing the semiconductor channel material using the liquid phase method, the wafer is first baked in an HMDS atmosphere. Experiments have shown that hexamethyldisilazane (HMDS) is an organic binder that can effectively improve the adhesion density of the semiconductor channel material on the wafer surface, achieving a larger on-state current and allowing for control of the luminous brightness of Micro-LEDs over a wider current range. Furthermore, experiments have revealed that the concentration of the semiconductor channel material in the dispersion does not significantly affect the final adhesion density of the semiconductor channel material on the wafer surface. The deposition density limit is determined by the interaction force between the wafer surface and the carbon nanotubes. Therefore, the wafer binder treatment in this invention is the main driving force for improving the deposition density.

[0024] In a preferred embodiment, the method of placing the dispersion containing the semiconductor channel material on the surface of the wafer is as follows: immersing the wafer in the dispersion containing the semiconductor channel material and then lifting the wafer at a uniform speed, or spin-coating the dispersion containing the semiconductor channel material onto the wafer.

[0025] In a preferred embodiment, the semiconducting channel material is selected from carbon nanotubes. In actual operation, the semiconducting carbon nanotube powder is uniformly dispersed in chloroform reagent to obtain a liquid containing the semiconducting channel material dispersion.

[0026] In actual operation, the channel material film is patterned and etched, retaining only the channel material above the gate dielectric, and the high concentration of carbon nanotubes near the sidewall of the Micro LED is etched away, so that the carbon nanotubes on the entire wafer MOS driving unit are evenly distributed, and the effect of in-situ integration of Micro-LED pixel unit and MOS driving unit is better.

[0027] In a preferred embodiment, one end of the drain electrode is in contact with the channel material, and the other end is in contact with the P-type layer of the Micro-LED pixel unit through a P-via using a drain power supply line; one end of the source electrode is in contact with the channel material, and the other end is connected to the source power supply pad using a source power supply line.

[0028] In a preferred embodiment, when the MOS driving unit is placed outside the Micro-LED pixel unit, the materials of the source electrode, drain electrode, P electrode, and N electrode are all selected from non-ferrous metals or transparent conductive oxides, and the non-ferrous metals are selected from one of Ti, Au, Pd, Sc, Cr, and Ni.

[0029] In a preferred embodiment, when the MOS driving unit is placed in the region of the Micro-LED pixel unit, the materials of the source electrode, drain electrode, P electrode, and N electrode are selected from transparent conductive oxides.

[0030] In the actual operation of this invention, patterning can be achieved by high-precision photolithography or electron beam lithography.

[0031] The present invention also provides a Micro-LED device, the Micro-LED device comprising a Micro-LED array and a MOS transistor heterogeneous integrated array integrated in situ by an integrated fabrication method, wherein the Micro-LED array has two or more individually controlled Micro-LED pixel units, and the Micro-LED pixel units are connected in series with the MOS driving units in the MOS transistor heterogeneous integrated array.

[0032] In a preferred embodiment, the epitaxial structure of the Micro-LED pixel unit includes, from bottom to top, a buffer layer, an N-type layer, a multiple quantum well layer, and a P-type layer.

[0033] In a preferred embodiment, the MOS driving unit includes a bottom gate electrode, a gate dielectric layer, a channel material thin film, a source electrode, and a drain electrode.

[0034] The advantages and beneficial effects of this invention are:

[0035] 1. This invention proposes an integrated fabrication method for Micro-LED driving units on wafer-level silicon substrates without transfer. The fabrication process is based on silicon substrates and is carried out from bottom to top. It can realize wafer-level manufacturing processes, and the process flow is simple and compatible with the current mainstream all-silicon processes.

[0036] 2. This invention enables in-situ integration of Micro-LED pixel units and MOS driving units. Compared with the traditional process of transferring, aligning and bonding Micro-LED devices with the backplane of the driving circuit, this invention uses a liquid phase method to prepare channel materials, which greatly simplifies the process and reduces costs. At the same time, in-situ integration can achieve higher resolution (>1000 PPI) for Micro-LED devices, which is of great significance to the commercialization of Micro-LED devices. Attached Figure Description

[0037] Figure 1 This is a flowchart of the integrated manufacturing method of the wafer-level silicon substrate-free Micro-LED driving unit according to Embodiment 1 of the present invention;

[0038] Figure 2 This is a cross-sectional schematic diagram of the integrated manufacturing method of the wafer-level silicon substrate-free Micro-LED driving unit according to Embodiment 1 of the present invention;

[0039] Figure 3 This is a cross-sectional schematic diagram of the integrated manufacturing method of the wafer-level silicon substrate-free Micro-LED driving unit according to Embodiment 1 of the present invention;

[0040] Figure 4 This is a cross-sectional schematic diagram of the integrated manufacturing method of the wafer-level silicon substrate-free Micro-LED driving unit according to Embodiment 1 of the present invention;

[0041] Figure 5 This is a cross-sectional schematic diagram of the integrated manufacturing method of the wafer-level silicon substrate-free Micro-LED driving unit according to Embodiment 1 of the present invention;

[0042] Figure 6 This is a cross-sectional schematic diagram of the integrated manufacturing method of the wafer-level silicon substrate-free Micro-LED driving unit according to Embodiment 1 of the present invention;

[0043] Figure 7 This is a cross-sectional schematic diagram of the integrated manufacturing method of the wafer-level silicon substrate-free Micro-LED driving unit according to Embodiment 1 of the present invention;

[0044] Figure 8 This is a cross-sectional schematic diagram of the integrated manufacturing method of the wafer-level silicon substrate-free Micro-LED driving unit according to Embodiment 1 of the present invention;

[0045] Figure 9 This is a cross-sectional schematic diagram of the integrated manufacturing method of the wafer-level silicon substrate-free Micro-LED driving unit according to Embodiment 1 of the present invention;

[0046] Figure 10 This is a top view schematic diagram of the integrated device of the Micro-LED driving unit based on the liquid phase method in Embodiment 1 of the present invention;

[0047] Figure 11 This is the electrical schematic diagram of the integrated device of the Micro-LED driving unit based on the liquid phase method in Embodiment 1 of the present invention;

[0048] Figure 12 This is a cross-sectional schematic diagram of the integrated device of the Micro-LED driving unit based on the liquid phase method in Embodiment 2 of the present invention;

[0049] Figure 13 This is an optical micrograph of an actual device of the integrated device of the Micro-LED driving unit based on the liquid phase method in Embodiment 2 of the present invention. Detailed Implementation

[0050] To make the technical methods and solutions of the present invention clearer, the present invention will be further described below with reference to the accompanying drawings and embodiments. It should be explained that the following embodiments are illustrative and do not limit the scope of application of the present invention.

[0051] Example 1

[0052] like Figure 1The diagram shows a flowchart of an integrated manufacturing method for a wafer-level silicon substrate-based Micro-LED driver unit without transfer, comprising the following steps:

[0053] Step S100: An LED epitaxial layer is epitaxially grown on a silicon substrate, wherein the LED epitaxial layer comprises, from bottom to top, a buffer layer, an N-type layer, a multiple quantum well layer, and a P-type layer;

[0054] Specifically, such as Figure 2 As shown, an LED epitaxial structure is epitaxially grown on a silicon wafer substrate 100 using metal-organic chemical vapor deposition (MOCVD). The epitaxial growth material can be gallium nitride or gallium arsenide. The epitaxial layer, from bottom to top, includes a buffer layer 110, an N-type layer 120, a multiple quantum well layer 130, and a P-type layer 140. In this embodiment, the buffer layer 110 is a high-temperature AlN layer, the N-type layer 120 is Si-doped gallium nitride, the multiple quantum well layer 130 is an 8-period indium gallium nitride / gallium nitride quantum well, and the P-type layer 140 is Mg-doped gallium nitride.

[0055] Step S200: Pattern the LED epitaxial layer on the wafer substrate to form a Micro-LED array.

[0056] Specifically, such as Figure 3 As shown, a patterned mask is fabricated on the epitaxial layer using a high-precision photolithography process. The mask material is silicon dioxide. Inductively coupled plasma etching (ICP) is performed in a Cl2 / BCl3 atmosphere to remove the P-type layer 140 and the multi-quantum well layer 130 outside the light-emitting region. To ensure clean etching, a certain depth is usually over-etched. After removing the mask, a Micro-LED array is formed. The Micro-LED array contains two or more individually controllable Micro-LED pixel units. The size of each Micro-LED pixel unit should be less than 50 μm. In this embodiment, for ease of explanation, the Micro-LED array has only 6 Micro-LED pixel units, and the size of each Micro-LED pixel unit is 20 μm.

[0057] Step S300: Deposit a passivation insulating layer on the entire Micro-LED array on the wafer.

[0058] After ICP etching, defects and dangling bonds remain on the sidewalls of the Micro-LED pixel unit, forming non-radiative recombination centers. To reduce the impact of sidewall defects and dangling bonds, and also to isolate the Micro-LED pixel unit from short-circuit interference with the subsequent MOS driving unit, a passivation insulating layer needs to be deposited, such as... Figure 4 As shown. The passivation insulating layer 150 material can be SiO2, Al2O3, HfO2, AlN, SiN. xIn this embodiment, Al2O3 material is used, which can be one or more combinations of materials such as atomic layer deposition (ALD), PECVD, or magnetron sputtering. To ensure better coverage of the Micro-LED pixel unit, ALD deposition technology with good step coverage is preferred. To reduce the impact of subsequent processes, the thickness of the passivation insulating layer 150 is recommended to be in the range of 100nm-250nm; in this embodiment, a thickness of 200nm is used.

[0059] Step S400: A patterned bottom gate electrode is deposited on the passivated insulating layer by vapor deposition.

[0060] The passivation insulating layer 150 isolates the Micro-LED pixel units, allowing MOS driving units to be fabricated directly on the Micro-LED pixel units or in areas outside the Micro-LED pixel units. If the MOS driving units are fabricated in areas outside the Micro-LED pixel units, there is no need to consider the MOS driving units blocking light and reducing Micro-LED light output. The bottom gate electrode material can be one or more combinations of non-ferrous metals such as Ti, Au, Pd, and Ni. In this embodiment, as... Figure 5 As shown, in order to improve the integration density of Micro-LED and MOS driving unit, MOS driving unit is directly fabricated on Micro-LED pixel unit. Using photolithography, negative photoresist is used as mask, and the bottom gate electrode 160 is deposited on Micro-LED pixel unit by lift-off. The material of bottom gate electrode 160 is transparent conductive oxide ITO. This can improve the integration density without reducing the light extraction efficiency of Micro-LED pixel unit.

[0061] Step S500: Deposit the gate dielectric on the bottom gate electrode and pattern the gate dielectric.

[0062] To isolate the bottom gate electrode from short circuits in the channel material or the source and drain electrodes, and to simultaneously enable control of the channel current by the bottom gate electrode, a dielectric layer needs to be deposited on the bottom gate electrode, such as... Figure 6 As shown. It can be one of Al2O3, HfO2, Y2O3, etc., preferably a high-k dielectric. In this embodiment, HfO2 is selected as the material for the gate dielectric layer 170. The gate dielectric layer 170 requires excellent film quality and step coverage, and is deposited using ALD deposition. The gate dielectric layer 170 should completely cover the bottom gate electrode 160. Furthermore, the interconnection between the bottom gate electrode power supply line and the source electrode, drain electrode, and their power supply lines must be isolated, such as... Figure 10As shown in the top view, the bottom gate power supply line 280 overlaps with the source power supply line 250, requiring isolation by the gate dielectric 170. To achieve optimal control of the channel current by the bottom gate electrode, the thickness of the gate dielectric layer 170 should be controlled within the range of 10nm-50nm; this embodiment uses 25nm. For some regions where a dielectric layer is not required, such as... Figure 10 The source power supply pad 270 in the middle needs to be patterned by photolithography and the gate dielectric material is removed by ICP process.

[0063] Step S600: Perform via etching on the passivation insulating layer.

[0064] The passivation insulating layer 150 completely covers the Micro-LED array. To allow for subsequent metal electrode connections to the Micro-LEDs, connection windows need to be opened. Theoretically, this step could be moved to step S300, but since the metal electrodes are to be placed in the final step, it is postponed to step S500 to minimize the impact of subsequent pass sequences on the connection windows. Using photolithography, a pattern is formed using photoresist as a mask. ICP etching is then used to remove the passivation insulating layer material within the vias, and finally, the photoresist used for the mask is washed away. The result is as follows... Figure 7 As shown, there are two types of vias: one is a P-via 180 located on the P-type layer region of the Micro-LED pixel unit, with one P-via 180 on each Micro-LED pixel unit, which is subsequently used for the deposition of the P electrode; the other is an N-via 190 located outside the Micro-LED pixel unit, which is subsequently used for the deposition of the N electrode. The N electrode is a common cathode for the entire Micro-LED array, and there is only one N-via 190 for each array.

[0065] Step S700: Prepare a channel material thin film based on the liquid phase method, and perform patterned etching on the channel material;

[0066] The delayed step S600 in the preparation of the channel material thin film is to reduce the adverse effects of photolithography and resist removal processes on the cleanliness of the channel material. In this case, carbon nanotubes are used as the channel material. Semiconductor carbon nanotube powder is uniformly dispersed in chloroform reagent to obtain a liquid containing the semiconductor channel material dispersion. The carbon nanotube thin film is prepared using a liquid-phase method. First, the wafer is baked in an HMDS atmosphere at 140℃ for 30 minutes. HMDS is an organic tackifier that can improve the adhesion density of carbon nanotubes on the wafer surface. At room temperature (23℃), the wafer is slowly and vertically immersed in a chloroform solution containing the semiconductor carbon nanotube dispersion, and then lifted at a uniform rate of 2 μm / s. During the lifting process, chloroform readily volatilizes, allowing the semiconductor carbon nanotubes to adhere to the wafer surface. Patterns were formed on a wafer containing a carbon nanotube thin film using photolithography. Photoresist was used as a mask, and ICP etching was performed in an O2 atmosphere to ensure complete etching of the carbon nanotubes. The etching time was 1 minute. The photoresist mask was then removed sequentially using a resist remover, acetone, and isopropanol. Figure 8 As shown, only the carbon nanotubes 200 on the gate dielectric 170 remain, while all carbon nanotubes in other areas are removed.

[0067] Step S800: Deposit patterned electrodes on the Micro-LED array and channel material film.

[0068] The vias on the Micro-LED array have been opened, and the carbon nanotube thin film, serving as the channel material, has also been prepared. In step S700, electrodes are deposited to connect the Micro-LED pixel units and the carbon nanotube MOS driving units in series. Using photolithography, a negative resist is used as a mask to form a negative resist pattern, and electrode materials are deposited. In this embodiment, the carbon nanotube MOS driving unit is located on the Micro-LED pixel unit. To better contact the gallium nitride p-type layer 140 and increase Micro-LED light output, transparent oxide ITO is deposited as the electrode using an electron beam evaporation device. Figure 9 As shown, an N-electrode 210 is deposited at the N-via 190 position, a P-electrode 220 is deposited at the P-via 180 position, and a source electrode 240 and a drain electrode 230 are deposited on the carbon nanotube film, forming a channel with a length of 2 μm. All Micro-LED pixel units in a Micro-LED array share a single N-electrode 210, and the Micro-LED units and carbon nanotube MOS driving units are connected in series using the interconnection of the P-electrode 220 and the drain electrode 230.

[0069] Based on the above integrated manufacturing method of wafer-level silicon substrate transfer-free Micro-LED driving unit, a device integrating Micro-LED array and carbon nanotube MOS driver was manufactured. Figure 10This is a schematic diagram (top view) of the integrated device of the Micro-LED driving unit based on the liquid phase method in Embodiment 1 of the present invention. Figure 9 yes Figure 10 The cross-sectional view is taken from the AA direction. The N electrode 210 is the common cathode of the Micro-LED array in Example 1. The Micro-LED array has six Micro-LED pixel units, each with a P electrode 220. The P electrode 220 and drain electrode 230 are interconnected to connect the Micro-LED unit and the carbon nanotube MOS driving unit in series. A vertical column of Micro-LED pixel units is connected in parallel via the source power supply line 250 in the series-connected carbon nanotube MOS driving unit, and is powered by the source power supply pad 260. A horizontal row of Micro-LED pixel units is connected via the gate power supply line 280 in the series-connected carbon nanotube MOS driving unit, and the channel current is controlled by the gate power supply pad 270. In Example 1, the electrode material is transparent oxide ITO, thus forming a P-type MOS structure for the carbon nanotube MOS driving unit. When the N electrode 210 is connected to -3V, the source power supply pad 260 is connected to 0V, and the gate power supply pad 270 is connected to the negative electrode, thus illuminating the corresponding Micro-LED pixel unit. Figure 10 This is the electrical schematic diagram of the integrated device of the Micro-LED driving unit based on the liquid phase method in Embodiment 1 of the present invention. It can be clearly seen that when the N electrode 210 is connected to a low potential, power can be supplied to the source power supply pad 260 and the gate power supply pad 270 to achieve the addressing and lighting of the Micro-LED device.

[0070] Example 2

[0071] Example 2 is another device integrating a Micro-LED array with a carbon nanotube MOS driver, and its device structure is as follows. Figure 11As shown. The main manufacturing process of Example 2 is the same as that of Example 1, with carbon nanotubes still used as the channel material. The only difference lies in the photolithography patterns and film materials used in several steps. The most obvious difference is that the carbon nanotube MOS driving units are not placed on the Micro-LED pixel units, but rather placed side-by-side nearby. In Example 2, the spacing between the Micro-LED pixel units is larger, allowing for the placement of a carbon nanotube MOS driving unit at the same interval as the Micro-LED pixel units. Because the carbon nanotube MOS driving units are not placed on the Micro-LED pixel units, there is no need to consider the light absorption of the colored metal electrodes. The bottom gate electrode 160 in Example 2 is made of a Ti / Au metal combination, and the gate dielectric layer 170 is made of HfO2. In step S700, electrode deposition is performed in two stages. The source electrode 230 and drain electrode 240 of the carbon nanotube MOS driving unit are made of Sc, while the N electrode 210 and P electrode 220 on the Micro-LED array are made of ITO. The P electrode 220 of the Micro-LED pixel unit and the source electrode 230 of the carbon nanotube MOS driving unit are in contact through ITO, thus forming a series connection between the Micro-LED pixel unit and the carbon nanotube N-type MOS driving unit, realizing a device integrating the Micro-LED array and the carbon nanotube N-type MOS driving unit. Unlike Example 1, in Example 2, the Micro-LED pixel units in one vertical column are connected in parallel through the drain power supply lines in the series carbon nanotube N-type MOS driving units. When the N electrode 210 is connected to 0V, the drain power supply pad 260 is connected to 3V, and the gate power supply pad 270 is connected to the positive electrode, thereby enabling the corresponding Micro-LED pixel unit to be lit.

[0072] Figure 13 This is an optical microscopic image of an actual device in Example 2, wherein the Micro LED pixel size is 10μm×10μm, the Micro LED pixel pitch is 15μm, and the PPI of the entire device can reach 1025.

[0073] Comparative Example 1

[0074] The other conditions were the same as in Example 1, except that the wafer was not baked in a 140°C HMDS atmosphere for 30 minutes, resulting in a decrease in the distribution density of carbon nanotubes.

[0075] The above descriptions are merely two relatively detailed typical embodiments of the present invention. It should be noted that, in order to make the description of the present invention concise, not all possible combinations of the various technical features in the above process steps have been described. Without departing from the principle of the present invention, several improvements and adjustments can be made, and these improvements and adjustments should also be considered within the scope of protection of the present invention.

Claims

1. An integrated preparation method of a wafer-level silicon substrate transfer-free Micro-LED driving unit, characterized in that: A passivation insulating layer is covered on a Micro-LED array of a wafer containing the Micro-LED array, a patterned bottom gate electrode is evaporated on the passivation insulating layer, a gate dielectric layer is deposited on the bottom gate electrode, and the gate dielectric layer is patterned and etched, the passivation insulating layer is through-hole etched to form a P through-hole located on a P type layer region of a Micro-LED pixel unit and an N through-hole located on a region outside the Micro-LED pixel unit, a dispersion liquid containing a semiconductor channel material is arranged on a surface of the wafer, and after drying, a channel material film is obtained on the surface of the wafer, the channel material film is patterned and etched, then an N electrode is evaporated at the position of the N through-hole, an P electrode is evaporated at the position of the P through-hole, and a source electrode and a drain electrode are evaporated on the channel material film, all the Micro-LED pixel units in one Micro-LED array share one N electrode, and the Micro-LED unit and the MOS driving unit are connected in series by interconnection of the P through-hole and the drain electrode.

2. The integrated preparation method of the wafer-level silicon substrate transfer-free Micro-LED driving unit according to claim 1, wherein: The method for obtaining the wafer containing the Micro-LED array is: epitaxially growing an LED epitaxial layer on a silicon substrate, the LED epitaxial layer comprises, from bottom to top, a buffer layer, an N type layer, a multi-quantum well layer and a P type layer, and the LED epitaxial layer is patterned to form a Micro-LED array, and the Micro-LED array contains two or more Micro-LED pixel units that can be controlled individually.

3. The integrated preparation method of the Micro-LED driving unit without transfer of the wafer-level silicon substrate according to claim 1, characterized in that: The material of the passivation insulating layer is selected from at least one of SiO2, Al2O3, HfO2, AlN, SiN x ​ The thickness of the passivation insulating layer is 100 nm-250 nm. The passivation insulating layer is deposited on the Micro-LED array of the wafer containing the Micro-LED array by using one of ALD deposition, PECVD deposition and magnetron sputtering.

4. The integrated preparation method of the wafer-level silicon substrate transfer-free Micro-LED driving unit according to claim 1, characterized in that: The bottom gate electrode is arranged in a region outside the Micro-LED pixel unit or in the region of the Micro-LED pixel unit, and the bottom gate electrode is connected with a gate power supply pad through a bottom gate power supply line. When the bottom gate electrode is arranged in the region outside the Micro-LED pixel unit, the material of the bottom gate electrode is selected from one of Ti, Au, Pd and Ni.

5. The integrated preparation method of the Micro-LED driving unit without transfer of the wafer-level silicon substrate according to claim 1, characterized in that: When the gate dielectric layer is deposited on the bottom gate electrode, the gate dielectric layer is controlled to completely cover the bottom gate electrode and to cut off the interconnection between the bottom gate power supply line and the source electrode, the drain electrode and their power supply lines. The material of the gate dielectric layer is selected from one of AlO x , HfO x , Y2O3. The thickness of the gate dielectric layer is 10 nm-50 nm.

6. The integrated preparation method of the Micro-LED driving unit without transfer of the wafer-level silicon substrate according to claim 1, characterized in that: Before the dispersion liquid containing the semiconductor channel material is arranged on the surface of the wafer, the wafer is first baked in an HMDS atmosphere at 130 DEG C-150 DEG C for 15 min-30 min.

7. The integrated preparation method of the wafer-level silicon substrate transfer-free Micro-LED driving unit according to claim 1, wherein: the way of placing the dispersion liquid containing the semiconductor channel material on the surface of the wafer is to immerse the wafer in the dispersion liquid containing the semiconductor channel material and then uniformly lift the wafer, or to spin the dispersion liquid containing the semiconductor channel material on the wafer; the semiconductor channel material is selected from carbon nanotubes.

8. The integrated preparation method of the wafer-level silicon substrate transfer-free Micro-LED driving unit according to claim 1, wherein: the one end of the drain electrode is in contact with the channel material, and the other end is in contact with the P-type layer of the Micro-LED pixel unit through the P via and the drain power supply line; the one end of the source electrode is in contact with the channel material, and the other end is connected with the source power supply pad through the source power supply line.

9. The integrated preparation method of the wafer-level silicon substrate transfer-free Micro-LED driving unit according to claim 1, wherein: when the MOS driving unit is placed in the area outside the Micro-LED pixel unit, the materials of the source electrode, the drain electrode, the P electrode and the N electrode are selected from colored metals or transparent conductive oxides, and the colored metal is selected from one of Ti, Au, Pd, Sc, Cr and Ni; when the MOS driving unit is placed in the area of the Micro-LED pixel unit, the materials of the source electrode, the drain electrode, the P electrode and the N electrode are selected from transparent conductive oxides. The Micro-LED device comprises a Micro-LED array and a MOS heterojunction array integrated in situ by the integrated preparation method according to any one of claims 1-9, the Micro-LED array has two or more individually controlled Micro-LED pixel units, and the Micro-LED pixel units are connected in series with the MOS driving units in the MOS heterojunction array; the epitaxial structure of the Micro-LED pixel unit comprises, from bottom to top, a buffer layer, an N-type layer, a multi-quantum well layer and a P-type layer; the MOS driving unit comprises a bottom gate electrode, a gate dielectric layer, a channel material film, a source electrode and a drain electrode.

10. A Micro-LED device, characterized by: ​ ​ ​

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