Preparation method of semiconductor structure and deposition equipment

Abstract

The invention relates to the field of semiconductor manufacturing, provides a preparation method of a semiconductor structure and deposition equipment, and at least can improve the yield of a film layer and save working time. The preparation method comprises the following steps: carrying out a first deposition step on a substrate, namely introducing a first gas and a second gas, and detecting a first variable quantity of a plasma load impedance imaginary part; if the first variable quantity reaches a first numerical value, performing first cleaning treatment; a second deposition step is carried out on the substrate, and the second deposition step comprises the steps that third gas and fourth gas are introduced, and a second variable quantity of a plasma load impedance imaginary part is detected; if the second variable quantity reaches a second numerical value, carrying out second cleaning treatment; etching the substrate, and detecting a third variable quantity of a plasma load impedance imaginary part; if the third variable quantity reaches a third numerical value, performing third cleaning treatment; and repeating the second deposition step and the etching step until the groove is filled with the first film layer and the second film layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing, and in particular to a method for preparing a semiconductor structure and a deposition apparatus. Background Technology

[0002] Thin film deposition is an essential step in the integrated circuit manufacturing process. Thin film deposition technology uses physical or chemical methods to attach one or more substances in a certain state to the surface of a substrate material, thereby forming a thin film layer on the substrate material surface.

[0003] In semiconductor manufacturing processes, the filling technology of high aspect ratio trenches is a critical step affecting device performance and reliability. Currently, high-density plasma chemical vapor deposition (HDPCVD) is widely used in the industry for trench filling. However, these processes have extremely stringent requirements for plasma density, uniformity, and vacuum control precision, leading to a significant increase in the cost of supporting equipment. Furthermore, the films deposited by these methods often suffer from poor internal stress control, resulting in insufficient adhesion between the film and the substrate, affecting interface stability and long-term device reliability.

[0004] Another alternative is the Deposition-Etch-Dep (DED) process, which uses a cycle of deposition and anisotropic etching to improve the filling morphology. However, this process requires breaking the vacuum environment and transferring the wafer to different equipment between the deposition and etching stages, which not only significantly increases the process cycle time but also introduces risks such as particle contamination, oxidation, and mechanical damage, leading to an increase in wafer defect density and posing a serious challenge to the yield of advanced processes. Summary of the Invention

[0005] This disclosure provides a method for fabricating a semiconductor structure and a deposition apparatus, which at least helps to improve the yield of the film and save working time.

[0006] According to some embodiments of this disclosure, one aspect of this disclosure provides a method for fabricating a semiconductor structure, comprising: providing a substrate having a groove therein; performing a first deposition step on the substrate, the first deposition step being used to deposit a first film layer in the substrate, the first deposition step including introducing a first gas and a second gas, and detecting a first change in the imaginary part of the plasma load impedance; if the first change reaches a first value, performing a first cleaning process; performing a second deposition step on the substrate, the second deposition step being used to deposit a second film layer on the first film layer, the second deposition step including introducing a third gas and a fourth gas, and detecting a second change in the imaginary part of the plasma load impedance; if the second change reaches a second value, performing a second cleaning process; performing an etching step on the substrate, the etching step being used to remove a portion of the second film layer, and detecting a third change in the imaginary part of the plasma load impedance; if the third change reaches a third value, performing a third cleaning process; repeating the second deposition step and the etching step until the groove is filled with the first film layer and the second film layer.

[0007] In some embodiments, the semiconductor structure includes a deposition chamber in which the first deposition step, the second deposition step, and the etching step are performed.

[0008] In some embodiments, a fourth change in the real part of the plasma load impedance is also detected in the second deposition step; if the fourth change reaches a fourth value and the second change reaches a second value, a second cleaning process is performed.

[0009] In some embodiments, the etching step further detects a fifth change in the real part of the plasma load impedance; if the fifth change reaches a fifth value and the third change reaches a third value, a third cleaning process is performed.

[0010] In some embodiments, the first deposition step includes PEALD; the second deposition step includes PECVD.

[0011] In some embodiments, the first film layer and the second film layer are made of the same material.

[0012] In some embodiments, the first gas includes a silicon-containing reactant, the second gas and the third gas are both oxidizing reactants, and the fourth gas includes TEOS.

[0013] In some embodiments, the first deposition step includes: introducing the first gas through a first air intake channel for a first time; introducing a second gas through a second air intake channel, and causing the first gas to react with the second gas to form a first film layer.

[0014] In some embodiments, the second deposition step includes: introducing the fourth gas through a third air intake channel for a second duration; and introducing the second gas through a second air intake channel, and causing the fourth gas to react with the second gas to form a second film.

[0015] According to some embodiments of the present disclosure, another aspect of the present disclosure provides a deposition apparatus for performing a method for fabricating a semiconductor structure as described in any of the above embodiments, comprising: a deposition chamber; and an air intake mechanism located within the deposition chamber, the air intake mechanism including at least a first air intake channel, a second air intake channel, and a third air intake channel.

[0016] The technical solutions provided in this disclosure have at least the following advantages: The semiconductor structure fabrication method provided in this disclosure achieves flexible switching of process integration and improved deposition film yield by tightly coupling process control, endpoint detection, and chamber health management through the physical quantity of the imaginary part of impedance. First, this solution enables the continuous execution of three core processes—the first deposition step, the second deposition step, and the etching step—within a single chamber through flexible switching of gas chemistry and plasma conditions. Specifically, it allows for alternating cycles of deposition (especially high-conformity deposition) and etching (such as sputtering etching or reactive etching to smooth the surface or open bottlenecks) required to fill the grooves. This allows for the completion of the "deposition-etching-redeposition" cycle without breaking the vacuum or transferring the wafer, significantly improving process efficiency, reducing interface contamination, and achieving more precise morphology control. Second, based on the first, second, and third changes as the first deposition endpoint, the second deposition endpoint, and the etching endpoint, respectively, a non-invasive physical measurement method (impedance measurement method) independent of process chemistry is used. Regardless of whether a silicon source gas (such as SiH4), an oxygen source, or an etching gas (such as CF4) is introduced, changes in plasma impedance can sensitively reflect the combined changes in the surface state (deposited film coverage) of the chamber walls (electrodes, surfaces) and the overall electrical properties of the wafer surface film. This is more universal than methods that rely on the spectral signals of specific elements. Finally, forming a thin film in the same chamber effectively removes the accumulation of reaction byproducts on the chamber walls and electrodes. The vacuum-free process greatly reduces the risk of particulate contamination caused by wafer transport and exposure, achieving a smoother and more controllable filling surface profile. Attached Figure Description

[0017] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure; Figures 2-6 This is a flowchart of the semiconductor structure corresponding to each step in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure; Figure 7 This is a schematic diagram of a deposition apparatus according to an embodiment of the present disclosure; Figure 8 A cross-sectional view of an air intake mechanism provided in one embodiment of this disclosure; Figure 9 A top view of an air intake mechanism provided in one embodiment of this disclosure; Figure 10 A bottom view of an air intake mechanism provided in one embodiment of this disclosure; Figure 11 Various cross-sectional views of an air intake mechanism provided for one embodiment of this disclosure. Detailed Implementation

[0019] As can be seen from the background technology, the yield of film layers in the current semiconductor manufacturing process is not good.

[0020] This disclosure provides a hybrid process for filling trenches, combining PEALD (Plasma-Enhanced Atomic Layer Deposition), PECVD (Plasma-Enhanced Chemical Vapor Deposition), and etching. This hybrid process fully leverages the excellent step coverage and thickness control capabilities of PEALD in aspect ratio structures, combined with the high deposition rate of PECVD, and further supplemented by in-situ etching to precisely correct over-deposition at trench openings, thereby achieving a seamless, gap-free, and perfectly filled effect. The film formed by this method not only possesses excellent density and low stress characteristics, but also, due to the self-limiting surface reaction mechanism of the PEALD process, significantly enhances the interfacial adhesion between the film and the substrate, while avoiding damage to the substrate from high-energy ions. This improves process efficiency while ensuring the structural integrity and electrical performance of the device.

[0021] It should be noted that the terminology used herein is for the purpose of describing particular implementations only and is not intended to limit the exemplary implementations according to embodiments of this disclosure. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0022] Unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure. It should also be understood that, for ease of description, the dimensions of the various parts shown in the drawings are not drawn to actual scale. Techniques, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters in the following drawings denote similar items; therefore, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

[0023] In the description of the embodiments of this disclosure, it should be understood that the orientation or positional relationship indicated by directional terms such as "front, back, up, down, left, right", "horizontal, vertical, horizontal" and "top, bottom" is generally based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this disclosure and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of the embodiments of this disclosure; the directional terms "inner" and "outer" refer to the inner and outer contours relative to the outline of each component itself.

[0024] For ease of description, spatial relative terms such as "above," "on top of," "on the upper surface of," "above," etc., are used herein to describe the spatial positional relationship of a device or feature as shown in the figures to other devices or features. It should be understood that spatial relative terms are intended to encompass different orientations in use or operation beyond the orientation of the device as described in the figures. For example, if the device in the figures were inverted, a device described as "above" or "on top of" other devices or structures would subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein will be interpreted accordingly.

[0025] Furthermore, it should be noted that the use of terms such as "first" and "second" to define components is merely for the purpose of distinguishing the corresponding components. Unless otherwise stated, the above terms have no special meaning and therefore should not be construed as limiting the scope of protection of this disclosure.

[0026] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0027] Figure 1 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure; Figures 2-6 This is a flowchart illustrating the semiconductor structure corresponding to each step in a method for fabricating a semiconductor structure according to an embodiment of this disclosure.

[0028] According to some embodiments of this disclosure, one aspect of this disclosure provides a method for preparing a semiconductor structure to improve the yield of deposited film layers.

[0029] refer to Figure 1 The preparation method includes: providing a substrate having grooves within it; performing a first deposition step on the substrate, the first deposition step being used to deposit a first film layer within the substrate, the first deposition step including introducing a first gas and a second gas, and detecting a first change in the imaginary part of the plasma load impedance; if the first change reaches a first value, performing a first cleaning process; performing a second deposition step on the substrate, the second deposition step being used to deposit a second film layer on the first film layer, the second deposition step including introducing a third gas and a fourth gas, and detecting a second change in the imaginary part of the plasma load impedance; if the second change reaches a second value, performing a second cleaning process; performing an etching step on the substrate, the etching step being used to remove a portion of the second film layer, and detecting a third change in the imaginary part of the plasma load impedance; if the third change reaches a third value, performing a third cleaning process; repeating the second deposition step and the etching step until the grooves are filled with the first film layer and the second film layer.

[0030] The semiconductor structure fabrication method provided in this disclosure achieves flexible switching of process integration and improved deposition film yield by tightly coupling process control, endpoint detection, and chamber health management through the physical quantity of the imaginary part of impedance. First, this solution enables the continuous execution of three core processes—the first deposition step, the second deposition step, and the etching step—within a single chamber through flexible switching of gas chemistry and plasma conditions. Specifically, it allows for alternating cycles of deposition (especially high-conformity deposition) and etching (such as sputtering etching or reactive etching to smooth the surface or open bottlenecks) required to fill the grooves. This allows for the completion of the "deposition-etching-redeposition" cycle without breaking the vacuum or transferring the wafer, significantly improving process efficiency, reducing interface contamination, and achieving more precise morphology control. Second, based on the first, second, and third changes as the first deposition endpoint, the second deposition endpoint, and the etching endpoint, respectively, a non-invasive physical measurement method (impedance measurement method) independent of process chemistry is used. Regardless of whether a silicon source gas (such as SiH4), oxygen source, or etching gas (such as CF4) is introduced, changes in plasma impedance can sensitively reflect the combined changes in the surface state (deposited film coverage) of the chamber walls (electrodes, surfaces) and the overall electrical properties of the wafer surface film. This is more universal than methods relying on the spectral signals of specific elements. Finally, forming a thin film in the same chamber effectively removes the accumulation of reaction byproducts on the chamber walls and electrodes. The vacuum-free process greatly reduces the risk of particulate contamination from wafer transport and exposure, achieving a smoother and more controllable filled surface profile.

[0031] The method for fabricating the semiconductor structure provided in the above embodiments will be described in detail below with reference to the accompanying drawings.

[0032] refer to Figure 2 The preparation method includes: providing a substrate 100, wherein the substrate 100 has a groove 101.

[0033] In some embodiments, the substrate 100 may be a wafer. The groove 101 may include, but is not limited to, STI shallow trench isolation or deep via.

[0034] refer to Figure 3 The preparation method includes: performing a first deposition step on a substrate 100, wherein the first deposition step is used to deposit a first film layer 102 within the substrate 100; the first deposition step includes introducing a first gas and a second gas, and detecting a first change in the imaginary part of the impedance of the substrate 100. Using the imaginary part of impedance as the endpoint of the first deposited film layer, the impedance signal can more clearly reflect the relative changes (such as ΔR and ΔX) driven by variations in wafer surface morphology and material properties, greatly improving the signal-to-noise ratio and reliability of using impedance as a method to determine the process endpoint and monitor process stability.

[0035] The imaginary part of the impedance (X) primarily reflects the system's reactance characteristics and is strongly correlated with the capacitance effect. During deposition, it directly corresponds to the thickness and dielectric constant of the insulating dielectric film on the wafer surface. The real part of the impedance (R) typically reflects the energy dissipation and resistivity characteristics (such as ion density and collisions) of the plasma or thin film. The sensor probe (usually located below the wafer) and the plasma / electrode above it form an equivalent capacitance (C). As the insulating dielectric (such as silicon oxide SiO2) film grows on the wafer surface, the dielectric layer of this "capacitor" thickens, causing a change in capacitance. This change in capacitance C directly causes a change in the imaginary part of the impedance X1, allowing the value of the imaginary part of the impedance to be obtained.

[0036] The imaginary part of the plasma load impedance refers to the overall imaginary part of the impedance formed by the detection substrate, the first film layer on the substrate, the subsequently formed second film layer, the plasma, and the deposition chamber, not the imaginary part of the impedance of a single film layer. Furthermore, the embodiments of this disclosure do not concern themselves with the imaginary parts of impedance in the initial and final states, but rather with the variable value of the imaginary part of impedance for the entire stage or the entire step.

[0037] In some embodiments, the first deposition step includes: introducing a first gas through a first air intake channel for a first time; and introducing a second gas through a second air intake channel, and causing the first gas to react with the second gas to form a first film.

[0038] In some embodiments, the first deposition step includes PEALD. The first gas comprises a silicon-containing reactant, and the second gas is an oxidizing reactant. In a specific example, the first gas may be silane, and the second gas may be oxygen.

[0039] The execution time of PEALD deposition can be determined by monitoring the first change in the imaginary part of the impedance, ΔX1. Since the PEALD-deposited film is extremely thin, its impact on the bulk plasma characteristics is negligible, and the change in its real resistance, ΔR1, is usually insignificant. However, the formation of the thin insulating layer significantly alters the surface electrical properties, leading to a decrease in sheath capacitance (C) and thus an increase in capacitive reactance. Therefore, ΔX1 exhibits a significant negative step. When this step is completed and reaches a stable plateau, it indicates that the groove surface has been uniformly covered, and the process can proceed to the next step, the first cleaning process.

[0040] In some embodiments, if the first change reaches a first value, a first cleaning process is performed.

[0041] The first cleaning process mainly includes the purification of gas delivery pipelines and the purification of the reaction chamber itself. Purifying the gas pipelines aims to prepare a clean gas delivery environment for subsequent processes, preventing premixing or residual reactions of different process gases within the pipelines. The reaction chamber can be purified by purging it with a non-reactive gas (such as argon) to remove residual reactants and byproducts. During this process, the chamber pressure remains essentially constant. This purification method can be performed simultaneously with pipeline purification, shortening the overall purification time. Alternatively, evacuation can be used to bring the chamber to a baseline vacuum, significantly reducing the pressure.

[0042] The completion status of the purification process can be monitored in real time using impedance. When the plasma is shut off, the impedance will instantly jump from the dynamically changing "plasma operating mode" to the high-impedance "purge / vacuum mode," forming a clear right-angle turn on the impedance trajectory diagram. When the impedance value enters and remains in this high-impedance steady state, it indicates that the chamber environment has been cleaned and the conditions for process switching have been met.

[0043] refer to Figure 4 The preparation method includes: performing a second deposition step on a substrate 100, the second deposition step being used to deposit a second film layer 103 on a first film layer 102, the second deposition step including introducing a third gas and a fourth gas, and detecting a second change in the imaginary part of the plasma load impedance.

[0044] In some embodiments, a fourth change in the real part of the plasma load impedance is also detected in the second deposition step; if the fourth change reaches a fourth value and the second change reaches a second value, a second cleaning process is performed.

[0045] Similarly, the real part of the detection plasma load impedance refers to the real part of the impedance of the entire system formed by the detection substrate, the first film layer on the substrate, the subsequently formed second film layer, the plasma, and the deposition chamber, not just the real part of the impedance of a single film layer. Furthermore, the embodiments of this disclosure do not concern themselves with the real parts of impedance in the initial and final states, but rather with the variable value of the real part of impedance for the entire stage or step.

[0046] The execution time of PECVD deposition needs to comprehensively consider the fourth change in the real part of the impedance, ΔR2, and the second change, ΔX2. During conformal deposition, the continuous increase in the inner surface area of ​​the groove 101 exacerbates plasma power dissipation, manifested as a steady decrease in ΔR2. Simultaneously, the increase in effective capacitance area (A) caused by the deposited film exceeds the equivalent sheath thickening (d) effect caused by the increase in film thickness, resulting in an increase in sheath capacitance. Therefore, ΔX2 continuously shifts in the negative direction. By calibrating the relationship between the cumulative values ​​of ΔR2 and ΔX2 and the deposition thickness, the deposition process can be precisely controlled to ensure that deposition is stopped when the groove opening size narrows to no less than one-third of the initial value and no top sealing occurs, and then proceeds to the next step of purification.

[0047] In some embodiments, if the second change reaches a second value, a second cleaning process is performed.

[0048] In some embodiments, the second deposition step includes PECVD.

[0049] In some embodiments, the first gas includes a silicon-containing reactant, the second and third gases are both oxidizing reactants, and the fourth gas includes TEOS (tetraethyl orthosilicate).

[0050] In some embodiments, the first film layer and the second film layer are made of the same material, such as silicon oxide.

[0051] In some embodiments, the second deposition step includes: introducing a fourth gas through a third air intake channel for a second duration; and introducing a second gas through a second air intake channel, and causing the fourth gas to react with the second gas to form a second film.

[0052] refer to Figure 5 The preparation method includes: etching a substrate 100, wherein the etching step is used to remove part of the second film layer 103, and detecting the third change in the imaginary part of the plasma load impedance.

[0053] In some embodiments, if the third change reaches a third value, a third cleaning process is performed.

[0054] In some embodiments, a fifth change in the real part of the plasma load impedance is also detected during the etching step; if the fifth change reaches a fifth value and the third change reaches a third value, a third cleaning process is performed.

[0055] The duration of the etching process is primarily determined by the third change in the imaginary part of the impedance, ΔX3. Since this process only thins the upper film of the groove to enlarge the opening, without changing the total surface area of ​​the material or the underlying material, the plasma chemical environment remains stable. Therefore, the fifth change in the real resistance, ΔR3, remains essentially unchanged or fluctuates only slightly. However, the enlargement of the opening at the top of the groove causes the local electric field distribution to flatten, resulting in a slight increase in the sheath thickness (d) in that region. Consequently, the overall capacitance decreases slightly, manifested as a clear positive shift of ΔX3 (increased capacitive reactance). When the shift of ΔX3 reaches the preset target value (corresponding to a specific opening size), the etching endpoint is reached, after which chamber cleaning can be performed.

[0056] refer to Figure 6 The preparation method includes repeating the second deposition step and the etching step until the groove is filled with the first film layer and the second film layer, and the first film layer and the second film layer together serve as the passivation film 110.

[0057] By repeating cycles of PECVD deposition and etching, the groove can be gradually filled. During this process, the changes in ΔR2 and ΔX2 decrease as the opening at the top of the groove gradually narrows. When the changes in both approach zero and reach a stable state, it indicates that the groove 101 has been completely filled.

[0058] Regarding the relationship between impedance baseline values ​​and process status: The absolute value of impedance is affected by multiple parameters such as pressure, temperature, and power. Under the premise that key process parameters remain constant, different processes exhibit significant differences in impedance baseline values ​​at the initial stage of plasma ignition due to variations in the properties of the gases used. In CF4-based etching processes, the strong electronegativity of F atoms traps a large number of electrons, leading to a sharp drop in electron density and a significant increase in plasma resistance (R3). Furthermore, the sheath structure becomes thicker and more complex due to the low electron density, reducing capacitance; therefore, it has the highest resistance baseline value and the largest negative reactance baseline value. In TEOS / O2-based PECVD processes, the low ionization efficiency of macromolecular TEOS, coupled with the weak electronegativity of O2, results in a lower plasma density. The resistance (R2) is higher than that of the PEALD process (R1), but still significantly lower than R3 of the etching process. These characteristic impedance baseline values ​​provide direct evidence for identifying the process status.

[0059] When process parameters are adjusted, the absolute value of impedance may drift, but the relative change trend of impedance within each process stage (such as a step change in ΔX, a monotonic change in ΔR, etc.) still retains its physical characteristics. Therefore, by monitoring the relative change in impedance, stable judgment and endpoint control of the process state can be achieved under varying parameter conditions.

[0060] In some embodiments, the semiconductor structure includes a deposition chamber in which a first deposition step, a second deposition step, and an etching step are performed. This allows for the formation of a thin film within the same chamber, effectively removing the accumulation of reaction byproducts on the chamber walls and electrodes. The vacuum-free process significantly reduces the risk of particulate contamination from wafer transport and exposure, achieving a smoother and more controllable surface profile.

[0061] The semiconductor structure fabrication method provided in this disclosure achieves flexible switching of process integration and improved deposition film yield by tightly coupling process control, endpoint detection, and chamber health management through the physical quantity of the imaginary part of impedance. First, this solution enables the continuous execution of three core processes—the first deposition step, the second deposition step, and the etching step—within a single chamber through flexible switching of gas chemistry and plasma conditions. Specifically, it allows for alternating cycles of deposition (especially high-conformity deposition) and etching (such as sputtering etching or reactive etching to smooth the surface or open bottlenecks) required to fill the grooves. This allows for the completion of the "deposition-etching-redeposition" cycle without breaking the vacuum or transferring the wafer, significantly improving process efficiency, reducing interface contamination, and achieving more precise morphology control. Second, based on the first, second, and third changes as the first deposition endpoint, the second deposition endpoint, and the etching endpoint, respectively, a non-invasive physical measurement method (impedance measurement method) independent of process chemistry is used. Regardless of whether a silicon source gas (such as SiH4), oxygen source, or etching gas (such as CF4) is introduced, changes in plasma impedance can sensitively reflect the combined changes in the surface state (deposited film coverage) of the chamber walls (electrodes, surfaces) and the overall electrical properties of the wafer surface film. This is more universal than methods relying on the spectral signals of specific elements. Finally, forming a thin film in the same chamber effectively removes the accumulation of reaction byproducts on the chamber walls and electrodes. The vacuum-free process greatly reduces the risk of particulate contamination from wafer transport and exposure, achieving a smoother and more controllable filled surface profile.

[0062] Accordingly, on the other hand, a deposition apparatus for performing a method for fabricating a semiconductor structure as described in any of the above embodiments is also provided, which has the same or corresponding technical features as described in the above embodiments, and will not be described in detail here.

[0063] Figure 7 This is a schematic diagram of a deposition apparatus according to an embodiment of the present disclosure; Figure 8 A cross-sectional view of an air intake mechanism provided in one embodiment of this disclosure; Figure 9 A top view of an air intake mechanism provided in one embodiment of this disclosure; Figure 10 A bottom view of an air intake mechanism provided in one embodiment of this disclosure; Figure 11Various cross-sectional views of an air intake mechanism provided for one embodiment of this disclosure.

[0064] refer to Figure 7 The deposition equipment includes: a deposition chamber 11; an air intake mechanism 10, which is located inside the deposition chamber 11 and includes at least a first air intake channel 1011, a second air intake channel 1012, and a third air intake channel 1013.

[0065] In some embodiments, the air intake mechanism 10 may be a gas spray head device.

[0066] In some embodiments, reference Figures 8-10 The air intake mechanism can include multiple air inlets, which are spaced apart on the top of the gas distribution structure. Each air inlet is connected to a cavity, improving the uniformity of gas within the cavity. Each air inlet corresponds to one air intake channel.

[0067] It should be noted that, Figure 9 and Figure 10 Only one arrangement of the first, second, and third air intake channels is shown. There can be two arrangements of the first, second, and third air intake channels. The arrangement and shape of the air outlets near the chamber can be set according to requirements, and the arrangement and shape of the air inlets away from the chamber can be set according to requirements.

[0068] In some embodiments, the air intake mechanism 10 includes a gas distribution structure 120, which includes a plurality of mutually isolated spray chambers arranged horizontally. The air inlets and spray chambers are connected and arranged in a one-to-one correspondence, and their distribution pattern is consistent. The relative contact surface morphology of the two is also basically the same. The outer surface of each air inlet and each spray chamber is an arc surface with a central angle of 90°. Different gas supply systems supply reaction gases to each spray chamber through the air inlets.

[0069] In some embodiments, the air intake mechanism 10 further includes a spray base, with the air inlet located on the spray base. The spray base and the gas distribution structure are preferably made of the same material, such as aluminum alloy or other metals that do not react with the reactant gas and are not corroded, or ceramic, quartz, or other corrosion-resistant materials. The surfaces of each structure can be coated as needed, such as anodized. The spray base can be coupled to a radio frequency (RF) power supply to serve as the RF power inlet for the reaction chamber, exciting the plasma.

[0070] In some embodiments, by setting three or more independent gas inlet channels, and then combining the first deposition step, the second deposition step, and the etching step, multiple reactive gases can be independently controlled and efficiently mixed in the same process chamber. Each gas channel can be flexibly switched and execute multiple process modules such as plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced atomic layer deposition (PEALD), and etching within the same reaction chamber according to process requirements and without disrupting the vacuum.

[0071] Specifically, in a specific example, a certain amount of first gas is provided through the first gas inlet channel. After a first time, a certain amount of second gas is provided through the second gas inlet channel, and the first gas reacts with the second gas, so that the wafer is exposed to plasma to drive the reaction between the first gas and the second gas and form a first film layer. Then, an inert gas, such as argon, is introduced through the first gas inlet channel for a first cleaning process.

[0072] Then, a certain amount of fourth gas is provided through the third gas inlet channel. After the second time, a certain amount of third gas is provided through the second gas inlet channel. Argon is provided through the first gas inlet channel, and the argon, third gas and fourth gas react to generate plasma and expose the substrate surface to plasma. In the presence of plasma, a thin film is allowed to be deposited on the wafer surface to form a second film layer. Then, an inert gas, such as argon, is introduced through the third gas inlet channel for the second cleaning process.

[0073] Furthermore, a certain amount of etching gas is provided through the first air intake channel. After the third time, argon gas is provided through the second air intake channel, and plasma is generated to expose the substrate surface to the plasma and allow etching of the second film surface while the plasma is present. Then, an inert gas, such as argon gas, is introduced through the first air intake channel for the second cleaning process.

[0074] In some embodiments, the cross-sectional dimensions of the vent holes in the spray chamber and the deposition chamber are designed with different dimensions. That is, in order to accommodate the mixing trench filling process of different processes, the shape of the vent holes will be designed accordingly for different types of gases.

[0075] refer to Figure 11 (a) For the first gas, the second gas, the third gas and the fourth gas, a stepped design is used to make the atomization more uniform, thereby forming a better uniformity of the first film layer and the second film layer.

[0076] refer to Figure 11(b) and (c) For etching gases, use a horn-shaped design or a dumbbell-shaped design with a different size, because the shower head will be etched to form a fluoride layer, which will cause the diameter of the vent to change. The horn-shaped or dumbbell-shaped outlet can resist the change in flow rate when the diameter changes, that is, the change in flow rate is smaller.

[0077] refer to Figure 11 (d) For inert gases, use a funnel-shaped or stepped design for the inlet / outlet to optimize the temperature, velocity and pressure distribution of the gas flow.

[0078] Continue to refer to Figure 7 The deposition apparatus includes a base 12, which is disposed at the bottom of the deposition chamber 11 and is used to support the substrate; and an exhaust port 13, which is disposed in a portion of the bottom area of ​​the deposition chamber 11.

[0079] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, wherein the substrate has a groove; A first deposition step is performed on the substrate, the first deposition step being used to deposit a first film layer in the substrate, the first deposition step including introducing a first gas and a second gas, and detecting a first change in the imaginary part of the plasma load impedance; If the first change reaches the first value, the first cleaning process is performed; A second deposition step is performed on the substrate, the second deposition step being used to deposit a second film layer on the first film layer, the second deposition step including introducing a third gas and a fourth gas, and detecting a second change in the imaginary part of the plasma load impedance; If the second change reaches the second value, a second cleaning process is performed; An etching step is performed on the substrate to remove a portion of the second film layer, and the third change in the plasma load impedance is detected. If the third change reaches the third value, a third cleaning process is performed; Repeat the second deposition step and the etching step until the groove is filled with the first film layer and the second film layer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The semiconductor structure includes a deposition chamber, in which the first deposition step, the second deposition step, and the etching step are performed.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that, In the second deposition step, a fourth change in the real part of the plasma load impedance is also detected; if the fourth change reaches a fourth value and the second change reaches a second value, a second cleaning process is performed.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that, In the etching step, a fifth change in the real part of the plasma load impedance is also detected; if the fifth change reaches a fifth value and the third change reaches a third value, a third cleaning process is performed.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that, The first deposition step includes PEALD; the second deposition step includes PECVD.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that, The first film layer and the second film layer are made of the same material.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that, The first gas includes silicon-containing reactants, the second gas and the third gas are both oxidizing reactants, and the fourth gas includes TEOS.

8. The method for preparing a semiconductor structure according to claim 1, characterized in that, The first deposition step includes: introducing the first gas through a first air intake channel for a first time; introducing the second gas through a second air intake channel, and causing the first gas to react with the second gas to form a first film layer.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, The second deposition step includes: introducing the fourth gas through the third air intake channel for a second duration; introducing the second gas through the second air intake channel, and causing the fourth gas to react with the second gas to form a second film layer.

10. A deposition apparatus for performing a method for fabricating a semiconductor structure as described in any one of claims 1 to 9, characterized in that, include: Deposition chamber; An air intake mechanism is located within the deposition chamber, and the air intake mechanism includes at least a first air intake channel, a second air intake channel, and a third air intake channel.

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