Semiconductor device grouping method based on conduction resistance at normal temperature and related device

Abstract

The invention discloses a semiconductor device grouping method based on conduction resistance at normal temperature and a related device, and belongs to the technical field of semiconductor manufacturing. The method comprises the following steps: under the conditions of normal-temperature typical gate bias and normal-temperature atypical gate bias, respectively measuring on-resistances of a plurality of semiconductor devices to obtain normal-temperature parameters of a plurality of groups of on-resistances of the semiconductor devices; and if the normal temperature parameter difference of the on-resistors under the same gate bias is smaller than or equal to the preset threshold value, determining that the high temperature parameter difference of the on-resistors in the group is within the allowable difference range, so that the plurality of semiconductor devices in the group can be divided into the same group. It can be seen that according to the embodiment of the invention, the parameters at high temperature can be estimated by measuring the on-resistance under the normal-temperature typical gate bias and the normal-temperature atypical gate bias, and then the semiconductor devices are grouped, so that the problem of current imbalance caused by the immature preparation process of the semiconductor devices is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method and related apparatus for grouping semiconductor devices based on on-resistance at room temperature. Background Technology

[0002] Due to the immaturity of semiconductor device fabrication processes, it is difficult to maintain consistent device parameters, inevitably leading to dynamic and static current imbalances when devices are connected in parallel. This imbalance causes unequal losses and voltage / current stress among the parallel devices, particularly creating higher overshoot stress on the weakest components, jeopardizing the safety of other parallel devices. Furthermore, current imbalances among parallel devices can cause thermal imbalances, reducing the overall system lifespan, affecting the safe operation of the converter, and forcing the entire parallel module to operate at a derating rate. Additionally, semiconductor devices operate over a wide temperature range, and wafer-level devices are prone to oxidation at high temperatures, making it difficult to measure device parameters at high temperatures. Therefore, how to group newly manufactured semiconductor devices is a pressing technical problem that needs to be solved. Summary of the Invention

[0003] This application provides a method and related apparatus for grouping semiconductor devices based on on-resistance at room temperature. By measuring the on-resistance under typical and atypical gate bias voltages at room temperature, the parameters at high temperatures can be estimated, and the semiconductor devices can be grouped to reduce the current imbalance problem caused by immature semiconductor device fabrication processes.

[0004] The first aspect of this application provides a method for grouping semiconductor devices based on their on-resistance at room temperature, the method comprising: Under typical and atypical gate bias conditions at room temperature, the on-resistance of multiple semiconductor devices was measured to obtain multiple sets of on-resistance parameters of the semiconductor devices at room temperature. If the difference in on-resistance at room temperature under the same gate bias is less than or equal to a preset threshold, then the difference in high-temperature on-resistance of the group is determined to be within the allowable range, and the multiple semiconductor devices included in the group are classified into the same group.

[0005] Optionally, the on-resistance includes the channel resistance and the epitaxial layer resistance, and the epitaxial layer resistance includes the junction field-effect transistor region resistance and the drift region resistance.

[0006] Optionally, the channel resistance is related to the transfer characteristics of the semiconductor device, and the on-resistance is related to the output characteristics of the semiconductor device.

[0007] Optionally, the channel resistance decreases with increasing temperature and has a negative temperature coefficient; the epitaxial layer resistance increases with increasing temperature and has a positive temperature coefficient; and the on-resistance of the plurality of semiconductor devices is measured at the same temperature.

[0008] Optionally, the channel resistance varies with the gate bias voltage, and the formula for the channel resistance varying with the gate bias voltage is as follows: , in, Channel resistance, The length of the channel. The width of the channel. For the electron mobility of the inversion layer, The characteristic capacitance of the gate oxide layer. For gate bias, This is the threshold voltage.

[0009] Optionally, the epitaxial resistance does not change with the gate bias voltage.

[0010] Optionally, the semiconductor device includes a silicon carbide metal-oxide-semiconductor field-effect transistor.

[0011] A second aspect of this application provides a semiconductor device grouping device based on on-resistance at room temperature, the device comprising: The on-resistance measurement unit is used to measure the on-resistance of multiple semiconductor devices under typical and atypical gate bias conditions at room temperature, and obtain multiple sets of on-resistance parameters of the semiconductor devices at room temperature. The device grouping unit is used to determine that the high-temperature parameter difference of the on-resistance of the group is within the allowable range if the difference in the room temperature parameter of the on-resistance under the same gate bias voltage is less than or equal to a preset threshold, and to classify the multiple semiconductor devices included in the group into the same group.

[0012] A third aspect of this application provides an electronic device, including: a processor and a memory; The processor is connected to a memory, wherein the memory is used to store computer programs and the processor is used to invoke the computer programs to execute the methods as described in the first aspect of the embodiments of this application.

[0013] A fourth aspect of this application provides a computer-readable storage medium storing a computer program, the computer program including program instructions, which, when executed by a processor, perform the method as described in the first aspect of this application.

[0014] This application measures the on-resistance of multiple semiconductor devices under typical and atypical gate bias conditions at room temperature, obtaining room-temperature parameters of multiple sets of on-resistance for the semiconductor devices. If the difference in room-temperature parameters of each set of on-resistance under the same gate bias is less than or equal to a preset threshold, then the difference in high-temperature parameters of that set of on-resistance is determined to be within the allowable range. Therefore, the multiple semiconductor devices included in that set can be grouped into the same group. It can be seen that the embodiments of this application can estimate the high-temperature parameters by measuring the on-resistance under typical and atypical gate bias conditions at room temperature, thereby grouping the semiconductor devices and reducing the current imbalance problem caused by immature semiconductor device fabrication processes. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 A schematic diagram of the operating environment for a semiconductor device grouping application based on on-resistance at room temperature, according to an embodiment of this application, is shown. Figure 2 A schematic flowchart of a semiconductor device grouping method based on on-resistance at room temperature provided in one embodiment of this application is shown. Figure 3 This illustration shows a schematic diagram of a semiconductor device grouping device based on on-resistance at room temperature according to an embodiment of this application; Figure 4 A schematic diagram of the structure of a computer device provided in one embodiment of this application is shown. Detailed Implementation

[0017] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0018] Please refer to Figure 1 This illustration shows a schematic diagram of a semiconductor device grouping application runtime environment based on on-resistance at room temperature, according to an embodiment of this application. The application runtime environment may include: terminal 10 and server 20.

[0019] Terminal 10 includes, but is not limited to, electronic devices such as mobile phones, computers, smart voice interaction devices, smart home appliances, in-vehicle terminals, game consoles, e-book readers, multimedia playback devices, and wearable devices. Application clients can be installed on terminal 10.

[0020] In this embodiment, the application described above can be any application capable of providing semiconductor device grouping services based on on-resistance at room temperature. Typically, this application is an industrial application. Of course, in addition to industrial applications, other types of applications can also provide services based on semiconductor device grouping dependent on on-resistance at room temperature. For example, research applications, browser applications, virtual reality (VR) applications, augmented reality (AR) applications, etc., are not limited in this embodiment. Optionally, a client of the above application runs on terminal 10.

[0021] Server 20 provides background services to clients of applications in terminal 10. For example, server 20 can be a background server for the aforementioned applications. Server 20 can be a standalone physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDN (Content Delivery Network), and big data and artificial intelligence platforms. Optionally, server 20 can simultaneously provide background services to applications in multiple terminals 10.

[0022] Optionally, terminal 10 and server 20 can communicate with each other via network 30. Terminal 10 and server 20 can be directly or indirectly connected via wired or wireless communication, which is not limited herein.

[0023] Please refer to Figure 2 This document illustrates a flowchart of a semiconductor device grouping method based on on-resistance at room temperature, according to an embodiment of this application. This method can be applied to computer devices, which refer to electronic devices capable of data computation and processing. For example, the executing entity for each step could be... Figure 1 The application runtime environment shown is either terminal 10 or server 20. The method may include the following steps: Step 201: Under typical gate bias and atypical gate bias at room temperature, the on-resistance of multiple semiconductor devices is measured to obtain multiple sets of on-resistance of the semiconductor devices.

[0024] Semiconductor devices are electronic devices whose conductivity lies between that of a good conductor and an insulator. They utilize the special electrical properties of semiconductor materials to perform specific functions and can be used to generate, control, receive, transform, amplify signals, and perform energy conversion.

[0025] Semiconductor devices use silicon, germanium, or gallium arsenide as semiconductor materials and can be used as rectifiers, oscillators, light emitters, amplifiers, photometers, and other similar devices. To distinguish them from integrated circuits, they are sometimes also called discrete devices.

[0026] In one embodiment provided in this application, the semiconductor device includes a silicon carbide metal-oxide-semiconductor field-effect transistor (SiC MOSFET).

[0027] Here, ambient temperature, also called general temperature or room temperature, is generally defined as 25℃. In chemical processes, it is often represented by AMB, which stands for ambiance. In my country, ambient temperature in engineering is calculated as 20℃, which is the temperature in most parts of my country during spring and autumn, such as circulating water temperature (natural water temperature). However, in the laboratory, due to the influence of internal and external factors, ambient temperature is difficult to maintain a stable value for a long time and will fluctuate within a certain range. Therefore, the ambient temperature in this application can be 10℃-30℃.

[0028] Among them, on-resistance refers to the ratio of the voltage across a semiconductor device to the on-current after it is turned on. It is an important parameter of semiconductors. Therefore, this application also selects this parameter for classifying semiconductor devices.

[0029] In semiconductor devices, on-resistance mainly includes channel resistance. Junction Field Effect Transistor (JEFT) Resistance Drift region resistance substrate resistance and contact resistance And so on. Among them, channel resistance JEFT resistor and drift region resistance Occupying the semiconductor on-resistance The main part, JEFT resistor and drift region resistance It forms the epitaxial layer resistor That is, the on-resistance of SiCMOSFET It can be represented as:

[0030] Therefore, in one embodiment provided in this application, the on-resistance Including channel resistance and epitaxial layer resistance The epitaxial layer resistance Including junction field-effect transistor resistance and drift region resistance The channel resistance is related to the transfer characteristics of the semiconductor device, and the on-resistance is related to the output characteristics of the semiconductor device. In addition, current sharing is divided into dynamic and static current sharing; transfer characteristics are related to dynamic current sharing, and output characteristics are related to static current sharing.

[0031] In one embodiment provided in this application, the channel resistance varies with the gate bias voltage, and the formula for the channel resistance varying with the gate bias voltage is as follows: , in, Channel resistance, The length of the channel. The width of the channel. For the electron mobility of the inversion layer, The characteristic capacitance of the gate oxide layer. For gate bias, This is the threshold voltage.

[0032] In one embodiment provided in this application, the epitaxial resistance does not change with the gate bias voltage.

[0033] In one embodiment provided in this application, the channel resistance decreases with increasing temperature and has a negative temperature coefficient; the epitaxial layer resistance increases with increasing temperature and has a positive temperature coefficient; and the on-resistance of the plurality of semiconductor devices is measured at the same temperature.

[0034] Step 202: If the difference in room temperature parameters of the on-resistance of each group under the same gate bias voltage is less than or equal to a preset threshold, then the difference in high temperature parameters of the on-resistance of that group is determined to be within the allowable range, and the multiple semiconductor devices included in that group are classified into the same group.

[0035] Here, "multiple" refers to at least two. If there are more than two, such as three, then if two of the three have a room-temperature parameter difference less than or equal to a preset threshold, these two are grouped together, and the third belongs to a different group. The preset threshold for the room-temperature parameter difference of the on-resistance under typical gate bias at room temperature can be equal to or unequal to the preset threshold for the room-temperature parameter difference of the on-resistance under atypical gate bias at room temperature; this is not limited further. Furthermore, the preset threshold can be determined based on the standard values ​​of the room-temperature parameters of the on-resistance under typical and atypical gate bias at room temperature. For example, if the standard value is 10mΩ, then semiconductor devices with an on-resistance within 10±0.1mΩ are grouped together.

[0036] High temperature is defined relative to normal temperature. For example, anything above normal temperature can be called high temperature. If normal temperature is 20°C, then anything above 20°C is considered high temperature; if normal temperature is 35°C, then anything above 35°C is considered high temperature. Again, no specific limitation is made; the high temperature range of a semiconductor device can be determined based on its specific type.

[0037] Similarly, the difference can be determined based on the specific type of semiconductor device, and can be a relative or absolute value. For example, if the on-resistance is 10mΩ, the difference can be ±0.1mΩ or 1% of the on-resistance; if the on-resistance is 10mΩ, the difference can be ±0.05mΩ or 0.5% of the on-resistance; no specific limitation is made here.

[0038] This application measures the on-resistance of multiple semiconductor devices under typical and atypical gate bias conditions at room temperature, obtaining room-temperature parameters of multiple sets of on-resistance for the semiconductor devices. If the difference in room-temperature parameters of each set of on-resistance under the same gate bias is less than or equal to a preset threshold, then the difference in high-temperature parameters of that set of on-resistance is determined to be within the allowable range. Therefore, the multiple semiconductor devices included in that set can be grouped into the same group. It can be seen that the embodiments of this application can estimate the high-temperature parameters by measuring the on-resistance under typical and atypical gate bias conditions at room temperature, thereby grouping the semiconductor devices and reducing the current imbalance problem caused by immature semiconductor device fabrication processes.

[0039] In a specific application scenario provided in this application embodiment, firstly, at room temperature and typical gate bias voltage... Below, the on-resistance of multiple SiC MOSFETs Perform the measurement and record the results. , ··· At room temperature and below typical gate bias 5V gate bias Below, the on-resistance of multiple SiC MOSFETs Perform the measurement and record the results. , ··· ; Within the preset threshold range, if , This allows us to conclude that multiple SiC MOSFETs have the same channel resistance at room temperature. and epitaxial layer resistance Therefore, it can be deduced that multiple SiC MOSFETs have the same on-resistance at the same high temperature. Therefore, it can be deduced that multiple SiC MOSFETs have the same transfer and output characteristics at high temperatures, and thus these multiple SiC MOSFETs can be grouped into the same device group. In other cases, it can be deduced that multiple SiC MOSFETs do not simultaneously have the same transfer and output characteristics, and these multiple SiC MOSFETs cannot be grouped into the same device group. The above method can be used to group SiC MOSFETs.

[0040] Figure 3 A schematic diagram of a semiconductor device grouping device based on on-resistance at room temperature is shown according to an embodiment of this application. The device includes: The on-resistance measurement unit 301 is used to measure the on-resistance of multiple semiconductor devices under typical gate bias and atypical gate bias conditions at room temperature, and obtain room temperature parameters of multiple sets of on-resistance of semiconductor devices. Device grouping unit 302 is used to determine that the high temperature parameter difference of the on-resistance of the group is within the allowable difference range if the difference in the room temperature parameter of the on-resistance under the same gate bias voltage is less than or equal to a preset threshold, and to classify the multiple semiconductor devices included in the group into the same group.

[0041] Optionally, the on-resistance includes the channel resistance and the epitaxial layer resistance, and the epitaxial layer resistance includes the junction field-effect transistor region resistance and the drift region resistance.

[0042] Optionally, the channel resistance is related to the transfer characteristics of the semiconductor device, and the on-resistance is related to the output characteristics of the semiconductor device.

[0043] Optionally, the channel resistance decreases with increasing temperature and has a negative temperature coefficient; the epitaxial layer resistance increases with increasing temperature and has a positive temperature coefficient; and the on-resistance of the plurality of semiconductor devices is measured at the same temperature.

[0044] Optionally, the channel resistance varies with the gate bias voltage, and the formula for the channel resistance varying with the gate bias voltage is as follows: , in, Channel resistance, The length of the channel. The width of the channel. For the electron mobility of the inversion layer, The characteristic capacitance of the gate oxide layer. For gate bias, This is the threshold voltage.

[0045] Optionally, the epitaxial resistance does not change with the gate bias voltage.

[0046] Optionally, the semiconductor device includes a silicon carbide metal-oxide-semiconductor field-effect transistor.

[0047] Figure 4 A schematic diagram of the structure of a computer device provided in one embodiment of this application is shown, including a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, it implements the functions of the computer system based on the semiconductor device grouping method with on-resistance at room temperature in any of the above embodiments.

[0048] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a computer, causes the computer to perform the functions of the computer system of the semiconductor device grouping method based on on-resistance at room temperature in any of the above embodiments.

[0049] This application also provides a computer program product containing instructions that, when executed by a computer, cause the computer to perform the functions of the computer system based on the semiconductor device grouping method with on-resistance at room temperature in any of the above embodiments.

[0050] It is understood that the specific examples in this application are only intended to help those skilled in the art better understand the implementation methods of this application, and are not intended to limit the scope of the invention.

[0051] It is understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not limit the implementation process of the embodiments of this application in any way.

[0052] It is understood that the various implementation methods described in this application can be implemented individually or in combination, and the implementation methods in this application are not limited in this respect.

[0053] Unless otherwise stated, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0054] It is understood that the processor in the embodiments of this application can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method embodiments can be completed by the integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0055] It is understood that the memory in the embodiments of this application may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Specifically, non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM). It should be noted that the memory in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0056] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0057] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the aforementioned method implementations, and will not be repeated here.

[0058] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0059] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0060] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0061] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0062] The above are merely specific embodiments of this application, but the scope of protection of this invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this invention should be determined by the scope of the claims.

Claims

1. A method for grouping semiconductor devices based on on-resistance at room temperature, characterized in that, The method includes: Under typical and atypical gate bias conditions at room temperature, the on-resistance of multiple semiconductor devices was measured to obtain multiple sets of on-resistance parameters of the semiconductor devices at room temperature. If the difference in on-resistance at room temperature under the same gate bias is less than or equal to a preset threshold, then the difference in high-temperature on-resistance of the group is determined to be within the allowable range, and the multiple semiconductor devices included in the group are classified into the same group.

2. The method according to claim 1, characterized in that, The on-resistance includes the channel resistance and the epitaxial layer resistance, and the epitaxial layer resistance includes the junction field-effect transistor region resistance and the drift region resistance.

3. The method according to claim 2, characterized in that, The channel resistance is related to the transfer characteristics of the semiconductor device, and the on-resistance is related to the output characteristics of the semiconductor device.

4. The method according to claim 2, characterized in that, The channel resistance decreases with increasing temperature and has a negative temperature coefficient; the epitaxial layer resistance increases with increasing temperature and has a positive temperature coefficient; and the on-resistance of the plurality of semiconductor devices is measured at the same temperature.

5. The method according to claim 2, characterized in that, The channel resistance changes with the gate bias voltage, and the formula for the change in channel resistance with gate bias voltage is as follows: ， in, Channel resistance, The length of the channel. The width of the channel. For the electron mobility of the inversion layer, The characteristic capacitance of the gate oxide layer. For gate bias, This is the threshold voltage.

6. The method according to claim 2, characterized in that, The epitaxial resistance does not change with the gate bias voltage.

7. The method according to claim 1, characterized in that, The semiconductor device includes a silicon carbide metal-oxide-semiconductor field-effect transistor.

8. A semiconductor device grouping device based on on-resistance at room temperature, characterized in that, The device includes: The on-resistance measurement unit is used to measure the on-resistance of multiple semiconductor devices under typical and atypical gate bias conditions at room temperature, and obtain multiple sets of on-resistance parameters of the semiconductor devices at room temperature. The device grouping unit is used to determine that the high-temperature parameter difference of the on-resistance of the group is within the allowable range if the difference in the room temperature parameter of the on-resistance under the same gate bias voltage is less than or equal to a preset threshold, and to classify the multiple semiconductor devices included in the group into the same group.

9. An electronic device, characterized in that, include: Processor and memory; The processor is connected to a memory, wherein the memory is used to store a computer program, and the processor is used to invoke the computer program to perform the method as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, the computer program including program instructions that, when executed by a processor, perform the method as described in any one of claims 1-7.

Images