Mask structure, preparation method and preparation method of semiconductor device

Abstract

The invention discloses a mask structure, a preparation method and a preparation method of a semiconductor device, and the mask structure comprises a buffer layer which is disposed at one side of a substrate; the first hard mask layer and the second hard mask layer are sequentially stacked on the surface, far away from the substrate, of the buffer layer; wherein a groove is formed in the surface, away from the substrate, of the second hard mask layer, the groove penetrates through the first hard mask layer in the thickness direction of the second hard mask layer, at least part of the bottom of the groove is exposed out of the surface of the buffer layer, and the first hard mask layer and the second hard mask layer are made of different materials. The thickness of the second hard mask layer is greater than that of the first hard mask layer, so that the surface of the substrate is protected, and the deformation of the substrate is reduced.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of semiconductor technology, and particularly relate to a mask structure, a preparation method and a preparation method of a semiconductor device. BACKGROUND

[0002] In the process of preparing a semiconductor device, a hard mask structure is often used. However, when forming a hard mask on a semiconductor substrate, the substrate material is often damaged or the substrate is deformed, thereby resulting in poor performance of the semiconductor device. SUMMARY

[0003] The present application provides a mask structure, a preparation method and a preparation method of a semiconductor device, which realizes protection of the surface of the substrate and reduces the deformation of the substrate.

[0004] In a first aspect, an embodiment of the present application provides a mask structure, comprising: a buffer layer arranged on one side of a substrate; a first hard mask layer and a second hard mask layer are stacked in sequence on the surface of the buffer layer away from the substrate; wherein the second hard mask layer is provided with a groove away from the surface of the substrate, the groove penetrates the first hard mask layer along the thickness direction of the second hard mask layer, the bottom of the groove at least partially exposes the surface of the buffer layer, the material of the first hard mask layer and the second hard mask layer is different, and the thickness of the second hard mask layer is greater than the thickness of the first hard mask layer.

[0005] Optionally, the thickness of the second hard mask layer is in the range of 8KA-12KA, and the thickness of the first hard mask layer is in the range of 5KA-10KA.

[0006] Optionally, the thickness of the first hard mask layer is greater than the thickness of the buffer layer.

[0007] Optionally, the thickness of the buffer layer is in the range of 200A-800A.

[0008] Optionally, the etching selectivity ratio of the first hard mask layer to the buffer layer is greater than 5.

[0009] Optionally, the second hard mask layer and the buffer layer comprise a silicon dioxide layer, and the first hard mask layer comprises a polysilicon layer.

[0010] In a second aspect, an embodiment of the present application provides a preparation method of a mask structure, comprising: providing a substrate, and forming a buffer layer on the surface of the substrate; forming a first hard mask layer and a second hard mask layer on the surface of the buffer layer away from the substrate in sequence; the first hard mask layer and the second hard mask layer are made of different materials, and the thickness of the second hard mask layer is greater than the thickness of the first hard mask layer; forming a groove on the surface of the second hard mask layer away from the substrate, wherein the groove penetrates the first hard mask layer along the thickness direction of the second hard mask layer, and the bottom of the groove at least partially exposes the surface of the buffer layer.

[0011] Optionally, forming the groove on the surface of the second hard mask layer away from the substrate comprises: forming a photoresist layer on the surface of the second hard mask layer away from the substrate, and the photoresist layer is provided with a pattern of the groove; forming the groove in the second hard mask layer and the first hard mask layer according to the pattern; removing the photoresist layer.

[0012] Optionally, the groove is formed in the second hard mask layer and the first hard mask layer by dry etching.

[0013] In a third aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device, comprising: providing a substrate; forming the mask structure according to any of the embodiments of the present application on the surface of the substrate; performing ion implantation on the substrate at positions corresponding to the groove by blocking of the mask structure.

[0014] The mask structure provided by the embodiment of the present application comprises: a buffer layer, a first hard mask layer and a second hard mask layer arranged in sequence on one side of a substrate, wherein the second hard mask layer is provided with a groove on the surface away from the substrate, the groove penetrates the first hard mask layer along the thickness direction of the second hard mask layer, and the bottom of the groove at least partially exposes the surface of the buffer layer. The buffer layer is used to protect the surface of the substrate, so as to avoid the problems of damage to the surface of the substrate and abnormal appearance caused by over-etching of the first hard mask layer during groove etching of the first hard mask layer. Further, by setting the first hard mask layer and the second hard mask layer to be made of different materials and the thickness of the second hard mask layer to be greater than the thickness of the first hard mask layer, the side wall has better perpendicularity, the accuracy of shape transfer is improved, the stress of the first hard mask layer acting on the substrate is reduced by using the thicker second hard mask layer, and part of the stress is released by the groove penetrating the first hard mask layer, so as to reduce the deformation of the substrate. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 A structural schematic diagram of the mask structure is provided for the embodiment of the present application; Figure 2 A flowchart of a preparation method of a mask structure is provided for an embodiment of the present application. Figure 3 An intermediate structure diagram in the preparation of a mask structure is provided for an embodiment of the present application. Figures 4-5 An intermediate structure diagram in the preparation of a mask structure is provided for another embodiment of the present application. Figure 6 A flowchart of a preparation method of a semiconductor device is provided for an embodiment of the present application. Figure 7 A surface diagram of a semiconductor device is provided for related art. Figure 8 A surface diagram of a semiconductor device is provided for an embodiment of the present application. Figure 9 A yield diagram of a semiconductor device on a wafer is provided for related art. Figure 10 A yield diagram of a semiconductor device on a wafer is provided for an embodiment of the present application. Figure 11 A substrate surface implantation concentration diagram is provided for related art. Figure 12 A substrate surface implantation concentration diagram is provided for an embodiment of the present application. DETAILED DESCRIPTION

[0016] To make the objectives, technical solutions and advantages of embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0017] In a semiconductor device preparation process, a hard mask structure is often used, which can include a polysilicon material layer. The polysilicon material layer is disposed on a substrate, and a pattern is transferred to the polysilicon material layer through etching, and finally to the substrate. However, the polysilicon material layer and the substrate have different thermal expansion coefficients. During deposition of the polysilicon material layer, if the deposition temperature is high, and then during the cooling process, due to the difference in thermal expansion coefficients, thermal stress will be generated between the polysilicon material layer and the substrate, resulting in warping of the substrate edge. When the polysilicon material layer is etched to form a transfer pattern, the substrate surface is also prone to over-etching, causing unevenness of the substrate surface and abnormal appearance.

[0018] Therefore, Figure 1A structural diagram of a mask structure is provided for an embodiment of the present application, see Figure 1 , comprising: a buffer layer 120 arranged on one side of a substrate 110; A first hard mask layer 130 and a second hard mask layer 140 are sequentially stacked on the surface of the buffer layer 120 away from the substrate 110; wherein the surface of the second hard mask layer 140 away from the substrate 110 is provided with a groove 150, the groove 150 penetrates the first hard mask layer 130 along the thickness direction of the second hard mask layer 140, the bottom of the groove 150 at least partially exposes the surface of the buffer layer 120, the material of the first hard mask layer 130 and the second hard mask layer 140 is different, and the thickness of the second hard mask layer 140 is greater than the thickness of the first hard mask layer 130.

[0019] Specifically, the material of the substrate 110 can be silicon or silicon carbide. In some embodiments, the substrate 110 can include a base and an epitaxial layer located on one side of the base. For example, the epitaxial layer can be formed on the surface of the base by epitaxial growth. The surface of the substrate 110 is sequentially formed with a buffer layer 120, a first hard mask layer 130, and a second hard mask layer 140. The buffer layer 120, the first hard mask layer 130, and the second hard mask layer 140 can all be formed by a deposition process. In the thickness direction, a groove 150 penetrates the first hard mask layer 130 and the second hard mask layer 140, and the bottom of the groove 150 exposes at least part of the buffer layer 120. The remaining first hard mask layer 130 and second hard mask layer 140 can act as a barrier layer to transfer the shape of the groove 150 in the second hard mask layer 140 to the substrate 110 in a lithography process or an implantation process. It should be noted that the shape of the groove 150 can be set according to the design needs of the semiconductor device, for example, the groove 150 can be designed as a continuous groove 150 or a discontinuous groove 150. For example, the shape of the groove 150 can be formed in the first hard mask layer 130 and the second hard mask layer 140 by an etching process. In the embodiment of the present application, the materials of the first hard mask layer 130 and the second hard mask layer 140 are different, which can avoid the problem that the first hard mask layer 130 and the second hard mask layer 140 form a relatively thick film layer when the materials are the same. For a relatively thick film layer, the etching time will be longer than for a relatively thin film layer, and as the etching time increases, the cumulative effect of ion bombardment in dry etching will also accumulate, which can easily lead to a decrease in the etching rate of the sidewall, thereby causing the problem of sidewall tilt. By setting the first hard mask layer 130 and the second hard mask layer 140 to be different materials, the cumulative effect can be reduced through a segmented etching process, so that the sidewall has good perpendicularity, thereby improving the accuracy of shape transfer. The buffer layer 120 can act as a stop layer to stop the etching process of the first hard mask layer 130 when the etching depth reaches the buffer layer 120, which can avoid over-etching of the first hard mask layer 130 and damage to the surface of the substrate 110 and abnormal appearance. The first hard mask layer 130 is usually formed on the substrate 110 by a deposition method. Since the material properties of the first hard mask layer 130 and the substrate 110 are different, for example, the thermal expansion coefficients are different, the first hard mask layer 130 will generally have a certain stress acting on the substrate 110 after being prepared, which can cause the substrate 110 to deform greatly, thereby causing problems such as defocus in subsequent lithography processes. In the embodiment of the present application, the second hard mask layer 140 is arranged on the first hard mask layer 130, and the thickness of the second hard mask layer 140 is greater than the thickness of the first hard mask layer 130. The stress generated by the first hard mask layer 130 is partially offset by the thicker second hard mask layer 140, thereby reducing the stress of the first hard mask layer 130 acting on the substrate 110.Further, the groove 150 penetrates the first hard mask layer 130, and can also release part of the stress, which is conducive to reducing the deformation of the substrate 110.

[0020] The mask structure provided by the embodiment of the application comprises, from one side of the substrate 110, a buffer layer 120, a first hard mask layer 130, and a second hard mask layer 140, wherein the second hard mask layer 140 is provided with a groove 150 away from the surface of the substrate 110, the groove 150 penetrates the first hard mask layer 130 along the thickness direction of the second hard mask layer 140, and the bottom of the groove 150 at least partially exposes the surface of the buffer layer 120. The surface of the substrate 110 is protected by the buffer layer 120, so as to avoid the problem of damage to the surface of the substrate 110 and abnormal appearance caused by over-etching of the first hard mask layer 130 in the process of etching the groove 150 on the first hard mask layer 130. Further, by setting the first hard mask layer 130 and the second hard mask layer 140 to be different materials, and by setting the thickness of the second hard mask layer 140 to be greater than the thickness of the first hard mask layer 130, the side wall has better perpendicularity, the accuracy of the transfer shape is improved, the stress of the first hard mask layer 130 acting on the substrate 110 is reduced by the thicker second hard mask layer 140, and part of the stress is released by the groove 150 penetrating the first hard mask layer 130, which is conducive to reducing the deformation of the substrate 110.

[0021] Based on the above embodiment, the thickness of the second hard mask layer 140 is greater than the thickness of the first hard mask layer 130. On the one hand, the second hard mask layer 140 can be used to offset the stress of the first hard mask layer 130, and on the other hand, the second hard mask layer 140 can be used to provide the main thickness of the mask structure, so that the thickness requirement of the first hard mask layer 130 can be reduced, and thus the stress influence caused by the first hard mask layer 130 is further reduced. When etching the groove 150 on the first hard mask layer 130, the etching time can be better controlled for the first hard mask layer 130 with smaller thickness, and the influence of over-etching on the thickness of the buffer layer 120 is reduced. In the embodiment of the application, optionally, the thickness of the second hard mask layer 140 ranges from 8KA to 12KA, for example, the thickness of the second hard mask layer 140 can be 8KA, 9KA, 10KA, 11KA or 12KA. The thickness of the first hard mask layer 130 ranges from 5KA to 10KA. For example, the thickness of the first hard mask layer 130 can be 5KA, 6KA, 7KA, 8KA, 9KA or 10KA.

[0022] Optionally, the thickness of the first hard mask layer 130 is greater than the thickness of the buffer layer 120. Specifically, the main body of the first hard mask layer 130 serves as a mask structure, and the thickness of the first hard mask layer 130 is greater than the thickness of the buffer layer 120. In the process of etching to form the groove 150, the buffer layer 120 serves as a stop layer and can be used to protect the surface of the substrate 110 from etching damage. When ion implantation is performed using a mask structure, the buffer layer 120 serves as a pad layer, and by designing the deposition thickness of the buffer layer 120, parameters such as ion implantation depth and shallow ion implantation concentration in the substrate 110 during ion implantation can be adjusted, thereby regulating the performance parameters of the prepared semiconductor device. For example, a thinner buffer layer 120 can increase the depth of ion implantation into the substrate 110, and a thicker buffer layer 120 can reduce the depth of ion implantation into the substrate 110 and the shallow ion implantation concentration. Optionally, the thickness of the buffer layer 120 ranges from 200A to 800A, for example, the thickness of the buffer layer 120 is 200A, 300A, 400A, 500A, 600A, 700A, or 800A. In combination with the above embodiments, a relatively small thickness of the first hard mask layer 130 can better control the etching time, thereby reducing the impact of over-etching on the thickness of the buffer layer 120, and thus more favorably maintaining the uniform thickness of the buffer layer 120 and making the ion implantation parameters meet the design expectations.

[0023] Optionally, the etching selectivity of the first hard mask layer 130 to the buffer layer 120 is greater than 5. The etching selectivity is a ratio of etching rates between a desired material and a material that should not be etched during etching. Here, the first hard mask layer 130 is the target material for etching, and the buffer layer 120 is the material that should not be etched. The higher the etching selectivity, the faster the etching rate of the first hard mask layer 130 and the slower the etching rate of the buffer layer 120. For example, in the embodiment of the present application, the etching selectivity of the first hard mask layer 130 to the buffer layer 120 is greater than 5, which can be considered as high selectivity, thereby ensuring that the buffer layer 120 will not be further etched after the first hard mask layer 130 is etched, and reducing the impact of over-etching of the first hard mask layer 130 on the buffer layer 120. Optionally, the first hard mask layer 130 can be a polysilicon layer, and the buffer layer 120 can be a silicon dioxide layer. In dry etching, the selectivity of polysilicon to silicon dioxide is high, and even if there is slight over-etching of the first hard mask layer 130, the actual thickness of the buffer layer 120 consumed is very low. Optionally, the second hard mask layer 140 can be a silicon dioxide layer, which can serve as a mask during etching of the first hard mask layer 130. Due to the high selectivity of polysilicon to silicon dioxide, etching of the second hard mask layer 140 can be reduced, the masking effect of the second hard mask layer 140 can be improved, and the impact of etching of the first hard mask layer 130 on the sidewall of the groove 150 of the second hard mask layer 140 can be reduced.

[0024] Figure 2 A flowchart of a preparation method of a mask structure is provided for an embodiment of the present application, Figure 3 A schematic diagram of an intermediate structure in the preparation of a mask structure is provided for an embodiment of the present application, referring to Figure 2 and Figure 3 , comprising: S110, providing a substrate 110, and forming a buffer layer 120 on a surface of the substrate 110; Specifically, the material of the substrate 110 can be silicon or silicon carbide. In some embodiments, the substrate 110 can include a base and an epitaxial layer, and the epitaxial layer is located on one side of the base. For example, the epitaxial layer can be formed on the surface of the base by epitaxial growth. After the surface of the substrate 110 is pre-cleaned, the buffer layer 120 is deposited on the surface of the substrate 110.

[0025] S120, sequentially forming a first hard mask layer 130 and a second hard mask layer 140 on a surface of the buffer layer 120 away from the substrate 110; the first hard mask layer 130 and the second hard mask layer 140 are made of different materials, and the thickness of the second hard mask layer 140 is greater than that of the first hard mask layer 130; the structure is as shown in Figure 3 .

[0026] S130, forming a groove 150 on a surface of the second hard mask layer 140 away from the substrate 110, wherein the groove 150 penetrates the first hard mask layer 130 along the thickness direction of the second hard mask layer 140, and the bottom of the groove 150 at least partially exposes the surface of the buffer layer 120.

[0027] Specifically, in the thickness direction, the groove 150 penetrates the first hard mask layer 130 and the second hard mask layer 140, and the bottom of the groove 150 exposes at least part of the buffer layer 120. The remaining first hard mask layer 130 and second hard mask layer 140 can be used as a barrier layer to transfer the shape of the groove 150 to the substrate 110 in the lithography process or implantation process. It should be noted that the shape of the groove 150 can be set according to the design needs of the semiconductor device, for example, the groove 150 can be designed as a continuous groove 150 or a discontinuous groove 150. For example, the shape of the groove 150 can be formed by etching the first hard mask layer 130 and the second hard mask layer 140. In the embodiment of the present application, the first hard mask layer 130 and the second hard mask layer 140 are made of different materials, which can avoid the problem that the first hard mask layer 130 and the second hard mask layer 140 are made of the same material and form a relatively thick film layer. For a relatively thick film layer, the etching time will be longer than that of a relatively thin film layer, and as the etching time increases, the cumulative effect of ion bombardment in dry etching will also accumulate, which can easily cause the sidewall etching rate to decrease, thereby causing the problem of sidewall tilt. By setting the first hard mask layer 130 and the second hard mask layer 140 to be made of different materials, the cumulative effect can be reduced through a segmented etching process, so that the sidewall has good verticality, thereby improving the accuracy of shape transfer. Among them, the buffer layer 120 can be used as a stop layer to etch the first hard mask layer 130 during the groove 150 etching process. When the etching depth reaches the buffer layer 120, the etching rate decreases, which can avoid over-etching of the first hard mask layer 130 to cause damage to the surface of the substrate 110 and abnormal appearance. The first hard mask layer 130 is usually formed on the substrate 110 by a deposition method. Because the material properties of the first hard mask layer 130 and the substrate 110 are different, for example, the thermal expansion coefficients are different, after the first hard mask layer 130 is prepared, a certain stress will act on the substrate 110, which can cause the substrate 110 to deform greatly, thereby causing problems such as defocus in the subsequent lithography process. In the embodiment of the present application, the second hard mask layer 140 is arranged on the first hard mask layer 130, and the thickness of the second hard mask layer 140 is greater than the thickness of the first hard mask layer 130. The stress generated by the relatively thick second hard mask layer 140 on the first hard mask layer 130 is partially offset, thereby reducing the stress of the first hard mask layer 130 acting on the substrate 110. Further, the groove 150 penetrates the first hard mask layer 130, which can also play a role in releasing part of the stress, which is beneficial to reduce the deformation of the substrate 110.

[0028] Optionally, the groove 150 is formed on the surface of the second hard mask layer 140 away from the substrate 110, comprising: forming a photoresist layer 160 on the surface of the second hard mask layer 140 away from the substrate 110, and the photoresist layer 160 is provided with a pattern of the groove 150; According to the pattern, grooves 150 are formed in the second hard mask layer 140 and the first hard mask layer 130; The photoresist layer 160 is removed.

[0029] Specifically, Figures 4-5 An intermediate structure diagram for preparing a mask structure of another embodiment of the present application is shown in FIG. 6. Figure 4 And Figure 5 The photoresist layer 160 is formed on the surface of the second hard mask layer 140 away from the substrate 110, and the photoresist layer 160 is exposed and developed so that the pattern corresponding to the groove 150 is transferred to the photoresist layer 160. The photoresist layer 160 is used as a mask to etch the second hard mask layer 140 and the first hard mask layer 130, so that the pattern corresponding to the groove 150 is transferred to the second hard mask layer 140 and the first hard mask layer 130. In order to further improve the perpendicularity of the sidewall of the groove 150, the second hard mask layer 140 and the first hard mask layer 130 are etched by dry etching to form the groove 150. For example, the first hard mask layer 130 can be a polysilicon layer, and the second hard mask layer 140 can be a silicon dioxide layer. Therefore, different plasma etching can be used for the second hard mask layer 140 and the first hard mask layer 130. For example, chlorine-based plasma etching can be used for the first hard mask layer 130, and fluorine-based plasma etching can be used for the second hard mask layer 140.

[0030] Figure 6 A flowchart of a preparation method of a semiconductor device according to an embodiment of the present application is shown in FIG. 7. Figure 6 The preparation method comprises the following steps: S210, providing a substrate 110; Specifically, the material of the substrate 110 can be silicon or silicon carbide. In some embodiments, the substrate 110 can include a base and an epitaxial layer, and the epitaxial layer is located on one side of the base. For example, the epitaxial layer can be formed on the surface of the base by epitaxial growth.

[0031] S220, forming a mask structure of any embodiment of the present application on the surface of the substrate 110; S230. Ion implantation is performed on the substrate 110 at the location corresponding to the groove 150 by means of a mask structure. Specifically, the groove 150 of the mask structure penetrates the first hard mask layer 130 and the second hard mask layer 140, and at least part of the buffer layer 120 is exposed at the bottom of the groove 150. The remaining first hard mask layer 130 and the second hard mask layer 140 can serve as barrier layers, forming an implantation region at the bottom of the substrate 110 corresponding to the groove 150 during the implantation process. The buffer layer 120 can serve as a stop layer. During the etching of the groove 150 of the first hard mask layer 130, when the etching depth reaches the buffer layer 120, the etching rate decreases, which can prevent over-etching of the first hard mask layer 130 and avoid damage to the surface of the substrate 110 and abnormal appearance. Figure 7 A schematic diagram of the surface of a semiconductor device provided for related technologies. Figure 8 This is a schematic diagram of the surface of a semiconductor device provided in an embodiment of the present invention. See also: Figure 7 and Figure 8 , Figure 7 Traditional single-layer or double-layer mask structures are used for semiconductor devices. Due to the lack of a buffer layer 120, there is some over-etching on the surface of the substrate 110, resulting in abnormal color appearance (manifesting as yellowing) on ​​the substrate 110. In this embodiment of the invention, a three-layer structure consisting of a buffer layer 120, a first hard mask layer 130, and a second hard mask layer 140 effectively protects the surface of the substrate 110, resulting in a better surface appearance.

[0032] In this embodiment of the invention, a second hard mask layer 140 is disposed on the first hard mask layer 130, and the thickness of the second hard mask layer 140 is greater than the thickness of the first hard mask layer 130. The thicker second hard mask layer 140 partially offsets the stress generated by the first hard mask layer 130, thereby reducing the stress exerted by the first hard mask layer 130 on the substrate 110. Furthermore, the groove 150 penetrates the first hard mask layer 130, which can also release some stress, thus helping to reduce the deformation of the substrate 110. Figure 9 This diagram illustrates the yield of on-wafer semiconductor devices for related technologies. Figure 10 This is a schematic diagram illustrating the yield of a semiconductor device on a wafer according to an embodiment of the present invention. (See attached diagram.) Figure 9 and Figure 10 Traditional mask structures suffer from low yields at the edges of the substrate 110 due to stress issues causing deformation. However, the mask structure of this embodiment reduces stress on the substrate 110, resulting in better yields for the semiconductor devices at the edges (shown in green).

[0033] When performing ion implantation using a mask structure, the buffer layer 120 serves as a pad. By designing the deposition thickness of the buffer layer 120, parameters such as the ion implantation depth and shallow ion implantation concentration in the substrate 110 during the ion implantation process can be adjusted, thereby controlling the performance parameters of the fabricated semiconductor device. For example, a thinner buffer layer 120 can increase the ion implantation depth into the substrate 110, while a thicker buffer layer 120 can decrease the ion implantation depth into the substrate 110 and the shallow ion implantation concentration. Optionally, the thickness of the buffer layer 120 ranges from 200 Å to 800 Å, for example, the thickness of the buffer layer 120 is 200 Å, 300 Å, 400 Å, 500 Å, 600 Å, 700 Å, or 800 Å. Figure 11 A schematic diagram illustrating the implantation concentration on a substrate surface, provided for related technologies. Figure 12 This is a schematic diagram of the substrate surface implantation concentration provided in an embodiment of the present invention. See also... Figure 11 and Figure 12 Traditional mask structures suffer from uneven ion implantation concentrations on the substrate 110 surface due to over-etching after mask formation. This unevenness (as shown in the figure, the values ​​represent concentration distribution parameters, which are dispersed and lack uniformity) negatively impacts semiconductor device performance. In contrast, the mask structure of this embodiment, by designing the deposition thickness of the buffer layer 120, protects the surface structure of the substrate 110 while simultaneously allowing for the regulation of performance parameters of the fabricated semiconductor device, resulting in a more uniform ion implantation concentration on the substrate 110 surface.

[0034] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A mask structure, characterized in that, include: A buffer layer is disposed on one side of the substrate; A first hard mask layer and a second hard mask layer are sequentially stacked on the surface of the buffer layer away from the substrate; wherein, a groove is provided on the surface of the second hard mask layer away from the substrate, the groove penetrates the first hard mask layer along the thickness direction of the second hard mask layer, and the bottom of the groove at least partially exposes the surface of the buffer layer, the first hard mask layer and the second hard mask layer are made of different materials, and the thickness of the second hard mask layer is greater than the thickness of the first hard mask layer.

2. The mask structure according to claim 1, characterized in that, The thickness of the second hard mask layer ranges from 8KA to 12KA, and the thickness of the first hard mask layer ranges from 5KA to 10KA.

3. The mask structure according to claim 1, characterized in that, The thickness of the first hard mask layer is greater than the thickness of the buffer layer.

4. The mask structure according to claim 3, characterized in that, The thickness of the buffer layer ranges from 200A to 800A.

5. The mask structure according to claim 1, characterized in that, The etching selectivity of the first hard mask layer to the buffer layer is greater than 5.

6. The mask structure according to claim 5, characterized in that, The second hard mask layer and the buffer layer comprise silicon dioxide layers; the first hard mask layer comprises a polysilicon layer.

7. A method for fabricating a mask structure, characterized in that, include: A substrate is provided, and a buffer layer is formed on the surface of the substrate; A first hard mask layer and a second hard mask layer are sequentially formed on the surface of the buffer layer away from the substrate; The first hard mask layer and the second hard mask layer are made of different materials, and the thickness of the second hard mask layer is greater than the thickness of the first hard mask layer; A groove is formed on the surface of the second hard mask layer away from the substrate, wherein the groove penetrates the first hard mask layer along the thickness direction of the second hard mask layer, and the bottom of the groove at least partially exposes the surface of the buffer layer.

8. The method for fabricating the mask structure according to claim 7, characterized in that, A groove is formed on the surface of the second hard mask layer away from the substrate, including: A photoresist layer is formed on the surface of the second hard mask layer away from the substrate, and the pattern of the groove is formed on the photoresist layer; The grooves are formed in the second hard mask layer and the first hard mask layer according to the pattern; Remove the photoresist layer.

9. The method for preparing the mask structure according to claim 8, characterized in that, The grooves are formed in the second hard mask layer and the first hard mask layer using dry etching.

10. A method for fabricating a semiconductor device, characterized in that, include: Provide substrate; The mask structure according to any one of claims 1-6 is formed on the surface of the substrate; Ion implantation is performed on the substrate at the location corresponding to the groove by blocking the mask structure.

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