Semiconductor structure preparation method and semiconductor structure

Abstract

The invention relates to a semiconductor structure preparation method and a semiconductor structure, and relates to the technical field of semiconductor manufacturing, and the method comprises the steps: providing a substrate which comprises an interlayer dielectric layer; forming an initial metal layer on the interlayer dielectric layer; the initial metal layer is etched by adopting a negative development process based on a target photomask to obtain a metal column, and the target photomask comprises a pattern used for limiting an interconnection structure; forming an interlayer metal layer covering the interlayer dielectric layer and the outer surface of the metal column by adopting a positive development process based on the target photomask; a dielectric layer covering the interlayer metal layer is formed, the dielectric layer comprises a through hole, and the interlayer dielectric layer, exposed out of the top surface of the metal column, of the through hole is at least used for metal blocking; and forming an interconnection structure in the through hole. And at least the problems of poor contact, abnormal conduction, abnormal morphology and the like in the prepared metal plug can be avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure preparation method and a semiconductor structure. BACKGROUND

[0002] Metallic plug is a key structure in semiconductor device manufacturing, mainly used for electrical connection and physical protection, and electrical connection between devices. Its core requirements include low resistivity, good contact performance, and adhesion to insulating layer, etc.

[0003] The applicant found that in the metallic plug prepared by the conventional technology, there are problems such as poor contact, abnormal conduction, and abnormal morphology. SUMMARY

[0004] Therefore, it is necessary to provide a semiconductor structure preparation method and a semiconductor structure to at least avoid the problems such as poor contact, abnormal conduction, and abnormal morphology in the prepared metallic plug, and improve the conduction performance, yield, and reliability of the prepared metallic plug.

[0005] To achieve the above object and other related objects, one aspect of the present application provides a semiconductor structure preparation method, comprising:

[0006] providing a substrate, the substrate comprising an interlayer dielectric layer;

[0007] forming an initial metal layer on the interlayer dielectric layer;

[0008] etching the initial metal layer based on a target mask to obtain a metal column, the target mask comprising a pattern for defining an interconnection structure;

[0009] forming an interlayer metal layer covering the interlayer dielectric layer and the outer surface of the metal column based on a positive development process of the target mask;

[0010] forming a dielectric layer covering the interlayer metal layer, the dielectric layer comprising a via hole, the via hole exposing the interlayer dielectric layer on the top surface of the metal column at least for metal barrier;

[0011] forming an interconnection structure in the via hole.

[0012] In the semiconductor structure preparation method in the above embodiments, based on the target mask including a pattern for defining an interconnection structure, a negative development process is adopted to etch the initial metal layer on the interlayer dielectric layer to obtain a metal pillar, then an interlayer metal layer covering the metal pillar is formed, and then a positive development process is adopted based on the target mask to etch the interlayer metal layer, so that the etched interlayer metal layer at least covers the outer surface of the metal pillar and the top surface of the interlayer dielectric layer located at the periphery of the metal pillar, the top surface of the interlayer dielectric layer lower than the top surface of the metal pillar, and the interlayer metal layer covering the outer surface of the metal pillar is at least used for metal blocking. Further, a dielectric layer covering the interlayer metal layer is formed, the dielectric layer including a via exposing at least part of the top surface of the metal pillar, the interlayer dielectric layer exposing the top surface of the metal pillar at least used for metal blocking, avoiding the metal pillar from being oxidized or penetrating into the via in the dielectric layer in subsequent processes, thereby effectively improving the performance, reliability and yield of the subsequent formation of the interconnection structure in the via in the dielectric layer. Moreover, in the embodiments of the present disclosure, the metal pillar, the interlayer metal layer covering the outer surface of the metal pillar, and the via for forming the interconnection structure can be prepared by means of the same mask, without increasing the design and preparation cost of the mask.

[0013] In some embodiments, the initial metal layer includes a first barrier material layer and a first metal material layer stacked in sequence in a direction away from the substrate; the metal pillar is formed by: based on the target mask, a negative development process is adopted to etch and remove the first barrier material layer and the first metal material layer outside the pattern, the remaining first barrier material layer used to constitute a first barrier layer, and the remaining first metal material layer used to constitute a first metal layer, and the first barrier layer and the first metal layer used to constitute the metal pillar. Due to the blocking effect of the first barrier layer, the first metal layer can be prevented from penetrating into the interlayer dielectric layer in subsequent process, and an electric current leakage channel is avoided, thereby improving the performance and reliability of the semiconductor structure.

[0014] In some embodiments, the interlayer metal layer is formed by: forming a second barrier layer covering the outer surface of the metal pillar and the top surface of the interlayer dielectric layer, the top surface of the second barrier layer on the top surface of the interlayer dielectric layer lower than the top surface of the second barrier layer on the top surface of the metal pillar; forming a second metal layer covering the outer surface of the second barrier layer; and based on the target mask, a positive development process is adopted to etch and remove the second metal layer on the top surface of the metal pillar, the remaining second barrier layer and the remaining second metal layer used to constitute the interlayer metal layer. Since the second barrier layer covers the outer surface of the metal pillar, the metal in the metal pillar can be prevented from penetrating outward in subsequent processes, an electric current leakage channel is avoided, and the performance and reliability of the semiconductor structure are improved.

[0015] In some embodiments, forming the dielectric layer includes: forming the dielectric layer covering the ILM layer by a deposition process; and etching the dielectric layer to form a via exposing at least a portion of the top surface of the metal pillar based on a target mask, with the second barrier layer on the top surface of the metal pillar as an etching stop layer. Since the second barrier layer covers the outer surface of the metal pillar, the metal in the metal pillar can be prevented from penetrating into the dielectric layer or the via in the dielectric layer in subsequent processes, thus avoiding the formation of current leakage channels and improving the performance and reliability of the semiconductor structure.

[0016] In some embodiments, the first barrier layer and the second barrier layer are made of the same material, which can reduce the complexity and cost of the manufacturing process.

[0017] In some embodiments, the first metal layer and the second metal layer are made of the same material, which can reduce the complexity and cost of the manufacturing process.

[0018] In some embodiments, forming the interconnection structure in the via includes: forming a conductive material layer filling the via by a deposition process; and planarizing the conductive material layer on the top surface of the dielectric layer, while retaining the conductive material layer in the via to form the interconnection structure. The interconnection structure is used to realize at least one of a film layer, an element, or a circuit on the side of the dielectric layer away from the substrate, and is connected to the ILM layer via the interconnection structure to realize electrical interconnection between layers.

[0019] In some embodiments, another aspect of the present disclosure provides an interconnection structure, including a substrate, an ILM layer, a metal pillar, a dielectric layer, and an interconnection structure. The substrate includes an ILD layer. The ILM layer is located on the ILD layer. The metal pillar is embedded in the ILM layer, and the ILM layer covers at least a portion of the outer surface of the metal pillar for metal barrier. The dielectric layer covers the metal pillar. The interconnection structure penetrates the dielectric layer and extends to the top surface of the metal pillar.

[0020] In some embodiments, the metal pillar includes a first barrier material layer and a first metal material layer stacked in the direction away from the substrate. The ILM layer includes a second barrier layer surrounding the first metal layer and covering the outer surface of the first metal layer, and a second metal layer surrounding the metal pillar. The second metal layer is located on the surface of the first barrier layer away from the ILD layer. The first metal layer is located in a sealed space enclosed by the first barrier layer and the second barrier layer, thus avoiding the penetration of the first metal layer outward to form a current leakage channel. The second metal layer is located on the surface of the first barrier layer away from the ILD layer, and the top surface of the second metal layer can be higher than the top surface of the first metal layer, thus reducing the step difference between the top surface of the first metal layer and the top surface of the second barrier layer, and reducing the warping stress of the film layer.

[0021] In some embodiments, the dielectric layer includes silicon oxide, silicon nitride, silicon carbon nitride, silicon oxynitride, or a combination thereof. The interconnection structure penetrates the dielectric layer and extends to the second barrier layer on the top surface of the metal pillar.

[0022] In some embodiments, the first barrier layer comprises Ti, TiN, TaN, WN, or a combination thereof.

[0023] In some embodiments, the first metal layer includes W, Cu, Ti, Al, Co, Ni, Cr, Pt, Ga, Hf, AlCu, or a combination thereof.

[0024] In some embodiments, the second barrier layer comprises Ti, TiN, TaN, WN, or a combination thereof.

[0025] In some embodiments, the second metal layer includes W, Cu, Ti, Al, Co, Ni, Cr, Pt, Ga, Hf, AlCu, or a combination thereof. Attached Figure Description

[0026] To better describe and illustrate embodiments and / or examples of the applications disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed applications, the embodiments and / or examples currently described, or the best mode of conduct of these applications as currently understood.

[0027] Figure 1 This is a schematic cross-sectional view of the semiconductor structure obtained after forming a through-hole in a comparative embodiment of the semiconductor structure fabrication method of this disclosure.

[0028] Figure 2 For Figure 1 A schematic diagram of the cross-sectional structure of the semiconductor structure obtained after the interconnect structure is formed inside the through-hole;

[0029] Figure 3 To obtain by scanning electron microscopy (SEM) Figure 2 A schematic cross-sectional view of the interconnect structure;

[0030] Figure 4 This is a schematic flowchart of a semiconductor structure fabrication method provided in one embodiment of the present disclosure;

[0031] Figure 5 This is a schematic cross-sectional view of the semiconductor structure obtained after forming the first metal material layer in a semiconductor structure fabrication method according to an embodiment of the present disclosure.

[0032] Figure 6 This is a schematic cross-sectional view of the semiconductor structure obtained after forming a metal pillar in a semiconductor structure fabrication method according to an embodiment of the present disclosure.

[0033] Figure 7 This is a schematic cross-sectional view of the semiconductor structure obtained after forming a second metal layer in a semiconductor structure fabrication method according to an embodiment of the present disclosure.

[0034] Figure 8 In one embodiment of the semiconductor structure fabrication method of this disclosure, planarization treatment is performed. Figure 7 A schematic cross-sectional view of the semiconductor structure obtained after the second metal layer is applied.

[0035] Figure 9 This is a schematic cross-sectional view of the semiconductor structure obtained after forming a dielectric layer in a semiconductor structure fabrication method according to an embodiment of the present disclosure.

[0036] Figure 10 This is a schematic cross-sectional view of the semiconductor structure obtained after forming an interconnect structure in a semiconductor structure fabrication method according to an embodiment of the present disclosure.

[0037] Figure 11 To obtain by scanning electron microscopy (SEM) Figure 10 A cross-sectional view of the interconnect structure.

[0038] Explanation of reference numerals in the attached figures:

[0039] 10. Substrate; 11. Interlayer dielectric layer; 121. First barrier material layer; 131. First metal material layer; 12. First barrier layer; 13. First metal layer; 14. Dielectric layer; 15. Via; 16. Third barrier layer; 17. Interconnect structure; 22. Second barrier layer; 23. Second metal layer; 200. Metal pillar. Detailed Implementation

[0040] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0042] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or part discussed below may be referred to as the second element, component, area, layer, or part.

[0043] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0044] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0045] Embodiments of the application are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of this disclosure. Thus, variations from the illustrated shape can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. The regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of regions of the device and are not intended to limit the scope of this disclosure.

[0046] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this disclosure. Although the illustrations only show components related to this disclosure and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component can be arbitrarily changed in actual implementation, and the layout of the components may also be more complex.

[0047] Please see Figures 1-2 In some embodiments, a method for fabricating a semiconductor structure is provided, including steps S101-S103.

[0048] Step 1201: Provide a substrate 10, and form an interlayer dielectric layer 11, a first barrier layer 12, a first metal layer 13 and a dielectric layer 14 sequentially stacked on the substrate 10 in a direction away from the substrate 10;

[0049] Step S102: Form a via 15 that penetrates the dielectric layer 14 and exposes part of the top surface of the first metal layer 13 towards the substrate 101;

[0050] Step S103: After forming a third barrier layer 16 covering the inner surface of the through hole 15, an interconnection structure 17 is formed in the through hole 15.

[0051] Please see Figure 3 The applicant obtained a cross-sectional view of the fabricated interconnect structure 17 using a scanning electron microscope (SEM). The view revealed that the first metal layer 13 extends into the via 15, forming a contact surface with the interconnect structure 17 within the via 15. The morphology of this contact surface is uncontrollable, easily leading to interfacial gaps, poor contact, and high impedance.

[0052] The applicant's analysis revealed that the temperature during the high-temperature plasma deposition process in step S103, approximately 400°C, caused the first metal layer 13 to expand due to heat, overflowing and extending into the via 15. Because the thermal expansion is not a uniform stress, the portion of the first metal layer 13 extending into the via 15 has an irregular top surface, such as a convex arc surface. Furthermore, the interconnect structure 17 subsequently deposited within the via 15 may have an interface gap with the top surface of the first metal layer 13 within the via 15, resulting in poor conductive contact and high impedance.

[0053] Please refer to Figure 4 In some embodiments, a method for fabricating a semiconductor structure is provided, comprising:

[0054] Step S22: Provide a substrate, on which an interlayer dielectric layer is included;

[0055] Step S24: Form an initial metal layer on the interlayer dielectric layer;

[0056] Step S26: Based on the target photomask, a negative development process is used to etch the initial metal layer to obtain metal pillars. The target photomask includes a pattern for defining the interconnect structure.

[0057] Step S28: Based on the target photomask, a positive development process is used to form an interlayer metal layer covering the interlayer dielectric layer and the outer surface of the metal pillar;

[0058] Step S210: Form a dielectric layer covering the interlayer metal layer, the dielectric layer including vias, the vias exposing the interlayer dielectric layer on the top surface of the metal pillar for at least metal blocking;

[0059] Step S211: Form an interconnect structure within the through hole.

[0060] For example, please refer to Figure 4 Based on a target photomask including a pattern for defining interconnect structures, an initial metal layer on the interlayer dielectric layer is etched using a negative development process to obtain metal pillars. Then, an interlayer metal layer covering the metal pillars is formed. Next, based on the target photomask, a positive development process is used to etch the interlayer metal layer, ensuring that the etched interlayer metal layer at least covers the outer surface of the metal pillars. The top surface of the interlayer dielectric layer surrounding the metal pillars is lower than the top surface of the interlayer dielectric layer covering the outer surface of the metal pillars, thus serving as a metal barrier. Further, a dielectric layer covering the interlayer metal layer is formed. This dielectric layer includes vias exposing at least a portion of the top surface of the metal pillars. The interlayer dielectric layer exposed by these vias serves as a metal barrier, preventing the metal pillars from being oxidized or penetrating into the vias in subsequent processes. This effectively improves the performance, reliability, and yield of the interconnect structures subsequently formed in the vias within the dielectric layer. Furthermore, in the embodiments of this disclosure, the same photomask can be used to prepare the metal pillar, the interlayer metal layer covering the outer surface of the metal pillar, and the through-hole for forming the interconnect structure, without increasing the design and preparation cost of the photomask.

[0061] Please refer to Figure 5In some embodiments, in step S22, a substrate 10 is provided, the substrate 10 including an interlayer dielectric layer 11; the substrate 10 may be composed of a semiconductor material, an insulating material, a conductive material, or any combination thereof. The substrate may be a single-layer structure or a multilayer structure. For example, the substrate 10 may be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 10 may be a layered substrate including materials such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. Therefore, the type of substrate 10 should not limit the scope of protection of this disclosure. One or more of word line structures, bit line structures, capacitor structures, and transistor structures may be formed within the substrate 10. The material of the interlayer dielectric layer 11 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, or combinations thereof. In step S22, one or more of the following processes may be used to form the interlayer dielectric layer 11: deposition, oxidation, or spin-coating dielectric layer.

[0062] Please continue to refer to this. Figure 5 In some embodiments, in step S24, a first barrier material layer 121 may be formed on the top surface of the interlayer dielectric layer 11 using a deposition process. Then, a first metal material layer 131 may be formed on the top surface of the first barrier material layer 121 using a deposition process. The material of the first barrier material layer 121 may include Ti, TiN, TaN, WN, or combinations thereof. The material of the first metal material layer 131 may include W, Cu, Ti, Al, Co, Ni, Cr, Pt, Ga, Hf, AlCu, or combinations thereof.

[0063] Please refer to Figure 6 In some embodiments, the initial metal layer includes a first barrier material layer 121 and a first metal material layer 131 sequentially stacked along a direction away from the substrate 10; the formation of metal pillars in step S26 includes:

[0064] Step S261: Based on the target photomask, a negative development process is used to etch and remove the first blocking material layer 121 and the first metal material layer 131 outside the pattern. The remaining first blocking material layer 121 is used to form the first blocking layer 12, and the remaining first metal material layer 131 is used to form the first metal layer 13. The first blocking layer 12 and the first metal layer 13 are used to form the metal pillar 200.

[0065] The principle of negative development is as follows: Before exposure, the photoresist is a hydrophobic polymer, soluble in organic solvents (NTD developer) but insoluble in alkaline solutions (TMAH developer). Exposure triggers a photochemical reaction, producing acid. After baking (de-protection reaction), the polymer's polarity changes, becoming a hydrophilic polymer, no longer soluble in NTD developer (but soluble in alkaline solutions). Therefore, unexposed areas can be washed away by NTD developer, while exposed areas remain after development, achieving exposure characteristics similar to negative photoresist. In the negative development process, both the developer and rinsing solution use organic solvents, replacing the traditional water-based TMAH system. It achieves pattern inversion by dissolving unexposed areas, and combined with a bright-field mask, it can improve the contrast and edge precision of small-sized patterns.

[0066] Please continue to refer to this. Figure 6 Due to the blocking effect of the first barrier layer 12, the first metal layer 13 can be prevented from penetrating into the interlayer dielectric layer 11 in subsequent process steps, thus avoiding the formation of current leakage channels and improving the performance and reliability of the semiconductor structure.

[0067] Please refer to Figure 7 In some embodiments, forming an interlayer metal layer in step S28 includes:

[0068] Step S281: Form a second barrier layer 22 covering the outer surface of the metal pillar 200 and the top surface of the interlayer dielectric layer 11, wherein the top surface of the second barrier layer 22 on the top surface of the interlayer dielectric layer 11 is lower than the top surface of the second barrier layer 22 on the top surface of the metal pillar;

[0069] Step S282: Form a second metal layer 23, the second metal layer 23 covering the outer surface of the second barrier layer 22;

[0070] Step S283: Using the second barrier layer 22 on the top surface of the metal pillar as the etching stop layer, and employing a positive development process based on the target photomask, the second metal layer 23 on the top surface of the metal pillar is etched away. The remaining second barrier layer 22 and the remaining second metal layer 23 are used to form the interlayer metal layer.

[0071] In contrast to negative development (where the exposed areas become insoluble), positive development works on the principle that the photoresist in the exposed areas undergoes a chemical reaction, dissolving more rapidly in the developer; while the unexposed areas dissolve or dissolve very slowly. Therefore, after development, the areas exposed to light are washed away, exposing the underlying substrate, while the unexposed areas are preserved.

[0072] Please continue to refer to this. Figure 7In step S281, a second barrier layer 22 can be formed using a deposition process, covering the outer surface of the metal pillar 200 and the top surface of the interlayer dielectric layer 11. The top surface of the second barrier layer 22 is lower than the top surface of the first metal layer 13. The top surface of the second barrier layer 22 can be flush with the top surface of the first barrier layer 12 to minimize the risk of forming a step and increasing the risk of current leakage. The material of the second barrier layer 22 can be the same as that of the first barrier layer 12 to reduce the cost of the fabrication process.

[0073] Please continue to refer to this. Figure 7 In step S282, a deposition process can be used to form a second metal layer 23. The second metal layer 23 covers the outer surface of the second barrier layer 22. The second metal layer 23 protrudes directly above the top surface of the first metal layer 13 to facilitate subsequent etching to remove the second metal layer 23 directly above the top surface of the first metal layer 13.

[0074] Please refer to Figure 8 In some embodiments, in step S283, using the second barrier layer 22 on the top surface of the metal pillar as the etching stop layer, a positive etching process and a dry etching process are used based on the target photomask to etch and remove the second metal layer 23 on the top surface of the metal pillar. The remaining second barrier layer 22 and the remaining second metal layer 23 are used to form an interlayer metal layer. The first metal layer 13 is located within the closed space formed by the first barrier layer 12 and the second barrier layer 22, which can prevent the first metal layer 13 from penetrating outward in subsequent process steps, avoid the generation of current leakage channels, and improve the performance and reliability of the fabricated semiconductor structure.

[0075] Please refer to Figure 9 In some embodiments, forming the dielectric layer 14 in step S210 includes:

[0076] Step S211: A dielectric layer 14 covering the interlayer metal layer is formed using a deposition process;

[0077] Step S212: Using the second barrier layer 22 on the top surface of the metal pillar as the etching stop layer, and based on the target photomask positive development etching medium layer 14, form a through hole 15 that exposes at least part of the top surface of the metal pillar.

[0078] Please continue to refer to this. Figure 9 Since the second barrier layer 22 covers the outer surface of the metal pillar, it can prevent the metal in the metal pillar from penetrating into the dielectric layer 14 or the through-hole 15 in the dielectric layer 14 during subsequent process fabrication, thereby avoiding the generation of current leakage channels and improving the performance and reliability of the semiconductor structure.

[0079] Please continue to refer to this. Figure 9The material of the dielectric layer 14 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, or combinations thereof. The via 15 can expose the second barrier layer 22 on the top surface of the first metal layer 13. Due to the covering and blocking effect of the second barrier layer 22, the diffusion or penetration of the first metal layer 13 into the via 15 can be effectively prevented.

[0080] Please refer to Figure 10 In some embodiments, forming an interconnect structure 17 within the via 15 includes: forming a conductive material layer that at least fills the via 15 using a deposition process; planarizing and removing the conductive material layer on the top surface of the dielectric layer 14, leaving the conductive material layer within the via 15 to form the interconnect structure 17. The interconnect structure 17 enables at least one of the following: a film layer, a component, or a circuit on the side of the dielectric layer 14 facing away from the substrate 10. These components are then connected to an interlayer metal layer via the interconnect structure 17, achieving interlayer electrical interconnection.

[0081] Please continue to refer to this. Figure 10 In some embodiments, a third barrier layer 16 covering at least the inner surface of the via 15 can be formed first using a deposition process, and then an interconnect structure 17 filling at least the via 15 can be deposited. Then, a planarization process is used to remove the third barrier layer 16 and the interconnect structure 17 from the top surface of the dielectric layer 14, resulting in the interconnect structure 17 located within the via 15. The material of the interconnect structure 17 can include, but is not limited to, W, Cu, Ti, Al, Co, Ni, Cr, Pt, Ga, Hf, or combinations thereof. The material of the third barrier layer 16 can include, but is not limited to, Ti, TiN, TaN, WN, or combinations thereof.

[0082] Please continue to refer to this. Figure 10 In some embodiments, the first metal layer 13 and the second metal layer 23 are made of the same material, which can reduce the complexity and cost of the manufacturing process.

[0083] Please refer to Figure 11 The applicant obtained the data using a scanning electron microscope (SEM). Figure 10 A cross-sectional view of the interconnect structure 17 shows that the second metal layer 23 is covered and blocked by the second barrier layer 22, and there is no upward protrusion of the second metal layer 23.

[0084] It should be understood that, although Figure 4 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Furthermore, although... Figure 4At least some of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0085] Based on the same inventive concept, this disclosure also provides a semiconductor structure prepared using the aforementioned semiconductor structure preparation method.

[0086] Please continue to refer to this. Figure 10 In some embodiments, a semiconductor structure is provided, including a substrate 10, an interlayer metal layer, metal pillars, a dielectric layer 14, and an interconnect structure 17. The substrate 10 includes an interlayer dielectric layer 11; the interlayer metal layer is located on the interlayer dielectric layer 11; the metal pillars are embedded in the interlayer metal layer, and a portion of the interlayer metal layer covering the outer surface of the metal pillars serves as a metal barrier; the dielectric layer 14 covers the metal pillars; and the interconnect structure 17 penetrates the dielectric layer 14 and extends to the top surface of the metal pillars.

[0087] Please continue to refer to this. Figure 10 In some embodiments, the metal pillar 200 includes a first barrier layer 12 and a first metal layer 13 sequentially stacked in a direction away from the substrate 10; the interlayer metal layer includes a second barrier layer 22 surrounding the first barrier layer 12 and covering the outer surface of the first metal layer 13, and a second metal layer 23 surrounding the metal pillar 200; wherein the second metal layer 23 is located on the surface of the first barrier layer 12 away from the interlayer dielectric layer 11. The first metal layer 13 is located within the sealed space enclosed by the first barrier layer 12 and the second barrier layer 22, preventing the first metal layer 13 from penetrating outward and forming a current leakage channel. The second metal layer 23 is located on the surface of the first barrier layer 12 away from the interlayer dielectric layer 11, and the top surface of the second metal layer 23 may be higher than the top surface of the first metal layer 13, thereby reducing the step difference between the top surface of the first metal layer 13 and the top surface of the second barrier layer 22, and reducing the warping stress of the film layer.

[0088] Please continue to refer to this. Figure 10 In some embodiments, the dielectric layer 14 includes silicon oxide, silicon nitride, silicon carbide nitride, silicon oxynitride, or a combination thereof; the interconnect structure 17 penetrates the dielectric layer 14 and extends to the second barrier layer 22 at the top surface of the metal pillar.

[0089] Please continue to refer to this. Figure 10 In some embodiments, the first barrier layer 12 includes Ti, TiN, or a combination thereof.

[0090] Please continue to refer to this. Figure 10 In some embodiments, the first metal layer 13 includes Cu, Al, AlCu, or a combination thereof.

[0091] Please continue to refer to this. Figure 10 In some embodiments, the second barrier layer 22 includes Ti, TiN, or a combination thereof.

[0092] Please continue to refer to this. Figure 10 In some embodiments, the second metal layer 23 includes Cu, Al, AlCu, or a combination thereof.

[0093] Please continue to refer to this. Figure 10 The top surface of the second barrier layer 22 can be flush with the top surface of the first barrier layer 12 to minimize the risk of forming a step and increasing the risk of current leakage. The material of the second barrier layer 22 can be the same as that of the first barrier layer 12 to reduce the cost of the manufacturing process.

[0094] Please continue to refer to this. Figure 10 The first metal layer 13 is located within the sealed space formed by the first barrier layer 12 and the second barrier layer 22, which can prevent the first metal layer 13 from penetrating outward in subsequent process steps, avoid the generation of current leakage channels, and improve the performance and reliability of the semiconductor structure.

[0095] In some embodiments, an electronic device is provided, comprising: a semiconductor structure prepared by the semiconductor structure preparation method in any of the foregoing embodiments; or a semiconductor structure in any of the foregoing embodiments.

[0096] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0097] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0098] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0099] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the scope of protection of this disclosure. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, wherein the substrate includes an interlayer dielectric layer; An initial metal layer is formed on the interlayer dielectric layer; Based on the target photomask, the initial metal layer is etched using a negative development process to obtain metal pillars. The target photomask includes a pattern for defining the interconnect structure. Based on the target photomask, an interlayer metal layer is formed by using a positive development process to cover the interlayer dielectric layer and the outer surface of the metal pillar; the top surface of the interlayer dielectric layer located around the metal pillar is lower than the top surface of the metal pillar. A dielectric layer is formed covering the interlayer metal layer, the dielectric layer including vias that expose the interlayer dielectric layer on the top surface of the metal pillar for at least metal blocking; The interconnect structure is formed within the through hole.

2. The semiconductor structure fabrication method according to claim 1, characterized in that, The initial metal layer includes a first barrier material layer and a first metal material layer stacked sequentially along a direction away from the substrate; Forming the metal pillar includes: Based on the target photomask using a negative development process, the first blocking material layer and the first metal material layer outside the pattern are etched and removed. The remaining first blocking material layer is used to form the first blocking layer, and the remaining first metal material layer is used to form the first metal layer. The first blocking layer and the first metal layer are used to form the metal pillar.

3. The semiconductor structure fabrication method according to claim 2, characterized in that, Forming the interlayer metal layer includes: A second barrier layer is formed covering the outer surface of the metal pillar and the top surface of the interlayer dielectric layer. The top surface of the second barrier layer is lower than the top surface of the second barrier layer on the top surface of the metal pillar. A second metal layer is formed, which covers the outer surface of the second barrier layer; Using the second barrier layer on the top surface of the metal pillar as the etching stop layer, and employing a positive development process based on the target photomask, the second metal layer on the top surface of the metal pillar is etched away. The remaining second barrier layer and the remaining second metal layer are used to form the interlayer metal layer.

4. The semiconductor structure fabrication method according to claim 3, characterized in that, Forming the dielectric layer includes: A dielectric layer covering the interlayer metal layer is formed using a deposition process; Using the second barrier layer on the top surface of the metal pillar as the etching stop layer, the dielectric layer is etched based on the target photomask to form a through hole that exposes at least a portion of the top surface of the metal pillar.

5. The semiconductor structure fabrication method according to claim 3, characterized in that, The first barrier layer and the second barrier layer are made of the same material; and / or The first metal layer and the second metal layer are made of the same material.

6. The semiconductor structure fabrication method according to claim 4, characterized in that, The interconnect structure is formed within the through-hole, comprising: A conductive material layer is formed using a deposition process to at least fill the vias; The conductive material layer on the top surface of the dielectric layer is removed by planarization, and the conductive material layer remaining in the via is used to form the interconnect structure.

7. A semiconductor structure, characterized in that, include: Substrate, wherein the substrate includes an interlayer dielectric layer; An interlayer metal layer is located on the interlayer dielectric layer; A metal pillar, embedded within the interlayer metal layer, wherein the portion of the interlayer metal layer covering the outer surface of the metal pillar serves at least as a metal barrier; A dielectric layer covers the metal pillar; An interconnect structure extends through the dielectric layer and to the top surface of the metal pillar.

8. The semiconductor structure according to claim 7, characterized in that, The metal pillar includes a first barrier material layer and a first metal material layer stacked sequentially in a direction away from the substrate; The interlayer metal layer includes a second barrier layer surrounding the first barrier layer and covering the outer surface of the first metal layer, and a second metal layer surrounding the metal pillar; The second metal layer is located on the surface of the first barrier layer away from the interlayer dielectric layer.

9. The semiconductor structure according to claim 8, characterized in that, The dielectric layer includes silicon oxide, silicon nitride, silicon carbide nitride, silicon oxynitride, or a combination thereof; The interconnect structure penetrates the dielectric layer and extends to the second barrier layer on the top surface of the metal pillar.

10. The semiconductor structure according to any one of claims 7-9, characterized in that, Includes at least one of the following features: The first barrier layer comprises Ti, TiN, TaN, WN, or a combination thereof; The first metal layer includes W, Cu, Ti, Al, Co, Ni, Cr, Pt, Ga, Hf, AlCu, or a combination thereof; The second barrier layer comprises Ti, TiN, TaN, WN, or a combination thereof; The second metal layer includes W, Cu, Ti, Al, Co, Ni, Cr, Pt, Ga, Hf, AlCu, or a combination thereof.

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