Transistor, inverter and manufacturing method thereof, and memory cell

Abstract

The invention provides a transistor, an inverter, a manufacturing method thereof and a memory unit. The transistor includes a substrate, a stack structure and a gate structure. The stacked structure is arranged on the substrate and comprises a drain electrode, a source electrode, a semiconductor layer, a first buffer layer and a second buffer layer. The source electrode is disposed on the drain electrode. The semiconductor layer is disposed between the drain electrode and the source electrode. The first buffer layer is disposed between the drain electrode and the semiconductor layer. The second buffer layer is disposed between the source electrode and the semiconductor layer. The gate structure is disposed on the substrate, wherein the gate structure extends in the overlook direction of the substrate and penetrates through the stack structure. The gate structure includes a gate electrode and a gate dielectric layer. The gate dielectric layer is disposed between the gate electrode and the stack structure.

Description

TECHNICAL FIELD

[0001] The present application relates to an inverter, and particularly to an inverter integrated with low temperature poly-silicon transistors and oxide transistors and having a three-dimensional structure. BACKGROUND

[0002] In the back-end of line (BEOL) of an electronic device, the density of logic operation units compatible with each other is low and the logic operation units occupy relatively large spaces. Accordingly, if the occupied spaces of the logic operation units can be reduced, the area usage efficiency of the electronic device can be improved. SUMMARY

[0003] The present application provides a transistor which can improve the area usage efficiency of an electronic device.

[0004] Some embodiments of the present application provide a transistor including a substrate, a stack structure, and a gate structure. The stack structure is disposed on the substrate and includes a drain electrode, a source electrode, a semiconductor layer, a first buffer layer, and a second buffer layer. The source electrode is disposed on the drain electrode. The semiconductor layer is disposed between the drain electrode and the source electrode. The first buffer layer is disposed between the drain electrode and the semiconductor layer. The second buffer layer is disposed between the source electrode and the semiconductor layer. The gate structure is disposed on the substrate, wherein the gate structure extends in a top-down direction of the substrate and penetrates the stack structure. The gate structure includes a gate electrode and a gate dielectric layer. The gate dielectric layer is disposed between the gate electrode and the stack structure.

[0005] The present application provides an inverter which can improve the area usage efficiency of an electronic device.

[0006] Some embodiments of the present invention provide an inverter, which includes a substrate, a stacked structure, a gate structure, and a second semiconductor layer. The stacked structure is disposed on the substrate and includes a first stacked structure and a second stacked structure disposed on the first stacked structure. The first stacked structure includes a first source electrode, a first drain electrode, a first semiconductor layer, a first buffer layer, and a second buffer layer. The first drain electrode is disposed on the first source electrode. The first semiconductor layer is disposed between the first source electrode and the first drain electrode. The first buffer layer is disposed between the first source electrode and the first semiconductor layer. The second buffer layer is disposed between the first drain electrode and the first semiconductor layer. The second stacked structure includes a second drain electrode, a second source electrode, and an insulating layer. The second source electrode is disposed on the second drain electrode. The insulating layer is disposed between the second drain electrode and the second source electrode. The gate structure is disposed on the substrate, wherein the gate structure extends in a top view of the substrate and penetrates the stacked structure. The gate structure includes a gate electrode and a gate dielectric layer. The gate dielectric layer is disposed between the gate electrode and the stacked structure. The second semiconductor layer is disposed between the gate structure and the second stacked structure, wherein the second semiconductor layer is in contact with the second source electrode and the second drain electrode.

[0007] This invention provides a method for manufacturing an inverter, which can improve the area utilization efficiency of electronic devices.

[0008] Some embodiments of the present invention provide a method for manufacturing an inverter, comprising the following steps: (A) forming a first stacked structure material layer including a first semiconductor layer. (B) forming a second stacked structure material layer on the first stacked structure material layer. (C) forming a first contact window and a second contact window, wherein the first contact window is electrically connected to a first source electrode and a first drain electrode in the first stacked structure material layer, and the second contact window is electrically connected to a second source electrode and a second drain electrode in the second stacked structure material layer. (D) removing a portion of the second stacked structure material layer to form a first trench, and forming a second semiconductor layer in the first trench, wherein the second semiconductor layer contacts a second source electrode and a second drain electrode. (E) removing a portion of the first stacked structure material layer through the first trench to form a second trench, wherein the width of the second trench is smaller than the width of the first trench. (F) forming a gate structure filling the first trench and the second trench.

[0009] The present invention provides a memory unit that can improve the area utilization efficiency of electronic devices.

[0010] Some embodiments of the present invention provide a memory cell including a cross-coupled first inverter and a second inverter. The first inverter and the second inverter are inverters as described in the above embodiments. The first inverter and the second inverter share a first source electrode and a first semiconductor layer.

[0011] Based on the above, in the inverter and its manufacturing method provided by the present invention, by having two transistors share a vertically extending gate structure, the inverter of the present invention can have a three-dimensional structure. Therefore, the area of ​​the inverter of the present invention can be reduced to have a relatively small size, thereby facilitating its integration into various electronic devices and improving the area utilization efficiency of electronic devices.

[0012] In the memory cell provided by this invention, two inverters that are cross-coupled to each other share a source electrode and a semiconductor layer. Based on this, the memory cell of this invention can further reduce its area and has a relatively small size, thereby improving the area utilization efficiency of electronic devices. Attached Figure Description

[0013] Figure 1 This is a schematic flowchart of a transistor manufacturing method according to an embodiment of the present invention;

[0014] Figures 2A to 2F This is a schematic flowchart illustrating a method for manufacturing an inverter according to an embodiment of the present invention.

[0015] Figure 3 This is a circuit diagram of an inverter according to an embodiment of the present invention;

[0016] Figure 4 This is a partial cross-sectional schematic diagram of a memory cell according to an embodiment of the present invention;

[0017] Figure 5 This is a circuit diagram of a memory cell according to an embodiment of the present invention. Detailed Implementation

[0018] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

[0019] Figure 1 This is a schematic flowchart illustrating a method for manufacturing a transistor 10 according to an embodiment of the present invention.

[0020] Please refer to Figure 1 In this embodiment, transistor 10 can be formed by performing the following steps, but the present invention is not limited thereto.

[0021] Step (1): Form a drain electrode D on substrate 12.

[0022] The drain electrode D may be disposed on the substrate 12. In some embodiments, the substrate 12 may be a semiconductor substrate, but the invention is not limited thereto. In some embodiments, the material of the substrate 12 may include elemental semiconductors, compound semiconductors, alloy semiconductors, or other suitable materials. For example, the material of the substrate 12 may include silicon, germanium, indium antimonide, indium arsenide, indium phosphide, gallium nitride, gallium arsenide, gallium antimonide, lead telluride, or combinations thereof. In other embodiments, the substrate 12 may also be a silicon-on-insulator (SOI) substrate.

[0023] In some embodiments, the drain electrode D can be formed by performing the following steps, but the invention is not limited thereto. First, a drain electrode material layer is formed by performing a chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) process. Then, this drain electrode material layer is patterned to form the drain electrode D. In this embodiment, the drain electrode D has an annular structure in the planar direction Z of the substrate 12. That is, the drain electrode D has an opening in the substrate 12 exposed in a direction perpendicular to the planar direction Z (e.g., direction X), wherein the opening has a size L1 in the direction perpendicular to the planar direction Z of the substrate 12 (e.g., direction X). In some embodiments, the annular structure of the drain electrode D is a circular annular structure, and its opening is a circular opening, but the invention is not limited thereto. In some embodiments, the material of the drain electrode D may include a suitable metal or metal alloy. For example, the material of the drain electrode D may include copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), cobalt (Co), or combinations thereof, but the present invention is not limited thereto.

[0024] Step (2): Form a buffer layer BF1 on the substrate 12.

[0025] A buffer layer BF1 may be disposed on the substrate 12. In some embodiments, the buffer layer BF1 may cover the drain electrode D disposed on the substrate 12 and may fill the opening of the drain electrode D. In some embodiments, the buffer layer BF1 may be formed by an atomic layer deposition process, but the present invention is not limited thereto. In some embodiments, the material of the buffer layer BF1 may include an oxide semiconductor. For example, the material of the buffer layer BF1 may include copper oxide (CuO), nickel oxide (NiO), bismuth oxide (Bi2O3), or other suitable oxide semiconductors, and the present invention is not limited thereto.

[0026] Step (3): Form the doped region DR1 in the buffer layer BF1.

[0027] In some embodiments, the doped region DR1 may overlap with the opening of the drain electrode D in the Z-direction of the substrate 12 and have a size L2 in the X-direction. In this embodiment, the size L2 of the doped region DR1 is larger than the size L1 of the opening of the drain electrode D. Therefore, a portion of the doped region DR1 overlaps with the drain electrode D in the Z-direction of the substrate 12. In some embodiments, the doped region DR1 may be formed by an ion implantation process, but the invention is not limited thereto. In some embodiments, the doped region DR1 may include a heavily doped n-type impurity. For example, the doped region DR1 may include phosphorus or arsenic, but the invention is not limited thereto.

[0028] Step (4): Form a semiconductor layer SE on the buffer layer BF1.

[0029] A semiconductor layer SE may be disposed on the buffer layer BF1. In some embodiments, the semiconductor layer SE may cover the buffer layer BF1. In this embodiment, the semiconductor layer SE is formed using low-temperature polysilicon (LTPS) technology. Based on this, in this embodiment, the material of the semiconductor layer SE may include polysilicon. More specifically, the semiconductor layer SE may cover the buffer layer BF1, and the semiconductor layer SE may cover the doped region DR1.

[0030] Step (5): Form a buffer layer BF2 on the semiconductor layer SE.

[0031] Buffer layer BF2 may be disposed on semiconductor layer SE. In some embodiments, buffer layer BF2 may cover semiconductor layer SE. In some embodiments, buffer layer BF2 may be formed by the same or similar process as buffer layer BF1, but the invention is not limited thereto. In some embodiments, the material of buffer layer BF1 may include oxide semiconductor. For example, the material of buffer layer BF2 may include copper oxide, nickel oxide, bismuth oxide, or other suitable oxide semiconductor, and the invention is not limited thereto.

[0032] Step (6): Form the doped region DR2 in the buffer layer BF2.

[0033] In some embodiments, the doped region DR2 has a width L2 in the X direction. In some embodiments, the doped region DR2 may be formed by the same or similar process as the doped region DR1, but the invention is not limited thereto. In some embodiments, the doped region DR2 may include a heavily doped n-type impurity. For example, the doped region DR2 may include phosphorus or arsenic, but the invention is not limited thereto.

[0034] Step (7): Form the source electrode S on the buffer layer BF2.

[0035] The source electrode S may be disposed on the buffer layer BF2. In some embodiments, the source electrode S may be formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition, but the present invention is not limited thereto. In some embodiments, the material of the source electrode S may include a suitable metal or metal alloy. For example, the material of the source electrode S may include copper, aluminum, tungsten, nickel, cobalt, or combinations thereof, but the present invention is not limited thereto.

[0036] Step (8): Form a trench Tr that penetrates the source electrode S, buffer layer BF2, semiconductor layer SE and buffer layer BF1.

[0037] In some embodiments, a trench Tr can be formed by performing a suitable patterning process, with the sidewalls of the trench Tr exposing the source electrode S, buffer layer BF2, semiconductor layer SE, and buffer layer BF1, and the bottom of the trench Tr exposing the substrate 12. More specifically, a portion of the source electrode S, buffer layer BF2, semiconductor layer SE, and buffer layer BF1 can be removed to form the trench Tr, wherein the substrate 12 can serve as an etch stop layer, but the invention is not limited thereto. In this embodiment, the trench Tr overlaps with the opening of the drain electrode D in a direction perpendicular to the top view direction Z (e.g., direction X), and the trench Tr has a dimension L1 in the direction X. In this embodiment, the trench Tr has a circular (or cylindrical) structure in the top view direction Z of the substrate 12, but the invention is not limited thereto.

[0038] In this embodiment, the formation of the trench Tr removes most of the doped regions DR1 and DR2. Since the size L2 of the doped regions DR1 and DR2 in the X direction is larger than the size L1 of the trench Tr in the X direction, a portion of the doped region DR1 disposed in the buffer layer BF1 and a portion of the doped region DR2 disposed in the buffer layer BF2 remain, which are exposed by the sidewalls of the trench Tr.

[0039] Step (9): Form a gate dielectric layer 16B in the trench Tr.

[0040] In some embodiments, the gate dielectric layer 16B can be formed by performing the following steps, but the invention is not limited thereto. First, a gate insulating material layer is formed by performing a chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) process. Then, this gate insulating material layer is patterned to form the gate dielectric layer 16B. In this embodiment, the gate dielectric layer 16B is conformally formed on the sidewall of the trench Tr and covers the source electrode S, doped region DR2, semiconductor layer SE, doped region DR1, and drain electrode D exposed by the sidewall of the trench Tr. In some embodiments, the gate dielectric layer 16B may also conformally cover the exposed portion of the substrate 12. In some embodiments, the material of the gate dielectric layer 16B may include a suitable dielectric material. For example, the material of the gate dielectric layer 16B may include silicon oxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), tantalum oxide (Ta2O5), titanium oxide (TiO2), zinc oxide (ZnO2) or hafnium oxide (HfO2), but the present invention is not limited thereto.

[0041] Step (10): Form gate electrode 16A in trench Tr.

[0042] In some embodiments, the gate electrode 16A can be formed by performing the following steps, but the invention is not limited thereto. First, a gate material layer is formed by performing a chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) process. Then, this gate material layer is patterned to form the gate electrode 16A. In this embodiment, the gate electrode 16A is filled in a trench Tr, and the gate electrode 16A and the gate dielectric layer 16B can form a gate structure 16. In some embodiments, the material of the gate electrode 16A may include a suitable metal or metal alloy. For example, the material of the gate electrode 16A may include copper, aluminum, tungsten, nickel, cobalt, or combinations thereof, but the invention is not limited thereto.

[0043] This completes the manufacturing method of transistor 10 in this embodiment, but the manufacturing method of transistor 10 provided by the present invention is not limited thereto.

[0044] The following will refer to Figure 1 The structure of transistor 10 in this embodiment is briefly described, but the present invention is not limited thereto.

[0045] In this embodiment, transistor 10 is a vertical transistor formed using low-temperature polycrystalline silicon technology, which includes a substrate 12, a stacked structure 14, and a gate structure 16.

[0046] The remaining details concerning substrate 12 can be found in the above embodiments and will not be repeated here.

[0047] More specifically, the stacked structure 14 can be disposed on the substrate 12. In this embodiment, the stacked structure 14 includes a stack of a drain electrode D, a source electrode S, a semiconductor layer SE, a buffer layer BF1, and a buffer layer BF2, wherein the drain electrode D, the buffer layer BF1, the semiconductor layer SE, the buffer layer BF2, and the source electrode S are stacked on the substrate 12 from bottom to top, but the present invention is not limited thereto.

[0048] More specifically, the drain electrode D may be disposed on the substrate 12. In some embodiments, the drain electrode D may have a ring-shaped structure in the Z-direction of the substrate 12. Further details regarding the drain electrode D can be found in the foregoing embodiments and will not be repeated here.

[0049] More specifically, the source electrode S can be disposed on the drain electrode D. In some embodiments, the source electrode S has a ring-shaped structure in the top view Z direction of the substrate 12. The source electrode S may, for example, have a similar shape to the drain electrode D in the top view Z direction of the substrate 12, but the invention is not limited thereto. The remaining description relating to the source electrode S can be referred to the foregoing embodiments, and will not be repeated here.

[0050] More specifically, the semiconductor layer SE can be disposed between the drain electrode D and the source electrode S. As mentioned earlier, the transistor 10 is formed using low-temperature polycrystalline silicon technology. Therefore, in this embodiment, the material of the semiconductor layer SE may include polycrystalline silicon. Further details regarding the semiconductor layer SE can be found in the foregoing embodiments and will not be repeated here.

[0051] More specifically, the buffer layer BF1 can be disposed between the drain electrode D and the semiconductor layer SE. In this embodiment, the material of the buffer layer BF1 can include an oxide semiconductor. In some embodiments, the oxide semiconductor included in the buffer layer BF1 can have a band gap of 2.0 eV to 3.0 eV, but the present invention is not limited thereto. In this embodiment, the buffer layer BF1 can include a doped region DR1, wherein the doped region DR1 can be in direct contact with the semiconductor layer SE, the doped region DR1 can be in direct contact with the drain electrode D, and the doped region DR1 includes heavily doped n-type impurities. Accordingly, the buffer layer BF1 can include a region with relatively high conductivity (the doped region DR1) and a region with relatively low conductivity (the region other than the doped region DR1). Further descriptions of the buffer layer BF1 and the doped region DR1 can be found in the foregoing embodiments and will not be repeated here.

[0052] More specifically, the buffer layer BF2 can be disposed between the source electrode S and the semiconductor layer SE. In this embodiment, the material of the buffer layer BF2 can include an oxide semiconductor. In some embodiments, the oxide semiconductor included in the buffer layer BF2 can have a band gap of 2.0 eV to 3.0 eV, but the present invention is not limited thereto. In this embodiment, the buffer layer BF2 can include a doped region DR2, wherein the doped region DR2 can be in direct contact with the semiconductor layer SE, the doped region DR2 can be in direct contact with the source electrode S, and the doped region DR2 includes heavily doped n-type impurities. Accordingly, the buffer layer BF2 can include a region with relatively high conductivity (doped region DR2) and a region with relatively low conductivity (the region other than the doped region DR2). Further descriptions of the buffer layer BF2 and the doped region DR2 can be found in the foregoing embodiments and will not be repeated here.

[0053] In some embodiments, the doped region DR1 in buffer layer BF1 and the doped region DR2 in buffer layer BF2 can serve as a channel contact. More specifically, in this embodiment, the doped region DR1, the doped region DR2, and the semiconductor layer SE located between the doped region DR1 and the doped region DR2 in the top view Z direction of the substrate 12 can form a channel layer of the transistor 10. Accordingly, the aforementioned channel layer has a vertical structure extending in the top view Z direction of the substrate 12, making the transistor 10 of this embodiment a vertical transistor.

[0054] In some embodiments, the gate structure 16 may be disposed on the substrate 12. In this embodiment, the gate structure 16 extends in the top Z direction of the substrate 12 and penetrates the stacked structure 14. More specifically, the stacked structure 14 may have a via through which the gate structure 16 penetrates, the via being formed by the sidewalls of a trench Tr, and the gate structure 16 has a columnar structure in the top Z direction of the substrate 12. In some embodiments, the gate structure 16 has a cylindrical structure in the top Z direction of the substrate 12, but the invention is not limited thereto. In this embodiment, the gate structure 16 may include a gate electrode 16A and a gate dielectric layer 16B.

[0055] More specifically, the gate electrode 16A can be filled in the trench Tr. In this embodiment, the gate electrode 16A partially overlaps with the semiconductor layer SE in the X direction. Further details regarding the gate electrode 16A can be found in the foregoing embodiments and will not be repeated here.

[0056] More specifically, the gate dielectric layer 16B can be disposed between the gate electrode 16A and the stacked structure 14. In this embodiment, the gate dielectric layer 16B can be conformally disposed on the sidewall of the trench Tr and on the surface of the substrate 12 exposed by the trench Tr. Accordingly, the gate dielectric layer 16B can contact the doped region DR1 in the buffer layer BF1 and the doped region DR2 in the buffer layer BF2. Further details regarding the gate dielectric layer 16B can be found in the foregoing embodiments and will not be repeated here.

[0057] Figures 2A to 2F This is a schematic flowchart illustrating a method for manufacturing an inverter according to an embodiment of the present invention.

[0058] In this embodiment, the inverter 20 can be formed by performing the following steps, but the present invention is not limited thereto.

[0059] Step (A): Form a first stacked structure material layer ST1 on the substrate 22.

[0060] Please refer to Figure 2A In this embodiment, the first stacked structure material layer ST1 may include an insulating layer PV1, a source electrode S1, a buffer layer BF1, a semiconductor layer SE, a buffer layer BF2, a drain electrode D1, and an insulating layer PV2, but the present invention is not limited thereto.

[0061] More specifically, the insulating layer PV1 may be disposed on the substrate 22. In some embodiments, the insulating layer PV1 may be formed by a thermal oxidation process, but the invention is not limited thereto. In some embodiments, the material of the insulating layer PV1 may include oxides. For example, the material of the insulating layer PV1 may include silicon oxide, but the invention is not limited thereto.

[0062] More specifically, the source electrode S1 can be disposed on the insulating layer PV1. In some embodiments, the source electrode S1 can be formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition, but the present invention is not limited thereto. In some embodiments, the material of the source electrode S1 can include a suitable metal or metal alloy. For example, the material of the source electrode S1 can include copper, aluminum, tungsten, nickel, cobalt, or combinations thereof, but the present invention is not limited thereto.

[0063] More specifically, the buffer layer BF1 can be disposed on the insulating layer PV1 and can also be disposed on a portion of the source electrode S1. In some embodiments, the buffer layer BF1 can be formed by an atomic layer deposition process, but the present invention is not limited thereto. In some embodiments, the material of the buffer layer BF1 can include an oxide semiconductor. For example, the material of the buffer layer BF1 can include copper oxide, nickel oxide, bismuth oxide, or other suitable oxide semiconductors, and the present invention is not limited thereto. It is worth noting that a doped region DR1 can also be formed in the buffer layer BF1 using an ion implantation process. A description of the doped region DR1 can be found in the foregoing embodiments and will not be repeated here.

[0064] More specifically, the semiconductor layer SE can be disposed on the buffer layer BF1. In this embodiment, the semiconductor layer SE can be formed using low-temperature polycrystalline silicon technology. Accordingly, in this embodiment, the material of the semiconductor layer SE may include polycrystalline silicon.

[0065] More specifically, the buffer layer BF2 can be disposed on the semiconductor layer SE. In some embodiments, the buffer layer BF2 can be formed by the same or similar process as the buffer layer BF1, but the present invention is not limited thereto. In some embodiments, the material of the buffer layer BF2 may include an oxide semiconductor. For example, the material of the buffer layer BF2 may include copper oxide, nickel oxide, bismuth oxide, or other suitable oxide semiconductors, and the present invention is not limited thereto. It is worth noting that the doped region DR2 can also be formed in the buffer layer BF2 using an ion implantation process. The description of the doped region DR2 can be referred to the foregoing embodiments, and will not be repeated here.

[0066] More specifically, the drain electrode D1 can be disposed on the buffer layer BF2. In some embodiments, the drain electrode D1 can be formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition, but the present invention is not limited thereto. In some embodiments, the material of the drain electrode D1 can include a suitable metal or metal alloy. For example, the material of the drain electrode D1 can include copper, aluminum, tungsten, nickel, cobalt, or combinations thereof, but the present invention is not limited thereto.

[0067] In some embodiments, the insulating layer PV2 may be disposed on the insulating layer PV1, and may also be disposed on the source electrode S1 of other portions exposed by the buffer layer BF1. More specifically, the insulating layer PV2 may further encapsulate the buffer layer BF2, the semiconductor layer SE, and the buffer layer BF1, and the drain electrode D1 may also be disposed on the insulating layer PV2. In some embodiments, the insulating layer PV2 may be formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition, but the present invention is not limited thereto. In some embodiments, the material of the insulating layer PV2 may include a suitable dielectric material. For example, the material of the insulating layer PV2 may include silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof, but the present invention is not limited thereto.

[0068] Step (B): Form a second stacked structural material layer ST2 on the first stacked structural material layer ST1.

[0069] Please refer to Figure 2B In this embodiment, the second stacked structural material layer ST2 is disposed on the first stacked structural material layer ST1. The second stacked structural material layer ST2 may include an insulating layer PV3, a drain electrode D2, an insulating layer PV4, a source electrode S2, and an insulating layer PV5, but the present invention is not limited thereto.

[0070] More specifically, the insulating layer PV3 can be disposed on the buffer layer BF2 and can cover the drain electrode D1. In this embodiment, the insulating layer PV3 can also cover the drain electrode D1. In some embodiments, the insulating layer PV3 can be formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition, but the present invention is not limited thereto. In some embodiments, the material of the insulating layer PV3 can include a suitable dielectric material. For example, the material of the insulating layer PV3 can include silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof, but the present invention is not limited thereto.

[0071] More specifically, the drain electrode D2 can be disposed on the insulating layer PV3. In some embodiments, the drain electrode D2 can be formed by the same or similar process as the drain electrode D1, but the invention is not limited thereto. In some embodiments, the material of the drain electrode D2 can include a suitable metal or metal alloy. For example, the material of the drain electrode D2 can include copper, aluminum, tungsten, nickel, cobalt, or combinations thereof, but the invention is not limited thereto.

[0072] More specifically, the insulating layer PV4 can be disposed on the insulating layer PV3 and can cover the drain electrode D2. In this embodiment, the insulating layer PV4 can also cover the drain electrode D2. In some embodiments, the insulating layer PV4 can be formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition, but the present invention is not limited thereto. In some embodiments, the material of the insulating layer PV4 can include a suitable dielectric material. For example, the material of the insulating layer PV4 can include silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof, but the present invention is not limited thereto.

[0073] More specifically, the source electrode S2 may be disposed on the insulating layer PV4. In some embodiments, the source electrode S2 may be formed by the same or similar process as the source electrode S1, but the invention is not limited thereto. In some embodiments, the material of the source electrode S2 may include a suitable metal or metal alloy. For example, the material of the source electrode S2 may include copper, aluminum, tungsten, nickel, cobalt, or combinations thereof, but the invention is not limited thereto.

[0074] More specifically, the insulating layer PV5 can be disposed on the insulating layer PV4 and can cover the source electrode S2. In this embodiment, the insulating layer PV5 can also cover the source electrode S2. In some embodiments, the insulating layer PV5 can be formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition, but the present invention is not limited thereto. In some embodiments, the material of the insulating layer PV5 can include a suitable dielectric material. For example, the material of the insulating layer PV5 can include silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof, but the present invention is not limited thereto.

[0075] Step (C): Forming contact window CW1 and contact window CW2.

[0076] Please refer to Figure 2C In this embodiment, contact window CW1 can be electrically connected to source electrode S1 and source electrode S2, and contact window CW2 can be electrically connected to drain electrode D1 and drain electrode D2 in the second stacked structure material layer ST2. In some embodiments, contact window CW1 and contact window CW2 may include suitable conductive materials, but the present invention is not limited thereto.

[0077] More specifically, the contact window CW1 may include contact window CW11 and contact window CW12. In some embodiments, contact window CW11 may penetrate insulating layers PV2, PV3, PV4 and PV5 to be electrically connected to the source electrode S1, and contact window CW12 may penetrate insulating layer PV5 to be electrically connected to the drain electrode D1.

[0078] More specifically, the contact window CW2 may include contact window CW21 and contact window CW22. In some embodiments, contact window CW21 may penetrate insulating layers PV3, PV4 and PV5 to be electrically connected to the drain electrode D1, and contact window CW22 may penetrate insulating layers PV4 and PV5 to be electrically connected to the drain electrode D2.

[0079] In some embodiments, contact windows CW11, CW12, CW21 and CW22 may be formed sequentially by first patterning the corresponding insulating layers and then by a suitable deposition process, but the present invention is not limited thereto.

[0080] Step (D): Remove a portion of the second stacked structure material layer ST2 to form a trench Tr2, and form a semiconductor layer 28 in the trench Tr2.

[0081] Please refer to Figure 2D In some embodiments, the trench Tr2 can be formed by performing a suitable patterning process, wherein the sidewalls of the trench Tr2 expose the insulating layer PV5, the source electrode S2, the insulating layer PV4, and the drain electrode D2, and the bottom of the trench Tr2 exposes the insulating layer PV3. More specifically, the trench Tr2 can be formed by removing a portion of the insulating layer PV5, the source electrode S2, the insulating layer PV4, and the drain electrode D2 from the surface of the second stacked structural material layer ST2, wherein the insulating layer PV3 can serve as an etch stop layer, but the present invention is not limited thereto.

[0082] In some embodiments, the semiconductor layer 28 can be formed by an atomic layer deposition process. In this embodiment, the material of the semiconductor layer 28 includes an oxide semiconductor. For example, the material of the semiconductor layer 28 may include indium gallium oxide (IGO), indium tungsten oxide (IWO), indium gallium zinc oxide (IGZO), or other suitable oxide semiconductors, and the invention is not limited thereto. In some embodiments, the semiconductor layer 28 may be conformally formed in the trench Tr2 on the surface of the second stacked structure material layer ST2. More specifically, the semiconductor layer 28 may be conformally formed in the trench Tr2 and cover the contact window CW1, contact window CW2, and insulating layer PV5, but the invention is not limited thereto.

[0083] Step (E): Remove a portion of the first stacked structural material layer ST1 through trench Tr2 to form trench Tr1.

[0084] Please refer to Figure 2EIn some embodiments, trench Tr1 can be formed by performing a suitable patterning process. In this embodiment, trench Tr1 overlaps with trench Tr2 in the top view direction Z of substrate 22. More specifically, in this embodiment, the patterning process begins from the bottom of trench Tr2. In this embodiment, the width W1 of trench Tr1 in the X direction is smaller than the width W2 of trench Tr2 in the X direction. In some embodiments, the widths W1 and W2 are less than or equal to 5 micrometers, but the invention is not limited thereto.

[0085] In some embodiments, the sidewalls of trench Tr1 expose an insulating layer PV3, a drain electrode D1, a buffer layer BF2 (doped region DR2), a semiconductor layer SE, a buffer layer BF1 (doped region DR1), and a source electrode S1, and the bottom of trench Tr1 exposes the insulating layer PV1. More specifically, trench Tr1 can be formed by removing a portion of the insulating layer PV3, drain electrode D1, buffer layer BF2, semiconductor layer SE, buffer layer BF1, and source electrode S1 from the bottom of trench Tr2, wherein the insulating layer PV1 can serve as an etch stop layer, but the present invention is not limited thereto.

[0086] In this embodiment, a stacked structure 24A is formed after a portion of the first stacked structure material layer ST1 is removed.

[0087] Step (F): Forming gate structure 26 that fills trench Tr2 and trench Tr1.

[0088] Please refer to Figure 2F In this embodiment, the gate structure 26 may include a gate electrode 26A and a gate dielectric layer 26B, and can be formed by performing the following steps, but the present invention is not limited thereto.

[0089] First, a gate dielectric layer 26B can be formed in trenches Tr1 and Tr2 by performing chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In this embodiment, the gate dielectric layer 26B can be conformally formed on the sidewalls of trench Tr1 and trench Tr2, and covers the semiconductor layer 28 located in trench Tr2 and the insulating layer PV3, drain electrode D1, buffer layer BF2 (doped region DR2), semiconductor layer SE1, buffer layer BF1 (doped region DR1), and source electrode S1 exposed by trench Tr1. In some embodiments, the material of the gate dielectric layer 26B may include a suitable dielectric material. For example, the material of the gate dielectric layer 26B may include silicon oxide, silicon nitride, aluminum oxide, tantalum oxide, titanium oxide, zinc oxide, or hafnium oxide, but the present invention is not limited thereto.

[0090] In this embodiment, after forming the gate dielectric layer 26B, a gate electrode 26A can be formed in trenches Tr1 and Tr2 by performing chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In this embodiment, the gate electrode 26A fills trenches Tr1 and Tr2 and covers the semiconductor layer 28 on the surface of the second stacked structure material layer ST2 in direction X. In some embodiments, the material of the gate electrode 26A may include a suitable metal or metal alloy. For example, the material of the gate electrode 26A may include copper, aluminum, tungsten, nickel, cobalt, or combinations thereof, but the invention is not limited thereto.

[0091] In this embodiment, after the gate dielectric layer 26B and the gate electrode 26A are formed, a patterning process can be performed to expose the contact window CW1 and the contact window CW2, in which a portion of the semiconductor layer 28 is removed to form a stacked structure 24B.

[0092] It is worth noting that after forming the gate structure 26, an interconnect layer INT can be formed on the insulating layer PV5. In this embodiment, the interconnect layer INT may include interconnect layer INT1, interconnect layer INT2, interconnect layer INT3, and interconnect layer INT4, wherein interconnect layer INT1 is electrically connected to the gate electrode 26A, interconnect layer INT2 is electrically connected to the contact window CW11, interconnect layer INT3 is electrically connected to the contact window CW12, and interconnect layer INT4 is electrically connected to the contact window CW2, but the present invention is not limited thereto.

[0093] Thus, the manufacturing method of inverter 20 in this embodiment is completed, but the manufacturing method of inverter 20 provided by the present invention is not limited thereto.

[0094] The following will refer to Figure 2F and Figure 3 This embodiment briefly describes the structure of the inverter 20, wherein... Figure 3 This is a circuit diagram of an inverter according to an embodiment of the present invention.

[0095] In this embodiment, the inverter 20 can be a complementary metal-oxide-semiconductor (CMOS) inverter. More specifically, the inverter 20 can be composed of a P-type transistor and an N-type transistor connected in series, wherein the P-type transistor is the load transistor and the N-type transistor is the input transistor, but the present invention is not limited thereto.

[0096] Please refer to Figure 3 and Figure 2FIn this embodiment, the inverter 20 includes transistors 20A and 20B, wherein transistor 20A is a P-type transistor and transistor 20B is an N-type transistor. In some embodiments, transistor 20A may be disposed on substrate 22, and may be disposed between substrate 22 and transistor 20B in the top view Z direction of substrate 22. In other words, the inverter 20 may be a structure comprising stacked P-type and N-type transistors. Additionally, in this embodiment, transistor 20A may be transistor 10 as described in the previous embodiment. That is, transistor 20A is also formed using low-temperature polycrystalline silicon (LTPS) technology. In other embodiments, transistor 20B may comprise oxide semiconductor. Accordingly, the inverter 20 of this embodiment may be an inverter integrating a LPS thin-film transistor and an oxide thin-film transistor.

[0097] In this embodiment, the inverter 20 may further include an input line V. in Power cord V DD Grounding wire GND and output wire V OUT In some embodiments, the input line V in It can be electrically connected to the gate (gate electrode 26A) of transistors 20A and 20B, power line V DD It can be electrically connected to the source (source electrode S1) of transistor 20A, and the ground line GND can be electrically connected to the source (source electrode S2) of transistor 20B, and the output line V OUT It can be electrically connected to the drains (drain electrode D1 and drain electrode D2) of transistors 20A and 20B.

[0098] Please refer to Figure 2F From another perspective, inverter 20 may include substrate 22, stacked structure 24, gate structure 26 and semiconductor layer 28.

[0099] The remaining details regarding substrate 22 can be found in the description of substrate 12 in the foregoing embodiments, and will not be repeated here.

[0100] More specifically, the stacked structure 24 can be disposed on the substrate 22, and may include stacked structure 24A and stacked structure 24B. In this embodiment, stacked structure 24A is disposed between the substrate 22 and stacked structure 24B in the top view direction Z of the substrate 22.

[0101] More specifically, the stacked structure 24A may include a stack of source electrode S1, drain electrode D1, semiconductor layer SE, insulating layer PV1, buffer layer BF1, and buffer layer BF2, wherein the stacks are arranged from bottom to top on the substrate 22 in the order of insulating layer PV1, source electrode S1, buffer layer BF1, semiconductor layer SE, buffer layer BF2, and drain electrode D1, but the present invention is not limited thereto. In some embodiments, the stacked structure 24A may further include insulating layer PV2.

[0102] More specifically, the source electrode S1 may be disposed on the insulating layer PV1. In some embodiments, the source electrode S1 may have a ring-shaped structure in the Z-direction of the substrate 22. Further details regarding the source electrode S1 and the insulating layer PV1 can be found in the foregoing embodiments and will not be repeated here.

[0103] More specifically, the drain electrode D1 can be disposed on the source electrode S1. In some embodiments, the drain electrode D1 can have a ring-shaped structure in the top Z direction of the substrate 22. Further details regarding the drain electrode D1 can be found in the foregoing embodiments and will not be repeated here.

[0104] More specifically, the semiconductor layer SE can be disposed between the source electrode S1 and the drain electrode D1. In this embodiment, the semiconductor layer SE is formed using low-temperature polycrystalline silicon technology. That is, the material of the semiconductor layer SE may include polycrystalline silicon. Further details regarding the semiconductor layer SE can be found in the foregoing embodiments and will not be repeated here.

[0105] More specifically, the buffer layer BF1 can be disposed between the source electrode S1 and the semiconductor layer SE, and can be in contact with the semiconductor layer SE and the gate structure 26. In this embodiment, the buffer layer BF1 may include a doped region DR1. The doped region DR1 may include a heavily doped n-type impurity. For example, the doped region DR1 may include phosphorus or arsenic, but the present invention is not limited thereto. Further details regarding the buffer layer BF1 can be found in the foregoing embodiments and will not be repeated here.

[0106] More specifically, the buffer layer BF2 can be disposed between the drain electrode D1 and the semiconductor layer SE, and can contact the semiconductor layer SE and the gate structure 26. In this embodiment, the buffer layer BF2 may include a doped region DR2. The doped region DR2 may include a heavily doped n-type impurity. For example, the doped region DR2 may include phosphorus or arsenic, but the present invention is not limited thereto. Further details regarding the buffer layer BF2 can be found in the foregoing embodiments and will not be repeated here.

[0107] More specifically, the stacked structure 24B can be disposed on the stacked structure 24A, and can include a stack composed of a source electrode S2, a drain electrode D2, an insulating layer PV3, an insulating layer PV4 and an insulating layer PV5, wherein the insulating layer PV3, the drain electrode D2, the insulating layer PV4, the source electrode S2 and the insulating layer PV5 are stacked on the stacked structure 24A from bottom to top, but the present invention is not limited thereto.

[0108] More specifically, the drain electrode D2 can be disposed on the insulating layer PV3. In some embodiments, the drain electrode D2 can have a ring-shaped structure in the Z-direction of the substrate 22. Further details regarding the drain electrode D2 and the insulating layer PV3 can be found in the foregoing embodiments and will not be repeated here.

[0109] More specifically, the source electrode S2 can be disposed on the drain electrode D2. In some embodiments, the source electrode S2 can have a ring-shaped structure in the top Z direction of the substrate 22. Further details regarding the source electrode S2 can be found in the above embodiments and will not be repeated here.

[0110] More specifically, the insulating layer PV4 can be disposed between the drain electrode D2 and the source electrode S2. Further details regarding the insulating layer PV4 can be found in the foregoing embodiments and will not be repeated here.

[0111] More specifically, the insulating layer PV5 can be disposed on the source electrode S2. Further details regarding the insulating layer PV5 can be found in the foregoing embodiments and will not be repeated here.

[0112] In some embodiments, the gate structure 26 may be disposed on the substrate 22. In this embodiment, the gate structure 26 extends in the Z-direction of the substrate 22 and penetrates the stacked structure 24. More specifically, the stacked structure 24 may have a via through which the gate structure 26 penetrates, which is composed of the sidewalls of trench Tr1 and trench Tr2. In this embodiment, the width W1 of trench Tr1 in the X-direction is smaller than the width W2 of trench Tr2 in the X-direction. Accordingly, the sidewalls of the via of the stacked structure 24 may have steps, such that the gate structure 26 has two columnar structures of different sizes in the Z-direction of the substrate 22, but the invention is not limited thereto.

[0113] In this embodiment, the gate structure 26 may include a gate electrode 26A and a gate dielectric layer 26B.

[0114] More specifically, gate electrode 26A can be filled in trenches Tr1 and Tr2. In this embodiment, gate electrode 26A overlaps with a channel layer of semiconductor layer SE in direction X. Further details regarding gate electrode 26A can be found in the foregoing embodiments and will not be repeated here.

[0115] More specifically, the gate dielectric layer 26B can be disposed between the gate electrode 26A and the stacked structure 24. In this embodiment, the gate dielectric layer 26B can be conformally disposed on the sidewalls of trenches Tr1 and Tr2 and on the surface of the substrate 22 exposed by trench Tr1. Accordingly, the gate dielectric layer 26B can contact the doped region DR1 in buffer layer BF1 and the doped region DR2 in buffer layer BF2. Further details regarding the gate dielectric layer 26B can be found in the foregoing embodiments and will not be repeated here.

[0116] In some embodiments, the semiconductor layer 28 may be disposed between the gate structure 26 and the stacked structure 24B. In this embodiment, the semiconductor layer 28 is in contact with the source electrode S2 and the drain electrode D2. More specifically, the semiconductor layer 28 is in contact with the source electrode S2 and the drain electrode D2 exposed by the sidewalls of the trench Tr2. In some embodiments, the material of the semiconductor layer 28 may include an oxide semiconductor. For example, the material of the semiconductor layer 28 may include indium gallium oxide, indium tungsten oxide, indium gallium zinc oxide, or other suitable oxide semiconductors, and the invention is not limited thereto.

[0117] In this embodiment, since the width W1 of trench Tr1 in direction X is smaller than the width W2 of trench Tr2 in direction X, and the gate dielectric layer 26B can be conformally disposed on the sidewalls of trench Tr1 and trench Tr2, the gate electrode 26A can have different widths in direction X. More specifically, in this embodiment, the width of the gate electrode 26A surrounded by the semiconductor layer SE in direction X is smaller than the width of the gate electrode 26A surrounded by the semiconductor layer 28 in direction X.

[0118] In some embodiments, the width W1 of the gate structure 26 surrounded by the semiconductor layer SE in the X direction and the width W2 of the gate structure 26 surrounded by the semiconductor layer 28 in the X direction are less than or equal to 5 micrometers, but the present invention is not limited thereto.

[0119] In summary, transistor 20A may include a gate structure 26, a source electrode S1, a drain electrode D1, and a semiconductor layer SE located in trench Tr1, and transistor 20B may include a gate structure 26, a source electrode S2, a drain electrode D2, and a semiconductor layer 28 located in trench Tr2. That is, in this embodiment, transistor 20A and transistor 20B may share the gate structure 26.

[0120] In this embodiment, the doped region DR1 in buffer layer BF1, the doped region DR2 in buffer layer BF2, and the semiconductor layer SE located between buffer layers BF1 and BF2 in the top view direction Z of substrate 22 can form a channel layer of transistor 20A. Accordingly, the channel layer of transistor 20A has a vertical structure extending in the top view direction Z of substrate 22, making transistor 20A in this embodiment a vertical transistor. Furthermore, in this embodiment, semiconductor layer 28 also has a vertical structure extending in the top view direction Z of substrate 22, making transistor 20B in this embodiment also a vertical transistor.

[0121] In this embodiment, the inverter 20 may further include an interconnect layer INT. The interconnect layer INT may include interconnect layers INT1, INT2, INT3, and INT4. More specifically, the gate electrode 26A of the inverter 20 may be electrically connected to the interconnect layer INT1, and the gate electrode 26A may serve as an input terminal. The source electrode S1 of the inverter 20 may be electrically connected to the interconnect layer INT2 through a contact window CW11, and the source electrode S1 may serve as a power supply terminal. The source electrode S2 of the inverter 20 may be electrically connected to the interconnect layer INT3 through a contact window CW12, and the source electrode S2 may serve as a ground terminal. The drain electrodes D1 and D2 of the inverter 20 may be electrically connected to the interconnect layer INT4 through contact windows CW21 and CW22, respectively, and the drain electrodes D1 and D2 may serve as output terminals.

[0122] Based on the above, in this embodiment, transistors 20A and 20B can be stacked on top of each other in the top Z direction of the substrate 22, and transistors 20A and 20B can share the gate structure 26. Therefore, the inverter 20 of this embodiment can have a three-dimensional structure, and its area can be reduced to have a relatively small size. More specifically, the three-dimensional inverter 20 of this embodiment can reduce the area by about one-quarter compared to a planar inverter, making the inverter 20 of this embodiment easy to integrate into various electronic devices.

[0123] Figure 4 This is a partial cross-sectional schematic diagram of a memory cell according to an embodiment of the present invention, and Figure 5 This is a circuit diagram of a memory cell according to an embodiment of the present invention.

[0124] Please refer to the following at the same time Figure 4 and Figure 5In this embodiment, the memory unit 30 can be a static random-access memory (SRAM), but the present invention is not limited thereto. In some embodiments, the memory unit 30 may include two cross-coupled inverters 30A and 30B. In this embodiment, inverters 30A and 30B have a structure similar to that of inverter 20 in the aforementioned embodiment. Briefly, inverter 30A may include transistors 30A1 and 30A2 stacked on top of each other, and inverter 30B may include transistors 30B1 and 30B2 stacked on top of each other, wherein transistors 30A1 and 30B1 may have a structure similar to that of transistor 20A in the aforementioned embodiment, and transistors 30A2 and 30B2 may have a structure similar to that of transistor 20B in the aforementioned embodiment.

[0125] More specifically, transistor 30A1 may include a gate structure 36 (including a gate electrode 36A and a gate dielectric layer 36B), a source electrode S1, a drain electrode D1 and a semiconductor layer SE located in a trench Tr1, wherein doped regions DR1 and DR2 surround the gate structure 36, such that doped regions DR1, DR2 and the semiconductor layer SE located therebetween can form the channel layer of transistor 30A1.

[0126] More specifically, transistor 30A2 may include a gate structure 36, a source electrode S2, a drain electrode D2, and a semiconductor layer 38 located in trench Tr2. That is, in this embodiment, transistor 30A1 and transistor 30A2 may share the gate structure 36.

[0127] More specifically, transistor 30B1 may include a gate structure 36' (including a gate electrode 36A' and a gate dielectric layer 36B') located in trench Tr1', a source electrode S1, a drain electrode D1' and a semiconductor layer SE, wherein doped regions DR1' and DR2' surround the gate structure 36', such that doped regions DR1', DR2' and the semiconductor layer SE located therebetween can form the channel layer of transistor 30B1.

[0128] More specifically, transistor 30B2 may include a gate structure 36', a source electrode S2', a drain electrode D2', and a semiconductor layer 38' located in trench Tr2'. That is, in this embodiment, transistor 30B1 and transistor 30B2 may share the gate structure 36'.

[0129] In this embodiment, inverters 30A and 30B share the source electrode S1 and the semiconductor layer SE. More specifically, transistors 30A1 and 30B1 share the source electrode S1 and the semiconductor layer SE, which can further reduce the area and have a relatively small size.

[0130] In some embodiments, transistors 30A1 and 30B1 may be pull-up transistors in memory cell 30, and transistors 30A2 and 30B2 may be pull-down transistors in memory cell 30, but the present invention is not limited thereto. In this embodiment, inverters 30A and 30B may be coupled to power line V. DD Between the inverter 30A and the ground line GND, the source electrode S1 shared by inverters 30A and 30B can be connected to the power supply line V. DD The source electrode S2 of inverter 30A and the source electrode S2' of inverter 30B can each be coupled to the ground wire GND.

[0131] In this embodiment, the memory cell 30 may further include transistors 30C1 and 30C2. In some embodiments, transistor 30C1 may be electrically connected to inverter 30A, and transistor 30C2 may be electrically connected to inverter 30B. In this embodiment, transistors 30C1 and 30C2 may be transmission gates, which can be used to control the storage of the memory cell 30 during write and / or read operations, but the present invention is not limited thereto.

[0132] More specifically, transistor 30C1 may include a gate structure G3, a source electrode S3, a drain electrode D3, and a semiconductor layer SE3, and transistor 30C2 may include a gate structure G4, a source electrode S4, a drain electrode D4, and a semiconductor layer SE4. In some embodiments, gate structure G3 and gate structure G4 may be coupled to word line WL, source electrode S3 and source electrode S4 may be coupled to bit line BL1 and bit line BL2 respectively, drain electrode D3 may be coupled to drain electrode D1 of transistor 30A1 and drain electrode D2 of transistor 30A2, and drain electrode D4 may be coupled to drain electrode D1' of transistor 30B1 and drain electrode D2' of transistor 30B2.

[0133] In summary, in the transistor and its manufacturing method provided by the present invention, a channel layer with a vertical structure is formed by forming a doped region in the buffer layer to set a channel region contact between the source electrode and the drain electrode, thereby forming a vertical transistor with a novel structure.

[0134] In the inverter and its manufacturing method provided by this invention, by stacking two transistors on a substrate, the inverter of this invention can have a three-dimensional structure. Furthermore, by having the two transistors share a single gate structure, the area of ​​the inverter of this invention can be reduced to a relatively small size, thereby facilitating its integration into various electronic devices and improving the area utilization efficiency of the electronic devices.

[0135] In the memory cell provided by the present invention, by making the pull-up transistors in two cross-coupled inverters share a common source electrode and semiconductor layer, the memory cell of the present invention can further reduce the area and have a relatively small size, so as to improve the area utilization efficiency of electronic devices.

[0136] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A transistor, characterized in that, include: Substrate; A stacked structure, disposed on the substrate, includes: Drain electrode; The source electrode is disposed on the drain electrode; A semiconductor layer is disposed between the drain electrode and the source electrode; A first buffer layer is disposed between the drain electrode and the semiconductor layer; and A second buffer layer is disposed between the source electrode and the semiconductor layer; and a gate structure is disposed on the substrate, wherein the gate structure extends through the stacked structure in a top view of the substrate, and the gate structure includes: Gate electrode; and A gate dielectric layer is disposed between the gate electrode and the stacked structure.

2. The transistor according to claim 1, characterized in that, The materials of the first buffer layer and the second buffer layer include oxide semiconductors, and the material of the semiconductor layer includes polycrystalline silicon.

3. The transistor according to claim 1, characterized in that, The first buffer layer includes a first doped region, the second buffer layer includes a second doped region, and the first doped region and the second doped region are each in contact with the semiconductor layer and the gate dielectric layer.

4. The transistor according to claim 1, characterized in that, The gate structure has a columnar structure in the top view of the substrate.

5. An inverter, characterized in that, include: Substrate; A stacked structure, disposed on the substrate and including a first stacked structure and a second stacked structure disposed on the first stacked structure, wherein the first stacked structure includes: First source electrode; The first drain electrode is disposed on the first source electrode; A first semiconductor layer is disposed between the first source electrode and the first drain electrode; A first buffer layer is disposed between the first source electrode and the first semiconductor layer; and A second buffer layer is disposed between the first drain electrode and the first semiconductor layer, wherein the second stacked structure includes: Second drain electrode; The second source electrode is disposed on the second drain electrode; and An insulating layer is disposed between the second drain electrode and the second source electrode; A gate structure is disposed on the substrate, wherein the gate structure extends through the stacked structure in a top view of the substrate, and the gate structure includes: Gate electrode; and A gate dielectric layer is disposed between the gate electrode and the stacked structure; and A second semiconductor layer is disposed between the gate structure and the second stacked structure, wherein the second semiconductor layer is in contact with the second source electrode and the second drain electrode.

6. The inverter according to claim 5, characterized in that, The width of the gate structure surrounded by the first semiconductor layer is smaller than the width of the gate structure surrounded by the second semiconductor layer.

7. The inverter according to claim 5, characterized in that, The width of the gate structure surrounded by the first semiconductor layer and the width of the gate structure surrounded by the second semiconductor layer are less than or equal to 5 micrometers.

8. The inverter according to claim 5, characterized in that, The materials of the first buffer layer and the second buffer layer include oxide semiconductors, and the material of the first semiconductor layer includes polycrystalline silicon.

9. The inverter according to claim 5, characterized in that, The first buffer layer includes a first doped region, the second buffer layer includes a second doped region, and the first doped region and the second doped region are each in contact with the semiconductor layer and the gate dielectric layer.

10. The inverter according to claim 5, characterized in that, The material of the second semiconductor layer includes an oxide semiconductor.

11. The inverter according to claim 5, characterized in that, The gate structure has a columnar structure in the top view of the substrate.

12. The inverter according to claim 5, characterized in that, It also includes an interconnect layer, wherein the interconnect layer comprises: A first interconnect layer, wherein the gate electrode is electrically connected to the first interconnect layer and serves as an input terminal; The second interconnect layer, wherein the first source electrode is electrically connected to the second interconnect layer and serves as a power supply terminal; A third interconnect layer, wherein the second source electrode is electrically connected to the third interconnect layer and serves as a ground terminal; and The fourth interconnect layer, wherein the first drain electrode and the second drain electrode are electrically connected to the fourth interconnect layer and serve as output terminals.

13. A method for manufacturing an inverter, characterized in that, include: Forming a first stacked structure material layer including a first semiconductor layer; A second stacked structural material layer is formed on the first stacked structural material layer; A first contact window and a second contact window are formed, wherein the first contact window is electrically connected to the first source electrode in the first stacked structure material layer and the second source electrode in the second stacked structure material layer, and the second contact window is electrically connected to the first drain electrode in the first stacked structure material layer and the second drain electrode in the second stacked structure material layer. A portion of the second stacked structure material layer is removed to form a first trench, and a second semiconductor layer is formed in the first trench, wherein the second semiconductor layer is in contact with the second source electrode and the second drain electrode; A portion of the first stacked structural material layer is removed through the first trench to form a second trench, wherein the width of the second trench is smaller than the width of the first trench; as well as A gate structure is formed that fills the first trench and the second trench.

14. The method for manufacturing an inverter according to claim 13, characterized in that, The first semiconductor layer is formed using a low-temperature polycrystalline silicon process.

15. The method for manufacturing an inverter according to claim 13, characterized in that, The second semiconductor layer is formed by atomic layer deposition, and the material of the second semiconductor layer includes oxide semiconductor.

16. The method for manufacturing an inverter according to claim 13, characterized in that, The first stacked structure material layer includes a first buffer layer and a second buffer layer. The first buffer layer includes a first doped region, and the second buffer layer includes a second doped region. The first doped region and the second doped region are each in contact with the first semiconductor layer and the gate structure.

17. The method for manufacturing an inverter according to claim 16, characterized in that, The first doped region and the second doped region are formed using an ion implantation process.

18. A memory unit, characterized in that, include: A cross-coupled first inverter and a second inverter, wherein the first inverter and the second inverter are inverters according to claim 5. The first inverter and the second inverter share the first source electrode and the first semiconductor layer.

19. The memory unit according to claim 18, characterized in that, It also includes a first transmission transistor and a second transmission transistor, wherein the first transmission transistor is coupled to the first inverter and the second transmission transistor is coupled to the second inverter.

20. The memory unit according to claim 18, characterized in that, It is a type of static random access memory.

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