Chip packaging structure and wafer

Abstract

The invention relates to a chip packaging structure and a wafer. The chip packaging structure comprises a first chip unit and a second chip unit which are arranged in a stacked mode. A first groove is formed in the face, making contact with the second chip unit, of the first chip unit, and a second groove is formed in the face, making contact with the first chip unit, of the second chip unit. The first groove and the second groove are matched to form a heat dissipation liquid flow channel, the heat dissipation liquid flow channel comprises a first channel and a plurality of second channels, the first channel is communicated with the liquid injection cavity, the second channels are communicated with the first channel, and the distribution positions of the second channels correspond to the heating areas of the first chip unit and the second chip unit; and one side, far away from the first chip unit, of the second chip unit is provided with a heat dissipation liquid cavity communicated with the first channel. By arranging the heat dissipation liquid flow channel, close-range attachment of the heat dissipation liquid flow channel and a chip heat source is achieved, a heat dissipation path is greatly shortened, heat transfer resistance is reduced, and meanwhile precise targeted cooling of a chip hot spot area is achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a chip packaging structure and wafer. BACKGROUND

[0002] With the rapid development of artificial intelligence, high-performance computing and other fields, the market has put forward higher requirements on the computing power density and integration of integrated circuits. Three-dimensional packaging technology greatly improves system performance and space utilization through vertical stacking of chips, and has become an important development direction in the field of integrated circuits. However, the dense stacking of chips leads to a sharp increase in power density, and heat is highly concentrated in the vertical direction, forming a bottleneck restricting the development of 3D (Three-Dimensional) packaging technology.

[0003] In the existing heat dissipation scheme, the traditional air cooling technology sharply decreases in efficiency when the power of the device exceeds a threshold value, and cannot meet the heat dissipation needs of high-power-density chips. SUMMARY

[0004] Therefore, in view of the above technical problems, the present application provides a chip packaging structure and wafer capable of directly and efficiently dissipating heat from the inside of the chip packaging.

[0005] In a first aspect, the present application provides a chip packaging structure, comprising a first chip unit and a second chip unit stacked; a first groove is formed on the side of the first chip unit contacting the second chip unit, and a second groove is formed on the side of the second chip unit contacting the first chip unit; the first groove and the second groove cooperate to form a heat dissipation liquid flow channel, the heat dissipation liquid flow channel comprises a first channel and a plurality of second channels, the first channel is in communication with a liquid injection cavity, the second channel is in communication with the first channel, and the distribution positions of the plurality of second channels correspond to the heat generation areas of the first chip unit and the second chip unit; a heat dissipation liquid cavity is arranged on the side of the second chip unit away from the first chip unit, and the heat dissipation liquid cavity is in communication with the first channel.

[0006] In one of the embodiments, the liquid injection cavity and the first channel are in communication through a jet hole array; the aperture size of any jet hole in the jet hole array is smaller than the aperture size of the first channel.

[0007] In one of the embodiments, further comprising a temperature sensing unit and a flow adjusting unit; the temperature sensing unit is integrated in at least one heat generation area of the first chip unit and the second chip unit; and the flow adjusting unit is arranged in the heat dissipation liquid flow channel.

[0008] In one embodiment, the first channel includes at least one set of first liquid inlet channels and a first liquid outlet channel, and the two ends of at least one second channel are respectively connected to the set of first liquid inlet channels and the first liquid outlet channel; the first liquid inlet channel is connected to the liquid injection chamber, and the first liquid outlet channel is connected to the liquid outlet chamber; the heat dissipation liquid chamber is connected to the first liquid inlet channel and the first liquid outlet channel respectively.

[0009] In one embodiment, at least two sets of first liquid inlet channels and first liquid outlet channels are symmetrically arranged in the orthographic projection of the plane where the first chip unit is located; or, at least two first liquid inlet channels and at least two first liquid outlet channels are symmetrically arranged in the orthographic projection of the plane where the first chip unit is located; or, multiple first liquid inlet channels and first liquid outlet channels are symmetrically arranged in the orthographic projection of the plane where the first chip unit is located.

[0010] In one embodiment, the system further includes a cover plate, a first redistribution silicon layer, a second redistribution silicon layer, and a third redistribution silicon layer; the first redistribution silicon layer is disposed on the side of the first chip unit away from the second chip unit, and the cover plate is disposed on the side of the first redistribution silicon layer away from the first chip unit; the second redistribution silicon layer is disposed on the side of the second chip unit away from the first chip unit, and the third redistribution silicon layer is disposed on the side of the second redistribution silicon layer away from the second chip unit; a liquid injection chamber and a liquid outlet chamber are provided between the cover plate and the first redistribution silicon layer, and a heat dissipation liquid chamber is provided between the second redistribution silicon layer and the third redistribution silicon layer.

[0011] In one embodiment, a silicon spacer is also included, located between a first redistribution silicon layer and a second redistribution silicon layer, the silicon spacer, the first redistribution silicon layer and the second redistribution silicon layer forming a receiving cavity, and a first chip cell and a second chip cell located within the receiving cavity.

[0012] In one embodiment, the cover plate is provided with an inlet hole and an outlet hole, the inlet hole being connected to the injection chamber and the outlet hole being connected to the outlet chamber.

[0013] In one implementation, the distribution density of the second channel is positively correlated with the power consumption of each region in the first and second chip cells.

[0014] Secondly, this application provides a wafer including the chip packaging structure as described in the first aspect and any of its embodiments.

[0015] The chip packaging structure and wafer provided in this application include a heat dissipation liquid flow channel formed by the first trench and the second trench etched on opposite sides of the first chip unit and the second chip unit, and a first channel connected to the injection cavity and multiple second channels distributed at positions corresponding to the heat-generating areas of the chip. Combined with the heat dissipation liquid cavity connected to the first channel and located on the side of the second chip unit away from the first chip, the heat dissipation liquid flow channel and the heat dissipation liquid cavity are closely fitted to the heat source of the chip, significantly shortening the heat dissipation path of the chip and reducing the thermal resistance. At the same time, the corresponding arrangement of the second channels to the heat-generating areas of the chip facilitates precise targeted cooling of the hot spots of the chip, effectively suppressing the chip temperature, and eliminating the need for additional independent heat dissipation components. This chip packaging structure not only improves the integration and compactness of the chip packaging structure, but also adapts to the heat dissipation requirements of high power density chips.

[0016] Understandably, the beneficial effects that the wafer provided in the second aspect above can achieve can be referred to as the beneficial effects in the first aspect and any of its possible implementations, and will not be repeated here. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a chip packaging structure provided in an embodiment of this application;

[0019] Figure 2 This is a cross-sectional schematic diagram of a first chip unit and a second chip unit in a chip packaging structure provided in an embodiment of this application;

[0020] Figure 3 A schematic diagram of a heat dissipation liquid flow channel in a chip packaging structure provided in an embodiment of this application;

[0021] Figure 4 This is a schematic diagram showing the flow direction of coolant in a chip packaging structure provided in an embodiment of this application.

[0022] In the picture:

[0023] 110 - First chip unit; 120 - Second chip unit; 130 - Heat dissipation liquid flow channel; 140 - Cover plate; 150 - First redistribution silicon layer; 160 - Second redistribution silicon layer; 170 - Third redistribution silicon layer; 180 - Silicon spacer; 190 - Jet hole array;

[0024] 101 - Injection chamber; 102 - Outlet chamber; 103 - Heat dissipation chamber;

[0025] 111 - First trench; 121 - Second trench;

[0026] 131 - First Channel; 132 - Second Channel;

[0027] 141 - Liquid inlet; 142 - Liquid outlet;

[0028] 181 - Through silicon via; 182 - Metal conductor. Detailed Implementation

[0029] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0030] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0031] In the embodiments of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" and "second" may explicitly or implicitly include one or more of that feature.

[0032] It should be understood that the terminology used in the description of the various examples herein is for the purpose of describing the particular examples only and is not intended to be limiting. As used in the description of the various examples, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context explicitly indicates otherwise.

[0033] In this application, "multiple" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of a single item or a plurality of items.

[0034] It should also be understood that, in this application, unless otherwise expressly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a sliding connection, a detachable connection, or an integral part, etc.; it can be a direct connection or an indirect connection through an intermediate medium.

[0035] It should also be understood that the term "comprising" as used in this specification specifies the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0036] It should be understood that the terms "an embodiment," "another embodiment," and "an implementation" used throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment or implementation is included in at least one embodiment of this application. Therefore, phrases such as "in one embodiment of this application," "in another embodiment of this application," and "a possible design" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0037] With the rapid development of fields such as artificial intelligence and high-performance computing, the market has placed higher demands on the computing power density and integration level of integrated circuits. 3D packaging technology, through vertical chip stacking, significantly improves system performance and space utilization, becoming an important development direction in the current integrated circuit field. However, the dense stacking of chips leads to a sharp increase in power density and a high concentration of heat in the vertical direction, forming a bottleneck restricting the development of 3D packaging technology.

[0038] In existing heat dissipation solutions, traditional air cooling technology experiences a sharp decline in heat dissipation efficiency once the device power exceeds a threshold, failing to meet the heat dissipation requirements of high-power-density chips. In liquid cooling solutions, the external liquid cooling plate is far from the internal heat source of the chip, resulting in high thermal resistance and making it difficult to effectively cool the middle layer of stacked chips.

[0039] To address the aforementioned technical problems, this application provides a chip packaging structure. (Reference) Figure 1 , Figure 2 and Figure 3 , Figure 1 This is a schematic diagram of a chip packaging structure provided in an embodiment of this application. Figure 2 This is a cross-sectional schematic diagram of a first chip unit and a second chip unit in a chip packaging structure provided in an embodiment of this application. Figure 3 This is a schematic diagram of a heat dissipation liquid flow channel in a chip packaging structure provided in an embodiment of this application.

[0040] like Figure 1 , Figure 2 andFigure 3 As shown, this application provides a chip packaging structure, including a first chip unit 110 and a second chip unit 120 stacked together; a first trench 111 is formed on the side of the first chip unit 110 that contacts the second chip unit 120, and a second trench 121 is formed on the side of the second chip unit 120 that contacts the first chip unit 110; the first trench 111 and the second trench 121 cooperate to form a heat dissipation liquid flow channel 130, the heat dissipation liquid flow channel 130 includes a first channel 131 and multiple second channels 132, the first channel 131 communicates with the liquid injection cavity 101, the second channels 132 communicate with the first channel 131, and the distribution positions of the multiple second channels 132 correspond to the heat-generating areas of the first chip unit 110 and the second chip unit 120; and a heat dissipation liquid cavity 103 is provided on the side of the second chip unit 120 away from the first chip unit 110, the heat dissipation liquid cavity 103 communicates with the first channel 131.

[0041] This embodiment discloses a chip packaging structure, which mainly includes a first chip unit 110 and a second chip unit 120. The first chip unit 110 is integrated on top of the second chip unit 120 in a vertically stacked manner. This stacking design can reduce the planar space occupied by the integrated circuit, improve the functional integration and computing power density of the system, and meet the application requirements of high chip integration and high power density in fields such as artificial intelligence and high-performance computing.

[0042] In this embodiment, a first groove 111 is formed on the surface of the first chip unit 110 near the second chip unit 120, and a second groove 121 is formed on the surface of the second chip unit 120 near the first chip unit 110. The first groove 111 and the second groove 121 can be configured to match each other in shape and size, specifically, they can be completely identical. Of course, the first groove 111 and the second groove 121 can also be configured to have different shapes and sizes.

[0043] When the shapes and sizes of the first trench 111 and the second trench 121 are matched, after the first chip unit 110 and the second chip unit 120 are bonded and stacked, the first trench 111 and the second trench 121 can fit tightly together and jointly form a complete heat dissipation liquid flow channel 130. The heat dissipation liquid flow channel 130 is located directly between the two chip units, which makes the heat dissipation liquid flow channel 130 located on the heat source (inner) surface of the chip. This significantly shortens the path of heat transfer from the inside of the chip to the coolant in the heat dissipation liquid flow channel 130, effectively reduces the thermal resistance loss during the heat transfer process, and achieves efficient heat dissipation at close range inside the chip.

[0044] For example, the heat dissipation liquid flow channel 130 may specifically include a first channel 131 and multiple second channels 132. The first channel 131 serves as the main distribution path for the coolant and is connected to the external injection chamber 101. Its function is to receive the coolant from the injection chamber 101 and distribute the coolant evenly to the subsequent second channels 132, ensuring a stable supply and uniform distribution of coolant within the heat dissipation liquid flow channel 130. The multiple second channels 132 are branched and connected to the first channel 131, and the distribution positions of the second channels 132 correspond one-to-one with the high-power heat-generating areas of the first chip unit 110 and the second chip unit 120. This targeted distribution design allows the coolant to flow precisely through high heat flux density areas such as the chip's computing core and storage core, tilting heat dissipation resources towards key heat-generating areas and avoiding resource waste in traditional uniform heat dissipation modes. When the coolant enters the first channel 131 through the injection chamber 101 and is then distributed to the second channels 132, it comes into direct contact with the heat source on the chip surface. Heat is absorbed through a combination of convection and phase change heat transfer. Convection heat transfer relies on the coolant's flow to quickly remove heat from the channel walls, while phase change heat transfer utilizes the coolant's phase change from liquefaction to vaporization after absorbing heat, absorbing a large amount of latent heat to rapidly cool hot spots. This combination of heat transfer methods significantly improves heat dissipation efficiency and effectively controls the operating temperature of high-power-density chips.

[0045] For example, in addition to providing a heat dissipation liquid flow channel 130 between the first chip unit 110 and the second chip unit 120, a heat dissipation liquid cavity 103 can be further provided on the surface of the second chip unit 120 away from the first chip unit 110. The heat dissipation liquid cavity 103 can be a channel structure or a cavity structure. The channel structure heat dissipation liquid cavity 103 can be configured such that the denser channel structure is more concentrated in the high power consumption heat generation area of ​​the first chip unit 110 and the second chip unit 120, so as to ensure the heat dissipation effect of the high power consumption heat generation area of ​​the chip. The cavity structure heat dissipation liquid cavity 103 can be configured such that the orthographic projection of the heat dissipation liquid cavity 103 on the plane where the first chip unit 110 is located covers the orthographic projection of the high power consumption heat generation area of ​​the first chip unit 110 and the second chip unit 120 on the plane where the first chip unit 110 is located, so as to ensure the heat dissipation effect of the high power consumption heat generation area of ​​the chip.

[0046] in, Figure 1The schematic diagram of the chip packaging structure shown is exemplified by a chip packaging structure including one first chip unit 110 and one second chip unit 120, but this application is not limited thereto. If there is a higher requirement for the number of chips stacked in the chip packaging structure, multiple first chip units 110 and one second chip unit 120 can also be stacked in the chip packaging structure. In the direction from the first chip unit 110 to the second chip unit 120, a heat dissipation liquid flow channel 130 or a heat dissipation liquid cavity 103 can also be provided between two adjacent stacked first chip units 110 as needed. The heat dissipation liquid flow channel 130 or heat dissipation liquid cavity 103 located between two first chip units 110 is connected to the first channel 131 located between the first chip unit 110 and the second chip unit 120 to ensure that coolant can flow between any two adjacent stacked chip units to ensure the heat dissipation effect for the chip units.

[0047] Compared to traditional air cooling, the liquid cooling channel 130 in this embodiment directly reaches the heat-generating area inside the chip unit. Combined with a heat dissipation liquid cavity 103 located on at least one side of the second chip unit 120 away from the first chip unit 110, the heat dissipation efficiency of each chip unit within the chip package structure is significantly improved, meeting the heat dissipation requirements of high-power-density chips. Compared to external liquid cooling plate solutions in related technologies, the heat dissipation liquid channel 130 in this embodiment is directly formed by grooves on the chip surface. Combined with the heat dissipation liquid cavity 103, the coolant flowing to the heat dissipation liquid channel 130 and the heat dissipation liquid cavity 103 is closer to the heat source, significantly shortening the heat dissipation path, reducing thermal resistance, and achieving precise targeted cooling of hot spots in the chip unit. Furthermore, this chip package structure eliminates the need for additional independent heat dissipation components, achieving integrated heat dissipation functionality and chip package structure. This improves heat dissipation efficiency while maintaining the compactness of the package structure, enhancing the miniaturization and high-density of three-dimensional packaged integrated circuits.

[0048] like Figure 1As shown, in one embodiment of this application, a cover plate 140, a first redistribution silicon layer 150, a second redistribution silicon layer 160, and a third redistribution silicon layer 170 are also included. The first redistribution silicon layer 150 is disposed on the side of the first chip unit 110 away from the second chip unit 120, and the cover plate 140 is disposed on the side of the first redistribution silicon layer 150 away from the first chip unit 110. The second redistribution silicon layer 160 is disposed on the side of the second chip unit 120 away from the first chip unit 110, and the third redistribution silicon layer 170 is disposed on the side of the second redistribution silicon layer 160 away from the second chip unit 120. A liquid injection chamber 101 and a liquid outlet chamber 102 are provided between the cover plate 140 and the first redistribution silicon layer 150, and a heat dissipation liquid chamber 103 is provided between the second redistribution silicon layer 160 and the third redistribution silicon layer 170. Both the liquid outlet chamber 102 and the heat dissipation liquid chamber 103 are connected to the first channel 131.

[0049] The chip packaging structure in this embodiment includes a first chip unit 110, a second chip unit 120, and a microtrench heat dissipation layer disposed between them. The microtrench heat dissipation layer forms heat dissipation liquid flow channels 130, including a first channel 131 and multiple second channels 132. A first redistribution silicon layer 150 is disposed on the side of the first chip unit 110 away from the second chip unit 120. Its function is to redistribute and rewire the functional pads on the surface of the first chip unit 110. Since the first chip unit 110 is a high-power-density functional chip, its pad distribution density is high and its arrangement is irregular, making direct connection to external circuits or interconnect structures difficult. The first redistribution silicon layer 150 can adjust the spacing and position of the pads through photolithography and electroplating processes to match subsequent electrical interconnection requirements. It also provides physical protection for the surface circuitry of the first chip unit 110, preventing external damage to the chip during packaging or operation.

[0050] The cover plate 140 is disposed on the side of the first interconnect silicon layer 150 away from the first chip cell 110. The cover plate 140 can be made of single-crystal silicon compatible with the chip substrate material. Its coefficient of thermal expansion matches that of the first chip cell 110 and the first interconnect silicon layer 150, which can effectively reduce thermal stress caused by temperature changes and prevent warping deformation of the packaging structure. At the same time, the cover plate 140 can fit tightly with the first interconnect silicon layer 150 to form a sealing barrier, isolating external dust, moisture and other impurities, and ensuring the stable operation of the internal chip and heat dissipation structure.

[0051] The second wiring silicon layer 160 is disposed on the side of the second chip cell 120 away from the first chip cell 110, and the third wiring silicon layer 170 is disposed on the side of the second wiring silicon layer 160 away from the second chip cell 120. The second wiring silicon layer 160 and the third wiring silicon layer 170 form a double-layer wiring structure. The two work together to not only adjust the pad layout of the second chip cell 120 to achieve efficient connection between the second chip cell 120 and external circuits, but also reserve sufficient space between the double-layer wiring structure for arranging auxiliary heat dissipation structures, further enhancing the heat dissipation potential of the package structure.

[0052] To achieve stable circulation and efficient heat exchange of the coolant, this embodiment provides an injection chamber 101 and an outlet chamber 102 between the cover plate 140 and the first redistribution silicon layer 150. The injection chamber 101 receives low-temperature coolant from an external cooling system and stably delivers it to the first channel 131 and the second channel 132. The outlet chamber 102 recovers the high-temperature coolant that has flowed through the heat dissipation liquid flow channel 130 and completed heat exchange, thus achieving coolant recycling. Simultaneously, a heat dissipation liquid chamber 103 is provided between the second redistribution silicon layer 160 and the third redistribution silicon layer 170. This heat dissipation liquid chamber 103 expands the flow space and path of the coolant, serving to dissipate heat from the bottom of the second chip unit 120. When the coolant flows through the first channel 131 and the second channel 132, it can dissipate heat on the side of the first chip unit 110 and the second chip unit 120 that are close to each other. Some of the coolant can flow into the heat dissipation liquid cavity 103 to dissipate heat on the chip unit on one side of the heat dissipation liquid cavity 103, thereby further reducing the temperature of the chip unit and improving the heat dissipation efficiency.

[0053] The injection chamber 101, the outlet chamber 102, and the heat dissipation liquid chamber 103 are all connected to the first channel 131 in the heat dissipation liquid flow channel 130, forming a complete and closed-loop coolant circulation loop. This multi-chamber collaborative design not only ensures a sufficient supply of coolant but also improves the utilization rate of coolant and enhances the heat dissipation effect. At the same time, the setting of the first wiring silicon layer 150 and the second wiring silicon layer 160 effectively solves the problem of mismatch between the chip unit pads and the external interface, improves the electrical interconnection performance of the entire package structure, and realizes the integrated integration of heat dissipation function and electrical interconnection function.

[0054] In this embodiment, by adding a cover plate 140, a first redistribution silicon layer 150, a second redistribution silicon layer 160, and a third redistribution silicon layer 170, the integration of the packaging structure is improved and the heat dissipation performance is enhanced, while the electrical interconnect compatibility of the chip unit is optimized.

[0055] Please refer to Figure 1In one embodiment of this application, the first channel 131 includes at least one set of first liquid inlet channels and first liquid outlet channels, and the two ends of at least one second channel 132 are respectively connected to the first liquid inlet channels and the first liquid outlet channels; the first liquid inlet channel is connected to the liquid injection chamber 101, and the first liquid outlet channel is connected to the liquid outlet chamber 102; the heat dissipation liquid chamber 103 is connected to the first liquid inlet channel and the first liquid outlet channel respectively.

[0056] For example, in the chip packaging structure provided in this application, the liquid injection chamber 101 can be connected to the first liquid inlet channel in the first channel 131. The first liquid inlet channel is further connected to the second channel 132 and the heat dissipation liquid chamber 103, so that the coolant in the liquid injection chamber 101 can flow to the second channel 132 and the heat dissipation liquid chamber 103 through the first liquid inlet channel. At the same time, the first liquid outlet channel is connected to the second channel 132 and the heat dissipation liquid chamber 103, and also connected to the liquid outlet chamber 102, so that the coolant flowing through the second channel 132 and the heat dissipation liquid chamber 103 can further flow to the liquid outlet chamber 102 through the first liquid outlet channel. In this way, two types of coolant flow paths are formed: liquid injection chamber 101-first liquid inlet channel-second channel 132-first liquid outlet channel-liquid outlet chamber 102, and liquid injection chamber 101-first liquid inlet channel-heat dissipation liquid chamber 103-first liquid outlet channel-liquid outlet chamber 102. Since there are multiple second channels 132, they can include multiple coolant flow paths such as "injection chamber 101 - first inlet channel - second channel 132 - first outlet channel - outlet chamber 102".

[0057] This application does not limit the size settings of each second channel 132, nor the size settings of each part inside each second channel 132. The settings can be adjusted according to the needs, as long as a relatively large amount of coolant can flow through the heat source of the chip to improve the heat dissipation efficiency of the corresponding heat source area.

[0058] In this embodiment, by forming two types of coolant flow paths inside the chip packaging structure, namely, injection cavity 101-first inlet channel-second channel 132-first outlet channel-outlet cavity 102 and injection cavity 101-first inlet channel-heat dissipation liquid cavity 103-first outlet channel-outlet cavity 102, sufficient supply of coolant is ensured at multiple surfaces of the chip, which can improve the utilization rate of coolant and enhance the heat dissipation effect.

[0059] Please refer to Figure 1 In one embodiment of this application, the chip packaging structure further includes a temperature sensing unit and a flow regulation unit (not shown in the figure); the temperature sensing unit is integrated in at least one heat-generating area in the first chip unit 110 and the second chip unit 120; the flow regulation unit is disposed in the heat dissipation liquid flow channel 130.

[0060] For example, this application also integrates a temperature sensing unit and a flow regulation unit in the chip packaging structure. The temperature sensing unit can be embedded inside or on the surface of the chip unit. For example, temperature sensing units can be provided inside both the first chip unit 110 and the second chip unit 120. At least one temperature sensing unit can be set in the heat-generating area of ​​the chip unit to accurately and quickly measure the heat generation of the heat-generating area during the use of the chip unit.

[0061] The flow regulation unit included in the chip package structure is at least located inside the second channel 132. For example, at least one flow regulation unit can be provided in each second channel 132. This allows the flow rate of the coolant in the flow path of "liquid injection chamber 101 - first liquid inlet channel - second channel 132 - first liquid outlet channel - liquid outlet chamber 102" to be accelerated when the flow regulation unit in the second channel 132 is working, thereby accelerating the heat dissipation efficiency of the relevant area of ​​the chip unit corresponding to the path.

[0062] The flow regulation unit in the second channel 132 can be installed inside the second channel 132 near the first channel 131. This allows the coolant in the injection chamber to be quickly introduced into the second channel 132 through the first inlet channel when the flow regulation unit is turned on. This improves the flow rate efficiency of the coolant in the path of the second channel 132, thereby improving the heat dissipation efficiency of the chip unit area in the path of the second channel 132.

[0063] For example, the flow regulation unit can employ a micropump, and the flow rate and volume of coolant in the channel where the micropump is located can be controlled by adjusting the rotational speed of the micropump.

[0064] For example, the flow regulation unit can be a valve, and the flow rate and volume of coolant in the valve channel can be controlled by adjusting the valve opening.

[0065] Alternatively, at least one coolant flow path may be equipped with both a micro-pump and a valve. The embodiments provided in this application, which use micro-pumps and / or valves to control the coolant flow rate in the heat dissipation branch, are merely optional implementations provided by this application. However, this application is not limited to these methods, and other methods capable of controlling the coolant flow rate in the heat dissipation branch may also be employed.

[0066] It should also be added that, in the first channel 131, the second channel 132, and the heat dissipation liquid cavity 103 included in the chip packaging structure, a flow regulation unit can be set at any location as needed. This application does not limit the number and location of the flow regulation units required in the chip packaging structure, as long as the flow regulation unit can be used to regulate the flow rate and velocity of the coolant on its path to achieve a good heat dissipation effect on the chip area corresponding to the relevant path.

[0067] In this embodiment, by setting a temperature sensing unit in the chip unit and a flow regulation unit in the heat dissipation liquid flow channel 130 and / or heat dissipation liquid cavity 103, it is possible to drive the flow regulation unit in the coolant flow path corresponding to the abnormal high temperature area to start working when any temperature sensing unit detects an abnormal high temperature, so as to increase the flow rate and flow velocity of the coolant in the coolant flow path, thereby improving the heat dissipation efficiency of the coolant for the abnormal high temperature area of ​​the chip.

[0068] like Figure 1 As shown, in one embodiment of this application, the injection chamber 101 and the first channel 131 are connected by a jet hole array 190, and the aperture size of any jet hole in the jet hole array 190 is smaller than the aperture size of the first channel 131.

[0069] In this embodiment, the injection chamber 101 and the first channel 131 are connected by a jet hole array 190. The jet hole array 190 is composed of multiple tiny through holes (jet holes) arranged in an array. Its overall distribution is adapted to the extension direction of the first channel 131. That is, the extension direction of the jet hole is the same as the extension direction of the first channel 131, which is the direction in which the coolant can flow from the injection chamber 101 to the second channel 132. Moreover, the size of each jet hole is smaller than the size of the first channel 131. This size difference is the key to achieving jet impact heat dissipation.

[0070] The aperture size of the jet orifice refers to the size of the jet orifice in the direction perpendicular to the flow of coolant in the orifice, and the aperture size of the first channel 131 refers to the size of the first channel 131 in the direction perpendicular to the flow of coolant in the channel.

[0071] For example, the jet orifice array 190 may be disposed in the first channel 131 near one end of the injection chamber 101; or, the input end of the jet orifice array 190 may be connected to the output end of the injection chamber 101, and the output end of the jet orifice array 190 may be connected to the input end of the first channel 131.

[0072] When the coolant enters the injection chamber 101, it flows through the jet orifice array 190 under pressure. Since the flow cross-section of the jet orifice is much smaller than that of the first channel 131, according to the fluid mechanics continuity equation, the flow velocity of the coolant will increase significantly as the flow cross-section decreases, thereby forming a high-speed jet with strong impact force, which is directly injected into the interior of the first channel 131.

[0073] It is worth noting that when the chip packaging structure includes multiple first channels 131 connected to the liquid injection cavity 101, the distribution density of the jet hole array 190 corresponding to each first channel 131 can be matched with the thermal distribution characteristics of the chip unit. At the locations corresponding to the hot spots of the first chip unit 110 and the second chip unit 120, the arrangement of the jet holes can be appropriately densified, allowing more high-speed coolant to flow to the high heat flux density area. Combined with the distribution characteristics of the second channel 132, this results in a better cooling effect. Simultaneously, the fabrication process of the jet hole array 190 is compatible with the etching process of the heat dissipation liquid flow channel 130, and can be completed in the same photolithography process without additional process steps, effectively controlling the complexity of the packaging process and production costs.

[0074] After the high-speed jet enters the first channel 131, it quickly diffuses into the second channel 132. Its powerful impact reaches the thermal boundary layer between the chip unit surface and the coolant, allowing the low-temperature coolant to directly contact the heat source surface of the chip, improving the convective heat transfer coefficient and enhancing heat transfer efficiency to quickly remove the heat generated by the high-power-density chip. Simultaneously, the small size of the jet orifices allows for the regulation of the coolant flow rate, preventing coolant waste due to excessive local flow and preventing hotspot accumulation caused by insufficient local flow, effectively improving the temperature uniformity of the chip surface. Furthermore, the hierarchical structure of the jet orifice array 190 and the heat dissipation liquid flow channel 130 works synergistically. After being accelerated by the jet orifice array 190, the coolant undergoes initial distribution within the first channel 131 and is then diverted to the heat-generating area of ​​the chip unit via the second channel 132. This gives the entire heat dissipation system both high-efficiency heat transfer capability and certain flow control characteristics.

[0075] like Figure 1 As shown, in one embodiment of this application, a silicon spacer 180 is also included. The silicon spacer 180 is located between the first redistribution silicon layer 150 and the second redistribution silicon layer 160. The silicon spacer 180, the first redistribution silicon layer 150 and the second redistribution silicon layer 160 form a receiving cavity, and the first chip unit 110 and the second chip unit 120 are located in the receiving cavity.

[0076] The chip packaging structure of this embodiment includes a first chip unit 110, a second chip unit 120, a micro-trench heat dissipation layer (heat dissipation liquid flow channel 130 and heat dissipation liquid cavity 103), a cover plate 140, a first redistribution silicon layer 150, a second redistribution silicon layer 160, a third redistribution silicon layer 170, and a silicon spacer 180. The silicon spacer 180 is made of single-crystal silicon with the same material as the chip substrate. Its coefficient of thermal expansion is highly matched with that of the first redistribution silicon layer 150, the second redistribution silicon layer 160, and the chip unit, which can reduce thermal stress caused by temperature changes during the packaging process and chip operation, and avoid problems such as warping and deformation of the packaging structure.

[0077] A silicon spacer 180 is disposed between the first redistribution silicon layer 150 and the second redistribution silicon layer 160, and its overall shape is a closed frame (ring) structure adapted to the outline of the chip unit. The upper and lower end faces of the silicon spacer 180 are tightly bonded to the lower surface of the first redistribution silicon layer 150 near the second redistribution silicon layer 160 and the upper surface of the second redistribution silicon layer 160 near the first redistribution silicon layer 150, respectively, through a wafer bonding process. The three together form a sealed cavity, and the first chip unit 110, the second chip unit 120, and the heat dissipation liquid flow channel 130 located between them are all completely covered inside the cavity. This frame-shaped structure design provides sufficient space for the chip unit and the heat dissipation layer without occupying the functional area of ​​the chip, achieving a balance between structural compactness and functionality. The silicon spacer 180 can provide stable vertical support for the first redistribution silicon layer 150 and the second redistribution silicon layer 160, ensuring that the heat dissipation liquid flow channel 130 formed between the first chip unit 110 and the second chip unit 120 is intact, avoiding the shrinkage or collapse of the heat dissipation liquid flow channel 130 caused by the pressure generated during chip stacking, ensuring the smooth flow of coolant in the channel, and thus ensuring the stable operation of the liquid cooling system.

[0078] Meanwhile, the monocrystalline silicon material of the silicon spacer 180 has a moderate thermal conductivity, between that of metals and organic packaging materials, which can form a thermal isolation barrier between the first chip unit 110 and the second chip unit 120, reducing direct heat conduction between them. This prevents heat from spreading from one chip to another, allowing the heat dissipation liquid flow channel 130 to cool the hot spots of each chip unit more effectively, thus improving the temperature control accuracy of the heat dissipation system.

[0079] Furthermore, the closed-frame structure of the silicon spacer 180, in conjunction with the cover plate 140 and the redistribution silicon layer, can seal the cavity, preventing coolant leakage within the heat dissipation liquid flow channel 130 and improving the reliability of the liquid cooling system. It also isolates external dust, moisture, and other impurities, providing a clean and stable working environment for the chip unit. In the packaging process, the silicon spacer 180 can also serve as a precise positioning reference, assisting in the alignment and bonding of the first chip unit 110, the second chip unit 120, and the redistribution silicon layer, reducing alignment deviations during packaging and improving product yield.

[0080] like Figure 1 As shown, in one embodiment of this application, a through-silicon via (TSV) 181 is provided in the silicon spacer 180. The through-hole extension direction of the TSV 181 is perpendicular to the plane where the first chip unit 110 is located. In the direction perpendicular to the plane where the first chip unit 110 is located, the TSV 181 penetrates the silicon spacer 180, the second redistribution silicon layer 160, and the third redistribution silicon layer 170. The first redistribution silicon layer 150 and the second redistribution silicon layer 160 are electrically connected by a metal conductor 182 disposed in the TSV 181, and the second redistribution silicon layer 160 and the third redistribution silicon layer 170 are electrically connected by a metal conductor 182 disposed in the TSV 181.

[0081] In this embodiment, the through-silicon vias 181 penetrate the upper and lower end faces of the silicon spacer 180 and are arranged in an array on the outer side of the cavity. This arrangement can avoid the chip cells and the heat dissipation liquid flow channel 130 inside the cavity, thus avoiding obstruction or interference to the heat dissipation liquid flow channel 130. It can also improve the density and stability of electrical interconnection between redistribution silicon layers through array distribution, thus meeting the high bandwidth signal transmission requirements of 3D packaged integrated circuits.

[0082] The interior of the through-silicon via 181 is filled with a metal conductor 182, which can be made of copper. Copper has excellent electrical and thermal conductivity, enabling it to simultaneously perform the dual functions of electrical signal transmission and heat conduction. In terms of electrical connection, the first multi-layer silicon 150 and the second multi-layer silicon 160 are vertically connected through the metal conductor 182 within the through-silicon via 181. The two ends of the metal conductor 182 are tightly connected to the wiring layers of the first multi-layer silicon 150 and the second multi-layer silicon 160 respectively using a metal bonding process, ensuring low signal loss and stability in signal transmission. Simultaneously, the second multi-layer silicon 160 and the third multi-layer silicon 170 are also electrically connected through the through-silicon via 181 extending to the lower part of the silicon spacer 180 and the internal metal conductor 182, forming a vertical interconnect path connecting the first multi-layer silicon 150, the second multi-layer silicon 160, and the third multi-layer silicon 170. The silicon spacer 180 no longer only serves the functions of support, sealing and thermal isolation, but also realizes electrical interconnection between redistribution silicon layers through silicon vias 181, eliminating the need for additional interconnection components such as wire bonding or connectors, and greatly reducing the volume of the package structure.

[0083] Meanwhile, the metal conductor 182 within the through-silicon via 181 also plays a role in auxiliary heat dissipation. Heat generated during operation by the first redistribution silicon layer 150 and the second redistribution silicon layer 160 can be rapidly conducted to the silicon spacer 180 via the metal conductor 182, and then diffused to the surrounding environment from the silicon spacer 180, further enhancing the heat dissipation performance of the entire package structure. Furthermore, the fabrication process of the through-silicon via 181 is fully compatible with that of the chip unit and the heat dissipation liquid flow channel 130, and can be completed in the same photolithography, etching, and electroplating process without additional process steps, effectively reducing production costs and improving the feasibility of mass production. The array-distributed through-silicon vias 181 also have the advantage of redundant design; even if individual through-silicon vias 181 fail, the remaining through-silicon vias 181 can still ensure the normal operation of the electrical interconnects, improving the reliability and resilience of the entire chip package structure.

[0084] In one embodiment of this application, the distribution density of the second channel 132 is positively correlated with the power consumption of each region in the first chip unit 110 and the second chip unit 120.

[0085] In this embodiment, the distribution density of the second channel 132 is positively correlated with the power consumption of the first chip unit 110 and the second chip unit 120. That is, the higher the power consumption of the chip unit, the denser the distribution of the second channel 132. This design is a heat dissipation scheme based on the thermal distribution characteristics of the chip unit. During the operation of the chip, the power consumption of different functional units varies significantly. For example, the power consumption of functional units such as the CPU (Central Processing Unit) core, arithmetic unit, and memory controller is much higher than that of other auxiliary units. These high-power units generate a lot of heat and are prone to forming local hot spots. If the temperature of the hot spots is too high, it will lead to a decrease in chip performance and even permanent damage to the chip. If the heat dissipation liquid flow channel 130 adopts a uniform distribution design, it is impossible to accurately dissipate heat in hot spot areas, resulting in a waste of heat dissipation resources and low heat dissipation efficiency.

[0086] This embodiment correlates the distribution density of the second channels 132 with the chip power consumption. By setting more and denser second channels 132 in high-power hotspot areas, the contact area between the coolant and the area can be increased, thereby improving the coolant flow rate and achieving precise and efficient cooling of the hotspot areas. In low-power areas, the distribution density of the second channels 132 is appropriately reduced to avoid wasting heat dissipation resources and achieve efficient operation of the heat dissipation system.

[0087] Specifically, during the chip design phase, thermal simulation software can be used to simulate the thermal distribution of chip cells, determining the location and extent of high-power hotspots. Based on the simulation results, the distribution density of the second channel 132 is then designed. In hotspot areas, the spacing of the second channel 132 is reduced to 1 / 2 to 1 / 3 of the conventional spacing, while the depth of the second channel 132 can be increased to further improve heat dissipation efficiency. This differentiated distribution design effectively smooths the temperature gradient on the chip surface, controlling the maximum temperature difference within a certain range, improving the uniformity of chip temperature, and preventing localized overheating.

[0088] Furthermore, the distribution density of the second channel 132 can be flexibly adjusted according to the power consumption distribution characteristics of different types of chips, adapting to the heat dissipation requirements of various high-computing-power chips such as CPUs, GPUs (Graphics Processing Units), and AI (Artificial Intelligence) chips, significantly improving the versatility and adaptability of the chip packaging structure. At the same time, this distribution design does not require changes to the overall structure of the heat dissipation liquid flow channel 130; only the pattern of the photolithography mask needs to be adjusted, making it compatible with existing fabrication processes and facilitating mass production.

[0089] In an exemplary embodiment, the first channel may include a main distribution channel and a secondary channel, forming a coolant flow path of main distribution channel-secondary channel-secondary channel-(secondary channel)-main distribution channel. The secondary channel near the outlet chamber of the second channel may be selectively provided or omitted based on requirements. One main distribution channel may communicate with multiple secondary channels, and one secondary channel may communicate with multiple second channels. The second channels may also be referred to as capillary microgrooves.

[0090] The main distribution channel receives coolant, and the capillary micro-grooves are located in the area corresponding to the high-power functional units of the chip cell. The jet impact cavity (jet aperture array) is located above the main distribution channel, and the cavity has micro-holes to guide the coolant to the hot spot area of ​​the chip cell in the form of a jet.

[0091] Please refer to Figure 1 and Figure 3 In one embodiment of this application, the cover plate 140 is provided with a liquid inlet hole 141 and a liquid outlet hole 142. The liquid inlet hole 141 is connected to the liquid injection chamber 101, and the liquid outlet hole 142 is connected to the liquid outlet chamber 102.

[0092] In this embodiment, the cover plate 140 can be made of high-purity single-crystal silicon material, and its thickness is typically controlled between 200μm and 500μm. This ensures the mechanical strength of the cover plate 140 without increasing the overall thickness of the encapsulation structure. The liquid inlet 141 and liquid outlet 142 are fabricated using a deep silicon etching process. The diameter of the holes is adapted to the pipe interface of the external cooling system, and a reasonable hole size must be set to avoid excessive coolant flow resistance due to excessively small hole diameter.

[0093] The inlet port 141 is the entrance for coolant into the encapsulation structure. The external cooling system delivers low-temperature coolant to the filling chamber 101 through the inlet port 141, providing a continuous coolant supply to the heat dissipation liquid flow channel 130. The outlet port 142 is the outlet for coolant discharge. After heat exchange, the high-temperature coolant exits from the outlet chamber 102 through the outlet port 142, enters the external cooling system for cooling, and is then recycled. To improve the sealing of the interface, a copper metal layer can be electroplated onto the inner walls of the inlet port 141 and the outlet port 142. The copper metal layer can enhance the connection strength between the hole wall and the external pipeline, while preventing coolant leakage from the interface.

[0094] The cover plate 140 not only enables connection to an external cooling system but also provides a sealing protection for the internal components of the package structure, isolating them from external dust, moisture, and impurities, and preventing corrosion or short circuits in the chip's internal circuitry. Furthermore, the positions of the liquid inlet 141 and liquid outlet 142 can be flexibly adjusted according to the installation requirements of the package structure, adapting to different installation scenarios and improving the structure's versatility and practicality.

[0095] The external cooling system is a circuit system equipped with chip units, which can be used to control parameters such as the liquid flow rate, temperature, and flow rate of the coolant transmitted to the first channel through the liquid inlet.

[0096] Please continue to refer to Figure 1 and Figure 3 The chip packaging structure can be provided with multiple liquid inlet holes 141 and multiple liquid outlet holes 142, wherein the number of liquid inlet holes 141 and liquid outlet holes 142 can be set to be the same. Each liquid inlet hole 141 can be configured with a corresponding first liquid inlet channel, and each liquid outlet hole 142 can be configured with a corresponding first liquid outlet channel. One injection chamber can be provided with one or more first liquid inlet channels, and one outlet chamber can be provided with one or more first liquid outlet channels.

[0097] Based on this, one alternative implementation is provided in which at least two sets of first liquid inlet channels and first liquid outlet channels are symmetrically arranged in the orthographic projection of the plane where the first chip unit is located. Specifically, when the chip packaging structure has two first liquid inlet channels and two first liquid outlet channels, taking the plane where the first chip unit is located as a rectangle as an example, the first liquid inlet channel A1 can be located at the upper left corner of the rectangle, the first liquid outlet channel B1 at the lower left corner of the rectangle, the first liquid inlet channel A2 at the upper right corner of the rectangle, and the first liquid outlet channel B2 at the lower right corner of the rectangle. This arrangement allows for a sufficiently long path area between one set of first liquid inlet channels and the first liquid outlet channel, and also facilitates the fabrication of the relevant channels.

[0098] Another alternative implementation involves at least two first liquid inlet channels and at least two first liquid outlet channels symmetrically arranged in the orthographic projection of the plane containing the first chip unit. Specifically, in a chip package structure with two first liquid inlet channels and two first liquid outlet channels, taking a rectangular plane containing the first chip unit as an example, the first liquid inlet channel A1 can be located at the upper left corner of the rectangle, the first liquid outlet channel B1 at the lower left corner, the first liquid inlet channel A2 at the lower right corner, and the first liquid outlet channel B2 at the upper right corner. This arrangement allows for a sufficiently long path between the first liquid inlet channels and the first liquid outlet channels, and also facilitates the fabrication of the relevant channels.

[0099] Another alternative implementation involves symmetrically arranging multiple first liquid inlet channels and first liquid outlet channels in the orthographic projection of the plane containing the first chip unit. Specifically, in a chip packaging structure with two first liquid inlet channels and two first liquid outlet channels, taking a rectangular plane containing the first chip unit as an example, the first liquid inlet channel A1 can be located at the upper left corner of the rectangle, the first liquid outlet channel B1 at the lower right corner, the first liquid inlet channel A2 at the upper right corner, and the first liquid outlet channel B2 at the lower left corner. This arrangement allows for a sufficiently long path between the first liquid inlet channels and the first liquid outlet channels, and also facilitates the fabrication of the relevant channels.

[0100] like Figure 3 As shown, in one embodiment of this application, the first channel 131 is an annular channel, and both ends of the second channel 132 are connected to the first channel 131.

[0101] In this embodiment, the first channel 131 is designed as a ring channel, with both ends of multiple second channels 132 connected to the first channel 131. This ring structure design effectively optimizes the flow path of the coolant, improving the uniformity and efficiency of heat dissipation. The layout of the ring channel matches the contour of the chip unit, typically being square or circular. The center of the ring channel can coincide with the geometric center of the chip unit. This layout ensures that the coolant is evenly distributed from all positions of the ring channel to the second channels 132, avoiding uneven coolant supply. If a straight first channel 131 is used, there may be problems such as high coolant flow resistance and uneven flow distribution. The flow rate of the coolant differs significantly at both ends of the straight channel, resulting in inconsistent heat dissipation at both ends of the chip. The ring channel design effectively solves this problem, allowing the coolant to be evenly distributed 360° within the ring channel, ensuring that each second channel 132 receives a sufficient and uniform coolant supply.

[0102] Meanwhile, both ends of the second channel 132 are connected to the first channel 131, forming a bidirectional liquid inlet flow pattern. Coolant can flow in from both ends of the second channel 132 simultaneously, significantly increasing the flow rate and volume of coolant within the second channel 132 and enhancing convective heat transfer. Furthermore, the bidirectional liquid inlet design avoids dead zones within the second channel 132, ensuring that coolant flows through the entire area of ​​the second channel 132, achieving comprehensive cooling of the chip unit. The photolithography etching process for the annular channel is comparable in difficulty to that of a straight channel, requiring no additional process steps. Moreover, the annular channel structure is more stable and less prone to deformation due to structural stress. The annular channel design shortens the residence time of coolant within the heat dissipation liquid flow channel 130, ensuring the coolant remains at a low temperature and further improving heat transfer efficiency. Simultaneously, the annular channel also acts as a buffer, reducing pressure fluctuations in the coolant during flow and improving the stability of the heat dissipation system.

[0103] refer to Figure 4 , Figure 4 This is a schematic diagram illustrating the flow direction of coolant in a chip packaging structure provided in an embodiment of this application. Figure 4 The dashed arrows in the diagram indicate the direction of coolant flow. For example... Figure 1 and Figure 4 As shown, in one embodiment of this application, the liquid inlet 141 and the liquid outlet 142 are located at opposite ends of the first channel 131.

[0104] In this embodiment, the inlet hole 141 and the outlet hole 142 are located at opposite ends of the first channel 131. This arrangement effectively improves the flow efficiency of the coolant and enhances the heat dissipation effect. Figure 1 and Figure 4 As shown, the inlet hole 141 and outlet hole 142 are positioned at opposite ends, enabling the coolant to form a convection circulation within the first channel 131. After flowing into the injection chamber 101 from the inlet hole 141, the coolant flows along one end of the first channel 131 to the other, and finally exits through the outlet hole 142. This flow pattern effectively reduces the flow resistance of the coolant within the first channel 131, increases the flow velocity of the coolant, and ensures that the coolant in the heat dissipation fluid flow channel 130 is always in a state of rapid renewal, thereby enhancing the heat exchange effect.

[0105] If the inlet 141 and outlet 142 are located on the same side, a short circuit may occur in the first channel 131, causing some coolant to be discharged directly from the outlet 142 without flowing through the second channel 132, resulting in a significant reduction in heat dissipation efficiency. The arrangement at opposite ends avoids this short circuit, ensuring that the coolant flows through all the second channels 132, achieving comprehensive cooling of the chip unit. Simultaneously, this arrangement allows the temperature gradient of the coolant to be evenly distributed along the extension direction of the first channel 131, preventing localized overheating and further improving the uniformity of heat dissipation. The opposite arrangement of the inlet 141 and outlet 142 simplifies the connection of external piping, avoids pipe crossings, and reduces the difficulty of system integration. Furthermore, this arrangement reduces the mechanical stress of external piping on the packaging structure, improving its stability. The opposite arrangement of the inlet 141 and outlet 142 also improves the circulation efficiency of the coolant, shortens the circulation cycle, and ensures that the chip unit remains at a low temperature.

[0106] In addition, a heat dissipation method for chip packaging structure is provided, including: real-time monitoring of chip temperature distribution through an embedded temperature sensing unit; dynamic adjustment of coolant flow rate of each branch channel based on monitoring data; and inducing a phase change of coolant in capillary micro-grooves when needed by controlling at least one of coolant inlet temperature, system pressure, and flow regulation unit, so as to absorb more heat using latent heat.

[0107] For example, the heat dissipation method may specifically include the following steps:

[0108] System sensing steps: Real-time monitoring of temperature distribution within the chip unit using temperature sensing units distributed within the micro-trench heat dissipation layer;

[0109] Dynamic control steps: Based on the monitored temperature data, one or more hot spots are identified, and the coolant flow rate to the hot spots is adjusted through the flow regulation unit;

[0110] Synergistic heat dissipation steps: As the coolant flows through the capillary micro-grooves corresponding to the hot spot area, it absorbs heat through convection and phase change; and,

[0111] The overall heat dissipation intensity is controlled by adjusting the power of the micro-pump and the inlet temperature of the coolant.

[0112] Preferably, in the dynamic control step, a control algorithm based on fuzzy PID (Proportional-Integral-Derivative) is adopted to output the control signal by combining the temperature change rate and spatial gradient.

[0113] This heat dissipation method includes system sensing, dynamic regulation, and coordinated heat dissipation steps. By adjusting the flow distribution through real-time temperature data, it achieves precise and efficient cooling of internal hot spots.

[0114] For example, the intelligent controller pre-stores thermal characteristic parameters of different functional units of the chip. When the temperature sensor detects a sudden rise in the temperature of a certain processing core, the controller will immediately increase the opening of the flow control valve corresponding to that area and simultaneously increase the speed of the micro pump to ensure sufficient coolant supply, thereby achieving rapid temperature suppression.

[0115] In one embodiment of this application, a wafer is also provided, which includes the chip packaging structure of any of the above embodiments.

[0116] Wafer-level packaging enables mass production and efficient integration of chips. Using a single-crystal silicon wafer as the substrate, multiple chip package structures are simultaneously fabricated on the wafer through a series of semiconductor manufacturing processes such as photolithography, etching, and bonding. These package structures are arranged in an array on the wafer, with each package structure separated by dicing channels. The advantages of wafer-level packaging lie in its ability to achieve mass production of chips, significantly improving production efficiency, reducing the manufacturing cost per chip, and ensuring the performance consistency of each chip unit. This avoids performance fluctuations caused by individual differences in traditional packaging processes, thereby improving chip yield.

[0117] During wafer fabrication, all components of the chip packaging structure, including chip cells, redistribution silicon layers, silicon spacers, and heat dissipation liquid flow channels, are fabricated simultaneously using wafer-level processes. This eliminates the need to fabricate each component separately before assembly, simplifying the packaging process and shortening the production cycle. Furthermore, wafer-level packaging can further reduce chip size and increase integration, meeting the demands for miniaturized and high-density chips in fields such as artificial intelligence and high-performance computing.

[0118] Furthermore, the chip packaging structure on this wafer can share heat dissipation and interconnect systems, further improving system integration efficiency. Simultaneously, the wafer-level manufacturing process is compatible with existing semiconductor production lines, eliminating the need for significant additional equipment costs and facilitating large-scale deployment. Chips fabricated from this wafer offer advantages such as high heat dissipation efficiency, good temperature uniformity, compact structure, and stable performance, enabling long-term stable operation under high power density conditions, significantly improving chip reliability and lifespan. Moreover, this wafer allows for flexible adjustment of the chip packaging structure layout and parameters to meet the manufacturing needs of various high-performance chips, demonstrating promising application prospects.

[0119] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

[0120] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0121] Although preferred embodiments of the present application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the scope of protection of this application includes the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of this application.

[0122] This document uses specific examples to illustrate the chip packaging structure and wafer working principle and implementation method of this application. The above description of the embodiments is only for the purpose of helping to understand the specific settings and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation method and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

[0123] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip packaging structure, characterized in that, Includes a first chip unit and a second chip unit that are stacked together; A first groove is formed on the side of the first chip unit that contacts the second chip unit, and a second groove is formed on the side of the second chip unit that contacts the first chip unit. The first groove and the second groove cooperate to form a heat dissipation liquid flow channel. The heat dissipation liquid flow channel includes a first channel and multiple second channels. The first channel is connected to the liquid injection chamber, and the second channel is connected to the first channel. The distribution positions of the multiple second channels correspond to the heat-generating areas of the first chip unit and the second chip unit. The second chip unit has a heat dissipation liquid cavity on the side away from the first chip unit, and the heat dissipation liquid cavity is connected to the first channel.

2. The chip packaging structure according to claim 1, characterized in that, The injection chamber is connected to the first channel via a jet hole array; the diameter of any jet hole in the jet hole array is smaller than the diameter of the first channel.

3. The chip packaging structure according to claim 1, characterized in that, It also includes a temperature sensing unit and a flow regulation unit; The temperature sensing unit is integrated into at least one of the heating areas in the first chip unit and the second chip unit; The flow regulation unit is located within the heat dissipation liquid flow channel.

4. The chip packaging structure according to claim 1, characterized in that, The first channel includes at least one set of first inlet channels and first outlet channels, and the two ends of at least one second channel are respectively connected to one set of first inlet channels and first outlet channels; The first inlet channel is connected to the injection chamber, and the first outlet channel is connected to the outlet chamber; The heat dissipation liquid chamber is connected to the first liquid inlet channel and the first liquid outlet channel, respectively.

5. The chip packaging structure according to claim 4, characterized in that, At least two sets of the first liquid inlet channel and the first liquid outlet channel are symmetrically arranged in the orthographic projection of the plane where the first chip unit is located; or, At least two of the first liquid inlet channels and at least two of the first liquid outlet channels are symmetrically arranged in the orthographic projection of the plane containing the first chip unit; or, The multiple first liquid inlet channels and the first liquid outlet channels are symmetrically arranged in the orthographic projection of the plane where the first chip unit is located.

6. The chip packaging structure according to claim 1, characterized in that, It also includes a cover plate, a first wiring silicon layer, a second wiring silicon layer, and a third wiring silicon layer; The first redistribution silicon layer is disposed on the side of the first chip cell away from the second chip cell, and the cover plate is disposed on the side of the first redistribution silicon layer away from the first chip cell; The second redistribution silicon layer is disposed on the side of the second chip cell away from the first chip cell, and the third redistribution silicon layer is disposed on the side of the second redistribution silicon layer away from the second chip cell; The liquid injection chamber and the liquid outlet chamber are provided between the cover plate and the first redistribution silicon layer, and the heat dissipation liquid chamber is provided between the second redistribution silicon layer and the third redistribution silicon layer.

7. The chip packaging structure according to claim 6, characterized in that, It also includes a silicon spacer located between the first redistribution silicon layer and the second redistribution silicon layer. The silicon spacer, the first redistribution silicon layer, and the second redistribution silicon layer form a receiving cavity, and the first chip cell and the second chip cell are located within the receiving cavity.

8. The chip packaging structure according to claim 6, characterized in that, The cover plate is provided with an inlet hole and an outlet hole. The inlet hole is connected to the injection chamber, and the outlet hole is connected to the outlet chamber.

9. The chip packaging structure according to any one of claims 1 to 8, characterized in that, The distribution density of the second channel is positively correlated with the power consumption of each region in the first chip unit and the second chip unit.

10. A wafer, characterized in that, Includes the chip packaging structure as described in any one of claims 1 to 9.

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