Manufacturing method of semiconductor structure and semiconductor structure

Abstract

The invention provides a manufacturing method of a semiconductor structure and the semiconductor structure. The manufacturing method comprises the following steps: forming a first intermediate structure and a second intermediate structure; the first middle structure comprises a first carrier plate, a first electrical element located on one side of the first carrier plate, a first plastic packaging layer packaging the first electrical element and a conductive column. The second middle structure comprises a second carrier plate and a second electrical element mounted on one side of the second carrier plate; providing a first plastic package mold comprising a first sub-mold and a second sub-mold, wherein the first sub-mold is provided with a first accommodating cavity; the first middle structure is placed in the first containing cavity, the second middle structure is fixed to the second sub-mold, and the first containing cavity is filled with a plastic package material; the first sub-mold and the second sub-mold are closed, and the plastic package material forms a second plastic package layer; removing the mold and the second carrier plate, and forming a trace structure on one side, far away from the first plastic package layer, of the second plastic package layer; the trace structure is electrically connected to the electrode of the second electrical element and the conductive pillar, respectively.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] A semiconductor structure includes at least two stacked chip layers, and its fabrication process includes the following steps: First, a molding compound is fabricated, the molding compound including a first chip with exposed solder pads; then, a first redistribution layer electrically connected to the solder pads of the first chip is formed on the molding compound; then, a second chip is placed on the first redistribution layer with its solder pads away from the first redistribution layer; then, a molding compound encapsulating the second chip and the first redistribution layer is formed; then, a via is formed penetrating the molding compound, exposing a portion of the surface of the first redistribution layer; then, an electroplating process is used to form conductive pillars located within the vias and a second redistribution layer located on the molding compound, the second redistribution layer being electrically connected to the electrodes and conductive pillars of a second electrical component, respectively. This enables electrical connection between adjacent layers of electrical components.

[0003] In the above-mentioned fabrication process, when the depth of the via is large, the hole walls cannot be plated with conductive material during the electroplating process, which affects the yield of the semiconductor structure. Summary of the Invention

[0004] This application provides a method for manufacturing a semiconductor structure and a semiconductor structure.

[0005] A first aspect of this application provides a method for manufacturing a semiconductor structure, the method comprising:

[0006] A first intermediate structure and a second intermediate structure are formed; the first intermediate structure includes a first carrier plate, a molding compound structure located on one side of the first carrier plate, and a conductive post located on the side of the molding compound structure away from the first carrier plate; the molding compound structure includes a first electrical component and a first molding layer, the first molding layer at least encapsulating the side of the first electrical component; the conductive post is electrically connected to the electrode of the first electrical component; the second intermediate structure includes a second carrier plate and a second electrical component mounted on one side of the second carrier plate.

[0007] A first molding die is provided, the first molding die including a first sub-mold and a second sub-mold, the first sub-mold having a first receiving cavity;

[0008] The first intermediate structure is placed in the first receiving cavity, with the conductive post located on the side of the first carrier plate away from the bottom surface of the first receiving cavity. The second intermediate structure is fixed to the second sub-mold, and the first receiving cavity is filled with molding compound.

[0009] The first sub-mold and the second sub-mold are closed together, so that the second electrical component enters the molding compound in the first receiving cavity. The molding compound in the first receiving cavity forms a second molding layer that encapsulates the second electrical component and the conductive post.

[0010] Remove the first sub-mold, the second sub-mold, and the second carrier plate, and form a trace structure on the side of the second molding layer away from the first molding layer; the trace structure is electrically connected to the electrode of the second electrical component and the conductive post, respectively.

[0011] In one embodiment, the first intermediate structure further includes a first shielding structure, which is encapsulated by the first molding layer and surrounds the first electrical component; and / or,

[0012] The first intermediate structure also includes a metal block located between the encapsulation structure and the first carrier plate.

[0013] In one embodiment, when the first intermediate structure includes the first shielding structure and the metal block, the surface of the first shielding structure facing the metal block is connected to the metal block at all points.

[0014] In one embodiment, the molding structure further includes a first shielding structure, the first shielding structure being encapsulated by the first molding layer and disposed around the first electrical component; the process of forming the first intermediate structure includes:

[0015] A first shielding structure is formed on one side of the first carrier board; the first electrical component is mounted on the third carrier board;

[0016] A second molding die is provided, the second molding die including a third sub-mold and a fourth sub-mold, the third sub-mold being provided with a second receiving cavity;

[0017] The first carrier plate is placed in the second receiving cavity, with the first shielding structure located on the side of the first carrier plate away from the bottom surface of the second receiving cavity. The third carrier plate is fixed to the second sub-mold, and the second receiving cavity is filled with molding compound.

[0018] The third sub-mold and the fourth sub-mold are closed, so that the first electrical component enters the molding compound in the second receiving cavity, and the first electrical component is surrounded by the first shielding structure. The molding compound in the second receiving cavity forms a first molding layer. The first molding layer at least covers the side of the first electrical component and the side of the first shielding structure.

[0019] Remove the third sub-mold, the fourth sub-mold, and the third carrier plate;

[0020] The conductive post, which is electrically connected to the electrode of the first electrical component, is formed on the side of the first molding layer away from the first carrier plate.

[0021] In one embodiment, the first intermediate structure further includes a first shielding structure and a second shielding structure. The first shielding structure is encapsulated by the first molding layer and is disposed around the first electrical component. The second shielding structure is located on the side of the first molding layer away from the first carrier plate and surrounds the conductive post.

[0022] After the first sub-mold and the second sub-mold are closed, the second shielding structure enters the molding compound in the first receiving cavity, and the second shielding structure surrounds the second electrical component.

[0023] In one embodiment, the surface of the first shielding structure facing the second shielding structure is connected to the second shielding structure at all points.

[0024] In one embodiment, the first sub-mold is provided with a first magnetic element, and the first carrier plate is provided with a second magnetic element. At least one of the first magnetic element and the second magnetic element is a magnetic element that generates a magnetic field when energized, so that the other magnetic element is attracted by the magnetic field when energized; and / or,

[0025] The second sub-mold is provided with a third magnetic component, and the second carrier plate is provided with a fourth magnetic component. At least one of the third magnetic component and the fourth magnetic component is a magnetic component that can generate a magnetic field when energized, so that the other magnetic component is attracted in the magnetic field when energized.

[0026] In one embodiment, when the first sub-mold is provided with a first magnetic component and the first carrier plate is provided with a second magnetic component, the first magnetic component is a magnetic component that can generate a magnetic field when energized, and the second magnetic component is a magnetic component that can generate a magnetic field on its own or a magnetic component that can be magnetized in a magnetic field.

[0027] When the second sub-mold is provided with a third magnetic component and the second carrier plate is provided with a fourth magnetic component, the third magnetic component is a magnetic component that can generate a magnetic field when energized, and the fourth magnetic component is a magnetic component that can generate a magnetic field on its own or a magnetic component that can be magnetized in a magnetic field.

[0028] In one embodiment, both the first electrical component and the second electrical component include at least one of a chip and a passive device.

[0029] A second aspect of this application provides a semiconductor structure, the semiconductor structure comprising:

[0030] A molding compound structure; the molding compound structure includes a first electrical component, a first molding layer, and a first shielding structure, wherein the first molding layer at least encapsulates the side of the first electrical component and the side of the first shielding structure, and the first shielding structure surrounds the first electrical component;

[0031] A conductive post is located on one side of the encapsulated structure and is electrically connected to the electrode of the first electrical component;

[0032] The second electrical component is located on the side of the encapsulated structure facing the conductive post;

[0033] The second molding layer at least encapsulates the conductive post and the side surface of the second electrical component;

[0034] The trace structure is located on the side of the second encapsulation layer away from the encapsulation structure, and the trace structure is electrically connected to the electrode of the second electrical component and the conductive post, respectively.

[0035] In one embodiment, the semiconductor structure further includes a metal block located on the side of the molding compound structure away from the second electrical component, wherein the surfaces of the first shielding structure away from the second molding layer are all connected to the metal block; and / or,

[0036] The semiconductor structure further includes a second shielding structure located between the molding compound and the trace structure, the second shielding structure surrounding the second electrical component, and the second molding compound at least encapsulating the sides of the second shielding structure; the surface of the first shielding structure facing the second shielding structure is connected to the second shielding structure at all points; and / or

[0037] Both the first electrical component and the second electrical component include at least one of a chip and a passive device.

[0038] The main technical effects achieved by the embodiments of this application are:

[0039] The semiconductor structure manufacturing method and semiconductor structure provided in this application embodiment involve placing a first intermediate structure in the first receiving cavity of a first sub-mold, positioning the conductive pillar on the side of the first carrier plate away from the bottom surface of the first receiving cavity, and filling the first receiving cavity with molding compound. After the second sub-mold, on which the second intermediate structure is fixed, is closed with the first sub-mold, the molding compound in the first receiving cavity forms a second molding layer covering the conductive pillar and the second electrical component. The trace structure formed on the side of the second molding layer away from the first molding layer is electrically connected to the first electrical component through the conductive pillar, thereby realizing the electrical connection between the stacked first and second electrical components. Compared to the scheme of forming conductive pillars by electroplating through through-holes penetrating the second molding layer, since this application embodiment first forms the conductive pillars and then forms the second molding layer covering the conductive pillars, it avoids the problem of the through-hole surface not being able to be electroplated due to the excessive depth of the through-hole. The conductive pillars can ensure the electrical connection effect of the first and second electrical components, effectively improving the yield of the semiconductor structure. Attached Figure Description

[0040] Figure 1 This is a flowchart of a method for manufacturing a semiconductor structure provided in an exemplary embodiment of this application;

[0041] Figure 2 This is a cross-sectional view of the first intermediate structure provided in an exemplary embodiment of this application;

[0042] Figure 3 This is a cross-sectional view of the second intermediate structure provided in an exemplary embodiment of this application;

[0043] Figure 4 This is a cross-sectional view of the third intermediate structure provided in an exemplary embodiment of this application;

[0044] Figure 5 This is a cross-sectional view of the fourth intermediate structure provided in an exemplary embodiment of this application;

[0045] Figure 6 This is a partial cross-sectional view of the fifth intermediate structure provided in an exemplary embodiment of this application;

[0046] Figure 7 This is a partial cross-sectional view of the sixth intermediate structure provided in an exemplary embodiment of this application;

[0047] Figure 8 This is a partial cross-sectional view of a semiconductor structure provided in an exemplary embodiment of this application;

[0048] Figure 9 This is a partial cross-sectional view of the seventh intermediate structure provided in an exemplary embodiment of this application;

[0049] Figure 10This is a partial cross-sectional view of the eighth intermediate structure provided in an exemplary embodiment of this application;

[0050] Figure 11 This is a partial cross-sectional view of a semiconductor structure provided in another exemplary embodiment of this application;

[0051] Figure 12 This is a partial cross-sectional view of the first intermediate structure provided in another exemplary embodiment of this application;

[0052] Figure 13 yes Figure 12 The top view of the first intermediate structure shown;

[0053] Figure 14 This is a cross-sectional view of the ninth intermediate structure provided in an exemplary embodiment of this application;

[0054] Figure 15 This is a cross-sectional view of the tenth intermediate structure provided in an exemplary embodiment of this application;

[0055] Figure 16 This is a partial cross-sectional view of the eleventh intermediate structure provided in an exemplary embodiment of this application;

[0056] Figure 17 This is a partial cross-sectional view of the twelfth intermediate structure provided in an exemplary embodiment of this application;

[0057] Figure 18 This is a partial cross-sectional view of the thirteenth intermediate structure provided in an exemplary embodiment of this application;

[0058] Figure 19 This is a partial cross-sectional view of a semiconductor structure provided in another exemplary embodiment of this application. Specific Implementation

[0059] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0060] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0061] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0062] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0063] This application provides a method for manufacturing a semiconductor structure. For example... Figure 1 As shown, the manufacturing method includes the following steps 110 to 150.

[0064] In step 110, a first intermediate structure and a second intermediate structure are formed; the first intermediate structure includes a first carrier plate, a molding compound structure located on one side of the first carrier plate, and a conductive post located on the side of the molding compound structure away from the first carrier plate; the molding compound structure includes a first electrical component and a first molding layer, the first molding layer at least encapsulating the side of the first electrical component; the conductive post is electrically connected to the electrode of the first electrical component; the second intermediate structure includes a second carrier plate and a second electrical component mounted on one side of the second carrier plate.

[0065] In step 120, a first molding die is provided, the first molding die including a first sub-die and a second sub-die, the first sub-die having a first receiving cavity.

[0066] In step 130, the first intermediate structure is placed in the first receiving cavity, with the conductive post located on the side of the first carrier plate away from the bottom surface of the first receiving cavity. The second intermediate structure is fixed to the second sub-mold, and the first receiving cavity is filled with molding compound.

[0067] In step 140, the first sub-mold and the second sub-mold are closed, so that the second electrical component enters the encapsulating material in the first receiving cavity, and the encapsulating material in the first receiving cavity forms a second encapsulating layer that encapsulates the second electrical component and the conductive post.

[0068] In step 150, the first sub-mold, the second sub-mold, the first carrier plate, and the second carrier plate are removed, and a trace structure is formed on the side of the second molding layer away from the first molding layer; the trace structure is electrically connected to the electrode of the second electrical component and the conductive post, respectively.

[0069] The semiconductor structure manufacturing method provided in this application involves placing a first intermediate structure in the first receiving cavity of a first sub-mold, positioning the conductive pillar on the side of the first carrier plate away from the bottom surface of the first receiving cavity, and filling the first receiving cavity with molding compound. After the second sub-mold, on which the second intermediate structure is fixed, is closed with the first sub-mold, the molding compound in the first receiving cavity forms a second molding layer covering the conductive pillar and the second electrical component. The trace structure formed on the side of the second molding layer away from the first molding layer is electrically connected to the first electrical component through the conductive pillar, thereby realizing the electrical connection between the stacked first electrical component and the second electrical component. Compared to the approach of forming conductive pillars through a via penetrating the second molding compound layer using electroplating, this embodiment first forms the conductive pillar and then forms the second molding compound layer covering it. This avoids the problem of the via being too deep, preventing the surface of the via from being plated with metal. The conductive pillar ensures the electrical connection between the first and second electrical components, effectively improving the yield of the semiconductor structure. In contrast, the approach of forming conductive pillars through a via penetrating the second molding compound layer requires a larger diameter via to increase the probability of the via being plated. However, in this application, the cross-sectional area of ​​the conductive pillar can be set smaller, which helps to reduce the size of the semiconductor structure.

[0070] The following will describe in detail each step of the semiconductor structure manufacturing method provided in the embodiments of this application.

[0071] In step 110, a first intermediate structure and a second intermediate structure are formed; the first intermediate structure includes a first carrier plate, a molding compound structure located on one side of the first carrier plate, and a conductive post located on the side of the molding compound structure away from the first carrier plate; the molding compound structure includes a first electrical component and a first molding layer, the first molding layer at least encapsulating the side of the first electrical component; the conductive post is electrically connected to the electrode of the first electrical component; the second intermediate structure includes a second carrier plate and a second electrical component mounted on one side of the second carrier plate.

[0072] In one embodiment, both the first electrical component and the second electrical component include at least one of a chip and a passive device. The passive device includes at least one of an inductor, a resistor, and a capacitor. When the first electrical component and the second electrical component are chips, the chip's solder pads serve as electrodes; when the first electrical component and the second electrical component are passive devices, the pins of the passive device serve as electrodes.

[0073] In one embodiment, when both the first electrical component and the second electrical component are chips, this step can yield the following result: Figure 2 The first intermediate structure shown and Figure 3 The second intermediate structure shown.

[0074] like Figure 2 As shown, in the first intermediate structure, the first electrical component 101 is a chip 20. The chip 20 is attached to the first carrier board 11 via an adhesive layer 12. The front side of the chip 20 is away from the first carrier board 11. The first molding compound 61 is located on the first carrier board 11, encapsulating the side and the back side of the chip 20 opposite to the front side. The front side of the chip 20 has multiple solder pads. The front side of the chip 20 also has a protective layer 21 with multiple openings 211. Each opening 211 exposes at least a portion of the surface of a solder pad. The openings 211 correspond one-to-one with the solder pads of the chip 20, and each opening 211 exposes the corresponding solder pad.

[0075] like Figure 3 As shown, the second electrical component 102 of the second intermediate structure is a chip 40. The chip 40 is attached to the second carrier board 13 via an adhesive layer 14, with the front side of the chip 40 facing the second carrier board 13. The front side of the chip 40 has multiple solder pads. A protective layer 41 is provided on the front side of the chip 40, and the protective layer 41 has multiple openings 411, each opening 411 exposing at least a portion of the surface of a solder pad. Each opening 411 corresponds one-to-one with a solder pad on the chip 40, with each opening 411 exposing the corresponding solder pad.

[0076] In one embodiment, such as Figure 2 As shown, the first intermediate structure also includes a trace structure 32 located on the side of the first molding compound 61 away from the first substrate 11, and conductive posts 31 located on the side of the trace structure 32 away from the first molding compound 61. The trace structure 32 includes a plurality of first traces 321 and conductive portions 322 located within openings 211 of the protective layer 21. Each first trace 321 is electrically connected to the pads of the chip 20 through the conductive portions 322; each trace 321 may have at least one conductive post 31. Thus, the conductive posts 31 are electrically connected to the pads of the chip 20 through the first traces 321.

[0077] In some embodiments, the first intermediate structure may include a plurality of first electrical components 101, and the second intermediate structure may include a plurality of second electrical components 102.

[0078] In one embodiment, adhesive layers 12 and 14 may be made of easily peelable materials to facilitate the subsequent peeling of the first carrier plate 11 and the second carrier plate 13. For example, adhesive layers 12 and 14 may be made of heat-removable materials that can be de-adhesive by heating.

[0079] In one embodiment, the process of forming the first intermediate structure may include the following steps:

[0080] First, the chip 20 is mounted on the support plate with the front of the chip 20 facing the support plate.

[0081] Subsequently, a first molding compound 61 is formed, which encapsulates the side surface of the chip 20 and the back surface opposite to the front surface.

[0082] In one embodiment, before forming the first molding layer 61, some pretreatment steps, such as chemical cleaning or plasma cleaning, can be performed to remove impurities from the surface of the chip 20 so that the first molding layer 61 and the chip 20 can be more closely connected and there will be no delamination or cracking.

[0083] In one embodiment, the material of the first molding compound 61 can be a polymer resin, a resin composite material, or a polymer composite material. For example, the first molding compound 61 can be a resin with fillers, wherein the fillers can be inorganic particles. The first molding compound 61 can be formed by injection molding, compression molding, or transfer molding.

[0084] Subsequently, the support plate is removed to obtain a plastic encapsulation structure including the first plastic encapsulation layer 61 and the chip 20.

[0085] Subsequently, the encapsulated structure is attached to the first carrier plate 11 via the adhesive layer 12.

[0086] Subsequently, a trace structure 32 and a conductive post 31 located on the side of the trace structure 32 away from the first carrier plate 11 are formed on the surface of the encapsulated structure away from the first carrier plate 11.

[0087] In step 120, a first molding die is provided, the first molding die including a first sub-die and a second sub-die, the first sub-die having a first receiving cavity.

[0088] The first sub-mold is the lower mold, and the second sub-mold is the upper mold. This prevents the molding compound from flowing out of the first cavity after the first cavity of the first sub-mold is filled with molding compound.

[0089] In step 130, the first intermediate structure is placed in the first receiving cavity, with the conductive post located on the side of the first carrier plate away from the bottom surface of the first receiving cavity. The second intermediate structure is fixed to the second sub-mold, and the first receiving cavity is filled with molding compound.

[0090] This step yields the following result: Figure 4 The third intermediate structure shown. (As shown in the image) Figure 4 As shown, the first intermediate structure is placed in the first receiving cavity of the first sub-mold 51, and the conductive post 31 is located on the side of the first carrier plate 11 away from the bottom surface of the first receiving cavity; the second intermediate structure is fixed on the lower surface of the second sub-mold 52, facing the first intermediate structure, and the molding compound 621 covers the conductive post 31 and the trace layer 32.

[0091] In one embodiment, such as Figure 4As shown, a release film 512 is provided in the first receiving cavity, and the release film 512 is located between the inner surface of the first receiving cavity and the first intermediate structure. This facilitates the subsequent separation of the first intermediate structure and the first molding layer formed by the molding compound from the first sub-mold 51.

[0092] In one embodiment, such as Figure 4 As shown, the first sub-mold 51 is provided with a first magnetic element 511, and the first carrier plate is provided with a second magnetic element. At least one of the first and second magnetic elements is a magnetic element that generates a magnetic field when energized, so that the other magnetic element is attracted by the magnetic field when energized. Thus, when it is necessary to fix the first intermediate structure in the first receiving cavity of the first sub-mold, the magnetic element that generates a magnetic field when energized is energized among the first and second magnetic elements, so that the magnetic element generates a magnetic field, and the other magnetic element is attracted by the magnetic field, thereby allowing the first carrier plate of the first intermediate structure to be attracted to the first sub-mold. This prevents the first intermediate structure from moving in the first receiving cavity and also prevents the subsequent molding compound filled into the first receiving cavity from flowing into the gap between the bottom surface of the first carrier plate and the first sub-mold 52. After the first molding layer is formed, the energization of the magnetic element that generates a magnetic field when energized among the first and second magnetic elements can be stopped, and the attraction between the first and second magnetic elements disappears, allowing the first sub-mold to be separated from the first carrier plate. It should be noted that the release film 512 is very thin and has almost no effect on the attraction between the first and second magnetic elements.

[0093] In one embodiment, the first magnetic component is a magnetic component that generates a magnetic field when energized, and the second magnetic component is a magnetic component that generates its own magnetic field or can be magnetized in a magnetic field. This configuration eliminates the need to energize the second magnetic component, meaning the first carrier plate does not require connecting wires, simplifying its structure and facilitating subsequent process steps. Furthermore, the first sub-mold 51 is more convenient than the first carrier plate for setting up wires to energize the first magnetic component. In some embodiments, the first carrier plate is the second magnetic component, and the first carrier plate can be a permanent magnet, or its material can be iron, cobalt, nickel, or their alloys.

[0094] In one embodiment, such as Figure 4As shown, the second sub-mold 52 is provided with a third magnetic component 521, and the second carrier plate is provided with a fourth magnetic component. At least one of the third and fourth magnetic components is a magnetic component that generates a magnetic field when energized, so that when energized, the other magnetic component is subjected to an attractive or repulsive force in the magnetic field. Thus, when it is necessary to fix the second intermediate structure to the second sub-mold, energizing the magnetic component that generates a magnetic field among the third and fourth magnetic components causes it to generate a magnetic field, and the other magnetic component is subjected to an attractive force in the magnetic field. This allows the second carrier plate of the second intermediate structure to be attracted together with the second sub-mold, preventing the second intermediate structure from separating from the second sub-mold. After the first molding layer is formed, energizing the magnetic component that generates a magnetic field among the third and fourth magnetic components can be stopped, and the attractive force between the third and fourth magnetic components disappears, making it easier to separate the second sub-mold from the second carrier plate.

[0095] In one embodiment, the third magnetic component is a magnetic component that generates a magnetic field when energized, and the fourth magnetic component is a magnetic component that generates its own magnetic field or can be magnetized in a magnetic field. This configuration eliminates the need to energize the fourth magnetic component, meaning the second carrier plate does not require connecting wires, simplifying its structure. Furthermore, the second sub-mold 52 is more convenient than the second carrier plate for setting up wires to energize the third magnetic component. In some embodiments, the second carrier plate is the second magnetic component itself; the second carrier plate can be a permanent magnet, or its material can be iron, cobalt, nickel, or their alloys.

[0096] Figure 4 In the illustrated embodiment, the first sub-mold 51 is provided with a first magnetic element 511, and the second sub-mold 52 is provided with a third magnetic element 521. In other embodiments, only one of the first sub-mold 51 and the second sub-mold 52 may be provided with a magnetic element.

[0097] In one embodiment, the first carrier plate and the first sub-mold can also be fixed in other ways, such as the first carrier plate being fixed to the first sub-mold by an adhesive layer; the second carrier plate and the second sub-mold can also be fixed in other ways, such as the second carrier plate being fixed to the second sub-mold by an adhesive layer.

[0098] In step 140, the first sub-mold and the second sub-mold are closed, so that the second electrical component enters the encapsulating material in the first receiving cavity, and the encapsulating material in the first receiving cavity forms a second encapsulating layer that encapsulates the second electrical component and the conductive post.

[0099] This step yields the following result: Figure 5 The fourth intermediate structure is shown. (As shown in the image.) Figure 5As shown, the area of ​​the surface of the second carrier plate 13 facing the first carrier plate 11 is larger than the area of ​​the opening of the first receiving cavity; after the first sub-mold 51 and the second sub-mold 52 are closed, the second carrier plate 13 covers the opening of the first receiving cavity, and the edge region of the first intermediate structure abuts against the edge region of the first sub-mold 51 surrounding the first receiving cavity; the second molding layer 62 encapsulates the side and back of the chip 40, and encapsulates the conductive pillar 31; the surface of the conductive pillar 31 away from the first carrier plate 11 is covered by the second molding layer 62.

[0100] In one embodiment, after the first sub-mold 51 and the second sub-mold 52 are closed in step 140, the molding compound in the first receiving cavity can be cured to form a second molding layer 62.

[0101] In one embodiment, the amount of molding compound filled into the first receiving cavity can be determined by the thickness of the second molding layer to be formed as needed.

[0102] In step 150, the first sub-mold, the second sub-mold, and the second carrier plate are removed, and a trace structure is formed on the side of the second molding layer away from the first molding layer; the trace structure is electrically connected to the electrode of the second electrical component and the conductive post, respectively.

[0103] In this step, after removing the first sub-mold, the second sub-mold, and the second carrier plate, the fifth intermediate structure can be obtained. Figure 6 This is a partial structural diagram of the fifth intermediate structure. (See diagram below.) Figure 6 As shown, the opening 411 of the protective layer 41 of the chip 40 is exposed, thus exposing the solder pads of the chip 40. Figure 6 This is a partial structure of the fifth intermediate structure, which also includes a first carrier plate 11. Figure 6 Not shown in the image.

[0104] In one embodiment, the surface of the conductive post 31 away from the first substrate 11 is covered by a second molding compound 62. After removing the first sub-mold, the second sub-mold, and the second substrate, the method of manufacturing the semiconductor structure further includes the following steps: forming a plurality of openings in the second molding compound on the side of the conductive post away from the first molding compound, each opening exposing at least a portion of the surface of a conductive post away from the first molding compound.

[0105] This step yields the following result: Figure 7 The sixth intermediate structure is shown. (As shown in the image.) Figure 7 As shown, the second molding layer 62 forms openings 621 that correspond one-to-one with the conductive pillars 31, and each opening 621 exposes the portion of the corresponding conductive pillar 31 that is away from the first molding layer 61.

[0106] In one embodiment, step 150 can yield the following: Figure 8 The semiconductor structure shown. Figure 8 As shown, the trace structure 35 includes multiple traces 351, a conductive portion 352 located in the opening 411 of the protective layer 41, and a conductive structure 71 located in the opening 621. Each second trace 351 is electrically connected to the pad of the chip 40 through the conductive portion 352, and is electrically connected to the conductive post 31 through the conductive structure 71.

[0107] In one embodiment, the semiconductor structure further includes a conductive ball located on the side of trace 351 away from the second molding layer 62. The conductive ball facilitates soldering of the semiconductor structure to other structures.

[0108] In one embodiment, the semiconductor structure includes three or more layers of stacked electrical components. After step 150, the method for manufacturing the semiconductor structure further includes steps 160 and 170:

[0109] In step 160, a conductive pillar is formed on the side of the uppermost trace structure away from the first molding layer.

[0110] This step yields the following result: Figure 9 The seventh intermediate structure is shown. (As shown in the image.) Figure 9 As shown, each trace 351 may have at least one conductive post 34. Thus, the conductive post 34 is electrically connected to the pads of the chip 40 through the second trace 351.

[0111] In step 170, electrical components are stacked on the intermediate structure obtained in the previous step using a mold.

[0112] The specific process of this step is similar to that of steps 120 to 150, and will not be repeated here.

[0113] In step 180, a trace structure is formed on the surface of the semiconductor structure obtained in the previous step away from the first molding layer. The trace structure includes a plurality of third trace layers, each of which is electrically connected to the electrode of an adjacent electrical component.

[0114] Steps 160 to 180 can be repeated to finally obtain an eighth intermediate structure that includes electrical components arranged in multiple layers.

[0115] In one embodiment, when the final eighth intermediate structure comprises a four-layer stacked chip, the eighth intermediate structure is as follows: Figure 10As shown. The semiconductor structure includes chips 10, 40, 50, and 60 stacked sequentially; the semiconductor structure also includes a first molding compound 61 encapsulating chip 10, a second molding compound 62 encapsulating chip 40, a third molding compound 63 encapsulating chip 50, and a fourth molding compound 64 encapsulating chip 60; the semiconductor structure also includes a trace layer 32 located between the first molding compound 61 and the second molding compound 62, a trace layer 35 located between the second molding compound 62 and the third molding compound 63, a trace layer 37 located between the third molding compound 63 and the fourth molding compound 64, a trace layer 38 located on the side of the fourth molding compound 64 away from the first molding compound 61, a conductive post 31 located on the side of the trace layer 32 away from the first molding compound 61 and electrically connected to the trace layer 32, and a conductive post 31 located on the side of the trace layer 35 away from the second molding compound 62 and electrically connected to the trace layer 32. The trace layer 35 includes a conductive post 34 electrically connected to the third molding compound 63, and a conductive post 36 located on the side of the trace layer 37 away from the third molding compound 63 and electrically connected to the trace layer 37. The second molding compound 62 encapsulates the conductive post 31, the third molding compound 63 encapsulates the conductive post 34, and the fourth molding compound 64 encapsulates the conductive post 36. The first trace 321 of the trace layer 32 is electrically connected to the pads of the chip 20 via a conductive portion 372. The second trace 351 of the trace layer 35 is electrically connected to the pads of the chip 40 via a conductive portion 352 and to the conductive post 31 via a conductive structure 71. The third trace 371 of the trace layer 37 is electrically connected to the pads of the chip 50 via a conductive portion 372 and to the conductive post 34 via a conductive structure 72. The fourth trace 381 of the trace layer 38 is electrically connected to the pads of the chip 60 via a conductive portion 382 and to the conductive post 36 via a conductive structure 73. This semiconductor structure enables electrical connections between the various chip layers.

[0116] In one embodiment, the method for manufacturing the semiconductor structure further includes the following steps: forming an insulating layer covering the uppermost trace layer, and forming a plurality of vias on the insulating layer, each via exposing a portion of the surface of a trace; forming a conductive ball within each via.

[0117] This step yields the following result: Figure 11 The semiconductor structure shown. Figure 11 As shown, the insulating layer 65 covers the trace layer 38, and each through-hole of the insulating layer 65 has a conductive ball 81 electrically connected to the trace 381. The conductive ball can be made of solder, such as tin or nickel-gold.

[0118] In one embodiment, the method for manufacturing the semiconductor structure further includes: cutting the obtained semiconductor structure to obtain multiple semiconductor substructures, wherein the number of electrical components encapsulated by each molding layer in the semiconductor substructure may be one. In other embodiments, the number of electrical components encapsulated by at least one molding layer in the semiconductor substructure is two or more.

[0119] This application also provides another method for manufacturing a semiconductor structure. The following only describes the differences between this method and the semiconductor structure manufacturing method described in the above embodiments; similarities will not be repeated.

[0120] Figure 12 and Figure 13 This is a schematic diagram of the first intermediate structure in this embodiment. Figure 12 and Figure 13 As shown, the first intermediate structure further includes a first shielding structure 92, which is encapsulated by the first molding layer 61 and is disposed around the first electrical component 101. Figure 12 The first electrical component 101 shown is the chip 20. By providing a first shielding structure 92 surrounding the first electrical component 101, the first shielding structure 92 can improve the electromagnetic interference experienced by the first electrical component 101, which helps to improve the performance of the semiconductor structure.

[0121] In one embodiment, the material of the first shielding structure 92 may be a metal, such as copper.

[0122] In one embodiment, such as Figure 12 As shown, the first intermediate structure also includes a metal block 91 located between the encapsulation structure and the first carrier plate 11. By setting the metal block 91, the heat dissipation performance of the final semiconductor structure can be improved; and the metal block 91 can also shield electromagnetic interference, further improving the performance of the semiconductor structure. The orthographic projection of the first electrical component 101 onto the plane of the surface of the metal block 91 facing the first electrical component 101 can all fall on the metal block 91, thus the metal block 91 can effectively shield electromagnetic signals from interfering with the first electrical component 101.

[0123] In one embodiment, such as Figure 12 As shown, the first intermediate structure further includes a fifth molding compound 66, which is located on the side of the first molding compound 61 away from the conductive pillar 31. The fifth molding compound 66 encapsulates the metal block 91, and the surface of the metal block 91 away from the conductive pillar 31 is flush with the surface of the fifth molding compound 66 away from the conductive pillar 31. With this configuration, in the final semiconductor structure, the surface of the metal block 91 away from the first molding compound 61 is exposed, which can improve the heat dissipation performance of the semiconductor structure.

[0124] In one embodiment, such as Figure 12 As shown, when the first intermediate structure includes the first shielding structure 92 and the metal block 91, the surfaces of the first shielding structure 92 facing the metal block 91 are all connected to the metal block 91. With this configuration, there is no gap between the first shielding structure 92 and the metal block 91, which improves the shielding effect against electromagnetic interference.

[0125] In one embodiment, forming Figure 12 and Figure 13 The first intermediate structure shown may include the following steps:

[0126] First, a first shielding structure is formed on one side of the first carrier board; then the first electrical component is mounted on the third carrier board.

[0127] When the first electrical component is a chip, this step can yield the following result: Figure 14 The ninth intermediate structure shown and as follows Figure 15 The tenth intermediate structure is shown. (As shown in the image.) Figure 14 As shown, the ninth intermediate structure also includes a metal block 91 and a fifth molding layer 66; the ninth intermediate structure may include multiple metal blocks 91, each metal block 91 having a shielding structure 92 formed on it. Figure 15 As shown, the chip 20 is attached to the third carrier board 15 via the adhesive layer 16, and the front side of the chip 20 faces the third carrier board 15.

[0128] In one embodiment, Figure 14 The formation process of the ninth intermediate structure shown is as follows: First, the metal block 91 is attached to the first carrier plate 11 through the adhesive layer 12; then, the fifth plastic sealing layer 66 covering the side of the metal block 91 is formed; then, the shielding structure 92 is formed on the metal block 91.

[0129] Subsequently, a second molding die is provided, the second molding die including a third sub-die and a fourth sub-die, the third sub-die being provided with a second receiving cavity.

[0130] Subsequently, the first carrier plate is placed in the second receiving cavity, with the first shielding structure located on the side of the first carrier plate away from the bottom surface of the second receiving cavity. The third carrier plate is then fixed to the second sub-mold, and the second receiving cavity is filled with molding compound.

[0131] This step yields the following result: Figure 16 The eleventh intermediate structure is shown. (See example...) Figure 16 As shown, the ninth intermediate structure is placed in the second receiving cavity of the third sub-mold 53, and the first shielding structure 92 is located on the side of the first carrier plate 11 away from the bottom surface of the second receiving cavity; the tenth intermediate structure is fixed on the lower surface of the fourth sub-mold 54, facing the ninth intermediate structure; the molding compound 611 covers the first shielding structure 92; a release film 632 is provided between the ninth intermediate structure and the inner surface of the second receiving cavity.

[0132] In one embodiment, such as Figure 16As shown, the third sub-mold 53 is provided with a fifth magnetic component 531, and the first carrier plate 11 is provided with a sixth magnetic component. At least one of the fifth and sixth magnetic components is a magnetic component that can generate a magnetic field when energized, so that the other magnetic component is subjected to an attractive or repulsive force in the magnetic field when energized. The detailed description and beneficial effects of the fifth and sixth magnetic components are similar to those of the first and second magnetic components, and will not be repeated here.

[0133] In one embodiment, such as Figure 16 As shown, the fourth sub-mold 54 is provided with a seventh magnetic component 541, and the third carrier plate 15 is provided with an eighth magnetic component. At least one of the seventh and eighth magnetic components is a magnetic component that can generate a magnetic field when energized, so that the other magnetic component is subjected to an attractive or repulsive force in the magnetic field when energized. The detailed description and beneficial effects of the seventh and eighth magnetic components are similar to those of the third and fourth magnetic components, and will not be repeated here.

[0134] Subsequently, the third sub-mold and the fourth sub-mold are closed, allowing the first electrical component to enter the molding compound in the second receiving cavity, and the first electrical component is surrounded by the first shielding structure. The molding compound in the second receiving cavity forms a first molding layer; the first molding layer at least covers the side of the first electrical component and the side of the first shielding structure.

[0135] This step yields the following result: Figure 17 The twelfth intermediate structure shown. (As shown) Figure 17 As shown, the area of ​​the surface of the third carrier plate 15 facing the first carrier plate 11 is larger than the area of ​​the opening of the second receiving cavity; after the third sub-mold 53 and the fourth sub-mold 54 are molded together, the third carrier plate 15 covers the opening of the second receiving cavity, and the edge area of ​​the tenth intermediate structure abuts against the edge area of ​​the third sub-mold 53 surrounding the second receiving cavity; the chip 20 enters the molding compound in the second receiving cavity, and the molding compound and the adhesive layer 16 contact the area opposite to the second receiving cavity, the molding compound in the second receiving cavity forms the first molding layer 61, the first molding layer 61 encapsulates the side and back of the chip 20, and encapsulates the first shielding structure 92; the surface of the first shielding structure 92 away from the first carrier plate 11 is covered by the first molding layer 61.

[0136] Subsequently, the third sub-mold, the fourth sub-mold, and the third carrier plate are removed.

[0137] This step yields the thirteenth intermediate structure. Figure 18 This is a partial structural diagram of the thirteenth intermediate structure. (See diagram below.) Figure 18 As shown, the opening 211 of the protective layer 21 of chip 20 is exposed, thus exposing the solder pads of chip 20. Figure 18The thirteenth intermediate structure shown also includes a first carrier plate 11. Figure 18 Not shown in the image.

[0138] In one embodiment, after removing the third sub-mold, the fourth sub-mold, and the third carrier plate, the method for manufacturing the semiconductor structure further includes the following steps: forming an opening in the first molding layer on the side of the first shielding structure away from the metal block, the opening exposing at least a portion of the surface of the first shielding structure. The opening may be annular. A conductive connection may be provided within the opening to connect the first shielding structure to the second shielding structure.

[0139] Subsequently, the conductive post, which is electrically connected to the electrode of the first electrical component, is formed on the first molding layer.

[0140] This step yields the following result: Figure 12 and Figure 13 The first intermediate structure shown. (As shown) Figure 12 and Figure 13 As shown, the first intermediate structure also includes a second shielding structure 93. Each first trace 321 and each conductive post 32 is surrounded by the second shielding structure 93, which is connected to the first shielding structure via a conductive connection 97. In step 140, after the first sub-mold and the second sub-mold are closed, the second shielding structure 93 enters the molding compound in the first receiving cavity and surrounds the second electrical component. Thus, the second shielding structure 93 can shield the side of the second electrical component from electromagnetic interference.

[0141] In one embodiment, the surface of the first shielding structure 92 facing the second shielding structure 93 is connected to the second shielding structure 93 at all points, that is, the conductive connection portion 97 is annular. This arrangement eliminates gaps between the first and second shielding structures, improving the shielding effect against electromagnetic interference and further enhancing the performance of the semiconductor structure.

[0142] In this embodiment, after repeating steps 160 to 180, an insulating layer and conductive spheres are formed on the uppermost trace layer, resulting in the final product as shown below. Figure 19 The semiconductor structure shown. Figure 19As shown, each molding layer encapsulates a shielding structure. Specifically, the first molding layer 61 encapsulates the first shielding structure 92, the second molding layer 62 encapsulates the second shielding structure 93, the third molding layer 63 encapsulates the third shielding structure 94, and the fourth molding layer 64 encapsulates the fourth shielding structure 95. An insulating layer encapsulates the fifth shielding structure 96. The first shielding structure 92 and the second shielding structure 93 are connected by a conductive connection 97, the second shielding structure 93 and the third shielding structure 94 are connected by a conductive connection 98, the third shielding structure 94 and the fourth shielding structure 95 are connected by a conductive connection 991, and the fourth shielding structure 95 and the fifth shielding structure 96 are connected by a conductive connection 992. This effectively improves the electromagnetic interference shielding performance of the semiconductor structure.

[0143] This application also provides a semiconductor structure. For example... Figure 19 As shown, the semiconductor structure includes a molding compound, conductive pillars 31, a second electrical component 102, a second molding compound layer 62, and a trace structure 35.

[0144] The encapsulated structure includes a first electrical component 101, a first encapsulation layer 61, and a first shielding structure 92. The first encapsulation layer 61 at least encapsulates the side surface of the first electrical component 101 and the side surface of the first shielding structure 92, and the first shielding structure 92 surrounds the first electrical component 101. A conductive post 31 is located on one side of the encapsulation structure and is electrically connected to the electrode of the first electrical component 101. A second electrical component 102 is located on the side of the encapsulation structure facing the conductive post 31. The second encapsulation layer 62 at least encapsulates the conductive post 31 and the side surface of the second electrical component 102. A trace structure 35 is located on the side of the second encapsulation layer 62 away from the encapsulation structure, and the trace structure 35 is electrically connected to both the electrode of the second electrical component 102 and the conductive post 31.

[0145] In one embodiment, such as Figure 19 As shown, the semiconductor structure also includes a metal block 91 located on the side of the molding compound away from the second electrical component 102, and the surface of the first shielding structure 92 away from the second molding compound 62 is connected to the metal block 91 at various points.

[0146] In one embodiment, such as Figure 19 As shown, the semiconductor structure further includes a second shielding structure 93 located between the molding structure and the trace structure 35, the second shielding structure 93 surrounding the second electrical component 102; the surface of the first shielding structure 92 facing the second shielding structure 93 is connected to the second shielding structure 93 at all points.

[0147] In one embodiment, such as Figure 19As shown, both the first electrical component 101 and the second electrical component 102 include at least one of a chip and a passive device.

[0148] The embodiments of the semiconductor structure provided in this application and the embodiments of the semiconductor structure manufacturing method belong to the same inventive concept. The relevant details and beneficial effects can be referred to each other, and will not be repeated here.

[0149] It should be noted that the cross-sectional views in the embodiments of this application are all cross-sectional views obtained by cutting the corresponding three-dimensional structure along the stacking direction of the film layers.

[0150] It should be noted that the dimensions of layers and regions may be exaggerated in the accompanying drawings for clarity. Furthermore, it is understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or there may be intermediate layers. Additionally, it is understood that when an element or layer is referred to as being "below" another element or layer, it can be directly below the other element, or there may be more than one intermediate layer or element. Furthermore, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or two elements, or there may be more than one intermediate layer or element. Similar reference numerals throughout indicate similar elements.

[0151] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, The manufacturing method includes: A first intermediate structure and a second intermediate structure are formed; the first intermediate structure includes a first carrier plate, a molding compound structure located on one side of the first carrier plate, and a conductive post located on the side of the molding compound structure away from the first carrier plate; the molding compound structure includes a first electrical component and a first molding layer, the first molding layer at least encapsulating the side of the first electrical component; the conductive post is electrically connected to the electrode of the first electrical component; the second intermediate structure includes a second carrier plate and a second electrical component mounted on one side of the second carrier plate. A first molding die is provided, the first molding die including a first sub-mold and a second sub-mold, the first sub-mold having a first receiving cavity; The first intermediate structure is placed in the first receiving cavity, with the conductive post located on the side of the first carrier plate away from the bottom surface of the first receiving cavity. The second intermediate structure is fixed to the second sub-mold, and the first receiving cavity is filled with molding compound. The first sub-mold and the second sub-mold are closed together, so that the second electrical component enters the molding compound in the first receiving cavity. The molding compound in the first receiving cavity forms a second molding layer that encapsulates the second electrical component and the conductive post. Remove the first sub-mold, the second sub-mold, and the second carrier plate, and form a trace structure on the side of the second molding layer away from the first molding layer; the trace structure is electrically connected to the electrode of the second electrical component and the conductive post, respectively.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The first intermediate structure further includes a first shielding structure, which is encapsulated by the first molding layer and surrounds the first electrical component; and / or, The first intermediate structure also includes a metal block located between the encapsulation structure and the first carrier plate.

3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, When the first intermediate structure includes the first shielding structure and the metal block, the surface of the first shielding structure facing the metal block is connected to the metal block at all points.

4. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The encapsulation structure further includes a first shielding structure, which is encapsulated by the first encapsulation layer and surrounds the first electrical component; the process of forming the first intermediate structure includes: A first shielding structure is formed on one side of the first carrier board; the first electrical component is mounted on the third carrier board; A second molding die is provided, the second molding die including a third sub-mold and a fourth sub-mold, the third sub-mold being provided with a second receiving cavity; The first carrier plate is placed in the second receiving cavity, with the first shielding structure located on the side of the first carrier plate away from the bottom surface of the second receiving cavity. The third carrier plate is fixed to the second sub-mold, and the second receiving cavity is filled with molding compound. The third sub-mold and the fourth sub-mold are closed, so that the first electrical component enters the molding compound in the second receiving cavity, and the first electrical component is surrounded by the first shielding structure. The molding compound in the second receiving cavity forms a first molding layer. The first molding layer at least covers the side of the first electrical component and the side of the first shielding structure. Remove the third sub-mold, the fourth sub-mold, and the third carrier plate; The conductive post, which is electrically connected to the electrode of the first electrical component, is formed on the side of the first molding layer away from the first carrier plate.

5. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The first intermediate structure further includes a first shielding structure and a second shielding structure. The first shielding structure is encapsulated by the first molding layer and is disposed around the first electrical component. The second shielding structure is located on the side of the first molding layer away from the first carrier plate and surrounds the conductive post. After the first sub-mold and the second sub-mold are closed, the second shielding structure enters the molding compound in the first receiving cavity, and the second shielding structure surrounds the second electrical component.

6. The method for manufacturing a semiconductor structure according to claim 5, characterized in that, The surface of the first shielding structure facing the second shielding structure is connected to the second shielding structure at all points.

7. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The first sub-mold is provided with a first magnetic component, and the first carrier plate is provided with a second magnetic component. At least one of the first and second magnetic components is a magnetic component that generates a magnetic field when energized, so that the other magnetic component is attracted by an attraction force in the magnetic field when energized; and / or, The second sub-mold is provided with a third magnetic component, and the second carrier plate is provided with a fourth magnetic component. At least one of the third magnetic component and the fourth magnetic component is a magnetic component that can generate a magnetic field when energized, so that the other magnetic component is attracted in the magnetic field when energized.

8. The method for manufacturing a semiconductor structure according to claim 7, characterized in that, When the first sub-mold is provided with a first magnetic component and the first carrier plate is provided with a second magnetic component, the first magnetic component is a magnetic component that can generate a magnetic field when energized, and the second magnetic component is a magnetic component that can generate a magnetic field on its own or a magnetic component that can be magnetized in a magnetic field. When the second sub-mold is provided with a third magnetic component and the second carrier plate is provided with a fourth magnetic component, the third magnetic component is a magnetic component that can generate a magnetic field when energized, and the fourth magnetic component is a magnetic component that can generate a magnetic field on its own or a magnetic component that can be magnetized in a magnetic field.

9. A method for manufacturing a semiconductor structure according to any one of claims 1 to 8, characterized in that, Both the first electrical component and the second electrical component include at least one of a chip and a passive device.

10. A semiconductor structure, characterized in that, The semiconductor structure includes: A molding compound structure; the molding compound structure includes a first electrical component, a first molding layer, and a first shielding structure, wherein the first molding layer at least encapsulates the side of the first electrical component and the side of the first shielding structure, and the first shielding structure surrounds the first electrical component; A conductive post is located on one side of the encapsulated structure and is electrically connected to the electrode of the first electrical component; The second electrical component is located on the side of the encapsulated structure facing the conductive post; The second molding layer at least encapsulates the conductive post and the side surface of the second electrical component; The trace structure is located on the side of the second encapsulation layer away from the encapsulation structure, and the trace structure is electrically connected to the electrode of the second electrical component and the conductive post, respectively.

11. The semiconductor structure according to claim 10, characterized in that, The semiconductor structure further includes a metal block located on the side of the molding compound away from the second electrical component, and the surfaces of the first shielding structure away from the second molding layer are all connected to the metal block; and / or, The semiconductor structure further includes a second shielding structure located between the molding compound and the trace structure, the second shielding structure surrounding the second electrical component, and the second molding compound at least encapsulating the sides of the second shielding structure; the surface of the first shielding structure facing the second shielding structure is connected to the second shielding structure at all points; and / or Both the first electrical component and the second electrical component include at least one of a chip and a passive device.

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