Power module packaging structure based on lamination copper clamp interconnection

Abstract

The invention relates to a power module packaging structure based on lamination copper clamp interconnection, and belongs to the technical field of power module packaging. The power module comprises an insulating substrate, a metal layer, a power terminal, a signal terminal, a copper clamp and a chip. Wherein the metal layer is arranged on the surface of the insulating substrate, and the power terminal, the signal terminal, the copper clamp and the chip are all arranged on the insulating substrate and are electrically connected with the metal layer. The chip adopts a left-right and up-down symmetrical layout, and uses four direct-current positive terminals and two direct-current negative terminals, so that more current loops are provided. A plurality of copper clamps with different structures are used for replacing a traditional bonding wire to electrically connect the chip and the metal layer, and the copper clamps are arranged in a laminated manner, so that the parasitic inductance of the power module can be reduced, and the stability is improved. And meanwhile, the copper clamp and the metal layer are slotted, so that the length of a power loop of each chip can be balanced, and the current sharing performance of the power module is improved.

Description

Technical Field

[0001] This invention belongs to the field of power module packaging technology, and relates to a power module packaging structure based on stacked copper clip interconnection. Background Technology

[0002] With the widespread application and rapid development of power devices, silicon carbide (SiC) power semiconductor materials have become an ideal choice to overcome the limitations of traditional silicon-based devices due to their excellent electrical and thermal properties. At the same time, SiC power semiconductor devices have significant advantages such as high blocking voltage, low on-resistance, high switching frequency and low switching loss. However, multiple SiC chips are often connected in parallel in power modules to meet high power requirements. In order to fully utilize the performance of SiC devices, this poses a huge challenge to the reliability of power module packaging.

[0003] Wire bonding technology is widely used in power modules due to its low cost and high maturity. However, it introduces numerous parasitic parameters, resulting in high parasitic inductance and increased switching losses. Furthermore, in parallel applications of multiple SiC chips, the asymmetrical chip layout and unequal power loop lengths cause differences in parasitic inductance, leading to varying currents flowing through each chip and impacting module reliability. Therefore, reducing parasitic inductance and improving current sharing performance are paramount for enhancing power module package reliability. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a power module packaging structure based on stacked copper clip interconnection, which solves the problems of excessive switching losses and unbalanced junction temperature caused by excessive parasitic inductance and chip current imbalance in the prior art, so as to improve the overall performance and reliability of the power module.

[0005] To achieve the above objectives, the present invention provides the following technical solution: A semiconductor power module packaging structure includes an insulating substrate, a metal layer, power terminals, signal terminals, copper clips, and a chip. The metal layer is disposed on the surface of the insulating substrate, and the power terminals, signal terminals, copper clips, and chip are all disposed on the insulating substrate and electrically connected to the metal layer.

[0006] Multiple chips are disposed on an insulating substrate. Half of the chips are connected in parallel to form an upper bridge, and the other half of the chips are connected in parallel to form a lower bridge. The upper bridge chips are symmetrically distributed in the upper half of the insulating substrate, and the lower bridge chips are symmetrically distributed in the lower half of the insulating substrate.

[0007] The power terminals include a first DC positive terminal, a second DC positive terminal, a third DC positive terminal, a fourth DC positive terminal, a first DC negative terminal, a second DC negative terminal, and an AC terminal. The DC terminals and AC terminals are respectively disposed on opposite sides of the insulating substrate. The first DC positive terminal (1) and the second DC positive terminal (3) are respectively disposed on both sides of the first DC negative terminal (2), forming a current loop; the third DC positive terminal (4) and the fourth DC positive terminal (6) are respectively disposed on both sides of the second DC negative terminal (5), forming another current loop.

[0008] The copper clips include the first copper clip, the second copper clip, the third copper clip, the fourth copper clip, the fifth copper clip, the sixth copper clip, the seventh copper clip, and the eighth copper clip.

[0009] The first and second DC positive terminals are connected to the drain of one side of the chip in the upper bridge chip via the second and eighth copper clips, respectively. The third and fourth DC positive terminals are connected to the drain of the other side of the chip in the upper bridge chip via the first and seventh copper clips, respectively. The source of one side of the chip in the upper bridge chip is connected to the AC terminal via the third copper clip, and the source of the other side of the chip in the upper bridge chip is connected to the AC terminal via the fourth copper clip. The AC terminal is connected to the drain of all chips in the lower bridge chip. The source of one side of the chip in the lower bridge chip is connected to the second DC negative terminal via the fifth copper clip, and the source of the other side of the chip in the lower bridge chip is connected to the first DC negative terminal via the sixth copper clip.

[0010] Furthermore, the first and second copper clips have the same structure, the third and fourth copper clips have the same structure, the fifth and sixth copper clips have the same structure, and the seventh and eighth copper clips have the same structure.

[0011] The first and second copper clips are respectively located below the third and fourth copper clips, in the first layer; the fifth and sixth copper clips are at the same height as the third and fourth copper clips, in the second layer; and the seventh and eighth copper clips are located above the fifth and sixth copper clips, in the third layer.

[0012] Furthermore, the signal terminals include an upper bridge drain lead-out terminal, a first gate drive signal lead-out terminal, and a first Kelvin source lead-out terminal disposed on one side of the AC terminal, and a second gate drive signal lead-out terminal, a second Kelvin source lead-out terminal, a first temperature sensing pin, and a second temperature sensing pin disposed on the other side of the AC terminal.

[0013] Furthermore, the upper bridge drain terminal (14) is connected to the drain of the upper bridge chip, the first gate drive signal terminal is connected to the gate of the upper bridge chip, and the first Kelvin source terminal is connected to the source of the upper bridge chip; the second gate drive signal terminal is connected to the gate of the lower bridge chip, and the second Kelvin source terminal is connected to the source of the lower bridge chip.

[0014] Furthermore, it also includes AC terminal busbars, first DC negative terminal busbars, second DC negative terminal busbars, first DC positive terminal busbars, second DC positive terminal busbars, third DC positive terminal busbars, first gate drive signal busbars, second gate drive signal busbars, first Kelvin source busbars and second Kelvin source busbars.

[0015] Furthermore, the first DC positive terminal busbar is connected to the second DC positive terminal busbar via the first copper clip, and to the third DC positive terminal busbar via the second copper clip, thus achieving electrical connection with the drain of the upper bridge chip; the source of the upper bridge chip is electrically connected to the first Kelvin source lead-out terminal via the first source drive busbar, the gate of the upper bridge chip is electrically connected to the first gate drive signal lead-out terminal via the first gate drive signal busbar, and the source of the upper bridge chip is electrically connected to the AC terminal busbar via the third and fourth copper clips; The drain of the lower bridge chip is electrically connected to the AC terminal via the AC terminal busbar; the source of one chip in the lower bridge chip is electrically connected to the first DC negative terminal busbar via the fifth copper clip, and the source of the other chip in the lower bridge chip is electrically connected to the second DC negative terminal busbar via the sixth copper clip; the source of the lower bridge chip is electrically connected to the second Kelvin source lead-out terminal via the second source drive busbar, and the gate of the lower bridge chip is electrically connected to the second gate drive signal lead-out terminal via the second gate drive signal busbar.

[0016] Furthermore, in the AC terminal busbar, a slot is provided at the connection point with the lower bridge chip, wherein the slot length of the chip located inside the module in the lower bridge chip is greater than the slot length of the chip located at the edge of the module in the lower bridge chip.

[0017] Furthermore, in the third, fourth, seventh, and eighth copper clips, a slot is provided at the connection point with the chip on the side near the DC terminal of the upper bridge chip. In the fifth and sixth copper clips, a slot is provided at the connection point with the chip in the lower bridge chip near the DC terminal.

[0018] The beneficial effects of this invention are as follows: This invention provides a semiconductor power module packaging structure in which the chips are generally arranged symmetrically from left to right and top to bottom within the power module. It uses four DC positive terminals and two DC negative terminals, providing one set of current loops through the first DC positive terminal, the second DC positive terminal, and the first DC negative terminal, and another set of current loops through the third DC positive terminal, the fourth DC positive terminal, and the second DC negative terminal. This provides more current loops, reduces the difference in the length of the chip power loops, improves the current sharing performance of the power module, and reduces the parasitic inductance of the module.

[0019] Meanwhile, this invention uses copper clips instead of traditional bonding wires for electrical connection between the chip and the metal layer. This not only reduces the parasitic inductance of the power module but also improves the stability of the power module. Furthermore, this invention utilizes the plasticity of copper clips to construct copper clips of different shapes, which further makes the power circuits of each chip tend to be equal, thereby reducing the difference in parasitic inductance between chips and improving the current sharing performance of the power module.

[0020] Furthermore, by arranging the copper clips in a stacked manner, the current directions of adjacent upper and lower copper clips are opposite, thereby creating magnetic fields with opposite directions. The principle of magnetic field cancellation can be used to further reduce the parasitic inductance of the power module.

[0021] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0022] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein: Figure 1 This is a schematic diagram of the internal structure of the power module package; Figure 2 This is a schematic diagram of the first layer of copper clips connected inside the power module packaging structure. Figure 3 This is a schematic diagram of the structure of the first and second copper clips; Figure 4 A schematic diagram of the second layer of copper clip connection inside the power module packaging structure; Figure 5 A schematic diagram of the third and fourth copper clips; Figure 6 This is a schematic diagram of the structure of the fifth and sixth copper clips; Figure 7A schematic diagram of the third layer of copper clip connection inside the power module packaging structure; Figure 8 A schematic diagram of the structure of the seventh and eighth copper clips; Figure 9 This is a schematic diagram of the overall packaging structure of the power module; Figure 10 This is a side view of the power module package structure.

[0023] Figure label: 1 First DC positive terminal; 2 First DC negative terminal; 3 Second DC positive terminal; 4 Third DC positive terminal; 5 Second DC negative terminal; 6-Fourth DC positive terminal; 7 8-First DC negative terminal busbar; 9-First DC positive terminal busbar; 10-Insulating substrate; 11-Chip; 12-Second DC positive terminal busbar; 13-First Kelvin source busbar; 14-AC terminal busbar; 15-Upper bridge drain terminal; 16-First Kelvin source terminal; 17-First gate drive signal terminal; 18-AC terminal; 19-Second gate drive signal terminal 20-First temperature sensing pin; 21-Second temperature sensing pin; 22-First gate drive signal busbar; 23-Third DC positive terminal busbar; 24-Second Kelvin source busbar; 25-Second gate drive signal busbar; 26-Second DC negative terminal busbar; 27-First copper clip; 28-Second copper clip; 29-Third copper clip; 30-Fourth copper clip; 31-Fifth copper clip; 32-Sixth copper clip; 33-Seventh copper clip; 34-Eighth copper clip. Detailed Implementation

[0024] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0025] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0026] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0027] Please see Figures 1 to 10 An embodiment of the present invention provides a power module packaging structure based on stacked copper clip interconnection, which includes: an insulating substrate 9, a metal layer, power terminals, signal terminals, copper clips, and a chip 10. The metal layer is disposed on the surface of the insulating substrate 9, and the power terminals, signal terminals, copper clips, and chip 10 are all disposed on the insulating substrate 9 and electrically connected to the metal layer.

[0028] A portion of chip 10 is connected in parallel to form an upper bridge, and another portion is connected in parallel to form a lower bridge, with the number of upper and lower bridge chips being equal. The upper bridge chips are symmetrically distributed in an array in the upper half of the insulating substrate 9, and the lower bridge chips are symmetrically distributed in an array in the lower half of the insulating substrate 9. For example... Figure 1 As shown, the side with the chip arranged and closer to the AC terminal 17 is the upper half of the insulating substrate 9, and the side with the chip arranged and closer to the DC terminal is the lower half of the insulating substrate 9.

[0029] The power terminals include a first DC positive terminal 1, a second DC positive terminal 3, a third DC positive terminal 4, a fourth DC positive terminal 6, a first DC negative terminal 2, a second DC negative terminal 5, and an AC terminal 17. The first DC positive terminal 1 and the second DC positive terminal 3 are located on either side of the first DC negative terminal 2, and the third DC positive terminal 4 and the fourth DC positive terminal 6 are located on either side of the second DC negative terminal 5. The AC terminal 17 is disposed on the insulating substrate 9 at the opposite end to the DC terminals.

[0030] The copper clips include a first copper clip 27, a second copper clip 28, a third copper clip 29, a fourth copper clip 30, a fifth copper clip 31, a sixth copper clip 32, a seventh copper clip 33, and an eighth copper clip 34. The first copper clip 27 and the second copper clip 28 have the same structure; the third copper clip 29 and the fourth copper clip 30 have the same structure; the fifth copper clip 31 and the sixth copper clip 32 have the same structure; and the seventh copper clip 33 and the eighth copper clip 34 have the same structure. The first copper clip 27 and the second copper clip 28 are located below the third copper clip 29 and the fourth copper clip 30, in the first layer. The fifth copper clip 31 and the sixth copper clip 32 are at the same height as the third copper clip 29 and the fourth copper clip 30, in the second layer. The seventh copper clip 33 and the eighth copper clip 34 are located above the fifth copper clip 31 and the sixth copper clip 32, in the third layer. This layered design of the copper clips allows the current in adjacent copper clips to flow in opposite directions when the power module is powered on, thereby reducing the parasitic inductance of the module by utilizing the principle of magnetic field cancellation.

[0031] In this design, the first DC positive terminal 1 and the second DC positive terminal 3 are connected to the drain of one side of the chip in the upper bridge chip via the second copper clip 28 and the eighth copper clip 34. The third DC positive terminal 4 and the fourth DC positive terminal 6 are connected to the drain of the other side of the chip in the upper bridge chip via the first copper clip 27 and the seventh copper clip 33. The source of one side of the chip in the upper bridge chip is connected to the AC terminal 17 via the third copper clip 29, and the source of the other side of the chip in the upper bridge chip is connected to the AC terminal 17 via the fourth copper clip 30, thus forming a power loop from the DC positive terminal to the AC terminal. The AC terminal is connected to the drain of all the chips in the lower bridge chip. The source of one side of the chip in the lower bridge chip is connected to the second DC negative terminal 5 via the fifth copper clip 31, and the source of the other side of the chip in the lower bridge chip is connected to the first DC negative terminal 2 via the sixth copper clip 32, thus forming a power loop from the AC terminal to the DC negative terminal. This ensures that the power loops of each chip in the upper bridge and each chip in the lower bridge are equal, reducing the current difference between the chips. Meanwhile, the current directions in the first copper clip 27, the second copper clip 28, the seventh copper clip 33, and the eighth copper clip 34 are the same, and opposite to the current directions in the third copper clip 29, the fourth copper clip 30, the fifth copper clip 31, and the sixth copper clip 32. Therefore, the parasitic inductance of the circuit can be reduced based on the principle of magnetic field cancellation.

[0032] The signal terminals include an upper bridge drain lead-out terminal 14, a first Kelvin source lead-out terminal 15 and a first gate drive signal lead-out terminal 16 disposed on one side of the AC terminal 17, and a second gate drive signal lead-out terminal 19, a second Kelvin source lead-out terminal 18, a first temperature sensing pin 20 and a second temperature sensing pin 21 disposed on the other side of the AC terminal 17.

[0033] Specifically, the upper bridge drain terminal 14 is connected to the drain of the upper bridge chip, the first Kelvin source terminal 15 is connected to the source of the upper bridge chip, the first gate drive signal terminal 16 is connected to the gate of the upper bridge chip, the second gate drive signal terminal 19 is connected to the gate of the lower bridge chip, and the second Kelvin source terminal 18 is connected to the source of the lower bridge chip.

[0034] In addition, the semiconductor power module also includes an AC terminal busbar 13, a first DC negative terminal busbar 7, a second DC negative terminal busbar 26, a first DC positive terminal busbar 8, a second DC positive terminal busbar 11, a third DC positive terminal busbar 23, a first gate drive signal busbar 22, a second gate drive signal busbar 25, a first Kelvin source busbar 12, and a second Kelvin source busbar 24.

[0035] The first DC positive terminal busbar 8 is connected to the second DC positive terminal busbar 11 and the third DC positive terminal busbar 23 via the first copper clip 27 and the second copper clip 28, and is electrically connected to the drain of the upper bridge chip. The source of the upper bridge chip is electrically connected to the first Kelvin source lead-out terminal 15 via the first source drive busbar, the gate of the upper bridge chip is electrically connected to the first gate drive signal lead-out terminal 16 via the first gate drive signal busbar 22, and the source of the upper bridge chip is electrically connected to the AC terminal busbar 13 via the third copper clip 29 and the fourth copper clip 30.

[0036] The drain of the lower bridge chip is electrically connected to the AC terminal 17 via the AC terminal busbar 13. The source of one chip in the lower bridge chip is electrically connected to the first DC negative terminal busbar 7 via the fifth copper clip 31. The source of the other chip in the lower bridge chip is electrically connected to the second DC negative terminal busbar 26 via the sixth copper clip 32. The source of the lower bridge chip is electrically connected to the second Kelvin source lead-out terminal 18 via the second source drive busbar. The gate of the lower bridge chip is electrically connected to the second gate drive signal lead-out terminal 19 via the second gate drive signal busbar.

[0037] In summary, this invention provides a semiconductor power module packaging structure that adopts a symmetrical layout of the chip both horizontally and vertically. Four current loops are constructed in the module using four DC positive terminals and two DC negative terminals. By increasing the number of current loops, the length of the power loops of some chips can be reduced and the differences in the length of each power loop can be balanced, thereby further improving the current sharing performance of the module and reducing the parasitic inductance of the module. In addition, the staggered arrangement of positive and negative terminals can reduce the parasitic inductance caused by the DC terminals.

[0038] The first current loop is as follows: current flows in from the first DC positive terminal 1, passes through the second copper clip 28 and the eighth copper clip 34 to the upper bridge chip, then flows through the fourth copper clip 30 to the lower bridge chip, and finally returns to the first DC negative terminal 2 through the sixth copper clip 32. The second current loop is similar to the first: current flows in from the second DC positive terminal 3, passes through the second copper clip 28 and the eighth copper clip 34 to the upper bridge chip, then flows through the fourth copper clip 30 to the lower bridge chip, and finally returns to the first DC negative terminal 2 through the sixth copper clip 32.

[0039] The third current loop is as follows: current flows in from the third DC positive terminal 4, passes through the first copper clip 27 and the seventh copper clip 33 to the upper bridge chip, then flows through the third copper clip 29 to the lower bridge chip, and finally returns to the second DC negative terminal 5 through the fifth copper clip 31. The fourth current loop is similar to the third current loop: current flows in from the fourth DC positive terminal 6, passes through the first copper clip 27 and the seventh copper clip 33 to the upper bridge chip, then flows through the third copper clip 29 to the lower bridge chip, and finally returns to the second DC negative terminal 5 through the fifth copper clip 31.

[0040] Using copper clips instead of traditional bonding wires for electrical connections between the chip and the metal layer not only reduces the parasitic inductance of the power module but also improves its stability. Furthermore, arranging the copper clips in a stacked manner ensures that the current in adjacent clips flows in opposite directions, creating opposing magnetic fields. This principle of magnetic field cancellation further reduces the parasitic inductance of the power module.

[0041] Based on the above-described current loop, when current flows from the upper bridge chip into the lower bridge chip through the third copper clip 29 and the fourth copper clip 30, because the chip on one side of the upper bridge is closer to the DC negative terminal (this side is denoted as the first side), the power loop length of the chip on the first side will be shorter, resulting in more current flowing into it than the chip on the other side closer to the AC terminal (this side is denoted as the second side). To reduce this current imbalance, the present invention performs slotting treatment on the third copper clip 29 and the fourth copper clip 30 near the chip on the first side, such as... Figure 4 and Figure 5 As shown, this increases the power loop length of the first-side chip to solve the current imbalance problem caused by the different power loop lengths between the first and second-side chips. Similarly, the fifth, sixth, seventh, and eighth copper clips are also designed with slots made at the connection points near the first-side chip to improve the current sharing performance of the module.

[0042] Meanwhile, slotting was also made on the AC terminal busbar. When current flows from the AC terminal to the downbridge chip, the power circuit length of the chip inside the module in the downbridge is shorter, so more current will flow in. Therefore, a longer slot is made near the chip inside the module and a shorter slot is made near the chip at the edge of the module to reduce the difference in current of the downbridge chip and further improve the current sharing performance of the module.

[0043] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A power module packaging structure based on multilayer copper clip interconnection, characterized in that, It includes an insulating substrate (9), a metal layer, power terminals, signal terminals, copper clips, and a chip (10); the metal layer is disposed on the surface of the insulating substrate (9), and the power terminals, signal terminals, copper clips, and chip (10) are all disposed on the insulating substrate (9) and electrically connected to the metal layer; Among them, multiple chips (10) are disposed on an insulating substrate (9), half of the chips (10) are connected in parallel to form an upper bridge, and the other half of the chips (10) are connected in parallel to form a lower bridge; the upper bridge chips are symmetrically distributed in the upper half of the insulating substrate (9), and the lower bridge chips are symmetrically distributed in the lower half of the insulating substrate (9). The power terminals include a first DC positive terminal (1), a second DC positive terminal (3), a third DC positive terminal (4), a fourth DC positive terminal (6), a first DC negative terminal (2), a second DC negative terminal (5), and an AC terminal (17). The DC terminals and AC terminals (17) are respectively disposed on opposite sides of the insulating substrate (9). The first DC positive terminal (1) and the second DC positive terminal (3) are respectively disposed on both sides of the first DC negative terminal (2), forming a current loop. The third DC positive terminal (4) and the fourth DC positive terminal (6) are respectively disposed on both sides of the second DC negative terminal (5), forming another current loop. The copper clips include the first copper clip (27), the second copper clip (28), the third copper clip (29), the fourth copper clip (30), the fifth copper clip (31), the sixth copper clip (32), the seventh copper clip (33), and the eighth copper clip (34); The first DC positive terminal (1) and the second DC positive terminal (3) are connected to the drain of one side of the chip in the upper bridge chip through the second copper clip (28) and the eighth copper clip (34). The third DC positive terminal (4) and the fourth DC positive terminal (6) are connected to the drain of the other side of the chip in the upper bridge chip through the first copper clip (27) and the seventh copper clip (33). The source of one side of the chip in the upper bridge chip is connected to the AC terminal (17) through the third copper clip (29). The source of the other side of the chip in the upper bridge chip is connected to the AC terminal (17) through the fourth copper clip (30). The AC terminal is connected to the drain of all the chips in the lower bridge chip. The source of one side of the chip in the lower bridge chip is connected to the second DC negative terminal (5) through the fifth copper clip (31). The source of the other side of the chip in the lower bridge chip is connected to the first DC negative terminal (2) through the sixth copper clip (32).

2. The semiconductor power module packaging structure according to claim 1, characterized in that, The first copper clip (27) and the second copper clip (28) have the same structure. The third copper clip (29) and the fourth copper clip (30) have the same structure. The fifth copper clip (31) and the sixth copper clip (32) have the same structure. The seventh copper clip (33) and the eighth copper clip (34) have the same structure.

3. The semiconductor power module packaging structure according to claim 2, characterized in that, The first copper clip (27) and the second copper clip (28) are respectively located below the third copper clip (29) and the fourth copper clip (30), and are located on the first layer; the fifth copper clip (31) and the sixth copper clip (32) are at the same height as the third copper clip (29) and the fourth copper clip (30), and are located on the second layer; the seventh copper clip (33) and the eighth copper clip (34) are located above the fifth copper clip (31) and the sixth copper clip (32), and are located on the third layer.

4. The semiconductor power module packaging structure according to claim 1, characterized in that, The signal terminals include an upper bridge drain lead-out terminal (14), a first Kelvin source lead-out terminal (15) and a first gate drive signal lead-out terminal (16) disposed on one side of the AC terminal (17), and a second gate drive signal lead-out terminal (19), a second Kelvin source lead-out terminal (18), a first temperature sensing pin (20) and a second temperature sensing pin (21) disposed on the other side of the AC terminal (17).

5. The semiconductor power module packaging structure according to claim 4, characterized in that, The upper bridge drain terminal (14) is connected to the drain of the upper bridge chip, the first Kelvin source terminal (15) is connected to the source of the upper bridge chip, the first gate drive signal terminal (16) is connected to the gate of the upper bridge chip, the second gate drive signal terminal (19) is connected to the gate of the lower bridge chip, and the second Kelvin source terminal (18) is connected to the source of the lower bridge chip.

6. The semiconductor power module packaging structure according to claim 1, characterized in that, It also includes AC terminal busbar (13), first DC negative terminal busbar (7), second DC negative terminal busbar (26), first DC positive terminal busbar (8), second DC positive terminal busbar (11), third DC positive terminal busbar (23), first gate drive signal busbar (22), second gate drive signal busbar (25), first Kelvin source busbar (12) and second Kelvin source busbar (24); The first DC positive terminal busbar (8) is connected to the second DC positive terminal busbar (11) through the first copper clip (27), and to the third DC positive terminal busbar (23) through the second copper clip (28), thus achieving electrical connection with the drain of the upper bridge chip; the source of the upper bridge chip is electrically connected to the first Kelvin source lead-out terminal (15) through the first source drive busbar, the gate of the upper bridge chip is electrically connected to the first gate drive signal lead-out terminal (16) through the first gate drive signal busbar (22), and the source of the upper bridge chip is electrically connected to the AC terminal busbar (13) through the third copper clip (29) and the fourth copper clip (30); The drain of the lower bridge chip is electrically connected to the AC terminal (17) via the AC terminal busbar (13); the source of one side of the lower bridge chip is electrically connected to the first DC negative terminal busbar (7) via the fifth copper clip (31), and the source of the other side of the lower bridge chip is electrically connected to the second DC negative terminal busbar (26) via the sixth copper clip (32); the source of the lower bridge chip is electrically connected to the second Kelvin source lead-out terminal (18) via the second source drive busbar, and the gate of the lower bridge chip is electrically connected to the second gate drive signal lead-out terminal (19) via the second gate drive signal busbar.

7. The semiconductor power module packaging structure according to claim 6, characterized in that, In the AC terminal busbar (13), a slot is provided at the connection with the lower bridge chip, wherein the slot length of the chip located inside the module in the lower bridge chip is greater than the slot length of the chip located at the edge of the module in the lower bridge chip.

8. The semiconductor power module packaging structure according to any one of claims 1 to 7, characterized in that, In the third copper clip (29), the fourth copper clip (30), the seventh copper clip (33) and the eighth copper clip (34), a slot is provided at the connection point with the chip on the side of the upper bridge chip near the DC terminal; In the fifth copper clip (31) and the sixth copper clip (32), a slot is provided at the connection point with the chip on the side near the DC terminal in the lower bridge chip.

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