Semiconductor packaging structure and packaging method

Abstract

The invention relates to a semiconductor structure, and particularly discloses a semiconductor packaging structure and method, and the structure comprises a first wiring layer, a first mold, a second wiring layer, a second mold, and a third wiring layer which are sequentially stacked from bottom to top. A plurality of first wafer modules, a plurality of conductive columns e and a plurality of conductive columns f are arranged in the first molding; wherein the first wafer module is provided with a wafer a and a wafer b which are stacked; a plurality of second wafer modules and a plurality of conductive columns g are arranged in the second mold, and the second wafer modules are single wafers c; the third wiring layer can be electrically connected with the second wafer module, the second wiring layer, the first wafer module and the first wiring layer in sequence; the third wiring layer can be electrically connected with the second wafer module, the second wiring layer, the conductive column e and the first wiring layer in sequence; the third wiring layer can be electrically connected with the conductive column g, the second wiring layer, the conductive column f and the first wiring layer in sequence. The beneficial effects of the invention are that the transmission effect is improved, the data processing efficiency is improved, and the position of the wafer is not easy to shift.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a semiconductor packaging structure and packaging method. Background Technology

[0002] In the semiconductor field, there are multiple packaging structures, such as 2D packaging, 2.5D packaging, and 3D packaging.

[0003] The appropriate packaging method is selected based on the data and signal transmission requirements, and a specific packaging structure is designed to improve data transmission speed.

[0004] In semiconductor packaging structures, although there are multiple semiconductor wafers stacked (to improve data processing), the stacked wafers are still connected to other wafers laid out in the same plane, which makes data transfer not very efficient.

[0005] Furthermore, in 2.5D / 3D packaging, it is customary to fabricate layer by layer from bottom to top, placing the corresponding wafer in the appropriate position during this process before injection molding. Although the wafer is already fixed in position with adhesive, slight misalignment is inevitable during injection molding, thus affecting the overall quality of the semiconductor.

[0006] Therefore, this solution designs a semiconductor structure that allows stacked wafers to be connected to individual wafers via shorter lines. Furthermore, a corresponding packaging method is provided to ensure proper wafer positioning during packaging, thereby improving the overall semiconductor packaging effect and ultimately enhancing semiconductor performance. Summary of the Invention

[0007] The purpose of this invention is to overcome the shortcomings of the prior art and provide a semiconductor packaging structure and packaging method, which solves the problem of long transmission paths between stacked wafers and individual wafers in existing semiconductors, and also solves the problem of slight positional displacement of wafers in existing packaging methods.

[0008] The objective of this invention is achieved through the following technical solution: In a first aspect, a semiconductor packaging structure is provided, comprising a first wiring layer, a first molding layer, a second wiring layer, a second molding layer, and a third wiring layer stacked sequentially from bottom to top; The first mold has multiple first wafer modules, multiple conductive pillars e, and multiple conductive pillars f; wherein, the first wafer module has wafers a and wafers b stacked and connected together; The second molding has multiple second wafer modules and multiple conductive pillars g, wherein the second wafer module is a single wafer c; The third wiring layer can be electrically connected in sequence to the second chip module in the second mold, the second wiring layer, the first chip module in the first mold, and the first wiring layer to form a data transmission route A; The third wiring layer can be electrically connected in sequence to the second chip module in the second mold, the second wiring layer, the conductive pillar e in the first mold, and the first wiring layer to form a data transmission route B; The third wiring layer can be electrically connected in sequence to the conductive post g in the second mold, the second wiring layer, the conductive post f in the first mold, and the first wiring layer to form a data transmission route C.

[0009] As a preferred technical solution of this application, in the first chip module, chip a can quickly transmit data to chip b, forming a structure for rapid data transmission.

[0010] As a preferred technical solution of this application, the front and back sides of the first wiring layer have a first front protrusion and a first back protrusion, respectively; the front and back sides of the second wiring layer have a second front protrusion and a second back protrusion, respectively; the front and back sides of the third wiring layer have a third front protrusion and a third back protrusion, respectively; in the semiconductor packaging structure, electrical connections are made through the corresponding protrusions.

[0011] As a preferred technical solution of this application, the first molding is prepared as follows: an adhesive layer is applied to the corresponding substrate, wafer a is placed on the substrate and fixed by the adhesive layer, and then wafer b with adhesive on its lower surface is placed on wafer a, followed by injection molding. After injection molding, the substrate is removed to form a first wafer module. The substrate of the first molding is formed by injection molding. Multiple through-hole conductive holes are processed on the substrate by laser processing, and conductive pillars e and f are formed by deposition. Multiple through-hole first placement cavities are also processed. The substrate of the first molding with corresponding conductive pillars is adhered to the corresponding substrate, and the first wafer module is placed in the placement cavity with a gap between the first wafer module and the first placement cavity. The gap is then filled by injection molding. After removing the corresponding substrate, the first molding is finally formed.

[0012] As a preferred technical solution of this application, the second molding is prepared as follows: an adhesive layer is applied to the corresponding substrate, the wafer c is fixed to the substrate by the adhesive layer, and then injection molding is performed. After injection molding, the substrate is removed to form a second wafer module. The substrate of the second molding is formed by injection molding. Multiple through-hole conductive holes are processed on the substrate by laser processing, and then conductive pillars g are formed by deposition. Multiple through-hole second placement cavities are also processed. The substrate of the second molding with corresponding conductive pillars is adhered to the corresponding substrate. The second wafer module is placed in the second placement cavity, and there is a gap between the first wafer module and the second placement cavity. Then the gap is filled by injection molding. After removing the corresponding substrate, the second molding is finally formed.

[0013] As a preferred technical solution of this application, the front and back sides of the wafers a, b, and c all have corresponding conductive protrusions.

[0014] Secondly, a packaging method for a semiconductor packaging structure is also provided, comprising the following steps: First, the first mold and the second mold are prepared separately; Then, adhesive is applied to the corresponding substrate, and then the first wiring layer, the first molding layer, the second wiring layer, the second molding layer, and the third wiring layer are stacked sequentially from bottom to top; Then injection molding is performed, and finally the corresponding substrate is removed.

[0015] The present invention has the following advantages: (1) Improve transmission performance; The stacked wafers (first wafer module) are directly connected to each other on the second wiring layer – the transmission path is shorter, thereby improving transmission efficiency; In addition, the structure of semiconductors allows for multiple data transmission paths, and the appropriate path can be selected as needed, without all data having to pass through the first chip module and the second chip module, thereby improving the data transmission efficiency. (2) Improve data processing efficiency; The chips used in data processing are stacked together so that data can be transferred quickly among these chips; (3) The wafer position is not easily shifted; Since the first chip module is placed in the first mold and then injection molded to fix it, and the second chip module is placed in the second mold and then injection molded to fix it, during packaging, the first mold and the second mold are packaged as a whole with each wiring layer, so that the positions of the first chip module and the second chip module are not easily shifted. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of the present invention; Figure 2 This is a schematic diagram of the structure of the first wiring layer; Figure 3 This is a schematic diagram of the structure of the first molding; Figure 4 This is a schematic diagram of the second wiring layer. Figure 5 This is a schematic diagram of the second molding structure; Figure 6 This is a schematic diagram of the third wiring layer. In the diagram: 10-First wiring layer, 11-First protrusion on the front, 12-First protrusion on the back, 20-First molding, 21-First chip module, 22-Conductive pillar e, 23-Conductive pillar f, 30-Second wiring layer, 31-Second protrusion on the front, 32-Second protrusion on the back, 40-Second molding, 41-Second chip module, 42-Conductive pillar g, 50-Third wiring layer, 51-Third protrusion on the front, 52-Third protrusion on the back, 61-Conductive protrusion. Detailed Implementation

[0017] The present invention will be further described below with reference to the accompanying drawings, but the scope of protection of the present invention is not limited to the following description.

[0018] It should be noted that the orientation or positional relationship indicated by terms such as "left" and "right" is based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the invention is usually placed during use, or the orientation or positional relationship in which those skilled in the art would conventionally understand it. Such terms are only for the convenience of describing the invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention.

[0019] It should be noted that, unless otherwise specified, the embodiments and features and technical solutions in the present invention can be combined with each other.

[0020] Reference Figure 1 This embodiment provides a semiconductor packaging structure, including a first wiring layer 10, a first molding 20, a second wiring layer 30, a second molding 40, and a third wiring layer 50 stacked sequentially from bottom to top; The first mold 20 includes multiple first wafer modules 21, multiple conductive pillars e22, and multiple conductive pillars f23; and the first wafer module 21 has wafers a and wafers b stacked together; when wafers a and b are stacked, wafers a can quickly transmit data to wafers b, forming a structure for fast data transmission. The second molding 40 has multiple second wafer modules 41 and multiple conductive pillars g42, and the second wafer module 41 is a single wafer c; Thus, the following electrical connection circuit can be formed: (1) Data transmission route A: The third wiring layer 50 can be electrically connected in sequence to the second chip module 41 in the second mold 40, the second wiring layer 30, the first chip module 21 in the first mold 20, and the first wiring layer 10; (2) Data transmission route B: The third wiring layer 50 can be electrically connected in sequence to the second chip module 41 in the second mold 40, the second wiring layer 30, the conductive pillar e in the first mold 20, and the first wiring layer 10; (3) Data transmission route C: The third wiring layer 50 can be electrically connected in sequence to the conductive post g42 in the second mold 40, the second wiring layer 30, the conductive post f in the first mold 20, and the first wiring layer 10.

[0021] Therefore, when data is transmitted through the semiconductor: (1) it can be processed without processing; (2) it can be processed by a single chip c in the second chip module 41 (of course, it can also be processed by the first chip module 21 only through a corresponding structural design, but this structural design is not protected in this embodiment, but those skilled in the art can know it); (3) it can be processed by a single chip c in the second chip module 41, as well as by the stacked chips a and b in the first chip module 21. This method can improve the speed of data processing.

[0022] Furthermore, in this scheme, the stacked chips a and b in the first chip module 21 can be two or more of memory chips, logic chips, analog processors, etc., thus forming a relatively opposing data processing unit; this method allows certain data to be processed quickly through these chips (at a certain stage, data is only transferred between these stacked chips).

[0023] In this embodiment, wafers a, b, and c each have corresponding conductive bumps 61 on both the front and back sides. The first wiring layer 10 has a first front bump 11 and a first back bump 12 on its front and back sides, respectively. The second wiring layer 30 has a second front bump 31 and a second back bump 32 on its front and back sides, respectively. The third wiring layer 50 has a third front bump 51 and a third back bump 52 on its front and back sides, respectively. In the semiconductor packaging structure, electrical connections are made via these bumps—thereby transmitting data.

[0024] The preparation of the first mold 20 will be further explained below.

[0025] See Figure 2The first mold 20 has a substrate formed by injection molding. Multiple through-hole conductive holes are laser-processed on the substrate, and conductive pillars e22 and f23 are formed within the conductive holes by deposition. Furthermore, the first molded substrate also has multiple through-hole first placement cavities, within which a first wafer module 21 is placed.

[0026] The preparation of the second mold 40 will be further explained below.

[0027] See Figure 3 The second mold 40 has a substrate formed by injection molding. Multiple through-hole conductive holes are laser-machined into the substrate, and conductive pillars g42 are formed within the conductive holes by deposition. Furthermore, the first molded substrate also has multiple through-hole second placement cavities, within which a second wafer module 41 is placed. This specific embodiment also discloses a packaging method for a semiconductor packaging structure, the steps of which are as follows: S1. First, prepare the first mold 20 and the second mold 40 respectively; When the first mold 20 is being prepared: (1) an adhesive layer is applied to the corresponding substrate, wafer a is placed on the substrate and fixed by the adhesive layer, and then wafer b with adhesive on its lower surface is placed on wafer a, and then injection molding is performed. After injection molding, the substrate is removed to form the first wafer module 21; (2) the substrate of the first mold is formed by injection molding, and multiple conductive holes are formed on the substrate by laser processing, and then conductive pillars e22 and conductive pillars f23 are formed by deposition; (3) multiple first placement cavities are also processed; (4) the substrate of the first mold with corresponding conductive pillars is adhered to the corresponding substrate, the first wafer module 21 is placed in the placement cavity, and there is a gap between the first wafer module 210 and the first placement cavity; then the gap is filled by injection molding; after removing the corresponding substrate, the first mold 20 is finally formed.

[0028] When the second mold 40 is being prepared: (1) an adhesive layer is applied to the corresponding substrate, the wafer c is placed on the substrate and fixed by the adhesive layer, and then injection molding is performed. After injection molding, the substrate is removed to form the second wafer module 41; (2) the substrate of the second mold is formed by injection molding, and multiple conductive holes are formed on the substrate by laser processing, and then conductive pillars g42 are formed by deposition; (3) multiple second placement cavities are also processed; (4) the substrate of the second mold with corresponding conductive pillars is adhered to the corresponding substrate, the second wafer module 41 is placed in the second placement cavity, and there is a gap between the first wafer module 21 and the second placement cavity; then the gap is filled by injection molding; after removing the corresponding substrate, the second mold 40 is finally formed.

[0029] S2. Then, glue is adhered to the corresponding substrate, and then the first wiring layer 10, the first molding 20, the second wiring layer 30, the second molding 40, and the third wiring layer 50 are stacked sequentially from bottom to top. S3, then injection molding is performed, and finally the corresponding substrate is removed.

[0030] The above embodiments only illustrate preferred implementation methods, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of this invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this invention, and these all fall within the protection scope of this invention.

Claims

1. A semiconductor packaging structure, characterized in that: It includes a first wiring layer (10), a first molding (20), a second wiring layer (30), a second molding (40), and a third wiring layer (50) stacked from bottom to top. The first mold (20) has a plurality of first wafer modules (21), a plurality of conductive pillars e (22), and a plurality of conductive pillars f (23); wherein, the first wafer module (21) has wafers a and wafers b stacked and connected together; The second mold (40) has multiple second wafer modules (41) and multiple conductive pillars g (42), wherein the second wafer module (41) is a single wafer c; The third wiring layer (50) can be electrically connected in sequence to the second chip module (41) in the second mold (40), the second wiring layer (30), the first chip module (21) in the first mold (20), and the first wiring layer (10) to form a data transmission route A; The third wiring layer (50) can be electrically connected in sequence to the second chip module (41) in the second mold (40), the second wiring layer (30), the conductive pillar e in the first mold (20), and the first wiring layer (10) to form a data transmission route B; The third wiring layer (50) can be electrically connected in sequence to the conductive post g (42) in the second mold (40), the second wiring layer (30), the conductive post f in the first mold (20), and the first wiring layer (10) to form a data transmission route C.

2. The semiconductor packaging structure according to claim 1, characterized in that: In the first chip module (21), chip a can quickly transmit data to chip b, forming a structure for rapid data transmission.

3. A semiconductor packaging structure according to claim 1 or 2, characterized in that: The first wiring layer (10) has a front first protrusion (11) and a back first protrusion (12) on its front and back sides, respectively. The second wiring layer (30) has a front second protrusion (31) and a back second protrusion (32) on its front and back sides, respectively. The third wiring layer (50) has a front third protrusion (51) and a back third protrusion (52) on its front and back sides, respectively. In semiconductor packaging structures, electrical connections are made via corresponding bumps.

4. A semiconductor packaging structure according to claim 1 or 2, characterized in that: The first molding (20) is prepared as follows: An adhesive layer is applied to the corresponding substrate, and wafer a is fixed on the substrate by the adhesive layer. Then, wafer b with adhesive on its lower surface is placed on wafer a, and injection molding is performed. After injection molding, the substrate is removed to form the first wafer module (21). The first molded substrate is formed by injection molding. Multiple conductive holes that run through the top and bottom are processed on the substrate by laser. Then, conductive pillars e (22) and conductive pillars f (23) are formed by deposition. Multiple vertically penetrating first placement cavities were also machined; A first molded substrate with corresponding conductive pillars is adhered to the corresponding substrate, and the first wafer module (21) is placed in the placement cavity with a gap between the first wafer module (210) and the first placement cavity; then the gap is filled by injection molding; after removing the corresponding substrate, the first mold (20) is finally formed.

5. A semiconductor packaging structure and packaging method according to claim 1 or 2, characterized in that: The second molding (40) is prepared as follows: An adhesive layer is applied to the corresponding substrate, and the wafer c is fixed on the substrate by the adhesive layer. Then, injection molding is performed. After injection molding, the substrate is removed to form the second wafer module (41). The second molded substrate is formed by injection molding, and multiple through-hole conductive holes are formed on the substrate by laser processing. Then, conductive pillars g (42) are formed by deposition. Multiple second placement cavities that run vertically through the interior were also manufactured; A second molded substrate with corresponding conductive pillars is adhered to the corresponding substrate, the second wafer module (41) is placed in the second placement cavity, and there is a gap between the first wafer module (21) and the second placement cavity; then the gap is filled by injection molding; after removing the corresponding substrate, the second mold (40) is finally formed.

6. A semiconductor packaging structure according to claim 1 or 2, characterized in that: The front and back sides of wafers a, b, and c all have corresponding conductive bumps (61).

7. A packaging method for a semiconductor packaging structure according to any one of claims 1 to 6, characterized in that: The steps are as follows: First, the first mold (20) and the second mold (40) are prepared respectively; Then, glue is adhered to the corresponding substrate, and then the first wiring layer (10), the first molding (20), the second wiring layer (30), the second molding (40), and the third wiring layer (50) are stacked sequentially from bottom to top. Then injection molding is performed, and finally the corresponding substrate is removed.

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