Semiconductor device and method of forming integrated circuit package

Abstract

In accordance with an embodiment, a method includes forming a wafer including a plurality of bottom dies, the plurality of bottom dies including a first bottom die and a second bottom die, the first bottom die and the second bottom die being laterally spaced a first distance; bonding the first top die to the first bottom die in a face-to-face configuration; bonding a second top die to a second bottom die in a face-to-face configuration, the first top die and the second top die laterally spaced a second distance, the second distance being different from the first distance; and bonding an interconnect die to the first bottom die and the second bottom die in a face-to-face configuration, the interconnect die disposed between the first top die and the second top die. The embodiment of the invention provides a semiconductor device and a method of forming an integrated circuit package.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to semiconductor devices, and methods of forming integrated circuit packages. BACKGROUND

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers and semiconductor material layers on a semiconductor substrate, and patterning the various material layers using photolithographic techniques to form circuit components and elements thereon. Typically, tens or hundreds of integrated circuits are fabricated on a single semiconductor wafer. The individual dies are singulated by sawing along scribe lines. The individual dies are then packaged separately, packaged in multi-chip modules, or packaged in other types of packages.

[0003] The semiconductor industry continues to improve the integration density of various electronic elements (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, which allows more elements to be integrated into a given area. SUMMARY

[0004] According to an embodiment, a method of forming an integrated chip package includes forming a wafer including a plurality of bottom dies, the plurality of bottom dies including a first bottom die and a second bottom die, the first bottom die and the second bottom die laterally spaced apart by a first distance; bonding a first top die to the first bottom die in a face-to-face configuration; bonding a second top die to the second bottom die in a face-to-face configuration, the first top die and the second top die laterally spaced apart by a second distance, the second distance being different than the first distance; and bonding an interconnect die to the first bottom die and the second bottom die in a face-to-face configuration, the interconnect die disposed between the first top die and the second top die.

[0005] According to an embodiment, a method of forming an integrated chip package includes attaching a plurality of bottom dies to a substrate, the plurality of bottom dies including a first bottom semiconductor die, a second bottom semiconductor die and a third bottom semiconductor die arranged in a row; attaching a plurality of top dies over the plurality of bottom dies and electrically connected to the plurality of bottom dies, wherein the first bottom semiconductor die, the second bottom semiconductor die and the third bottom semiconductor die are electrically isolated from each other after attaching the plurality of top dies; attaching an interconnect die over the plurality of bottom dies after attaching the plurality of top dies, the interconnect die electrically connected to the first bottom semiconductor die and the third bottom semiconductor die; removing the substrate from an underside of the plurality of bottom dies; and attaching a package substrate to the underside of the plurality of bottom dies.

[0006] According to an embodiment, a semiconductor device includes: a first bottom semiconductor die and a second bottom semiconductor die disposed above a package substrate; a package disposed between and around the first bottom semiconductor die and the second bottom semiconductor die, the package bonded to a first semiconductor substrate of the first bottom semiconductor die and a second semiconductor substrate of the second bottom semiconductor die, the package adjacent to the first semiconductor substrate and the second semiconductor substrate; a first top semiconductor die disposed above and electrically connected to the first bottom semiconductor die; a second top semiconductor die disposed above and electrically connected to the second bottom semiconductor die; and an interconnect die disposed above and electrically connected to the first bottom semiconductor die and the second bottom semiconductor die, the interconnect die overlapping a first corner of the first bottom semiconductor die in a plan view. BRIEF DESCRIPTION OF DRAWINGS

[0007] Various aspects of the disclosure can be best understood from the following detailed description when read with the accompanying drawings. It is noted that, in accordance with industry standard practice, the various drawings are not drawn to scale. In fact, the dimensions of the various features can be arbitrarily enlarged or reduced for clarity. It is intended and understood that all connections between components are either direct or through- via but not both.

[0008] Figure 1 and Figure 2 Cross-sectional views of intermediate steps in process steps during formation and incorporation of semiconductor dies into an integrated circuit package are shown, according to some embodiments.

[0009] Figure 3 and Figure 4 Cross-sectional views of intermediate steps in process steps during formation and incorporation of additional semiconductor dies into an integrated circuit package are shown, according to some embodiments.

[0010] Figures 5 to 8 Cross-sectional views of intermediate steps during subsequent process steps in forming an integrated circuit package are shown, according to some embodiments.

[0011] Figures 9A to 9F Plan views of intermediate steps in process steps during formation of an integrated circuit package are shown, according to various embodiments. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. For simplicity, in the following description a particular site or location can be referred to as comprising, including, or consisting of certain components or steps. Of course, in the art of making and using the described technology, such components and steps should not be construed to limit the described examples to only those particular sites or locations described. For example, in the following description, forming a first component over or on a second component can include embodiments in which the first component and the second component are in direct contact, and can also include embodiments in which additional components are formed between the first component and the second component, such that the first component and the second component can not be in direct contact. Furthermore, the present disclosure can repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the illustrated embodiments and / or configurations.

[0013] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of describing

[0014] Various embodiments provide methods for forming a three-dimensional integrated circuit (3DIC) package, such as an integrated system on a chip (SoIC) package. Forming an integrated circuit package, such as an integrated chip package, includes forming two or more bottom semiconductor dies, such as bottom dies, in a wafer, such as a reconstituted wafer. One or more top semiconductor dies, such as top dies, can be formed, such as active side down, and face-to-face bonded with the bottom semiconductor dies, such as active side up. In addition, an interconnect die, such as active side down, can be face-to-face bonded with the two or more bottom semiconductor dies. The interconnect die electrically couples the respective bottom semiconductor dies to each other. A package substrate can also be attached to the structure to provide external electrical connections, such as power and / or interconnectivity with other devices, to the integrated chip package.

[0015] According to some embodiments, an interconnection die can directly couple three or more bottom semiconductor dies. Thus, the design of the integrated chip package benefits from greater flexibility in the size, shape, and relative position of the top semiconductor die and the bottom semiconductor dies. For example, a pair of bottom semiconductor dies can be located in the integrated chip package at positions diagonally or oppositely distal from one another while still benefiting from substantially direct communication (e.g., cross-talk). The substantially direct communication can be facilitated by one interconnection die, or by more interconnection dies if needed (or desired) for indirect paths, greater distances, and / or more complex intra-connectivity of the integrated chip package. For example, improved cross-talk between the bottom semiconductor dies can be particularly beneficial to overall functionality, such as computational efficiency. The integrated chip package embodiments disclosed herein having multi-cross interconnection dies can benefit from improved intra-connectivity as well as flexibility in the design of the package (e.g., relative position of components, smaller or larger package size or package shape), resulting in higher yield, improved reliability and performance, higher component density, and / or smaller size.

[0016] Figures 1 to 9F Cross-sectional (e.g., side view) and planar (e.g., top view) diagrams showing intermediate steps during the process of forming the integrated chip package 100 are shown according to some embodiments. In Figure 1 A wafer 10 is shown in FIG. 1. The wafer 10 includes bottom semiconductor dies 150. Each bottom semiconductor die 150 can be a logic die (e.g., an application processor (AP), a central processing unit, a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a hybrid memory cube (HBC), a static random access memory (SRAM) die, a wide IO memory die, a magnetoresistive random access memory (mRAM) die, a resistive random access memory (rRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front end (AFE) die), a biomedical die, or the like. Each bottom semiconductor die 150 can also be a system on a chip (SoC) die, or the like. The wafer 10 can include a substrate 117 (e.g., a semiconductor substrate), an interconnection structure 119 disposed on the substrate 117, a bonding layer 121 disposed on the interconnection structure 119, and bonding pads 123 disposed in the bonding layer 121 and exposed to a front surface of the wafer 10. The side of the wafer 10 including the exposed bonding pads 123 and the bonding layer 121 can also be referred to as the front side of the wafer 10.

[0017] The substrate 117 of the wafer 10 can include a crystalline silicon wafer. The substrate 117 can include various doped regions (e.g., a p-type substrate or an n-type substrate) depending on design requirements. According to some embodiments, the doped regions can be doped with p-type or n-type dopants. The doped regions can be doped with p-type dopants (e.g., boron or BF2); n-type dopants (e.g., phosphorus or arsenic); and / or combinations thereof. The doped regions can be configured for n-type fin field effect transistors (FinFETs) and / or p-type FinFETs. In some alternative embodiments, the substrate 117 can include an active layer of a semiconductor-on-insulator (SOI) substrate. The substrate 117 can include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as a multilayer substrate or a graded substrate, can also be used.

[0018] Active and / or passive devices (e.g., transistors, diodes, capacitors, resistors, etc.) can be formed in and / or on the substrate 117. These devices can be interconnected by an interconnect structure 119. The interconnect structure 119 electrically connects the devices on the substrate 117 to form one or more integrated circuits. The interconnect structure 119 can include one or more dielectric layers (e.g., one or more interlayer dielectric (ILD) layers, intermetal dielectric (IMD) layers, or the like) and interconnect lines or metallization patterns embedded in the one or more dielectric layers. The material of the one or more dielectric layers can include silicon oxide (SiO x where x > 0), silicon nitride (SiN x where x > 0), silicon oxynitride (SiO x N y where x > 0 and y > 0), or other suitable dielectric materials. The interconnect lines can include metal lines. For example, the interconnect lines include copper lines, copper pads, aluminum pads, or combinations thereof formed by one or more single damascene processes, dual damascene processes, or the like. The side of the wafer 10 including the exposed backside surface of the substrate 117 can also be referred to as the backside of the wafer 10 subsequently.

[0019] The bonding layer 121 can include a dielectric layer. Bonding pads 123 are embedded in the bonding layer 121, and the bonding pads 123 allow for connections to the devices on the interconnect structure 119 and the substrate 117. The material of the bonding layer 121 can be silicon oxide (SiO x where x > 0), silicon nitride (SiN x where x > 0), silicon oxynitride (SiO x N ywhere x > 0 and y > 0), tetraethyl orthosilicate (TEOS), or other suitable dielectric material, and the bond pad 123 can include a conductive pad (e.g., a copper pad), a conductive via (e.g., a copper via), or a combination thereof. The bonding layer 121 can be formed by depositing a dielectric material on the interconnect structure 119 using a chemical vapor deposition (CVD) process (e.g., a plasma-enhanced CVD process or other suitable process), patterning the dielectric material to form the bonding layer 121 including the opening or via, and filling the opening or via defined in the bonding layer 121 with a conductive material to form the bond pad 123 embedded in the bonding layer 121.

[0020] The bottom semiconductor die 150 also includes a through-substrate via (TSV) 111 that can be electrically connected to a metallization pattern in the interconnect structure 119. For example, the TSV 111 can be formed by forming a recess in the substrate 117 by etching, milling, laser techniques, combinations thereof, and / or the like. A thin barrier layer can be deposited conformally over the substrate 117 front side and within the opening, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, combinations thereof, and / or the like. The barrier layer can include a nitride or oxynitride, for example, titanium nitride, titanium oxynitride, tantalum nitride, tantalum oxynitride, tungsten nitride, combinations thereof, and / or the like. A conductive material is deposited over the thin barrier layer and within the opening. The conductive material can be formed by an electro-chemical plating process, CVD, ALD, PVD, combinations thereof, and / or the like. Examples of the conductive material are copper, tungsten, aluminum, silver, gold, combinations thereof, and / or the like. Excess conductive material and barrier layer can be removed from the substrate 117 front side by, for example, chemical mechanical polishing (CMP). Thus, according to some embodiments, the TSV 111 can include a conductive material and a thin barrier layer between the conductive material and the substrate 117. In a subsequent process step, the substrate 117 can be thinned to expose the TSV 111 (see Figure 6 ). After thinning, the TSV 111 provides an electrical connection from the substrate 117 backside to the substrate 117 front side. In various embodiments, the backside of the substrate 117 can refer to a side of the substrate 117 opposite the device and interconnect structure 119, while the front side of the substrate 117 can refer to a side of the substrate 117 on which the device and interconnect structure 119 are disposed.

[0021] Optionally, a dicing process is performed along the dicing streets 129 of the wafer 10 (see Figure 2). The singulation process singulates the bottom semiconductor dies 150 from each other along the dicing lanes 129. The dicing lanes 129 are disposed between adjacent bottom semiconductor dies 150 (which can be referred to as bottom dies). The singulation process can include a blade dicing process that cuts along the dicing lanes 129 using, for example, a high-speed rotating abrasive disk or a blade saw. The blade tip can include abrasive particles or a thin diamond layer.

[0022] In Figure 2 which the singulation process is performed to singulate the bottom semiconductor dies 150, the plurality of bottom semiconductor dies 150 can be formed into a reconstituted wafer 10'. For example, the bottom semiconductor dies 150 can be attached to a substrate 160, and a package 132 can be formed over and between the bottom semiconductor dies 150 to encapsulate the bottom semiconductor dies 150 in the package 132. The package 132 can be formed using compression molding, transfer molding, spin coating, or the like. The package 132 can be an epoxy or a molding compound, such as polyimide, polyphenylene sulfide (PPS), polyether ether ketone (PEEK), polyether sulfone (PES), a heat-resistant crystalline resin, combinations thereof, or the like. According to some embodiments, the package 132 forms a bond with the semiconductor substrate (e.g., substrate 117) of the bottom semiconductor dies. As shown, the package can be coterminous with the substrate 117. Note that some or all of the bottom semiconductor dies 150 can be the same type of device die (e.g., formed in the same wafer 10 or a plurality of wafers 10 of the same type) or can include multiple types of device dies.

[0023] After the package 132 is formed, a planarization process is performed to remove excess portions of the package 232 and expose the top surfaces of the bottom semiconductor dies 150. The planarization process can include a grinding process, a CMP process, or the like. As shown, the planarization process can level the top surfaces of the bottom semiconductor dies 150 with the top surface of the package 132. According to some embodiments, the planarization process can expose the bond layer 121 and the bond pads 123.

[0024] According to some embodiments (not specifically shown), the bond layer 121 and the bond pads 123 can be formed on the interconnect structures 119 after the reconstituted wafer 10' is formed. For example, after the package 132 is formed, a bond layer 121 can be formed that extends across the front surface (e.g., front side) of the wafer 10'. In addition, the bond pads 123 are embedded in the bond layer 121 directly over and electrically coupled to the interconnect structures 119 of the bottom semiconductor dies 150.

[0025] In Figure 3The image shows wafer 20. Wafer 20 includes top semiconductor dies 250. Each top semiconductor die 250 may be a logic die, memory die, power management die, radio frequency (RF) die, sensor die, microelectromechanical system (MEMS) die, signal processing die, front-end die, biomedical die, or the like, similar to the description above regarding bottom semiconductor die 150. Each top semiconductor die 250 may also be a system-on-a-chip (SoC) die, or the like.

[0026] The materials and fabrication processes of components in wafer 20 (e.g., top semiconductor die 250) may be referenced to similar components in wafer 10 / 10' (e.g., bottom semiconductor die 150), wherein components in bottom semiconductor die 150 beginning with the number "1" correspond to components in top semiconductor die 250 beginning with the number "2". For example, top semiconductor die 250 may include a substrate 217 having devices (e.g., transistors, capacitors, diodes, resistors, or the like) formed thereon, and interconnect structures 219. Interconnect structures 219 electrically connect devices on substrate 217 to form one or more integrated circuits. Interconnect structures 219 include one or more dielectric layers (e.g., one or more interlayer dielectric (ILD) layers, intermetallic dielectric (IMD) layers, or the like) and interconnect wiring or metallization patterns embedded in one or more dielectric layers.

[0027] A bonding layer 221 is disposed on the interconnect structure 219, and bonding pads 223 are disposed in the bonding layer 221. The bonding pads 223 allow connection between devices formed on the interconnect structure 219 and the substrate 217. The bonding layer 221 may include a dielectric layer and bonding pads 223, similar to the description above regarding the bonding layer 121 and bonding pads 123 of the bottom semiconductor die 150.

[0028] Similar to the above, the dicing process will be performed along the dicing track 229 of wafer 20 (see [link]). Figure 4 The dicing process isolates the top semiconductor dies 250 from each other along dicing 229. Dicing 229 is arranged between adjacent top semiconductor dies 250 (which may be referred to as top dies). The dicing process may include, for example, a blade cutting process using a high-speed rotating abrasive disc or blade saw to cut along dicing 229. The blade tip may contain abrasive particles or a thin layer of diamond.

[0029] exist Figure 4 In the middle, the monolithic top semiconductor die 250 is bonded to Figure 2The reconstructed wafer 10' is shown. As described above, the reconstructed wafer 10' may include a plurality of bottom semiconductor dies 150. Specifically, top semiconductor dies 250 are bonded to wafer 10' (e.g., bottom semiconductor dies 150), for example using a direct bonding process, which can form a metal-metal and dielectric-dielectric bonding configuration. The top semiconductor die 250 may be arranged face-down such that the front side (e.g., the active side) of the top semiconductor die 250 faces wafer 10', while the back side of the top semiconductor die 250 faces away from wafer 10'. In other words, the top semiconductor die 250 and the bottom semiconductor die 150 may have a face-to-face configuration. The top semiconductor die 250 is bonded to a bonding layer 121 on the front side of wafer 10' and bonding pads 123 in the bonding layer 121. For example, the bonding layer 221 of the top semiconductor die 250 can be directly bonded to the bonding layer 121 of the bottom semiconductor die 150, and the bonding pad 223 of the top semiconductor die 250 can be directly bonded to the bonding pad 123 of the bottom semiconductor die 150. According to embodiments, the bonding between the bonding layer 121 and the bonding layer 221 can be an oxide-oxide bonding, or similar. The direct bonding process also directly bonds the bonding pad 223 of the top semiconductor die 250 to the bonding pad 123 of the bottom semiconductor die 150 via direct metal-metal bonding and dielectric-dielectric bonding. According to some embodiments, the corresponding bonding pads 223, 123 can overhang each other, thereby forming a dielectric-metal bonding between the bonding layer 221 and the bonding pad 123 and / or between the bonding layer 121 and the bonding pad 223. Therefore, the electrical connection between the top semiconductor die 250 and the wafer 10' (e.g., the bottom semiconductor die 150) is provided by the physical connection between the bonding pad 123 and the bonding pad 223.

[0030] As an example, the direct bonding process begins by aligning the top semiconductor die 250 with the corresponding bottom semiconductor die 150 of the wafer 10', for example by applying a surface treatment to one or more of the bonding layers 121 or 221. The surface treatment may include a plasma treatment. The plasma treatment may be performed in a vacuum environment. Following the plasma treatment, the surface treatment may also include a cleaning process (e.g., rinsing with deionized water, or the like), which may be applied to one or more of the bonding layers 121 or 221. The direct bonding process may then proceed to align the bonding pads 223 with the bonding pads 123. Next, the direct bonding includes a pre-bonding step during which the top semiconductor die 250 is brought into contact with the wafer 10'. The pre-bonding may be performed at room temperature (e.g., from about 21°C to about 25°C). The direct bonding process continues with annealing, for example, at a temperature of about 150°C to about 400°C for about 0.5 hours to about 3 hours, causing the metal (e.g., copper) in bonding pad 123 to diffuse with the metal (e.g., copper) in bonding pad 223, thereby forming a direct metal-to-metal bond. Although illustrated as a top semiconductor die 250 bonded to each bottom semiconductor die 150, other embodiments may include any number of semiconductor dies 250 bonded to each bottom semiconductor die 150.

[0031] exist Figure 5 In this process, interconnect die 350 is bonded to wafer 10' (e.g., bottom semiconductor die 150), for example using a direct bonding process, similar to the description of attaching top semiconductor die 250 to bottom semiconductor die 150 (see [link to documentation]). Figure 4 Each interconnect die 350 may be a local silicon interconnect (LSI), a large scale integration package, an interposer die, or the like. For example, the interconnect die 350 may be a bridging die. In the illustrated cross-section, an interconnect die 350 is attached above a package region of wafer 10'. The interconnect die 350 may be arranged face-down such that the front side (e.g., the active side) of the interconnect die 350 faces wafer 10', while the back side of the interconnect die 350 faces away from wafer 10'. In other words, the interconnect die 350 and the bottom semiconductor die 150 may have a face-to-face configuration.

[0032] Since the interconnect die 350 electrically couples at least two bottom semiconductor dies 150 to each other, the interconnect die 350 can be referred to as electrically interposed (e.g., directly electrically interposed) between these respective bottom semiconductor dies 150. As shown in the figure, electrical path P xA general example is provided of how interconnect die 350 can couple to two bottom semiconductor dies 150. These bottom semiconductor dies 150 can also be coupled to corresponding top semiconductor dies 250.

[0033] The materials and fabrication processes of a portion of interconnect die 350 may be referenced to similar components in bottom semiconductor dies 150 and 250, wherein components in bottom semiconductor die 150 beginning with the number "1" and components in top semiconductor die 250 beginning with the number "2" correspond to components in interconnect die 350 beginning with the number "3". For example, interconnect die 350 may include a substrate 317 and interconnect structures 319 formed thereon. According to some embodiments, interconnect die 350 does not include active devices (e.g., transistors). Interconnect die 350 may or may not include passive devices (e.g., capacitors, diodes, resistors, or the like) formed in or on the surface of substrate 317. In other embodiments, interconnect die 350 may include active devices (e.g., transistors and the like). Interconnect structure 319 may electrically connect devices on substrate 317 (if present) to form one or more integrated circuits. Interconnect structure 319 includes one or more dielectric layers (e.g., one or more interlayer dielectric (ILD) layers, intermetallic dielectric (IMD) layers, or the like) and interconnect wiring or metallization patterns embedded in one or more dielectric layers.

[0034] The bonding process for interconnect die 350 can be performed similarly to the description above regarding bonding top semiconductor die 250 to bottom semiconductor die 150. For example, interconnect die 350 may also include a bonding layer 321 disposed on interconnect structure 319, and bonding pads 323 disposed in bonding layer 321 and exposed on the front surface of interconnect die 350. One side of interconnect die 350 including bonding pads 323 and bonding layer 321 may subsequently be referred to as the front side of interconnect die 350. Thus, interconnect die 350 can be attached using a direct bonding process, such that a metal-metal bond is formed between bonding pads 323 and bonding pads 123, and a dielectric-dielectric bond is formed between bonding layers 321 and 121. According to some embodiments, the respective bonding pads 323, 123 may overhang each other, thereby forming a dielectric-metal bond between bonding layers 321 and bonding pads 123 and / or between bonding layers 121 and bonding pads 323.

[0035] Furthermore, a package 232 is formed over the wafer 10', the top semiconductor die 250, and the interconnect die 350 to encapsulate each of the top semiconductor die 250 and the interconnect die 350. The package 232 may be formed using compression molding, transfer molding, spin coating, or the like. The package 232 may be an epoxy resin or molding compound resin, such as polyimide, polyphenylene sulfide (PPS), polyetheretherketone (PEEK), polyethersulfone (PES), heat-resistant crystalline resin, combinations thereof, or the like.

[0036] After the package 232 is formed, a planarization process is performed to remove excess portions of the package 232. Optionally, the planarization process may expose the top surface (e.g., substrate 217) of the top semiconductor die 250. The planarization process may include polishing processes, CMP processes, etc. Figure 5 As shown, the planarization process can make the top surface of the top semiconductor die 250 flush with the top surface of the package 232.

[0037] Although Figure 5 The interconnect dies 350 shown are bonded and electrically coupled to two bottom semiconductor dies 150, but some interconnect dies 350 may be bonded to more than two bottom semiconductor dies 150. For example, as discussed in more detail below, some interconnect dies 350 may be bonded and electrically coupled to three or more bottom semiconductor dies 150, such as four, five, or six bottom semiconductor dies 150. Interconnect dies 350 may be placed, for example, above a corner of a lower bottom semiconductor die 150. Specifically, in addition to adjacent (e.g., neighboring) bottom semiconductor dies 150 being coupled through an overlying interconnect die 350, other bottom semiconductor dies 150 may also be coupled through interconnect dies 350. Thus, a single interconnect die 350 can facilitate cross-communication (e.g., crosstalk) between the respective bottom semiconductor dies 150. Interconnect dies 350 may also be referred to as multi-cross-talk dies, multi-cross LSI dies, etc.

[0038] Still referencing Figure 5 The gap between adjacent bottom semiconductor dies 150 may have a lateral distance D1. Furthermore, the gap between adjacent top semiconductor dies 250 may have a lateral distance D2. Moreover, the gap between the interconnect die 350 and the adjacent top semiconductor die 250 may have a lateral distance D3. As shown, according to some embodiments, the distance D1 between adjacent bottom semiconductor dies 150 may be greater than the distance D2 between adjacent top semiconductor dies 250 bonded to the respective bottom semiconductor die 150. After the interconnect die 350 is bonded to the adjacent bottom semiconductor die 150, the distance D3 to one of the adjacent top semiconductor dies 250 may be substantially equal to or less than the distance D1. In other embodiments, the distance D3 may be greater than the distance D1.

[0039] exist Figure 6 In this embodiment, substrate 270 is attached above top semiconductor die 250, and a thinning process is performed on the back side of substrate 117. Substrate 270 may contain a suitable material (e.g., silicon). A thinning process is performed to expose TSV 111 through substrate 117. The thinning process on the back side of substrate 117 may be performed by a planarization process (e.g., CMP, grinding, or etching). The thinning process makes the surface of TSV 111 flush with the back side surface of substrate 117.

[0040] exist Figure 7 In this embodiment, dielectric layer 234 is formed on the back side of substrate 117 and the exposed surface of TSV 111. Dielectric layer 234 may comprise silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, low-k dielectric materials (e.g., phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), SiOxCy, spin-on glass, spin-on polymers, silicon-carbon materials, compounds thereof, composites thereof, combinations thereof, or the like). Dielectric layer 234 may be deposited by any suitable method, such as CVD, PECVD, spin coating, or the like.

[0041] Metallization pattern 236 can be formed in dielectric layer 234, for example, by depositing and patterning photoresist material on dielectric layer 234 using photolithography to expose portions of dielectric layer 234 where metallization pattern 236 will be formed. An etching process (e.g., anisotropic dry etching) can be used to form openings in dielectric layer 234 corresponding to the exposed portions of dielectric layer 234. The openings in dielectric layer 234 can expose TSV 111. A seed layer (not shown separately) is formed above the exposed surface of dielectric layer 234 and in the openings of dielectric layer 234. According to some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer comprising multiple sublayers formed of different materials. According to some embodiments, the seed layer comprises a titanium layer and a copper layer on the titanium layer. The seed layer can be formed by, for example, physical vapor deposition (PVD) or the like. Photoresist is then formed and patterned on the seed layer. The photoresist can be formed by spin coating or the like and can be exposed for patterning. The photoresist pattern corresponds to the metallization pattern 236. Patterning forms openings through the photoresist to expose the seed layer. A conductive material is then formed in the openings and on the exposed portions of the seed layer. The conductive material can be formed by plating (e.g., electroplating, electroless plating, or the like). The conductive material can comprise metals such as copper, titanium, tungsten, aluminum, or the like. The photoresist and portions of the seed layer on which the conductive material is not formed are then removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma or the like. After removing the photoresist, the exposed portions of the seed layer are removed, for example, using an acceptable etching process. The remaining seed layer and conductive material portions in the dielectric layer 234 form the metallization pattern 236. These metallization patterns 236 will be used to electrically connect the TSV 111 to external devices. According to some embodiments, the metallization pattern 236 may also include under-bump metallization (UBM).

[0042] Furthermore, conductive connectors 238 are formed on the metallization pattern 236. For example, conductive connectors 238 may be formed to be disposed on the metallization pattern 236 and electrically coupled to the bottom semiconductor die 150 via TSV111, thus electrically connecting to the top semiconductor die 250 and the interconnect die 350. Conductive connectors 238 may include controlled collapse chip connection (C4) bumps, ball grid array (BGA) connectors, solder balls, or the like. Conductive connectors 238 may contain conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or combinations thereof. According to some embodiments, conductive connectors 238 are formed by first forming a solder layer through evaporation, electroplating, printing, solder transfer, ball placement, or the like. After the solder layer is structurally formed, reflow may be performed to shape the material into the desired bump shape.

[0043] The conductive connector 238 will be used for bonding to the integrated chip package 100 and to additional electrical components, which may be a semiconductor substrate, a package substrate, a printed circuit board (PCB), or the like (see [link]). Figure 8 ).

[0044] exist Figure 8 In this embodiment, the packaging substrate 240 is coupled to the integrated chip package 100. The packaging substrate 240 may include an interposer, a package, a core substrate, a coreless substrate, a printed circuit board (PCB), or the like. According to an embodiment, the packaging substrate 240 includes a substrate core 260 and bonding pads 246 on the substrate core 260. The substrate core 260 may be made of a semiconductor material (e.g., silicon, germanium, diamond, or the like). Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, indium gallium phosphide, combinations thereof, and the like may be used. Furthermore, the substrate core 260 may be an SOI substrate. Typically, an SOI substrate includes a semiconductor material layer, such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof. In an alternative embodiment, the substrate core 260 is based on an insulating core, such as a glass fiber reinforced resin core. One example core material is glass fiber resin, such as FR4. Alternatives to the core material include bismaleimide triazine (BT) resin, or other PCB materials or films. For example, ABF build-up film or other laminated materials can be used for the substrate core 260.

[0045] The substrate core 260 may contain active and passive devices (not shown). A variety of devices (e.g., transistors, capacitors, resistors, combinations thereof, and the like) can be used to meet the structural and functional requirements of the device stack design. These devices can be formed using any suitable method.

[0046] The substrate core 260 may also include a metallization layer and vias (not shown), with bonding pads 246 physically and / or electrically coupled to the metallization layer and vias. The metallization layer may be formed over active and passive devices and is designed to connect the devices to form functional circuitry. The metallization layer may be formed of alternating layers of dielectric material (e.g., a low-k dielectric material) and conductive material (e.g., copper), with vias interconnecting the conductive material layers, and may be formed by any suitable process (e.g., deposition, damascene, dual damascene, or similar). According to some embodiments, the substrate core 260 substantially does not contain active or passive devices.

[0047] According to some embodiments, the conductive connector 238 is reflowed to attach the integrated chip package 100 to the bonding pad 246. The conductive connector 238 electrically and / or physically couples the package substrate 240 (including the metallization layer in the substrate die 260) to the integrated chip package 100. According to some embodiments, a solder mask layer 248 is formed on the substrate die 260. The conductive connector 238 may be disposed in openings in the solder mask layer 248 to electrically and mechanically couple to the bonding pad 246. The solder mask layer 248 may be used to protect areas of the substrate die 260 from external damage.

[0048] The conductive connector 238 may have an epoxy flux (not shown) formed thereon before reflow. At least some epoxy portions of the epoxy flux are retained after the integrated chip package 100 is attached to the package substrate 240. The retained epoxy portions can act as underfill to reduce stress and protect the joint formed during reflow of the conductive connector 238. According to some embodiments, an underfill 251 may be formed between the integrated chip package 100 and the package substrate 240, surrounding the conductive connector 238. The underfill 251 may be formed by a capillary flow process after the integrated chip package 100 is coupled to the package substrate 240, or by a suitable deposition method before the package substrate 240 is coupled to the integrated chip package 100.

[0049] According to embodiments, the package substrate 240 may include bonding pads 252 on the substrate die 260. Conductive connections 254 may be coupled to the bonding pads 252 to allow the package substrate 240 to be electrically coupled to external circuitry or devices. The conductive connections 254 may be ball grid array (BGA) connections, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, electroless nickel-electroless palladium-immersion gold (ENEPIG) formed bumps, or the like. The conductive connections 254 may contain conductive materials (e.g., solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or combinations thereof). According to some embodiments, a solder mask layer 248 is formed on the substrate die 260, and the conductive connections 254 may be disposed in openings in the solder mask layer 248 to be electrically and mechanically coupled to the bonding pads 252. The solder mask layer 248 can be used to protect the area of ​​the substrate core 260 from external damage.

[0050] According to some embodiments, passive devices (e.g., surface mount devices (SMDs, not shown) may also be attached to the package substrate 240 (e.g., bonding pads 246). For example, the passive device may be bonded to the same surface of the package substrate 240 as the conductive connection 238.

[0051] Figures 9A to 9F A plan view (e.g., top view) of an exemplary embodiment of the integrated chip package 100 is shown. Specifically, according to various embodiments, a bottom semiconductor die 150 (e.g., wafer 10'), a top semiconductor die 250, and an interconnect die 350 are shown.

[0052] exist Figure 9A The figure illustrates an integrated chip package 100A, wherein at least one interconnect die 350 is a quadrant interconnect die 350D electrically coupled to four bottom semiconductor dies 150. As shown, the quadrant interconnect die 350D can be directly electrically coupled (e.g., directly coupled) to the exemplary bottom semiconductor die 150A and up to three other bottom semiconductor dies 150. Thus, the exemplary bottom semiconductor die 150A can communicate directly with the three other bottom semiconductor dies 150. In the illustrated embodiment, the exemplary bottom semiconductor die 150A is capable of communicating with two directly adjacent bottom semiconductor dies 150 and a diagonally opposite bottom semiconductor die 150. Note that the interconnect dies 350 can provide electrical coupling to some or all of the possible pairs of bottom semiconductor dies 150 that are overlapped (e.g., joined) by the interconnect dies 350D. For example, the quadrant interconnect die 350D can facilitate up to six communication couplets between corresponding bottom semiconductor dies 150.

[0053] Also shown are exemplary electrical paths between an exemplary bottom semiconductor die 150A and other bottom semiconductor dies 150. For example, paths P1 and P2 communicate with two adjacent bottom semiconductor dies 150 via a first interconnect die 350D (e.g., on the upper left). Furthermore, a path P3 is also established via the first interconnect die 350D to the diagonal bottom semiconductor die 150. Moreover, a similar electrical path can be identified between the middle column bottom semiconductor dies 150 and the right column bottom semiconductor dies 150. Thus, all pairs of bottom semiconductor dies 150 communicate within one or two degrees via the four-section interconnect die 350D.

[0054] exist Figure 9B The diagram illustrates an integrated chip package 100B, wherein at least one interconnect die 350 is a trient interconnect die 350C electrically coupled to three bottom semiconductor dies 150. As shown, the trient interconnect die 350C can be directly electrically coupled (e.g., directly coupled) to an exemplary bottom semiconductor die 150B and up to two other bottom semiconductor dies 150. Thus, the exemplary bottom semiconductor die 150B can communicate directly with two other bottom semiconductor dies 150. Note that the trient interconnect die 350C can provide electrical coupling to some or all of the possible pairs of bottom semiconductor dies 150 that are overlapped (e.g., joined) by the trient interconnect die 350C. For example, the trient interconnect die 350C can facilitate up to three communication pairs between corresponding bottom semiconductor dies 150.

[0055] Additionally, an exemplary electrical path is shown between an exemplary bottom semiconductor die 150B and other bottom semiconductor dies 150. Figure 9A Analogous versions of paths P1, P2, and P3 are labeled to illustrate communication between an exemplary bottom semiconductor die 150B and some proximal bottom semiconductor dies 150. Furthermore, paths P4 and P5 illustrate a basic layout design that allows specific interconnect dies 350 (e.g., a three-segment interconnect die 350C) to facilitate communication between three bottom semiconductor dies 150. Thus, all pairs of bottom semiconductor dies 150 communicate within one or two levels via the three-segment and four-segment interconnect dies 350C, 350D. It should be understood that interconnect dies 350 (e.g., including the illustrated three-segment interconnect die 350C) can also facilitate communication between multiple top semiconductor dies 250, regardless of whether they are coupled to the same or different bottom semiconductor dies 150.

[0056] exist Figure 9CThe diagram illustrates an integrated chip package 100C, wherein at least one interconnect die 350 is a six-sextant interconnect die 350F electrically coupled to six bottom semiconductor dies 150. As shown, the six-sextant interconnect die 350F can be directly electrically coupled (e.g., directly coupled) to an exemplary bottom semiconductor die 150C and up to five other bottom semiconductor dies 150. Thus, the exemplary bottom semiconductor die 150C can communicate directly with five other bottom semiconductor dies 150. Note that the six-sextant interconnect die 350F can provide electrical coupling to some or all of the possible pairs of bottom semiconductor dies 150 that are overlapped (e.g., joined) by the six-sextant interconnect die 350F. For example, the six-sextant interconnect die 350F can facilitate up to fifteen communication pairs between corresponding bottom semiconductor dies 150.

[0057] Additionally, an exemplary electrical path is shown between an exemplary bottom semiconductor die 150C and other bottom semiconductor dies 150. Figure 9A and Figure 9B Similar versions of paths P1, P2, and P3 are labeled to illustrate communication between the exemplary bottom semiconductor die 150C and some near-end bottom semiconductor dies 150. Additionally, paths P4 and P5 are also established to the far-end bottom semiconductor die 150 via the six-part interconnect die 350F. Thus, all pairs of bottom semiconductor dies 150 are within the same level of communication via the six-part interconnect die 350F.

[0058] exist Figure 9D The figure illustrates an integrated chip package 100D, wherein at least one interconnect die 350 is a quintant interconnect die 350E electrically coupled to five bottom semiconductor dies 150. As shown, the quintant interconnect die 350E can be directly electrically coupled (e.g., directly coupled) to the exemplary bottom semiconductor die 150D and up to four other bottom semiconductor dies 150. Thus, the exemplary bottom semiconductor die 150D can communicate directly with the four other bottom semiconductor dies 150. Note that the quintant interconnect die 350E can provide electrical coupling to some or all of the possible pairs of bottom semiconductor dies 150 that are overlapped (e.g., joined) by the quintant interconnect die 350E. For example, the quintant interconnect die 350E can facilitate up to ten communication pairs between corresponding bottom semiconductor dies 150.

[0059] Additionally, an exemplary electrical path is shown between an exemplary bottom semiconductor die 150D and other bottom semiconductor dies 150. Figure 9CSimilar versions of paths P1, P2, P3, P4, and / or P5 are labeled to illustrate communication between the exemplary bottom semiconductor die 150D and all other bottom semiconductor dies 150. Furthermore, paths P4 and P5 illustrate a basic layout design that allows a particular interconnect die 350 (e.g., a five-segment interconnect die 350E) to facilitate communication between the five bottom semiconductor dies 150. Thus, all pairs of bottom semiconductor dies 150 communicate within a single level via the five-segment interconnect die 350E. As described above, it should be understood again that interconnect dies 350 (e.g., including the illustrated five-segment interconnect die 350E) can also facilitate communication between multiple top semiconductor dies 250, regardless of whether they are coupled to the same or different bottom semiconductor dies 150.

[0060] refer to Figure 9C and Figure 9D (and subsequent) Figure 9E and Figure 9F It should be understood that, according to some embodiments, interconnect chips 350E, 350F may be electrically coupled to the distal bottom semiconductor chip 150, rather than directly coupled to the intermediate (or sandwiched therein) bottom semiconductor chip 150 (e.g., intermediate column). For example, interconnect chips 350 may be bonded to the intermediate bottom semiconductor chip 150 using corresponding pseudo-bonding pads 323, 223 or entirely through corresponding bonding layers 321, 221. These embodiments highlight an advantage of flexible package design, as the distal bottom semiconductor chip 150 may need (or benefit from) crosstalk when the closer of the distal bottom semiconductor chip 150 (e.g., adjacent as a close neighbor) is undesirable, unreasonable, or infeasible. Furthermore, these distal bottom semiconductor chips 150 may need relatively lower critical crosstalk (e.g., less data communication, less frequent communication, less time-sensitive communication, etc.) compared to some bottom semiconductor chips 150 arranged more closely to each other. Moreover, size and shape preferences or constraints may also come into play.

[0061] exist Figure 9EThe diagram illustrates an integrated chip package 100E, in which an exemplary bottom semiconductor chip 150E and two interconnect chips 350 provide electrical connectivity to all bottom semiconductor chips 150 within an array. In the illustrated embodiment, two six-part interconnect chips 350F are electrically coupled above the four corners of the exemplary bottom semiconductor chip 150E. Due to the use of the six-part interconnect chips 350F at specific locations, the bottom semiconductor chips 150 in a three-by-three array have high electrical connectivity to each other. For example, most of the bottom semiconductor chips 150 are connected to most of the other bottom semiconductor chips 150 via a single interconnect chip 350F. Other semiconductor pairs can be electrically connected via two interconnect chips 350F.

[0062] Furthermore, it should be understood that each communication between non-adjacent bottom semiconductor chips 150 requiring two interconnect chips 350 has multiple electrical paths. For example, any top row bottom semiconductor chip 150 can communicate with any bottom row bottom semiconductor chip 150 via an electrical connection passing through any middle row bottom semiconductor chip 150. Therefore, for any pair of these top and bottom row bottom semiconductor chips 150, there may be three direct paths (e.g., through a minimum number of valid paths for chips 150, 350). This allows for an increased number of options in the package design due to greater flexibility in the electrical connectivity between the bottom semiconductor chips 150, 250 (even when they are far apart from each other).

[0063] Also shown is an exemplary electrical path between the bottom semiconductor dies 150 at the diagonal corners of the integrated chip package 100E. For example, a signal from the bottom semiconductor die 150 at the top left corner can travel via path P. A Through the upper interconnect die 350F, via path P B Through an exemplary bottom semiconductor die 150E, and via path P C The connection is made through the lower interconnect die 350F to the bottom right semiconductor die 150, and vice versa.

[0064] exist Figure 9FThe diagram illustrates an integrated chip package 100F, in which some exemplary dies 150Fs and three interconnect dies 350 provide electrical connectivity to all bottom semiconductor dies 150 within an array. In the illustrated embodiment, the three six-part interconnect dies 350Fs are electrically coupled above the four corners of each exemplary bottom semiconductor die 150F. Due to the use of six-part interconnect dies 350Fs in specific locations, the bottom semiconductor dies 150 in a four-by-three array have high electrical connectivity to each other. For example, most of the bottom semiconductor dies 150 are connected to most of the other bottom semiconductor dies 150 via a single interconnect die 350F. Other semiconductor pairs can be electrically connected via two interconnect dies 350Fs.

[0065] Furthermore, it should be understood that each communication between non-adjacent bottom semiconductor dies 150 requiring two interconnect dies 350 has multiple electrical paths. For example, through an electrical connection of any second column of bottom semiconductor dies 150, any first column (e.g., the leftmost column) of bottom semiconductor dies 150 can communicate with any third or fourth column of bottom semiconductor dies 150. Thus, for any pair of far-end bottom semiconductor dies 150, there are at least two or three direct paths. As described in the previous embodiments, this feature allows for an increased number of options in the package design due to greater flexibility in the electrical connections between the bottom semiconductor dies 150, 250 (even when they are far from each other).

[0066] Also shown is an exemplary electrical path between the bottom semiconductor dies 150 at the diagonal corners of the integrated chip package 100F. For example, a signal from the bottom semiconductor die 150 at the top left corner can travel via path P. A Through the left interconnect die 350F, via path P B Through one of the exemplary bottom semiconductor dies 150F, and via path P C The connection is made through the lower right interconnect die 350F to the lower right bottom semiconductor die 150, and vice versa.

[0067] The embodiments of this disclosure achieve various advantages. According to various embodiments, the integrated chip package 100 includes a bottom semiconductor die 150, a top semiconductor die 250, and one or more interconnect dies 350. Specifically, the bottom semiconductor die may be formed in a reconstructed wafer, and the top semiconductor die 250 and interconnect dies 350 are bonded above the bottom semiconductor die 150. The interconnect dies 350 may be bonded and electrically coupled to three or more of the bottom semiconductor dies 150 to facilitate essentially direct crosstalk communication between all respective bottom semiconductor dies 150. It should be understood that the bottom semiconductor die 150 may be a multifunctional die (e.g., a logic die) or have high complexity and / or advanced technology nodes. In any case, the bottom semiconductor dies 150 can benefit from the aforementioned crosstalk between each other, even when the bottom dies 150 cannot all be adjacent to each other (e.g., directly adjacent). Thus, the interconnect dies 350 allow this communication of the integrated chip package with other components in a diagonal direction, across a relatively large distance, and surrounding (or above) it. Therefore, integrated chip packages can be designed with more flexible chip configurations, shapes, and sizes, while also benefiting from improvements in functionality, performance, and reliability.

[0068] According to an embodiment, a method includes: forming a wafer including a plurality of bottom dies, the plurality of bottom dies including a first bottom die and a second bottom die, the first bottom die and the second bottom die being laterally spaced apart by a first distance; bonding a first top die to the first bottom die in a face-to-face configuration; bonding a second top die to the second bottom die in a face-to-face configuration, the first top die and the second top die being laterally spaced apart by a second distance, the second distance being different from the first distance; and bonding interconnect dies to the first bottom die and the second bottom die in a face-to-face configuration, the interconnect dies being disposed between the first top die and the second top die. In another embodiment, the plurality of bottom dies further includes a third bottom die and a fourth bottom die, and wherein bonding the interconnect dies to the first bottom die and the second bottom die includes bonding the interconnect dies to the third bottom die and the fourth bottom die. In another embodiment, the first bottom die, the second bottom die, the third bottom die, and the fourth bottom die have a four-partition layout, and wherein the interconnect dies are electrically interposed between all pairs of the plurality of bottom dies. In another embodiment, the plurality of bottom dies further includes a fifth bottom die and a sixth bottom die, wherein bonding interconnect dies to the first bottom die, the second bottom die, the third bottom die, and the fourth bottom die includes bonding interconnect dies to the fifth bottom die and the sixth bottom die, and wherein the interconnect dies are electrically interposed between all pairs of the plurality of bottom dies. In another embodiment, a second distance is greater than a first distance. In another embodiment, interconnect dies are laterally spaced from the first top die by a third distance, wherein the third distance is less than the first distance. In another embodiment, the wafer includes a reconfigured wafer, wherein a package separates each of the plurality of bottom dies.

[0069] According to an embodiment, a method of forming an integrated chip package includes: attaching a plurality of bottom dies to a substrate, the plurality of bottom dies including a first bottom semiconductor die, a second bottom semiconductor die, and a third bottom semiconductor die arranged in a row; attaching a plurality of top dies above the plurality of bottom dies and electrically connecting them to the plurality of bottom dies, wherein after attaching the plurality of top dies, the first bottom semiconductor die, the second bottom semiconductor die, and the third bottom semiconductor die are electrically isolated from each other; after attaching the plurality of top dies, attaching interconnect dies above the plurality of bottom dies, the interconnect dies being electrically connected to the first bottom semiconductor die and the third bottom semiconductor die; removing the substrate from under the plurality of bottom dies; and attaching a package substrate to under the plurality of bottom dies. In another embodiment, after attaching the interconnect dies: the interconnect dies are electrically connected to the second bottom semiconductor die; and each pair of the first bottom semiconductor die, the second bottom semiconductor die, and the third bottom semiconductor die is electrically coupled. In another embodiment, the interconnect dies are electrically interposed between the first bottom semiconductor die and the third bottom semiconductor die. In another embodiment, the interconnect die is directly and electrically inserted between the first bottom semiconductor die and the third bottom semiconductor die. In another embodiment, after the interconnect die is attached and before the package substrate is attached, the second bottom semiconductor die remains electrically isolated from the first bottom semiconductor die and the third bottom semiconductor die.

[0070] According to an embodiment, a semiconductor device includes: a first bottom semiconductor die and a second bottom semiconductor die disposed above a package substrate; a package body disposed between and surrounding the first bottom semiconductor die and the second bottom semiconductor die, the package body being bonded to a first semiconductor substrate of the first bottom semiconductor die and a second semiconductor substrate of the second bottom semiconductor die, the package body being adjacent to the first semiconductor substrate and the second semiconductor substrate; a first top semiconductor die disposed above and electrically connected to the first bottom semiconductor die; a second top semiconductor die disposed above and electrically connected to the second bottom semiconductor die; and an interconnect die disposed above and electrically connected to the first bottom semiconductor die and the second bottom semiconductor die, wherein the interconnect die overlaps with a first corner of the first bottom semiconductor die in a plan view. In another embodiment, each of the first bottom semiconductor die, the second bottom semiconductor die, the first top semiconductor die, and the second top semiconductor die includes at least one transistor, and wherein the interconnect die does not include a transistor. In another embodiment, the interconnect die overlaps with a second corner of the second bottom semiconductor die in a plan view. In another embodiment, a portion of the interconnect die extends directly between the first top semiconductor die and the second top semiconductor die. In another embodiment, a first distance between the first bottom semiconductor die and the second bottom semiconductor die is less than a second distance between the first top semiconductor die and the second top semiconductor die, and wherein the first distance is greater than a third distance between the interconnect die and the first top semiconductor die. In another embodiment, the semiconductor device further includes a third bottom semiconductor die and a fourth bottom semiconductor die disposed above the package substrate, wherein the interconnect die is disposed above and electrically connected to the third bottom semiconductor die and the fourth bottom semiconductor die. In another embodiment, all pairs of the first bottom semiconductor die, the second bottom semiconductor die, the third bottom semiconductor die, and the fourth bottom semiconductor die are electrically coupled via interconnect dies. In another embodiment, the semiconductor device further includes a fifth bottom semiconductor die and a sixth bottom semiconductor die disposed above the package substrate, wherein the interconnect die is disposed above and electrically connected to the fifth bottom semiconductor die and the sixth bottom semiconductor die.

[0071] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis to design or modify other processes and structures to perform the same purpose and / or achieve the same advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming an integrated chip package, comprising: A wafer comprising a plurality of bottom dies is formed, the plurality of bottom dies including a first bottom die and a second bottom die, the first bottom die and the second bottom die being laterally spaced apart by a first distance; The first top die is joined to the first bottom die in a face-to-face configuration; The second top die is joined to the second bottom die in a face-to-face configuration, with the first top die and the second top die laterally spaced apart by a second distance, which is different from the first distance. as well as Interconnect dies are bonded to the first bottom die and the second bottom die in a face-to-face configuration, the interconnect dies intersecting between the first top die and the second top die.

2. The method of claim 1, wherein the plurality of bottom dies further comprises a third bottom die and a fourth bottom die, and wherein bonding the interconnect die to the first bottom die and the second bottom die comprises bonding the interconnect die to the third bottom die and the fourth bottom die.

3. The method of claim 2, wherein the first bottom die, the second bottom die, the third bottom die and the fourth bottom die have a four-partition layout, and wherein the interconnecting die is electrically interposed between all pairs of the plurality of bottom dies.

4. The method of claim 2, wherein the plurality of bottom dies further comprises a fifth bottom die and a sixth bottom die, wherein the interconnect die is coupled to the first bottom die, the second bottom die, the third bottom die, and the fourth bottom die by coupling the interconnect die to the fifth bottom die and the sixth bottom die, and wherein the interconnect die is electrically interposed between all pairs of the plurality of bottom dies.

5. The method of claim 1, wherein the second distance is greater than the first distance.

6. The method of claim 1, wherein the interconnect die is laterally spaced from the first top die by a third distance, and wherein the third distance is less than the first distance.

7. The method of claim 1, wherein the wafer comprises a reconfigured wafer, wherein the package separates each of the plurality of bottom dies.

8. A method for forming an integrated chip package, comprising: Multiple bottom dies are attached to a substrate, the multiple bottom dies including a first bottom semiconductor die, a second bottom semiconductor die and a third bottom semiconductor die arranged in a row; Multiple top dies are attached above and electrically connected to the multiple bottom dies, wherein after the multiple top dies are attached, the first bottom semiconductor die, the second bottom semiconductor die, and the third bottom semiconductor die are electrically isolated from each other; After attaching the plurality of top dies, an interconnect die is attached above the plurality of bottom dies, the interconnect die being electrically connected to the first bottom semiconductor die and the third bottom semiconductor die; Remove the substrate from the underside of the plurality of bottom dies; as well as The packaging substrate is attached to the underside of the plurality of bottom dies.

9. The method of claim 8, wherein after attaching the interconnect die: The interconnect die is electrically connected to the second bottom semiconductor die; and Each pair of electrical couplings of the first bottom semiconductor die, the second bottom semiconductor die, and the third bottom semiconductor die.

10. A semiconductor device, comprising: A first bottom semiconductor die and a second bottom semiconductor die are disposed above the packaging substrate; A package is disposed between and around the first bottom semiconductor die and the second bottom semiconductor die, the package being bonded to a first semiconductor substrate of the first bottom semiconductor die and a second semiconductor substrate of the second bottom semiconductor die, the package being adjacent to the first semiconductor substrate and the second semiconductor substrate; A first top semiconductor die is disposed above the first bottom semiconductor die and electrically connected to the first bottom semiconductor die; The second top semiconductor die is disposed above the second bottom semiconductor die and is electrically connected to the second bottom semiconductor die; as well as An interconnect die is disposed above and electrically connected to the first bottom semiconductor die and the second bottom semiconductor die, wherein the interconnect die overlaps with a first corner of the first bottom semiconductor die in a plan view.

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