Oscillator leakage calibration

Abstract

An apparatus for oscillator leakage calibration is disclosed. In an example aspect, the apparatus includes a mixer circuit and a calibration circuit. The mixer circuit has a first stage including at least one transistor coupled between a mixer input and a mixer output, and a second stage including one or more transistors coupled between the at least one transistor and the mixer output. The mixer circuit also has a tuning circuit coupled to the at least one transistor. The calibration circuit includes: at least one resistor coupled between a power distribution node and at least one mixer node, wherein the at least one mixer node is coupled between the at least one transistor and the one or more transistors; and at least one switch coupled between the power distribution node and the at least one mixer node. The calibration circuit also includes a controller circuit coupled between the mixer node and the tuning circuit.

Description

Technical Field

[0001] This disclosure relates in general to signal communication or signal processing using electronic devices, and more specifically to circuit calibration for compensating for leakage from an oscillator coupled to a mixer circuit. Background Technology

[0002] Electronic devices include traditional computing devices such as desktop computers, laptops, smartphones, wearable devices like smartwatches, internet servers, and more. They also include other types of computing devices such as personal voice assistants (e.g., smart speakers), wireless access points or routers, thermostats and other automation controllers, robots, automotive electronics, devices embedded in other machines such as refrigerators and industrial tools, Internet of Things (IoT) devices, medical devices, and more. These diverse electronic devices provide services related to productivity, communication, social interaction, security, health and safety, remote management, entertainment, transportation, and information dissemination. Therefore, electronic devices play a vital role in modern society.

[0003] In today's interconnected world, many services provided by electronic devices rely at least in part on electronic communication. Electronic communication may include, for example, the use of one or more networks (such as the Internet, Wi-Fi, etc.). ® Electronic communication refers to the exchange of wireless or wired signals transmitted over a network (or cellular network) between two or more electronic devices. Therefore, electronic communication can include wireless transmission and reception or wired transmission and reception. To transmit and receive communications, electronic devices may use transceivers, such as wireless transceivers designed for wireless communication.

[0004] Therefore, some electronic communication can be achieved by transmitting signals between two wireless transceivers at two different electronic devices. For example, using a wireless transmitter, a smartphone can send wireless signals over the air to a base station (as part of uplink communication) to support mobile services. Using a wireless receiver, a smartphone can receive wireless signals transmitted from a base station over the air (as part of downlink communication) to enable mobile services. In the case of a smartphone, mobile services may include, for example, making voice and video calls, engaging in social media interactions, sending messages, watching movies, sharing videos, performing searches, using map information or navigation instructions, finding friends, participating in largely location-based services, transferring money, obtaining another service such as car rides, and so on.

[0005] Many mobile and communication-based services depend, at least in part, on the transmission or reception of wireless signals between two or more electronic devices. Therefore, researchers, electrical engineers, and other designers of electronic devices strive to develop wireless transceivers that can efficiently utilize wireless signals to provide these and other mobile services. SUMMARY

[0006] Local oscillator feedthrough (LOFT) refers to an oscillator signal that "leaks" through a mixer into a communication chain and adversely affects downstream signals. This document describes devices and techniques to counter such oscillator signal leakage. To transmit or receive wireless signals, a wireless interface device can include a communication chain (e.g., a transmit or receive chain) that processes a propagating signal. Such processing can require frequency conversion using a mixer. A mixer uses a local oscillator signal from a local oscillator (LO) to convert between frequencies. In described examples, a mixer circuit includes a mixer and a tuning circuit. The tuning circuit applies a calibration signal, such as a bias voltage, to the mixer to counteract LOFT. To determine the calibration signal, at least one transconductance transistor of the mixer can be analyzed in the direct current (DC) domain with one or more mixer switching transistors turned off. A DC bias current is routed through the transconductance transistor, and the calibration circuit measures an indication of the DC bias current using a voltage across at least one resistor. Based on the measured DC bias current, the calibration circuit adjusts at least one bias voltage using the tuning circuit to reduce a DC current offset that corresponds to a difference between currents flowing through positive and negative transconductance transistors. These techniques can be implemented in a variety of different ways. For example, the bias voltage can be coupled to a back gate or a front gate of the transconductance transistor. Additionally or alternatively, two resistors can be employed with respective voltages compared, or a voltage from one resistor can be compared to a reference voltage. Thus, the calibration circuit can adjust the tuning circuit to reduce at least the DC current offset to counteract oscillator leakage. In these ways, LOFT can be reduced without reliance on expensive external test equipment, but rather using on-board calibration circuitry. These and other implementations are described herein.

[0007] In example aspects, an apparatus for oscillator leakage calibration is disclosed. The apparatus includes a mixer circuit and a calibration circuit. The mixer circuit includes a first stage, a second stage, and a tuning circuit. The first stage includes at least one transistor coupled between a mixer input and a mixer output. The second stage includes one or more transistors coupled between the at least one transistor of the first stage and the mixer output, wherein the one or more transistors are coupled between a local oscillator signal input and the mixer output. The tuning circuit is coupled to the at least one transistor of the first stage. The calibration circuit includes at least one resistor, at least one switch, and a controller circuit. The at least one resistor is coupled between a power distribution node and at least one mixer node, wherein the at least one mixer node is coupled between the at least one transistor of the first stage and the one or more transistors of the second stage. The at least one switch is coupled between the power distribution node and the at least one mixer node. The controller circuit is coupled between the at least one mixer node and the tuning circuit.

[0008] In example aspects, an apparatus for oscillator leakage calibration is disclosed. The apparatus includes a mixer circuit and a calibration circuit. The mixer circuit includes a first stage and a second stage. The first stage includes at least one transistor coupled between a mixer input and a mixer output. The second stage includes one or more transistors coupled between the at least one transistor of the first stage and the mixer output. The mixer circuit further includes means for tuning the at least one transistor of the first stage. The calibration circuit includes at least one resistor and at least one switch. The at least one resistor is coupled between a power distribution node and at least one mixer node, wherein the at least one mixer node is coupled between the at least one transistor of the first stage and the one or more transistors of the second stage. The at least one switch is coupled in series with the at least one resistor between the power distribution node and the at least one mixer node. The calibration circuit further includes means for controlling the means for tuning based on at least one voltage associated with the at least one resistor.

[0009] In example aspects, a method for mixer calibration or for calibrating a mixer circuit to offset oscillator leakage is disclosed. The method includes closing a positive switch to connect at least one resistor to a positive mixer node coupled between a positive transistor of a first stage of a mixer circuit and a second stage of the mixer circuit. The method also includes measuring, using the at least one resistor, a positive voltage corresponding to the positive transistor of the first stage of the mixer circuit and opening the positive switch to disconnect the at least one resistor from the positive mixer node. The method additionally includes closing a negative switch to connect the at least one resistor to a negative mixer node coupled between a negative transistor of the first stage of the mixer circuit and the second stage of the mixer circuit. The method also includes measuring, using the at least one resistor, a negative voltage corresponding to the negative transistor of the first stage of the mixer circuit. The method further includes adjusting at least one bias voltage applied to at least one of the positive transistor or the negative transistor of the first stage of the mixer circuit based on the positive voltage and the negative voltage.

[0010] In example aspects, an apparatus for oscillator leakage calibration is disclosed. The apparatus includes a communication chain. The communication chain includes a mixer, at least one resistor, a positive switch, and a negative switch. The mixer includes a positive transistor having a positive channel terminal and a positive gate terminal. The mixer also includes a negative transistor having a negative channel terminal and a negative gate terminal. The positive switch is coupled in series with the at least one resistor between the positive channel terminal of the positive transistor and a power distribution node. A positive node is coupled between the positive switch and the at least one resistor. The negative switch is coupled in series with the at least one resistor between the negative channel terminal of the negative transistor and the power distribution node. A negative node is coupled between the negative switch and the at least one resistor. The communication chain also includes at least one bias voltage generator and a calibration circuit. The at least one bias voltage generator is coupled to the positive gate terminal of the positive transistor and the negative gate terminal of the negative transistor. The calibration circuit is coupled between the positive node and the at least one bias voltage generator and between the negative node and the at least one bias voltage generator. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 An environment with an example electronic device having a wireless interface device including an example mixer circuit and corresponding calibration circuit is illustrated.

[0012] Figure 2 are schematic diagrams illustrating example radio frequency (RF) front-ends and example transceivers that can each include at least one mixer circuit.

[0013] Figure 3is a schematic diagram illustrating an example communication chain including a mixer circuit having an associated local oscillator and a corresponding calibration circuit.

[0014] Figure 4 is a circuit diagram illustrating an example mixer circuit having a mixer and an example tuning circuit including a bias voltage generator and a bias control circuit.

[0015] Figure 5 is a schematic diagram illustrating an example calibration circuit and an example mixer circuit including an example mixer having multiple stages and a tuning circuit coupled to a first stage of the multiple stages.

[0016] Figure 6 is a circuit diagram illustrating an example mixer circuit and an example calibration circuit employing a comparator to adjust a back gate bias voltage of a transconductance transistor of the mixer circuit.

[0017] Figure 7 is a circuit diagram illustrating an example mixer circuit and an example calibration circuit employing a comparator to adjust a front gate bias voltage of a transconductance transistor of the mixer circuit.

[0018] Figure 8 is a circuit diagram illustrating an example mixer circuit and an example calibration circuit employing an analog-to-digital converter to adjust a back gate bias voltage of a transconductance transistor of the mixer circuit.

[0019] Figure 9 is a circuit diagram illustrating an example mixer circuit and an example calibration circuit employing an analog-to-digital converter to adjust a front gate bias voltage of a transconductance transistor of the mixer circuit.

[0020] Figure 10 is a flow diagram illustrating an example process for performing a calibration procedure to offset oscillator leakage associated with a mixer circuit or for calibrating a calibration circuit relative to mixer operation. DETAILED DESCRIPTION

[0021] Introduction and Summary

[0022] To facilitate transmission and reception of wireless signals, an electronic device can use a wireless interface device that includes a wireless transceiver and / or a radio frequency (RF) front-end. An electronic device communicates with wireless signals using EM signaling that exists at various frequencies that are part of the electromagnetic (EM) spectrum. These wireless signals can travel between two electronic devices while oscillating at a particular frequency, such as a kilohertz (kHz) frequency, a megahertz (MHz) frequency, or a gigahertz (GHz) frequency. However, the EM spectrum is a limited resource that limits how many signals can be simultaneously communicated in any given space region. There are billions of electronic devices that use this limited resource. To enable a larger number of simultaneous communications using EM signaling, the limited EM spectrum is shared among electronic devices. The EM spectrum can be shared using, for example, frequency-division multiplexing (FDM) techniques and / or time-division multiplexing (TDM) techniques.

[0023] FDM or TDM techniques can require that the EM spectrum be divided into different frequency bands and that communications be limited to occur within a designated frequency band. EM signals in different frequency bands can be simultaneously communicated in the same region without significantly interfering with one another. To transmit a signal within a target frequency band, a transmit chain of a wireless interface device can apply a mixer to the signal to up-convert a relatively lower frequency to reach the target frequency band. To recover information carried by a signal received within a target frequency band, a receive chain of the wireless interface device can apply a mixer to the received signal to down-convert from the target frequency band to a lower frequency to facilitate further processing.

[0024] To perform frequency conversion, a mixer operates in conjunction with a local oscillator that produces a local oscillator (LO) signal (LO signal). The mixer “combines” (e.g., multiplies) an input signal with the LO signal to produce an output signal. The input signal carries information, and the output signal continues to carry information after performing signal mixing to convert frequencies. The mixer can be configured so that the output signal has a higher frequency than the input signal in order to up-convert frequencies in a transmit chain as part of processing a signal to be transmitted. Alternatively, the mixer can be configured so that the output signal has a lower frequency than the input signal in order to down-convert frequencies in a receive chain as part of processing a received signal. The frequency of the output signal depends at least in part on the frequency of the LO signal provided by the local oscillator.

[0025] To provide a purer signal for downstream processing after frequency conversion at a mixer, little to no LO signal should "leak" through the mixer independent of the information-carrying output signal. Local oscillator feedthrough (LOFT) refers to LO signal "leakage" through a mixer into a communication chain (e.g., a transmit chain or a receive chain) and adversely affecting downstream signal processing. LOFT can limit the throughput of a system. For example, LOFT can increase an error vector magnitude (EVM) parameter, especially in the case of wideband signaling. The EVM parameter measures how closely a signal being transmitted or received matches an expected signal in timing, phase, and / or magnitude, as represented by a constellation diagram.

[0026] Specifically for transmit operations, LOFT can reduce effective radiated power (ERP), which is especially detrimental in systems that utilize beamforming. Moreover, for mmW massive phased array systems, LOFT is particularly impactful because "leaked" power on the field can potentially add together across elements of the antenna array. This total or combined "leaked" power can exceed the emission specification of 3GPP standards, which can be approximately -13 decibel-milliwatts (dBm) / MHz depending on the range. This emission constraint results in a relatively strict LOFT specification per antenna element, as each element is scaled down by a factor of 10*log(N), where "N" is the number of massive phased array elements that can be turned on simultaneously.

[0027] To further more efficiently utilize the limited EM spectrum, some wireless interface devices implement beamforming. Beamforming focuses transmission or reception in a target direction to facilitate spatial sharing of EM signals and / or increase the usable signal range. To implement beamforming, a wireless interface device is coupled to an antenna array having multiple antenna elements. To interface with the multiple antenna elements, a wireless interface device includes multiple communication chains. Employing multiple communication chains also makes it increasingly difficult to meet LOFT specifications.

[0028] In one approach, an external or additional filter can be used to filter out LO signal leakage at the output of, for example, a power amplifier of a transmit chain. However, such a filtering approach can introduce excessive loss to the generation and transmission of a transmit signal and the acquisition and processing of a receive signal. Such loss limits performance and significantly increases module cost and design complexity. Notably, LOFT is often generated at least in part by mismatches in a local oscillator or in a transconductance stage of a mixer. As process scaling reaches tens of nanometers (nm) and below, these mismatches are exacerbating in both the amount of difference and the frequency of occurrence between two or more components.

[0029] In another approach, calibration to combat LOFT can be performed using external radio frequency (RF) equipment during manufacturing and testing. But this approach is associated with several problems. First, automated test equipment (ATE) is expensive. Second, as frequencies increase to utilize more of the limited EM spectrum, signal processing and transmission are reaching millimeter wave (mmW) frequencies. These mmW frequencies can include frequencies above about 20 gigahertz (GHz), and LOFT can occur at such mmW frequencies as well as other frequencies. ATE operating at mmW frequencies is not currently available. If or when such ATE becomes available, the RF equipment used to capture the spectrum at these frequencies during testing will introduce even greater production cost and time loss due to testing.

[0030] In an additional approach, a power detector (PDET) can be coupled to a point along the communication chain to obtain an indication of a propagating signal including at least a portion of the LOFT. The on-chip power detector detects a power level of the propagating signal based on the indication and provides the detected power level to controller circuitry. The controller circuitry adjusts a tuning circuit for a transistor of the mixer (e.g., an amount of current applied to the transistor of the mixer) based on the detected power level. During calibration, the detected power level is produced by the mixer that is receiving the positive amplitude LO signal but receiving zero amplitude information carrying signal. Thus, the detected power level can substantially represent the LOFT. Accordingly, the controller circuitry can adjust the tuning circuit to reduce the detected power level, thereby reducing the LOFT.

[0031] This PDET approach requires the LO tone power to be within the detectable range of the PDET. However, due to the capabilities of the power detector, this approach can be ineffective for some devices, such as customer premises equipment (CPE) or base station (BS) devices. For example, if the threshold of the PDET is -20 dBm, the PDET approach can be effective for a user equipment (UE) environment that has -20 dBm LO tone power at the output port, but can be ineffective for a CPE that has -30 dBm LO tone power at the output port and a BS that has -45 dBm LO tone power at the output port. Furthermore, to improve effectiveness, the total noise or combined power of other tones should be significantly less than the LO power, as the PDET is not able to distinguish between different frequency components on its own.

[0032] In yet another approach involving calibration for combating LOFT, an end-to-end (e2e) loopback scheme can be employed. For such an e2e loopback scheme, the receive chain is used to measure the transmitted signal, and the measured signal is routed back through the receive chain for analysis. However, the e2e loopback scheme can subject the measured signal to the effects of non-idealities of the down-conversion RX mixer, and these non-idealities make signal analysis problematic.

[0033] For an alternative approach, this document describes devices and techniques that cancel local oscillator leakage without requiring reliance on PDET or external equipment to capture the RF transmission. Thus, the described devices and techniques can reduce production costs for wireless interface devices, including those operating at mmW frequencies. The techniques and devices can also enable performing calibration for reducing local oscillator leakage with on-board equipment, including after an electronic device has been deployed in the field.

[0034] Generally, a mixer circuit of a communication chain, such as a transmit chain, can perform frequency conversion using a LO signal from a local oscillator. In example implementations, the mixer circuit includes a mixer and a tuning circuit. The tuning circuit applies a calibration signal to the mixer to cancel LOFT, which can otherwise propagate along the communication chain. To determine the calibration signal, a portion of the circuit of the mixer can be operated. More specifically, during a calibration process, a switching transistor of the mixer can be turned off, and a transconductance amplifier of the mixer can be analyzed in a direct current domain (DC domain).

[0035] In example operations, a calibration circuit is coupled between at least one mixer node of the mixer and the tuning circuit of the mixer circuit. The calibration circuit measures a voltage corresponding to the mixer node, where the voltage is indicative of a current flowing through the transconductance amplifier of the mixer. A controller or controller circuit of the calibration circuit provides a control signal to the tuning circuit to adjust the voltage at the mixer node. The tuning circuit can include at least one bias voltage generator coupled to a gate of a transconductance transistor of the mixer. The transistor gate can correspond to a front gate terminal or a back gate terminal (also referred to as a body terminal) of the transconductance transistor. In a differential environment, the at least one bias voltage generator can also be coupled to the gate of a positive transconductance transistor or a negative transconductance transistor, including to the positive transconductance transistor and the negative transconductance transistor in a permissive “exclusive or” interpretation of the term “or.”

[0036] Thus, with differential signaling, the mixer includes a positive transconductance transistor and a negative transconductance transistor. A current offset or current mismatch between a positive current and a negative current flowing through the positive transconductance transistor and the negative transconductance transistor, respectively, can cause oscillator leakage. Reducing the current offset can reduce the oscillator leakage. Thus, the controller can cause at least one of the positive current and the negative current to change to reduce the current offset, thereby reducing the LOFT.

[0037] The calibration circuit can include at least one resistor coupled between the mixer node and a power distribution node, such as a supply voltage node. In a differential environment, the at least one resistor can be coupled to the positive mixer node and the negative mixer node. In some cases, the resistors are coupled to the positive mixer node and the negative mixer node with respective positive and negative switches, and a comparator is used to analyze the voltages at these mixer nodes using the resistors. In other cases, a positive resistor and a negative resistor are used, with the positive resistor coupled to the positive mixer node via a positive switch and the negative resistor coupled to the negative mixer node via a negative switch. An analog-to-digital converter (ADC) can be used to analyze the voltages at the positive mixer node and the negative mixer node. More specifically, the controller circuit can analyze the voltage difference between the two mixer nodes, and thus indirectly analyze the current difference between the positive current and the negative current flowing through the positive and negative transconductance transistors, respectively.

[0038] The controller circuit can establish one or more settings based on a calibration process, such as by storing at least one value in a register. These settings can control the bias voltage provided by the bias voltage generator to the gate terminal of the positive or negative transconductance transistor to reduce the voltage difference between the positive and negative mixer nodes. By reducing the difference between the voltages at the positive and negative mixer nodes, the current offset between the positive and negative transconductance transistors is likewise reduced. By reducing the current offset between the positive and negative transconductance transistors in the mixer, oscillator leakage is reduced. These and other implementations are described herein.

[0039] Description of Examples

[0040] Figure 1 An example environment 100 is illustrated with an electronic device 102 having a wireless interface device 120 that includes at least one example mixer circuit 130 and a calibration circuit 138. This document describes example implementations of the mixer circuit 130 and corresponding calibration circuit 138, which can be part of a radio frequency front end (RFFE), a transceiver, a communication processor, and so on, of a device. In the environment 100, the electronic device 102 communicates with a base station 104 over a wireless link 106.

[0041] In Figure 1In the depicted example, the example electronic device 102 is depicted as a smartphone. However, the electronic device 102 can be implemented as any suitable computing device or other electronic device. Examples of devices that can be implemented as the electronic device 102 include a cellular base station, a broadband router, an access point, a cellular or mobile phone, a gaming device, a navigation device, a media device, a laptop computer, a desktop computer, a tablet computer, and a server computer. Other examples of devices that can be implemented as the electronic device 102 include a network-attached storage (NAS) device, a smart appliance, a vehicle-based communication system, an Internet of Things (IoT) device, a sensor or security device, an asset tracker, a fitness management device, a wearable device such as smart glasses or a smart watch, a wireless power device (a transmitter or a receiver), a medical device, and so forth. The electronic device 102 can be referred to by different terms such as a user equipment (UE), a customer premises equipment (CPE), or a cellular subscriber modem (CSM).

[0042] The base station 104 communicates with the electronic device 102 via a wireless link 106, which can be implemented as any suitable type of wireless link that carries communication signals. Although depicted as a cellular radio network tower, the base station 104 can represent or be implemented as another device such as a satellite, a terrestrial broadcast tower, an access point, a CPE, a CSM, a peer-to-peer device, a mesh network node, a fiber line interface, another electronic device substantially as described above, and so forth. Thus, the wireless link 106 can extend between the electronic device 102 and the base station 104 in any of a variety of ways.

[0043] The wireless link 106 can include a downlink of data or control information communicated from the base station 104 to the electronic device 102. The wireless link 106 can also include an uplink of other data or control information communicated from the electronic device 102 to the base station 104. The wireless link 106 can be implemented using any suitable wireless communication protocol or standard. Examples of such protocols and standards include the 3rd Generation Partnership Project (3GPP) Long Term Evolution (LTE) standards such as the 4th Generation (4G), 5th Generation (5G), or 6th Generation (6G) cellular standards; IEEE 802.11 standards such as the 802.11g, ac, ax, ad, aj, or ay standards (e.g., Wi-Fi ® 6or WiGig ® ); IEEE 802.16 standards (e.g., WiMAX ® ); Bluetooth ® standards; Ultra-Wideband (UWB) standards (e.g., IEEE 802.15.4); and so forth. In some implementations, the wireless link 106 can wirelessly provide power, and the electronic device 102 or the base station 104 can include a power source or a power dissipater.

[0044] As shown with respect to some specific embodiments, electronic device 102 may include at least one application processor 108 and at least one computer-readable storage medium 110 (CRM 110). Application processor 108 may include any type of processor, such as a central processing unit (CPU) or a multi-core processor, configured to execute processor-executable instructions (e.g., code) stored in CRM 110. CRM 110 may include any suitable type of data storage medium, such as volatile memory (e.g., random access memory (RAM)), non-volatile memory (e.g., flash memory), optical media (e.g., optical disc), magnetic media (e.g., magnetic disk or magnetic tape), etc. In the context of this disclosure, CRM 110 is implemented to store instructions 112, data 114, and other information of electronic device 102, and therefore CRM 110 does not include transiently propagated signals or carrier waves.

[0045] Electronic device 102 may also include one or more input / output ports 116 (I / O ports 116) and at least one display 118. The I / O ports 116 enable data exchange or interaction with other devices, networks, or users. The I / O ports 116 may include serial ports (e.g., Universal Serial Bus (USB)). ® Display 118 may be a display screen or projection that presents graphical images provided by other components of electronic device 102, such as a user interface (UI) associated with an operating system, program, or application. Alternatively or additionally, display 118 may be implemented as a display port or virtual interface through which graphical content of electronic device 102 is conveyed or presented.

[0046] The electronic device 102 also includes at least one wireless interface device 120 and at least one antenna 122. Example wireless interface devices 120 provide connectivity to respective networks and peer devices via wireless links, which can be similarly or differently configured than the wireless link 106. The wireless interface devices 120 can facilitate communication over any suitable type of wireless network, such as a wireless local area network (LAN) (WLAN), a wireless personal area network (PAN) (WPAN), a peer-to-peer (P2P) network, a mesh network, a cellular network, a wireless wide area network (WAN) (WW AN), and / or a navigation network (e.g., the Global Positioning System (GPS) of North America or another satellite positioning system (SPS) or global navigation satellite system (GNSS)). In the context of the example environment 100, the electronic device 102 can bidirectionally communicate various data and control information with the base station 104 via the wireless interface devices 120. However, the electronic device 102 can communicate with other peer devices, alternative wireless networks, and so on, directly. Additionally, as described above, the electronic device 102 can alternatively be implemented as the base station 104, an access point, or another apparatus as set forth herein.

[0047] As Figure 1 As shown in FIG. 1, the wireless interface device 120 can include at least one communication processor 124, at least one transceiver 126, and at least one radio frequency front end 128 (RFFE 128). These components process data information, control information, and signals associated with communicating information for the electronic device 102 via the antenna 122. The communication processor 124 can be implemented as at least a portion of a system on a chip (SoC), a modem processor, or a baseband radio processor (BBP) that implements a digital communication interface for data, voice, messaging, or other applications of the electronic device 102. The communication processor 124 can include a digital signal processor (DSP) or one or more signal processing blocks (not shown) for encoding and modulating data for transmission and for demodulating and decoding received data. Additionally, the communication processor 124 can also manage (e.g., control or configure) aspects or operations of the transceiver 126, the RF front end 128, and other components of the wireless interface device 120 to implement various communication protocols or communication techniques.

[0048] In some cases, the application processor 108 and the communication processor 124 can be combined into one module or integrated circuit (IC), such as a SoC. Regardless, the application processor 108, the communication processor 124, or the processor(s) can be operatively coupled to one or more other components (such as the CRM 110 or the display 118) to enable control of or other interaction with various components of the electronic device 102. For example, the at least one processor 108 or the processor 124 can present one or more graphical images on a display screen implementation of the display 118 based on one or more wireless signals communicated (e.g., transmitted or received) via the at least one antenna 122 using components of the wireless interface device 120. Moreover, the application processor 108 or the communication processor 124 (including combinations thereof) can be implemented using digital circuitry that implements the logic or functionality described herein. Additionally, the communication processor 124 can also include or be associated with a memory (not separately depicted) (such as the same CRM 110 or another CRM) for storing data and processor-executable instructions (e.g., code).

[0049] As shown, the wireless interface device 120 can include at least one mixer circuit 130 described below. More specifically, the transceiver 126 can include at least one mixer circuit 130-1, or the RF front end 128 can include at least one mixer circuit 130-2 (including both components can have at least one mixer circuit 130 according to the optional but permissible “inclusive OR” interpretation of the term “or” herein). The transceiver 126 can also include circuitry and logic for filtering, switching, amplifying, channelizing, frequency translating, and so forth.

[0050] Frequency translating functionality can include frequency up-conversion or down-conversion of frequencies performed by a single conversion operation (e.g., with a direct-conversion architecture) or by multiple conversion operations (e.g., with a super-heterodyne architecture). The transceiver 126 can perform such frequency conversion (e.g., frequency translating) by using the mixer circuit 130-1 and an associated local oscillator 136. In general, the transceiver 126 can include filters, switches, amplifiers, mixers, and so forth for routing and conditioning signals transmitted or received via the antenna 122.

[0051] In addition to the mixer circuit 130-1, the transceiver 126 can also include an analog-to-digital converter (ADC) or a digital-to-analog converter (DAC) (not separately depicted) for converting signals between analog and digital formats. Figure 1ADCs and DACs (not shown). In operation, an ADC can convert an analog signal to a digital signal, and a DAC can convert a digital signal to an analog signal. Generally, an ADC or a DAC can be implemented as part of the communication processor 124, as part of the transceiver 126, or separately therefrom (e.g., as another part of an SoC, as part of the application processor 108, or as part of the RF front end 128).

[0052] Components or circuitry of the transceiver 126 can be implemented in any suitable manner, such as with a combined transceiver logic or separately as respective transmitter and receiver entities. In some cases, the transceiver 126 is implemented with multiple or different parts to implement respective transmit and receive operations (e.g., implemented with at least partially separate transmit and receive chains as depicted in Figure 2 Although not shown in Figure 1 The transceiver 126 can include logic to perform in-phase / quadrature (I / Q) operations (such as synthesis, phase correction, modulation, demodulation, etc.), although not shown in

[0053] The RF front end 128 can also include one or more mixers (such as the mixer circuitry 130-2), one or more filters, one or more switches, or one or more amplifiers for adjusting signals received via the antenna 122 or for adjusting signals to be transmitted via the antenna 122. The RF front end 128 can also include a local oscillator 136, a phase shifter (PS), a peak detector, a power meter, a gain control block, antenna tuning circuitry, an N-way multiplexer, a balun, etc. Configurable components of the RF front end 128, such as some phase shifters, an automatic gain controller (AGC), or tunable versions of the mixer circuitry 130-2, can be controlled by the communication processor 124 to implement communications in various modes, with different frequency bands, using beamforming, or with improved performance. In some implementations, the antenna 122 is implemented as at least one antenna array including multiple antenna elements. Thus, as used herein, an “antenna” can refer to at least one discrete or independent antenna, to at least one antenna array including multiple antenna elements, or to a portion of an antenna array (e.g., an antenna element), depending on the context or implementation.

[0054] In example implementations, the wireless interface device 120 includes at least one mixer circuit 130, at least one local oscillator 136 (LO 136), and at least one instance of calibration circuitry 138. The components can be positioned separately or jointly at the communication processor 124, the transceiver 126, the RF front end 128, or a combination thereof, including distributed across two or more sections or portions of the wireless interface device 120. In Figure 1In the example, mixer circuit 130 is depicted as having mixer circuit 130-1 as part of transceiver 126, mixer circuit 130-2 as part of RF front-end 128, and so on. However, the specific implementations of mixer circuit 130 described herein may additionally or alternatively be used in other parts of wireless interface device 120 or other parts of electronic device 102. Furthermore, each part may include more than one mixer circuit 130.

[0055] As described above, mixer circuit 130 can be included in electronic devices other than cellular phones (such as base station 104 or wireless access point). Alternatively, using a base station (or a mobile phone or other electronic device using a superheterodyne architecture), mixer circuit 130 as described herein can be used to implement, for example, an intermediate frequency (IF) band mixer for wireless interface device 120. Other electronic devices that may employ mixer circuit 130 and corresponding calibration circuit 138 include laptops, communication hardware for vehicles, wireless access points, wearable devices, etc., as described herein.

[0056] In an example implementation, mixer circuit 130 may include at least one instance of mixer 132 and tuning circuit 134. Mixer 132 is coupled to tuning circuit 134. Although some components are shown as Figure 1 This is a portion of the example mixer circuit 130, but a given mixer circuit can have more, fewer, or different components. See below for reference. Figures 4-9 An example of a mixer circuit is described.

[0057] During normal or "task" operation, the local oscillator 136 feeds the LO signal to mixer 132 of mixer circuit 130. The LO signal can be transmitted, for example, along a communication link ( Figure 1 (Not shown) Oscillator leakage (LOFT) can "leak" into other parts of the wireless interface device 120, with mixer 132 forming part of this communication chain. To address this oscillator leakage in the LOFT, calibration circuit 138 controls tuning circuit 134 to provide mixer 132 with one or more offset tuning signals, such as bias voltages. These offset tuning signals can be determined during initialization or "calibration" operation. Applying these tuning signals reduces LOFT to improve error vector magnitude (EVM), effective radiated power (ERP), unwanted spurious emissions, and other wireless performance characteristics. See below for reference. Figures 3-10 An example method for the calibration process is described. However, this document then refers to... Figure 2 Example implementations of the transceiver and RF front end are described.

[0058] Figure 2is a schematic diagram of circuit 200 illustrating an example RF front end 128 and an example transceiver 126 that can each include at least one mixer circuit 130. Figure 2 Antenna 122 and communication processor 124 are also depicted. Communication processor 124 communicates one or more data signals to other components (such as Figure 1 application processor 108) for further processing at 224 (e.g., for processing at the application level) for receive operations. For transmit operations, communication processor 124 communicates one or more data signals from other components to transceiver 126. As shown, circuit 200 can include a first mixer circuit 130-1, a second mixer circuit 130-2, a third mixer circuit 130-3, or a fourth mixer circuit 130-4, including one to four of such mixer circuits. However, circuit 200 can include a different number of mixers (e.g., more or fewer mixers), can include mixers coupled together in different ways, can include mixers in different locations, can include mixers implemented as part of a frequency converter, and so on.

[0059] As illustrated from left to right, in an example implementation, antenna 122 is coupled to RF front end 128, and RF front end 128 is coupled to transceiver 126. Transceiver 126 is coupled to communication processor 124. Example RF front end 128 includes at least one signal propagation path 222. At least one signal propagation path 222 can include at least one mixer circuit 130, such as mixer circuit 130-2 and mixer circuit 130-4. Example transceiver 126 includes at least one receive chain 202 (or receive path 202) and at least one transmit chain 252 (or transmit path 252). Although only one RF front end 128, one transceiver 126, and one communication processor 124 are shown at circuit 200, electronic device 102 or wireless interface device 120 of the electronic device can include multiple instances of any or all of such components. Additionally, although Figure 2 Although only certain components of transceiver 126 or RF front end 128 are explicitly depicted and shown as coupled together in a particular manner, transceiver 126 or RF front end 128 can include other unillustrated components (e.g., switches or duplexers), more or fewer components, components arranged in different ways, and so on.

[0060] In some implementations, the RF front end 128 couples the antenna 122 to the transceiver 126 via a signal propagation path 222. In operation, the signal propagation path 222 carries signals between the antenna 122 and the transceiver 126. During or as part of signal propagation, the signal propagation path 222 conditions the propagating signals, such as with the mixer circuit 130-2 or the mixer circuit 130-4. This enables the RF front end 128 to couple wireless signals 220 from the antenna 122 to the transceiver 126 as part of a receive operation. The RF front end 128 also enables transmit signals to be coupled from the transceiver 126 to the antenna 122 as part of a transmit operation that emits wireless signals 220. Although not explicitly shown in Figure 2 The RF front end 128 or the signal propagation path 222 of the RF front end can include one or more other components, such as another mixer, a filter, an amplifier (e.g., a power amplifier (PA) or a low noise amplifier (LNA)), an N-way multiplexer, a phase shifter, a diplexer, one or more switches, and so forth, although not explicitly shown in

[0061] In some implementations, the transceiver 126 can include at least one receive chain 202, at least one transmit chain 252, or both at least one receive chain 202 and at least one transmit chain 252. From left to right, the receive chain 202 can include a low noise amplifier 204 (LNA 204), a filter circuit 206, a mixer circuit 130-3 for frequency down-conversion, and an ADC 210. The transmit chain 252 can include a power amplifier 254 (PA 254), a filter circuit 256, a mixer circuit 130-1 for frequency up-conversion, and a DAC 260. However, the receive chain 202 or the transmit chain 252 can include other components (e.g., additional amplifiers or mixers, multiple filters, at least one transformer, one or more buffers, or at least one phase-locked loop) that are electrically or electromagnetically coupled anywhere along the depicted receive and transmit chains.

[0062] The receive chain 202 is coupled between the signal propagation path 222 of the RF front end 128 and the communication processor 124, e.g., via a low noise amplifier 204 and an ADC 210, respectively. The transmit chain 252 is coupled between the signal propagation path 222 and the communication processor 124, e.g., via a power amplifier 254 and a DAC 260, respectively. The transceiver 126 can also include at least one local oscillator 136 (LO 136) coupled to the mixer circuitry 130-1 or the mixer circuitry 130-3, including to both of these. The local oscillator 136 can be part of a synthesizer circuit (including one or more PLLs / VCOs and other circuitry) that can generate a local oscillator signal. For example, the transceiver 126 can include one local oscillator 136 per pair of transmit / receive chains, one local oscillator 136 per transmit chain and one local oscillator 136 per receive chain, multiple local oscillators 136 per transmit chain or receive chain, and so on. Each of the mixer circuitry 130-2 and the mixer circuitry 130-4 of the RF front end 128 can also be coupled to the same local oscillator 136 or to different local oscillators (not shown in FIG. 1). Figure 2

[0063] As depicted in the signal propagation direction for certain example implementations of the receive chain 202, the antenna 122 is coupled to the low noise amplifier 204 via the signal propagation path 222 and the mixer circuitry 130-4 of that signal propagation path, and the low noise amplifier 204 is coupled to the filter circuitry 206. The filter circuitry 206 is coupled to the mixer circuitry 130-3, and the mixer circuitry 130-3 is coupled to the ADC 210. The ADC 210 is in turn coupled to the communication processor 124. As depicted in the signal propagation direction for certain example implementations of the transmit chain 252, the communication processor 124 is coupled to the DAC 260, and the DAC 260 is coupled to the mixer circuitry 130-1. The mixer circuitry 130-1 is coupled to the filter circuitry 256, and the filter circuitry 256 is coupled to the power amplifier 254. The power amplifier 254 is coupled to the antenna 122 via the signal propagation path 222 using the mixer circuitry 130-2 of that signal propagation path. Although only one receive chain 202 and one transmit chain 252 are explicitly shown, the electronic device 102 or its transceiver 126 can include multiple instances of either or both components. Although the ADC 210 and the DAC 260 are illustrated as separately coupled to the communication processor 124, they can share a bus or other means for communicating with the processor 124.

[0064] ​As part of example signal reception operations, a mixer circuit 130-4 (if present) of the signal propagation path 222 downconverts a received signal (e.g., to an intermediate frequency (IF)) and forwards the downconverted signal to a low noise amplifier 204. The low noise amplifier 204 accepts the downconverted signal from the RF front end 128 and provides an amplified signal to a filter circuit 206 based on the accepted signal. The filter circuit 206 filters the amplified signal and provides a filtered signal to a mixer circuit 130-3. The mixer circuit 130-3 performs a frequency downconversion operation on the filtered signal to downconvert from one frequency to a lower frequency (e.g., from IF to a baseband frequency (BBF) in the case that there is a mixer circuit 130-4 “upstream,” or from a radio frequency (RF) to IF or BBF in the case that there is no mixer circuit 130-4). The mixer circuit 130-3 or multiple mixer circuits can perform the frequency downconversion in a single conversion step or through multiple conversion steps using at least one local oscillator 136. The mixer circuit 130-3 can provide the downconverted analog signal to an ADC 210 for analog-to-digital conversion and subsequently forward as a digital signal to the communication processor 124.

[0065] As part of example signal transmission operations, the DAC 260 converts digital signals received from the communication processor 124 to analog signals. The mixer circuit 130-1 accepts the analog signals from the DAC 260, either directly or indirectly, at BBF or IF. The mixer circuit 130-1 upconverts the analog signals to a higher frequency (such as to IF or RF) to produce the higher frequency signals as having a target synthesized frequency using signals generated by the local oscillator 136. The mixer circuit 130-1 provides the RF or other upconverted signals to the filter circuit 256. The filter circuit 256 filters the upconverted IF or RF signals and provides a filtered signal to the power amplifier 254. Thus, after filtering by the filter circuit 256, the power amplifier 254 amplifies the filtered signal and provides the amplified signal to the signal propagation path 222 for signal conditioning. For example, if the amplified signal is at IF, the RF front end 128 can use the mixer circuit 130-2 of the signal propagation path 222 to provide the RF signal to the antenna 122 for emission as a wireless signal 220.

[0066] As described herein, example implementations of the mixer circuit 130 can be deployed at any one or more of the example mixer circuits 130-1, 130-2, 130-3, or 130-4 in the transceiver 126 or the RF front end 128, or other mixer circuits of the electronic device 102 Figure 2The circuit 200 depicts only a few examples for the transceiver 126 and RF front end 128 (not all shown). However, the circuit 200 depicts only a few examples for the transceiver 126 and RF front end 128. In some cases, various components illustrated in the figures using separate schematic blocks or circuit elements can be fabricated or packaged in different discrete ways. For example, one physical module can include components of the RF front end 128 and some components of the transceiver 126, and another physical module can combine the communication processor 124 with the remaining components of the transceiver 126.

[0067] Further, in some cases, the antenna 122 can be co-packaged into a module with at least some components of the RF front end 128 or the transceiver 126. For example, in a non-limiting example corresponding to mmW implementations, the transceiver 126 can provide an IF signal to the RF front end 128. In some such cases, the RF front end 128 can be co-packaged into a module with an antenna array version of the antenna 122. Here, the RF front end 128 includes one or more mixer circuits 130-2 and 130-4 configured to upconvert and downconvert between IF / RF signals. The RF front end 128 also provides further signal conditioning, such as phase shifting for beamforming, etc. In another non-limiting example, such as for 5G New Radio (NR) Frequency Range 1 (FR1) implementations, the RF front end 128 can not include mixers (e.g., have a direct conversion architecture where frequency translation between BB and RF occurs in the transceiver 126). Even without mixers, the RF front end 128 can include other components, such as power amplifiers, low noise amplifiers, filters, or other conditioning circuits, for processing before or after the signal is processed by the transceiver 126 (for transmit or receive operations, respectively).

[0068] In alternative implementations, one or more components can be physically or logically “shifted” to different parts of the wireless interface device 120 and / or can be incorporated into different modules compared to the illustrated circuit 200. For example, the low noise amplifier 204 or the power amplifier 254 can alternatively or additionally be deployed in the RF front end 128. Similarly, the ADC 210 or the DAC 260 can alternatively be deployed in the communication processor 124. Further, a receive chain or a transmit chain can exist in the RF front end 128, and / or the depicted receive chain 202 or transmit chain 252 can extend into the RF front end 128 such that these chains are distributed at least partially across the transceiver 126 and the RF front end 128. Reference is next made to Figure 3 A general communication chain with a mixer circuit 130 is described.

[0069] Figure 3is a schematic diagram 300 illustrating an example communication chain 320 including a mixer circuit 130 having an associated local oscillator 136 and a corresponding calibration circuit 138. As illustrated, the communication chain 320 can accept an incoming signal 312 and use the mixer circuit 130 to produce an outgoing signal 314. The communication chain 320 can be implemented, for example, as the receive chain 202, the transmit chain 252, or a portion thereof (e.g., Figure 2 each of which).

[0070] In example implementations, the mixer circuit 130 is electrically or electromagnetically coupled along the communication chain 320. The local oscillator 136 and the calibration circuit 138 are coupled to the mixer circuit 130. The calibration circuit 138 can be coupled between the mixer 132 and the tuning circuit 134 of the mixer circuit 130. Although the two components (e.g., the local oscillator 136 and the calibration circuit 138) are depicted separately from the communication chain 320 in Figure 3 some cases, the local oscillator 136 or the calibration circuit 138 (including both in some cases) can be included entirely or partially as a component of the communication chain 320. Alternatively, but by way of example only, the local oscillator 136 can serve mixer circuits of multiple communication chains, and the calibration circuit 138 can be incorporated at least partially as part of a communication processor (e.g., Figure 1 and Figure 2 the communication processor 124 of the communication device 100).

[0071] As shown, the mixer circuit 130 includes the mixer 132 and the tuning circuit 134. The mixer 132 is coupled to the tuning circuit 134. In some cases, the calibration circuit 138 is coupled to the mixer 132 and the tuning circuit 134. In at least some of such cases, the calibration circuit 138 can be coupled between the tuning circuit 134 and the mixer 132 via a mixer node (not explicitly shown in Figure 3 ) coupled between two or more stages of the mixer 132. Multiple stages of the mixer 132 are described below with reference to Figure 5 The local oscillator 136 can be coupled to the mixer circuit 130 via the mixer 132.

[0072] In example operations, the local oscillator 136 generates the LO signal 306. The mixer 132 accepts or receives the input signal 302 from an upstream component (not shown in Figure 3 ) of the communication chain 320. The mixer 132 also accepts or receives the LO signal 306 from the local oscillator 136. Based on the input signal 302 and the LO signal 306, the mixer 132 produces the output signal 304. The mixer 132 provides or forwards the output signal 304 to a downstream component (not shown in Figure 3The mixer 132 converts a frequency (e.g., an input frequency) of the input signal 302 to another frequency (e.g., an output frequency) of the output signal 304 based on an LO frequency of the LO signal 306 and the input frequency of the input signal 302. The frequency conversion operation (or "frequency translation") can be an up-conversion operation (e.g., for a transmit chain) that increases the frequency or a down-conversion operation (e.g., for a receive chain) that decreases the frequency.

[0073] The calibration circuit 138 obtains an indication of a signal present with respect to the mixer 132, such as a voltage or current value, which is referred to herein as a signal indication 310. Based on the signal indication 310, the calibration circuit 138 generates a control signal 308. The calibration circuit 138 provides the control signal 308 to the mixer circuit 130 via the tuning circuit 134. In response to the control signal 308, the tuning circuit 134 modifies the behavior or operation of the mixer 132 to counteract (e.g., at least reduce, if not minimize) the feedthrough of the LO signal 306 into the output signal 304 (and thus along the communication chain 320).

[0074] The timing of the calibration process can vary based on implementation. In some cases, the calibration circuit 138 is initially run to establish a tuning value. The calibration circuit 138 can be run, for example, as part of a factory calibration during manufacture of the wireless interface device or assembly of the electronic device. The resulting tuning value can be stored by the wireless interface device for later use. The calibration process can be run at different temperatures to obtain and store different tuning values for different operating temperatures. Subsequently, the stored tuning value is retrieved or applied so that the tuning circuit 134 can calibrate the mixer circuit 130 and thereby reduce oscillator leakage or lower the LOFT. The subsequent use can occur, for example, during mission mode operation (e.g., in the field).

[0075] In other cases, the calibration process can be performed while the electronic device is in the field. In other cases, the calibration process can be performed by the device manufacturer and later by the device user again. The later calibration process can be performed once or repeatedly (e.g., at startup, at regular intervals, based on environmental and / or location changes, or in response to band or other frequency changes). In any such calibration process case, an example implementation of the calibration process can be performed in a manner that operates a portion of the mixer 132 in a DC mode, which will be described below with reference to Figure 5 However, next, example implementations are described in which the tuning circuit 134 includes a bias voltage generator with reference to Figure 4

[0076] Figure 4 ​is a circuit diagram 400 illustrating an example mixer circuit 130 having a mixer 132 and an example tuning circuit 134. The example tuning circuit 134 includes at least one instance of a bias voltage generator 402 and a bias control circuit 404. The circuit diagram 400 also includes the calibration circuit 138. As shown, the bias voltage generator 402 is coupled to the mixer 132, and the bias control circuit 404 is coupled to the bias voltage generator 402. Further, the bias voltage generator 402 is coupled between the bias control circuit 404 and the mixer 132.

[0077] In example implementations, the calibration circuit 138 is coupled between the mixer 132 and the bias voltage generator 402 of the tuning circuit 134. The calibration circuit 138 can also be coupled between the mixer 132 and the bias control circuit 404, with the bias control circuit 404 coupled between the calibration circuit 138 and the bias voltage generator 402. In example operations, the calibration circuit 138 obtains at least one signal indication 310 from the mixer 132, such as by sensing or measuring a voltage or current. The signal indication 310 can represent or otherwise indicate a current (e.g., a magnitude thereof) flowing through at least one transistor of the mixer 132.

[0078] Based on the signal indication 310, the calibration circuit 138 generates at least one control signal 308. For example, the calibration circuit 138 can generate the control signal 308 to reduce a difference between two currents flowing through two or more transistors of the mixer 132. The bias control circuit 404 accepts the control signal 308 and generates at least one calibration signal 406 based on the control signal 308. The bias control circuit 404 can be implemented using, for example, registers, a plurality of switches, one or more fuses, some combination thereof, and so forth. The registers, fuses, and so forth can be capable of maintaining data for the calibration signal 406 in the absence of power. Further, the bias control circuit 404 can be distributed such that, for example, one volatile register provides the calibration signal 406 "directly" to the bias voltage generator 402, while another non-volatile register retains the tuning value of the volatile register at power shutdown.

[0079] The bias control circuit 404 can provide the at least one calibration signal 406 to the bias voltage generator 402 during calibration and mission modes. Based on the calibration signal 406, the bias voltage generator 402 generates at least one bias voltage 408. For a differential mixer 132, the bias voltage generator 402 can generate a positive bias voltage and a negative bias voltage, and provide these voltages to respective gate terminals of positive and negative transistors of the mixer 132. This is described further below with reference to Figures 6-9 .

[0080] The bias voltage generator 402 can be implemented in any of various ways. For example, the bias voltage generator 402 can include one or more current sources (not shown) coupled between first and second power distribution nodes and one or more resistors (not shown) coupled in series with the one or more current sources between the first and second power distribution nodes. The first and second power distribution nodes can be implemented using, for example, a supply voltage node and a ground node. In some cases, the one or more current sources, which can be implemented using at least one adjustable current source, can be coupled in series with the at least one resistor. In other cases, the one or more resistors, which can be implemented using at least one adjustable resistor, can be coupled in series with the at least one current source. Adjusting the current or resistance values can adjust the voltage applied to the gate terminal of the transistor.

[0081] In some aspects, the bias voltage generator 402 can be implemented with a plurality of current sources and a plurality of switches, where each of the plurality of switches is respectively coupled to a current source of the plurality of current sources. To control the bias voltage 408, at least one register of the bias control circuit 404 can be coupled to the plurality of switches. In cases where the at least one register includes a plurality of bits, each of the plurality of bits can respectively correspond to a switch of the plurality of switches. Additionally or alternatively, the bias voltage generator 402 can be implemented with a plurality of resistors and a plurality of switches, where each of the plurality of switches is respectively coupled to a resistor of the plurality of resistors.

[0082] Figure 5 is a schematic diagram 500 illustrating an example calibration circuit 138 and an example mixer circuit 130. The example mixer circuit 130 includes an example tuning circuit 134 and an example mixer 132 having a plurality of stages 510-1 and 510-2. As shown, the mixer 132 includes a mixer input 502 to accept or receive the input signal 302 and a mixer output 504 to provide or transmit the output signal 304. The mixer 132 also includes an LO signal input 506 to accept or receive the LO signal 306. The tuning circuit 134 includes a control input 508 to accept or receive the control signal 308. The inputs and outputs can be implemented, for example, with at least a portion of a node, a port, a wire or other conductive element, at least a portion of a transistor (e.g., a terminal thereof), a combination thereof, and so forth.

[0083] In example implementations, the mixer 132 includes a plurality of stages, such as two stages: a first stage 510-1 and a second stage 510-2. However, other implementations of the mixer 132 can have a single stage or more than two stages. In some cases, the first stage 510-1 is implemented as a transconductance stage (or “Gm stage”) having at least one transistor, which is referred to herein as a transconductance transistor (e.g., as shown in FIG. 5A). In some cases, the second stage 510-2 is implemented as a current mirror stage (or “mirror stage”) having at least one transistor, which is referred to herein as a mirror transistor (e.g., as shown in FIG. 5A). Figures 6-9as shown). Thus, the second stage 510-2 can be implemented as a cascode stage having one or more transistors, which can be referred to herein as cascode transistors or switch transistors (including mixer switch transistors) (e.g., as shown). Figures 6-9 At least one mixer node 520 is coupled between the two stages of the mixer 132, such as between the first stage 510-1 and the second stage 510-2. Examples of multi-stage implementations of the mixer 132 having multiple transistors are described below with reference to FIGS. 6-8. Figures 6-9 Examples of multi-stage implementations of the mixer 132 having multiple transistors are described below with reference to FIGS. 6-8.

[0084] In example operations of the mixer circuit 130, the tuning circuit 134 generates the at least one bias voltage 408 based on the control signal 308. The tuning circuit 134 provides the bias voltage 408 to the mixer 132, such as to its first stage 510-1. The bias voltage 408 can affect the operation of the mixer 132 to reduce feedthrough of the LO signal 306 to the output signal 304 and to downstream components. In example aspects, the bias voltage 408 can compensate for imbalances in the positive and negative components of the mixer 132. In some implementations, the tuning circuit 134 includes at least one bias voltage generator 402 (BVG 402). The calibration circuit 138 can control the bias voltage generator 402 to generate the bias voltage 408, as described next.

[0085] As illustrated, the calibration circuit 138 includes at least one instance of the controller circuit 512, at least one resistor 514, and at least one switch 516. As described below, any one or more of these components can be coupled to at least one power distribution node 518. The power distribution node 518 can be implemented, for example, as a supply voltage node (e.g., a power rail) or a ground node (e.g., a ground plane).

[0086] In example implementations, the switch 516 is coupled between the mixer node 520 and the power distribution node 518. The resistor 514 is also coupled between the mixer node 520 and the power distribution node 518. In some cases, the switch 516 and the resistor 514 are coupled together in series between the mixer node 520 and the power distribution node 518. In at least some of such cases, the switch 516 is coupled between the resistor 514 and the mixer node 520, although other arrangements can alternatively be employed.

[0087] The controller circuit 512 is coupled between the mixer node 520 and the control input 508 of the tuning circuit 134. In some cases, the switch 516 is coupled between the mixer node 520 and the controller circuit 512. Alternatively, the switch 516 can be coupled between the mixer node 520 and the power distribution node 518 at a location that is not between the mixer node 520 and the controller circuit 512.

[0088] In an example operation, the calibration circuit 138 closes the switch 516 or places the switch 516 in a closed state. With the switch 516 closed, a current can flow between the power distribution node 518 and the transconductance transistor of the first stage 510-1 (not shown in Figure 5 The controller circuit 512 can sense or measure the level of this voltage as the signal indication 310. Because the voltage at the mixer node 520 changes based on the magnitude of the current flowing through the resistor 514 and the transconductance transistor of the first stage 510-1, this voltage can represent or indicate the magnitude of the current flowing through the transconductance transistor.

[0089] From a signal processing or information propagation perspective, or from a time perspective, the controller circuit 512 can operate "before" the tuning circuit 134. Based on the signal indication 310, the controller circuit 512 generates the control signal 308. The control signal 308 causes the tuning circuit 134 to use the bias voltage generator 402 to establish the bias voltage 408. The bias voltage generator 402 can apply the bias voltage 408 to the gate terminal of at least one transconductance transistor of the first stage 510-1. By adjusting the bias voltage 408, the current flowing through the transconductance transistor is likewise adjusted. The adjusted current changes the current flowing through the resistor 514, and thus changes the voltage measured with respect to the mixer node 520.

[0090] Accordingly, the controller circuit 512 can use the control signal 308 to change the current flowing through the transconductance transistor of the first stage 510-1 in response to changes in the signal indication 310. As described above and as depicted in Figures 6-9 In some aspects, the controller circuit 512 adjusts the positive current flowing through the positive transconductance transistor and the negative current flowing through the negative transconductance transistor to reduce the difference between them. By reducing this current offset between the positive portion and the negative portion of the mixer 132, the oscillator leakage in the output signal 304 is also reduced.

[0091] In certain figures (e.g., FIG. 5), the controller circuit 512 is shown as being separate from the tuning circuit 134. In other figures (e.g., FIG. 6), the controller circuit 512 is shown as being part of the tuning circuit 134. In some aspects, the controller circuit 512 is part of the tuning circuit 134. Figure 5In some embodiments, only a single line is used to depict the coupling of these components together, and these components can be single-ended with a single (or “unbalanced”) coupling line. However, these components can also be differential, and the coupling lines can likewise be differential (or “balanced”). For differential implementations, one or more of the depicted or described components can include a positive component and a negative component. By way of example only, the mixer node 520 can include a positive mixer node and a negative mixer node, the switch 516 can include a positive switch and a negative switch, and the resistor 514 can include a positive resistor and a negative resistor. Further, a signal can include a positive signal and a negative signal. For example, the signal indication 310 can include a positive signal indication and a negative signal indication at the same time or at different times, and the bias voltage 408 can include a positive bias voltage and a negative bias voltage to be applied to the gate of the positive transconductance transistor and the gate of the negative transconductance transistor, respectively.

[0092] The controller circuit 512 can be implemented at least in part using one or more digital circuits. These digital circuits can be part of the communication processor 124 or another part of the wireless interface device 120. Such digital circuits can also be distributed across multiple parts of the wireless interface device 120. The digital circuits can include, for example, an analog-to-digital converter (ADC) and a logic circuit, such as a state machine. The ADC can produce a digital version of the calibration signal 406. The logic circuit can determine at least one value of a register (e.g., Figure 4 based on the digital voltage level during the calibration mode). The logic circuit can iteratively use different values to reduce (if not minimize) the digital difference between the positive voltage level and the negative voltage level at the positive implementation and the negative implementation of the mixer node 520 to the extent that can be permitted given the quantization of the signal indication 310, the noise floor, and so on.

[0093] Additionally or alternatively, the controller circuit 512 can be implemented at least in part using one or more analog circuits. For example, as part of an analog control loop, the controller circuit 512 can include a comparator that compares the voltage level at the mixer node 520 (as represented by the signal indication 310) to a reference voltage level. Based on the signal indication 310, the controller circuit 512 produces the control signal 308 during the calibration mode using analog or digital circuits (e.g., a logic circuit, such as a state machine). The controller circuit 512 provides the control signal 308 to the tuning circuit 134 of the mixer circuit 130 (e.g., which can be forwarded as a digital or analog version of the calibration signal 406 with or without further processing). The use of the control signal 308 by the mixer circuit 130 is further described below with respect to FIG. 5. Figures 5-9 The use of the control signal 308 by the mixer circuit 130 is further described below with respect to FIG. 5.

[0094] Generally, the calibration circuit 138 can generate a control signal 308 to cancel out the LO signal 306 passing through ( Figure 3 The flow of a portion of the communication chain 320. In order to allow DC current to flow through the first stage 510-1 and resistor 514 without being diverted to the second stage 510-2, one or more switching transistors of the second stage 510-2 are turned off during calibration mode. By turning off one or more switching transistors of the second stage 510-2, at least one current flowing through at least one transistor of the first stage 510-1 is routed to also flow through at least one resistor 514.

[0095] In some respects, derived from at least one control signal 308 (e.g., Figure 4 At least one calibration signal 406 can be implemented as at least one calibration code determined by convergence to at least one code (e.g., a positive code and a negative code). The at least one converged code provides a minimum difference between the positive and negative voltage levels, as reflected by the positive and negative versions of signal indication 310 (which represent the positive and negative currents of the first stage 510-1). This convergence minimization of the current offset produces a minimum LOFT, at least relative to the LOFT caused by current mismatch in the transconductance transistors of the first stage 510-1 of mixer 132.

[0096] Here, minimum current offset or LOFT is the minimum value under one or more constraints, such as the implemented circuit components of calibration circuit 138, the capability of tuning circuit 134, or the available accuracy of the calibration values ​​of bits and / or control signals 308 in the digital circuitry portion of calibration circuit 138. Control signals 308 (such as, for example, Figure 4 One or more bits of at least one tuning value of the calibration signal 406 may be stored in at least one register (e.g., of the bias control circuit 404) that persists even without power. The tuning value may be stored in association with one or more other parameters (such as temperature) that can affect the tuning value. The register may be implemented using flash memory, programmable read-only memory (PROM), electrically erasable programmable read-only memory (EEPROM), one or more fuses, etc.

[0097] Therefore, in certain digital implementations of controller circuit 512, controller circuit 512 may determine whether to write to or otherwise store in at least one register during calibration mode. Figure 5 The tuning value (not shown in the diagram) is in the register. The register can be part of the controller circuit 512, part of the mixer circuit 130 (e.g., the tuning circuit 134 (such as...) Figure 4part of the bias control circuit 404), part of other control circuitry, some combination thereof, and so on. During the task mode, software, firmware, or other circuitry can read or otherwise retrieve the tuning values from the registers to apply the tuning values to the operation of the tuning circuit 134, such as to generate the calibration signal 406 that sets the bias voltage 408. Alternatively, the registers can be otherwise coupled to the tuning circuit 134 to expose their tuning values to control the operation of the tuning circuit 134.

[0098] The wireless interface device 120 can also have multiple registers. For example, one register can hold the tuning values without power (e.g., via non-volatile memory cells), and another register can hold the tuning values during the task mode after software, firmware, or circuitry loads the tuning values from one (non-volatile) register to the other (volatile) register. In other implementations, the calibration mode and the task mode can be merged, or the device can switch between the two modes fast enough and / or frequently enough that the calibration process is performed in a continuous loop or in a partially or fully continuous loop.

[0099] In some implementations, the device can enter the calibration mode and / or perform the calibration process once (or a few times) during manufacturing, and then can use the determined tuning values during the entire lifetime of the device during instances of the task mode. Additionally or alternatively, the device can enter the calibration mode and / or perform the calibration process multiple times after the device reaches the user. For example, the calibration process can be performed during power-up or reset, performed at regular intervals (e.g., twice a day or once an hour), performed during periods when the wireless interface device 120 is otherwise unused, performed in response to changing environmental (e.g., temperature or power level), performed based on changes in the location of the device, performed in combinations thereof, and so on. Each time the device enters the calibration mode and runs the calibration process, the stored tuning values can be updated. The device can then use the updated tuning values in the task mode.

[0100] Figures 6-9 are circuit diagrams 600-900, respectively, illustrating example mixer circuit 130 each including a respective instance of the tuning circuit 134 implemented with at least one bias voltage generator 402 (e.g., also as the tuning circuit of Figure 1 、 Figure 3 、 Figure 4 and Figure 5 The circuit diagrams 600-900 also illustrate example implementations of the calibration circuit 138 as the controller circuit 512, at least one resistor 514, and at least one switch 516. The first stage 510-1 and the second stage 510-2 of the mixer 132 are next described in conjunction with reference to Figures 6-9 Figure 1 ​Figure 3 Figure 4 Figure 5

[0101] The first stage 510-1 includes at least one transistor T, such as a positive transistor T+ and a negative transistor T-. These two transistors are also referred to herein as transconductance transistors. The second stage 510-2 includes one or more transistors M, such as a positive transistor M1+, a negative transistor M1-, another positive transistor M2+, and another negative transistor M2-. These four transistors are also referred to herein as switching transistors or mixer switching transistors.

[0102] The transistors of the mixer 132 can be arranged according to, for example, a double-balanced Gilbert cell architecture. The illustrated Gilbert cell architecture includes a supply or load line 602. The supply or load line 602 is coupled to a supply voltage (V.Supp) that can correspond to a power distribution node and to the one or more transistors M of the second stage 510-2. The at least one transistor T of the first stage 510-1 is coupled between the second stage 510-2 and the power distribution node, which in this example corresponds to ground. Thus, ground and the supply voltage (V.Supp) are two examples of the power distribution node in Figures 6-9

[0103] Each transistor T or transistor M can be implemented with any one or more of a variety of transistor types. Example transistor types include field effect transistors (FETs), junction FETs (JFETs), metal oxide semiconductor FETs (MOSFETs), bipolar junction transistors (BJTs), insulated gate bipolar transistors (IGBTs), and so forth. Manufacturers can manufacture FETs as either n-channel or p-channel transistor types and can manufacture BJTs as either NPN or PNP transistor types.

[0104] Each transistor can include at least one control terminal and one or more channel terminals. For FET transistors, the control terminal can correspond to a gate terminal, and the channel terminals can correspond to source terminals or drain terminals. For BJT transistors, the control terminal can correspond to a base terminal, and the channel terminals can correspond to emitter terminals or collector terminals. In some cases, the source terminal of an FET is analogous to the emitter terminal of a BJT, and the drain terminal of an FET is analogous to the collector terminal of a BJT. Thus, in Figures 6-9

[0105] ​​​​​​For a FET, the gate terminal can be implemented as a front gate terminal or a back gate terminal. In some cases, an FET may have both a front gate terminal and a back gate terminal (also referred to as a body terminal). Therefore, a positive transistor T+ may include a positive back gate terminal and a positive front gate terminal. Similarly, a negative transistor T- may include a negative back gate terminal and a negative front gate terminal.

[0106] To give just one example, Figures 6-9 The components are described as having a specific type of transistor (FET) because the described principles can be implemented using other types of transistors. Furthermore, in Figures 6-9 In this approach, components are arranged in a specific manner, such as utilizing a double-balanced architecture with a Gilbert cell configuration. However, alternative circuit arrangements may be employed for an alternative implementation of oscillator leakage calibration.

[0107] In the specific implementation of the example, (for example, Figure 5 The transistors of mixer 132 can be coupled together, such as Figures 6-9 As shown. For example, at least one transistor T of the first stage 510-1 is coupled between mixer input 502 (e.g., positive mixer input 502+ or negative mixer input 502-) and mixer output 504 (e.g., positive mixer output 504+ or negative mixer output 504-). One or more transistors M of the second stage 510-2 are coupled between at least one transistor T of the first stage 510-1 and mixer output 504. One or more transistors M are also coupled between local oscillator signal input 506 (e.g., positive LO signal input 506+ or negative LO signal input 506-) and mixer output 504. (e.g., Figure 4 and Figure 5 The bias voltage generator 402 of the tuning circuit 134 generates at least one bias voltage 408 (e.g., a positive bias voltage 408+ or a negative bias voltage 408-). At least one voltage 408 (e.g., a positive bias voltage 408+ or a negative bias voltage 408-) is coupled to the gate terminal of at least one transistor T (e.g., a positive transistor T+ or a negative transistor T-, respectively) of the first stage 510-1.

[0108] As shown in the specific implementation for differential signaling, each signal can be implemented using differential signals. Therefore, input signal 302 can be implemented as a positive input signal 302+ and a negative input signal 302-. Output signal 304 can be implemented as a positive output signal 304+ and a negative output signal 304-. Furthermore, LO signal 306 can be implemented as a positive LO signal 306+ and a negative LO signal 306-. Input signal 302 is coupled to mixer 132 via at least one gate terminal (e.g., front gate terminal) of at least one transistor T of the first stage 510-1. (e.g., Figures 1-3The local oscillator 136 is coupled to the mixer 132 via respective gate terminals of one or more transistors M of the second stage 510-2.

[0109] To perform the calibration process, one or more transistors M1+, M1-, M2+, and M2- of the second stage 510-2 of the mixer circuit 130 can be turned off to focus the analysis on the DC current flowing through the transconductance transistors of the first stage 510-1 of the mixer circuit 130. This off state is indicated in Figures 6-9 by depicting the mixer switch transistors for the calibration mode with short dashed lines. By turning off one or more transistors M1+, M1-, M2+, and M2- of the second stage 510-2, the current flowing through the positive transistor T+ and the negative transistor T- of the first stage 510-1 is directed to also flow through the resistor 514, or through the positive resistor 514+ and the negative resistor 514-, respectively.

[0110] Now the Figure 6 , Figure 7 , Figure 8 , and Figure 9 are handled individually to describe aspects of the various implementations depicted in the circuit diagrams 600, 700, 800, and 900, respectively. Figure 6 and Figure 7 both employ a comparator 512-1 as part of the controller circuit 512. However, the circuit diagram 600 couples the adjustable bias voltage 408 to the back gate terminals (e.g., body terminals) of the transistors of the first stage 502-1, but the circuit diagram 700 couples the adjustable bias voltage 408 to the front gate terminals of these transistors. Figure 8 and Figure 9 both employ an ADC 512-3 as part of the controller circuit 512. However, the circuit diagram 800 couples the adjustable bias voltage 408 to the back gate terminals (e.g., body terminals) of the transistors of the first stage 502-1, but the circuit diagram 900 couples the adjustable bias voltage 408 to the front gate terminals of these transistors.

[0111] Figure 6 is a circuit diagram 600 that illustrates an example mixer circuit 130 and an example calibration circuit that employs at least one comparator 512-1 to adjust a back gate bias voltage 408 of a transconductance transistor T of the mixer circuit 130. In the example implementation, at least one resistor 514 is switchably coupled to a positive mixer node 520+ and a negative mixer node 520-. A positive switch 516+ is coupled between the resistor 514 and the positive mixer node 520+. A negative switch 516- is coupled between the resistor 514 and the negative mixer node 520-.

[0112] The resistor 514 is coupled between a power distribution node 518 (e.g., a supply voltage node (SVN)) and at least one mixer node 520. The at least one switch 516 can likewise be coupled between the power distribution node 518 and the at least one mixer node 520. As shown, the at least one switch 516 and the at least one resistor 514 can be coupled together in series between the power distribution node 518 and the at least one mixer node 520. More specifically, the positive switch 516+ and the resistor 514 can be coupled in series between the positive mixer node 520+ and the power distribution node 518. Similarly, the negative switch 516- and the resistor 514 can be coupled in series between the negative mixer node 520- and the power distribution node 518.

[0113] The comparator 512-1 includes a first input, a second input, and an output. The first input is coupled to a node 604 coupled between the at least one switch 516 (e.g., the positive switch 516+ and the negative switch 516-) on one side and the resistor 514 on the other side. The second input is coupled to a reference voltage (V.ref). The reference voltage can be selected to obtain or achieve a target or specified current to be drawn through the at least one transistor T of the first stage 510-1. The output of the comparator 512-1 is typically coupled to an input of a state machine 512-2 or logic circuit. The state machine 512-2 can control the operation of the calibration process, which will be described below.

[0114] The output of the state machine 512-2 is provided to the bias voltage generator 402. Although not shown in FIG. 4 for the sake of clarity, the bias control circuit 404 (e.g., of FIG. 3) can be coupled between the state machine 512-2 and the bias voltage generator 402 to control the bias voltage generator 402 (e.g., by storing or otherwise maintaining a tuning value that sets the bias voltage 408). The bias voltage generator 402 generates at least one bias voltage 408, such as a positive bias voltage 408+ and a negative bias voltage 408-. The bias voltage generator 402 can provide the bias voltage 408 to a back gate terminal or body terminal of the at least one transistor T. Thus, the positive bias voltage 408+ can be coupled to a back gate terminal of the positive transistor T+ and the negative bias voltage 408- can be coupled to a back gate terminal of the negative transistor T-. Figures 6-9 Figure 4 The bias control circuit 404 (e.g., of FIG. 3) can be coupled between the state machine 512-2 and the bias voltage generator 402 to control the bias voltage generator 402 (e.g., by storing or otherwise maintaining a tuning value that sets the bias voltage 408). The bias voltage generator 402 generates at least one bias voltage 408, such as a positive bias voltage 408+ and a negative bias voltage 408-. The bias voltage generator 402 can provide the bias voltage 408 to a back gate terminal or body terminal of the at least one transistor T. Thus, the positive bias voltage 408+ can be coupled to a back gate terminal of the positive transistor T+ and the negative bias voltage 408- can be coupled to a back gate terminal of the negative transistor T-.

[0115] By way of example only, the back gate terminal can be designed into a transistor built with a fully depleted silicon on insulator (FDSOI) technology. For example, the back gate (or body) terminal can be used to change the threshold voltage of the transistor. Thus, changing the level of the bias voltage 408 applied to the back gate terminal of the transistor T changes the threshold voltage of the transistor T. For example, increasing the level of the bias voltage 408 applied to the back gate terminal of the transistor T can decrease the threshold voltage of the transistor T. ​

[0116] In example operations, state machine 512-2 can control operation of a calibration process by (e.g., calibration circuit 138 of Figure 1 , Figure 3 , Figure 4 and Figure 5 ). State machine 512-2 may, for example, control switch states. With positive switch 516+ in a closed state and negative switch 516- in an open state, current can flow through resistor 514 and positive transistor T+ between power distribution node 518 and ground. The current, due to a voltage drop from supply voltage node (SVN) caused by the current flowing through resistor 514, creates a voltage at node 604. A first input (e.g., the “+” input) of comparator 512-2 senses or measures the positive voltage V+ at node 604.

[0117] Comparator 512-1 compares the measured voltage from node 604 to a reference voltage (V.ref) at a second input (e.g., the “-” input). In response to a difference between the two voltages, comparator 512-1 produces an output signal that indicates the voltage difference. State machine 512-2 produces control signal 308 to reduce the voltage difference. The voltage difference can be reduced until, for example, the output of comparator 512-1 toggles back and forth. Thus, control signal 308 can cause bias voltage generator 402 to reduce or increase positive bias voltage 408+ to reduce the difference between the voltage at node 604 (which corresponds to the voltage at positive mixer node 520+) and the reference voltage (V.ref).

[0118] State machine 512-2 repeats the process for the negative portion of the mixer. With negative switch 516- in a closed state and positive switch 516+ in an open state, current can flow through resistor 514 and negative transistor T- between power distribution node 518 and ground. A first input (e.g., the “+” input) of comparator 512-2 senses or measures the negative voltage V- at node 604. Here, for Figure 6 and Figure 7 , node 604 can form a common node for analyzing the positive and negative portions of mixer circuit 130. State machine 512-2 causes bias voltage generator 402 to adjust negative bias voltage 408- to reduce the difference between the voltage at node 604 (which corresponds to the voltage at negative mixer node 520-) and the reference voltage (V.ref). The voltage difference can be reduced to within tolerances allowed by the hardware components, whether the control components are analog, digital, or a combination thereof.

[0119] In these ways, the current flowing through the positive transistor T+ and the negative transistor T- can be calibrated to be substantially equal, thereby reducing the current offset between the positive and negative branches of the mixer. Since current offset and oscillator leakage are related, this reduction in current offset also reduces oscillator leakage. By using at least one identical resistor for both the positive and negative portions of the calibration process, circuit diagram 600 can omit the "double sampling," which might otherwise be used to address resistor mismatch. By omitting double sampling, a single switch 516 (e.g., instead of a pair of switches) can be coupled to each of the positive mixer node 520+ and the negative mixer node 520- in the circuit to support the calibration process. Therefore, a single switch for each positive / negative node or differential branch applies less parasitic capacitance at the source terminal of the switching transistor M of the second stage 510-2 compared to two switches for each positive / negative node or differential branch. Parasitic effects at these terminals can significantly affect mixers, especially those with high-frequency LO signals, because the swing at these nodes is twice the LO frequency.

[0120] Figure 7 This is circuit diagram 700 illustrating an example mixer circuit 130 and an example calibration circuit, which uses comparator 512-1 to adjust the front gate bias voltage of the transconductance transistor T of mixer circuit 130. Circuit diagram 700 is similar to circuit diagram 600 except for how the bias voltage generator 402 is coupled to the transconductance transistor of the first stage 510-1. Although not shown in the figures, circuit diagram 700 (and...) Figure 9 The positive input signal 302+ and the negative input signal 302- can be coupled to the front gate of the positive transconductance transistor T+ and the negative transconductance transistor T- using at least one capacitor (e.g., an AC coupling capacitor).

[0121] In some cases, based on process technology or circuit layout, it may be more feasible to adjust the bias voltage on the front gate terminals of the positive transconductance transistor T+ and the negative transconductance transistor T- rather than the bias voltage on their back gate terminals. Figure 6 The calibration scheme described herein can be applied to or implemented for front-gate transistor biasing. For example... Figure 7 As shown, the output of at least one bias voltage generator 402 can be coupled to the front gate terminal of at least one transistor T of the first stage 510-1. Therefore, the bias voltage generator 402 can apply a positive bias voltage 408+ to the front gate terminal of the positive transistor T+. The bias voltage generator 402 can also, or alternatively, apply a negative bias voltage 408- to the front gate terminal of the negative transistor T-.

[0122] The calibration process can be similar to that for... Figure 6However, compared to the bias voltage generator 402 coupled to the back gate terminal of the transconductance transistor, the bias voltage generator 402 coupled to the front gate terminal of the transconductance transistor involves employing a higher resolution. The resolution difference can be an order of magnitude difference. For example, for a given ampere resolution of current flowing through the transconductance transistor, the bias generator voltage step for front gate control can be approximately 100 microvolts (uV), but the bias generator voltage step for back gate control can be approximately 1 millivolt (mV).

[0123] For at least some process technologies and circuits, the current offset of a mixer can vary linearly with temperature for a substantial portion of an operating temperature range (e.g., from below 0 degrees Celsius (°C) to near 100 °C). In at least some of such cases, a bias voltage generator with a temperature slope characteristic can be used to compensate for the current offset variation over a given temperature range. For example, a linear factor that scales with temperature variation can be applied to the tuning values of the bias control circuit 404 of the tuning circuit 134. This can reduce the frequency of repeating the calibration process. A temperature-compensated bias voltage generator 402 can be deployed in any of the implementations described herein or depicted in the figures, including Figures 6-9 implementations of the bias voltage generator 402.

[0124] Figure 8 is a circuit diagram 800 that illustrates an example mixer circuit 130 and an example calibration circuit that employs an analog-to-digital converter 512-3 (ADC 512-3) to adjust the back gate bias voltage or body bias voltage of the transconductance transistor T of the mixer circuit 130. The circuit diagram 800 is similar to the circuit diagram 600, except for how the at least one resistor 514 is coupled to the at least one mixer node 520 and how the controller circuit 512 is implemented.

[0125] In an example implementation, the at least one resistor 514 is implemented with a positive resistor 514+ and a negative resistor 514-. The positive resistor 514+ is switchably coupled to the positive mixer node 520+, and the negative resistor 514- is switchably coupled to the negative mixer node 520-. A positive switch 516+ is coupled between the positive resistor 514+ and the positive mixer node 520+. A negative switch 516- is coupled between the negative resistor 514- and the negative mixer node 520-.

[0126] Positive resistor 514+ and negative resistor 514- are coupled between a power distribution node 518 (e.g., supply voltage node (SVN)) and positive mixer node 520+ and negative mixer node 520-, respectively. Positive switch 516+ and negative switch 516- can likewise be coupled between power distribution node 518 and positive mixer node 520+ and negative mixer node 520-, respectively. As shown, at least one of the mixer nodes 516 and at least one of the resistors 514 can be coupled together in series between power distribution node 518 and at least one of the mixer nodes 520. More specifically, positive switch 516+ and positive resistor 514+ can be coupled together in series between positive mixer node 520+ and power distribution node 518. Similarly, negative switch 516- and negative resistor 514- can be coupled in series between negative mixer node 520- and power distribution node 518.

[0127] This results in a positive node 604+ coupled between positive switch 516+ on one side and positive resistor 514+ on the other side, and a negative node 604- coupled between negative switch 516- on one side and negative resistor 514- on the other side. A positive voltage at positive node 604+ and a negative voltage at negative node 604- can be coupled to controller circuit 512. Specifically, ADC 512-3 can have two inputs: a positive input (or first input) coupled to positive node 604+ and a negative input (or second input) coupled to negative node 604-. Alternatively, ADC 512-3 can have a single input that can be switchably coupled to positive node 604+ and negative node 604-. At least one output of ADC 512-3 is coupled to at least one input of state machine 512-2.

[0128] In example operations, under control of state machine 512-2, ADC 512-3 obtains samples of the positive voltage and the negative voltage at positive node 604+ and negative node 604-, respectively. The positive voltage sample can be obtained with positive switch 516+ closed and negative switch 516- open, and the negative voltage sample can be obtained with positive switch 516+ open and negative switch 516- closed. ADC 512-3 provides at least one ADC output signal 802 to state machine 512-2. In some cases, ADC output signal 802 corresponds to a digital value (e.g., a code) based on the positive voltage and the negative voltage (in analog form), such as the difference between the positive analog voltage and the negative analog voltage being implemented as the digital value. Alternatively, ADC 512-3 can convert the positive analog voltage sample and the negative analog voltage sample to a positive digital value and a negative digital value (e.g., codes), and forward these two digital values as at least one ADC output signal 802 to state machine 512-2. State machine 512-2 causes bias voltage generator 402 to adjust the positive bias voltage 408+ and the negative bias voltage 408- to reduce the difference between the two digital values. For example, the difference can be reduced to the limit of the resolution provided by the components, such as the bit width of ADC 512-3 or the step size of bias voltage generator 402. In circuit diagram 800, these positive bias voltage 408+ and negative bias voltage 408- are coupled to the back gate terminals of positive transistor T+ and negative transistor T-.

[0129] In comparison to circuit diagram 600 and circuit diagram 700, circuit diagram 800 can omit comparator 512-1. Furthermore, ADC 512-3 need not be an ADC dedicated for current offset calibration. Rather, ADC 512-3 can be an ADC borrowed from other circuits, such as ADC 210 used to receive signals in task mode. Figure 2 In general, many SoCs include at least one ADC that can be used as ADC 512-3 for the calibration process. Although the ADC approach can avoid using a comparator by employing positive resistor 514+ and negative resistor 514-, the calibration accuracy can be adversely affected with respect to mismatch between the two different resistance values for the ADC approach.

[0130] Double sampling can be used to eliminate resistor mismatch. Double sampling requires coupling each resistor to positive mixer node 520+ and negative mixer node 520- to obtain four sampled voltages. However, this double sampling involves opening and closing switches 516+ and 516- twice for each resistor, which can be time consuming. Figure 8In addition to the positive switch 516+ and negative switch 516- depicted, two more switches are added. Doubling this switch count from two to four enhances the detrimental parasitic effects at the source terminals of the mixer switching transistors. As described above, managing the parasitic effects at these nodes avoids adversely affecting mixer performance, especially for mixers with high-frequency LO signals, as these nodes experience voltage swings at twice the LO frequency. Additionally, the parasitic components at positive mixer node 520+ and negative mixer node 520- can limit the bandwidth of IF signaling.

[0131] Figure 9 This is circuit diagram 900 illustrating an example mixer circuit 130 and an example calibration circuit, which uses an analog-to-digital converter 512-3 to adjust the front gate bias voltage of the transconductance transistor T in mixer circuit 130. Circuit diagram 900 is similar to circuit diagram 800 except for how the bias voltage generator 402 is coupled to the transconductance transistors T+ and T- of the first stage 510-1.

[0132] Figure 8 The calibration scheme described herein can be applied to or implemented for front-gate transistor biasing. For example... Figure 9 As shown, the output of at least one bias voltage generator 402 can be coupled to the front gate terminal of at least one transistor T of the first stage 510-1. Therefore, the bias voltage generator 402 can apply a positive bias voltage 408+ to the front gate terminal of the positive transistor T+. Furthermore, the bias voltage generator 402 can apply a negative bias voltage 408- to the front gate terminal of the negative transistor T-. The calibration process can be performed by state machine 512-2, as described above with respect to circuit diagram 800. However, the above reference... Figure 7 The characteristics of the described front gate bias also apply.

[0133] Figure 10 This is a flowchart illustrating an example process 1000 for performing a calibration procedure to compensate for oscillator leakage associated with mixer circuitry or for operating calibration circuitry relative to the mixer. Process 1000 includes six blocks 1002-1012 specifying operations that can be performed for the method. In the example implementation, the operations of blocks 1002-1012 can be performed during calibration mode.

[0134] To perform the calibration process in calibration mode, one or more transistors M1+, M1-, M2+, and M2- of the second stage 510-2 of mixer circuit 130 can be turned off to focus the analysis on the DC current flowing through the transconductance transistors of the first stage 510-1 of mixer circuit 130. This off state... Figures 6-9The at least one current flowing through the positive and negative transistors T+ and T- of the first stage 510-1 is directed to also flow through the resistor 514, or through the positive and negative resistors 514+, 514- respectively, by turning off or switching off one or more of the transistors M1+, M1-, M2+, and M2- of the second stage 510-2. The accuracy of the DC measurement can also be improved by turning off the local oscillator or by disconnecting the local oscillator signal 306 from the gate terminals of one or more of the transistors M1+, M1-, M2+, and M2- of the second stage 510-2.

[0135] At block 1002, the calibration circuit closes a positive switch to connect the at least one resistor to a positive mixer node coupled between a positive transistor of a first stage of a mixer circuit and a second stage of the mixer circuit. For example, the controller circuit 512 can close the positive switch 516+ to connect the at least one resistor 514 to the positive mixer node 520+ coupled between the positive transistor T+ of the first stage 510-1 of the mixer circuit 130 and the second stage 510-2 of the mixer circuit 130. The connection can enable a positive DC current to flow through the at least one resistor 514 and the positive transistor T+ between the two power distribution nodes.

[0136] At block 1004, the calibration circuit measures a positive voltage corresponding to the positive transistor of the first stage of the mixer circuit using the at least one resistor. For example, the controller circuit 512 can measure the positive voltage V+ corresponding to the positive transistor T+ of the first stage 510-1 of the mixer circuit 130 using the at least one resistor 514. In some cases, the positive voltage V+ can be associated with a voltage drop across the at least one resistor 514 due to the positive DC current flowing through the at least one resistor 514 in addition to the positive transistor T+.

[0137] At block 1006, the calibration circuit disconnects the at least one resistor from the positive mixer node. For example, the controller circuit 512 can disconnect the at least one resistor 514 from the positive mixer node 520+. Thus, the resistor 514 that can be used to measure the positive and negative voltages can be disconnected from the positive mixer node 520+, or the positive resistor 514+ that is used to measure the positive voltage can be disconnected from the positive mixer node 520+.

[0138] At block 1008, the calibration circuit closes a negative switch to connect the at least one resistor to a negative mixer node coupled between a negative transistor of a first stage of the mixer circuit and a second stage of the mixer circuit. For example, the controller circuit 512 can close the negative switch 516- to connect the at least one resistor 514 to the negative mixer node 520- coupled between the negative transistor T- of the first stage 510-1 of the mixer circuit 130 and the second stage 510-2 of the mixer circuit 130. Here, the connection can require the resistor 514 or a negative resistor 514 available to measure the positive voltage and the negative voltage at different times.

[0139] At block 1010, the calibration circuit measures a negative voltage corresponding to a negative transistor of the first stage of the mixer circuit using the at least one resistor. For example, the controller circuit 512 can measure a negative voltage V- corresponding to the negative transistor T- of the first stage 510-1 of the mixer circuit 130 using the at least one resistor 514. Thus, the comparator 512-1 or the ADC 512-3 can obtain an indication of the positive DC current corresponding to the positive transistor T+ and the negative DC current corresponding to the negative transistor T- across the operations of block 1004 and block 1010.

[0140] At block 1012, the calibration circuit adjusts at least one bias voltage applied to at least one of the positive transistor or the negative transistor of the first stage of the mixer circuit based on the positive voltage and the negative voltage. For example, the controller circuit 512 can adjust at least one bias voltage 408 applied to at least one of the positive transistor T+ or the negative transistor T- of the first stage 510-1 of the mixer circuit 130 based on the positive voltage V+ and the negative voltage V-. This can be performed by the state machine 512-2, for example, to reduce a difference between the positive voltage V+ and the negative voltage V-. This can reduce a current offset of the mixer circuit 130 by adjusting the bias voltage 408 applied to at least one front gate terminal or at least one back gate terminal of a transconductance transistor of the first stage 510-1.

[0141] The operations of block 1012 can occur as part of a calibration mode. Subsequently, at least one stored tuning value determined during the calibration mode can be used in a task mode. For example, the tuning value can be used to tune the mixer circuit 130. In some cases, the determined tuning value can be retrieved from one register and loaded into another register coupled to the tuning circuit 134 or a portion thereof (e.g., a portion of the bias control circuit 404). The tuning circuit 134 can use the reserved tuning value generated during the calibration mode to tune the operation of the mixer 132 during the task mode.

[0142] Figure 10is a flow diagram illustrating example processes or methods related to oscillator leakage calibration. These processes are described in terms of a collection of blocks in a representative order. However, the operations do not necessarily have to be performed in the order discussed, since some of the operations can be performed in other orders or even in parallel. Moreover, one or more additional or different operations can be performed, depending on the circumstances. The operations represented by the illustrated blocks of each process can be performed by electronic devices, such as the electronic device 102 or the wireless interface device 120 of the electronic device. More specifically, the operations of the respective processes can be performed by the transceiver 126 or the mixer circuit 130 of the RF front end 128 in conjunction with other components, such as the calibration circuit 138. Figure 1

[0143] Detailed Examples

[0144] This section describes some aspects of example implementations and / or example configurations related to the apparatus and / or processes presented above.

[0145] Example Aspect 1 : An apparatus comprising:

[0146] a mixer circuit comprising:

[0147] a first stage comprising at least one transistor coupled between a mixer input and a mixer output;

[0148] a second stage comprising one or more transistors coupled between the at least one transistor of the first stage and the mixer output, the one or more transistors coupled between a local oscillator signal input and the mixer output; and

[0149] a tuning circuit coupled to the at least one transistor of the first stage; and

[0150] a calibration circuit comprising:

[0151] at least one resistor coupled between a power distribution node and at least one mixer node, the at least one mixer node coupled between the at least one transistor of the first stage and the one or more transistors of the second stage;

[0152] at least one switch coupled between the power distribution node and the at least one mixer node; and

[0153] a controller circuit coupled between the at least one mixer node and the tuning circuit.

[0154] ​Example Aspect 2: The apparatus of Example Aspect 1, wherein:

[0155] the at least one switch is coupled in series with the at least one resistor between the power distribution node and the at least one mixer node; and

[0156] the at least one switch is coupled between the at least one resistor and the at least one mixer node.

[0157] Example Aspect 3: The apparatus of Example Aspect 2 or 3, wherein:

[0158] the controller circuit is coupled between the tuning circuit and another node, the another node being coupled between the at least one switch and the at least one resistor.

[0159] Example Aspect 4: The apparatus of any of the preceding Example Aspects, wherein:

[0160] the controller circuit includes a comparator having a first input and a second input;

[0161] the first input of the comparator is coupled to the at least one mixer node; and

[0162] the second input of the comparator is coupled to a node configured to provide a reference voltage.

[0163] Example Aspect 5: The apparatus of Example Aspect 4, wherein:

[0164] the comparator has an output coupled to the tuning circuit; and

[0165] the controller circuit is configured to:

[0166] provide a control signal to the tuning circuit; and

[0167] adjust the control signal based on the reference voltage at the second input of the comparator and a voltage present at the first input of the comparator.

[0168] Example Aspect 6: The apparatus of Example Aspect 5, wherein:

[0169] the controller circuit is configured to adjust the control signal until the voltage present at the first input of the comparator is substantially equal to the reference voltage at the second input of the comparator; and

[0170] the voltage present at the first input of the comparator is representative of a current flowing through the at least one transistor of the first stage of the mixer circuit.

[0171] Example Aspect 7: The apparatus of Example Aspect 5 or 6, wherein:

[0172] the tuning circuit includes at least one bias voltage generator;

[0173] the at least one bias voltage generator is configured to apply at least one bias voltage to at least one gate of the at least one transistor of the first stage of the mixer circuit; and

[0174] the controller circuit is configured to adjust the control signal to vary the at least one bias voltage applied by the at least one bias voltage generator to the at least one gate of the at least one transistor of the first stage of the mixer circuit.

[0175] Example Aspect 8: The apparatus of Example Aspect 7, wherein:

[0176] the at least one transistor of the first stage of the mixer circuit includes a positive transistor and a negative transistor of the first stage of the mixer circuit;

[0177] the at least one bias voltage includes a positive bias voltage and a negative bias voltage;

[0178] the controller circuit is configured to adjust the control signal to vary the positive bias voltage based on a positive current flowing through the positive transistor; and

[0179] the controller circuit is configured to adjust the control signal to vary the negative bias voltage based on a negative current flowing through the negative transistor.

[0180] Example Aspect 9: The apparatus of any of the preceding Example Aspects, wherein:

[0181] the at least one resistor includes a positive resistor and a negative resistor.

[0182] Example Aspect 10: The apparatus of Example Aspect 9, wherein:

[0183] the at least one transistor of the first stage of the mixer circuit includes a positive transistor and a negative transistor; and

[0184] the controller circuit is configured to:

[0185] measure a positive voltage corresponding to the positive resistor and the positive transistor and a negative voltage corresponding to the negative resistor and the negative transistor;

[0186] provide a control signal to the tuning circuit; and

[0187] adjust the control signal based on the positive voltage and the negative voltage.

[0188] Example Aspect 11 : The apparatus of Example Aspect 10, wherein:

[0189] the positive voltage represents a positive current flowing through the positive transistor of the first stage of the mixer circuit, and the negative voltage represents a negative current flowing through the negative transistor of the first stage of the mixer circuit; and

[0190] the controller circuit is configured to adjust the control signal to reduce a difference between the positive voltage and the negative voltage.

[0191] Example Aspect 12: The apparatus of any of Example Aspects 9-11, wherein:

[0192] the controller circuit includes at least one analog-to-digital converter having at least one input, the at least one input of the analog-to-digital converter coupled to the positive resistor and the negative resistor.

[0193] Example Aspect 13: The apparatus of any of the preceding Example Aspects, wherein:

[0194] the tuning circuit includes at least one bias voltage generator;

[0195] the at least one transistor of the first stage includes a gate terminal; and

[0196] the at least one bias voltage generator of the tuning circuit is coupled to the gate terminal of the at least one transistor of the first stage.

[0197] Example Aspect 14: The apparatus of Example Aspect 13, wherein:

[0198] the gate terminal of the at least one transistor of the first stage includes a front gate terminal.

[0199] Example Aspect 15: The apparatus of Example Aspect 13, wherein:

[0200] the gate terminal of the at least one transistor of the first stage includes a back gate terminal.

[0201] Example Aspect 16: The apparatus of any of the preceding Example Aspects, wherein:

[0202] the tuning circuit includes at least one bias voltage generator, the at least one bias voltage generator including:

[0203] one or more current sources coupled between a first power distribution node and a second power distribution node; and

[0204] one or more resistors coupled in series with the one or more current sources between the first power distribution node and the second power distribution node.

[0205] Example Aspect 17: The apparatus of Example Aspect 16, wherein the one or more current sources comprise at least one adjustable current source.

[0206] Example Aspect 18: The apparatus of Example Aspect 16 or 17, wherein the one or more resistors comprise at least one adjustable resistor.

[0207] Example Aspect 19: The apparatus of any of the preceding Example Aspects, wherein:

[0208] the at least one transistor of the first stage comprises a positive first transistor and a negative first transistor;

[0209] the one or more transistors of the second stage comprise a positive second transistor and a negative second transistor;

[0210] the at least one mixer node comprises a positive mixer node and a negative mixer node, the positive mixer node coupled between the positive first transistor and the positive second transistor, the negative mixer node coupled between the negative first transistor and the negative second transistor; and

[0211] the at least one switch comprises a positive switch and a negative switch, the positive switch coupled in series with the at least one resistor between the power distribution node and the positive mixer node, the negative switch coupled in series with the at least one resistor between the power distribution node and the negative mixer node.

[0212] Example Aspect 20: The apparatus of any of the preceding Example Aspects, further comprising:

[0213] a wireless interface device comprising the mixer circuit and the calibration circuit;

[0214] a display screen; and

[0215] at least one processor operatively coupled to at least a portion of the wireless interface device and the display screen, the at least one processor configured to present one or more graphical images on the display screen based on one or more wireless signals communicated using the mixer circuit of the wireless interface device.

[0216] Example Aspect 21 : An apparatus comprising:

[0217] a mixer circuit, the mixer circuit comprising:

[0218] a first stage comprising at least one transistor coupled between a mixer input and a mixer output;

[0219] a second stage comprising one or more transistors coupled between the at least one transistor of the first stage and the mixer output; and

[0220] a means for tuning the at least one transistor of the first stage; and

[0221] a calibration circuit, the calibration circuit comprising:

[0222] at least one resistor coupled between a power distribution node and at least one mixer node, the at least one mixer node being coupled between the at least one transistor of the first stage and the one or more transistors of the second stage;

[0223] at least one switch coupled in series with the at least one resistor between the power distribution node and the at least one mixer node; and

[0224] a means for controlling the means for tuning based on at least one voltage associated with the at least one resistor.

[0225] Example Aspect 22: The apparatus of example aspect 21, wherein:

[0226] the at least one transistor of the first stage comprises a positive transistor and a negative transistor;

[0227] the at least one voltage comprises a positive voltage corresponding to the positive transistor and a negative voltage corresponding to the negative transistor; and

[0228] the means for controlling comprises a means for controlling the means for tuning based on the positive voltage and the negative voltage.

[0229] Example Aspect 23: The apparatus of example aspect 22, wherein:

[0230] the means for tuning comprises a means for adjusting a positive bias voltage of the positive transistor and a negative bias voltage of the negative transistor; and

[0231] the means for controlling comprises a means for controlling the means for tuning to reduce a difference between the positive voltage and the negative voltage by adjusting the positive bias voltage of the positive transistor and the negative bias voltage of the negative transistor.

[0232] Example Aspect 24: A method for mixer calibration, the method comprising:

[0233] closing a positive switch to connect at least one resistor to a positive mixer node, the positive mixer node being coupled between a positive transistor of a first stage of a mixer circuit and a second stage of the mixer circuit;

[0234] measuring, using the at least one resistor, a positive voltage corresponding to the positive transistor of the first stage of the mixer circuit;

[0235] opening the positive switch to disconnect the at least one resistor from the positive mixer node;

[0236] closing a negative switch to connect the at least one resistor to a negative mixer node, the negative mixer node being coupled between a negative transistor of the first stage of the mixer circuit and the second stage of the mixer circuit;

[0237] measuring, using the at least one resistor, a negative voltage corresponding to the negative transistor of the first stage of the mixer circuit; and

[0238] adjusting at least one bias voltage applied to at least one of the positive transistor or the negative transistor of the first stage of the mixer circuit based on the positive voltage and the negative voltage.

[0239] Example Aspect 25: The method of example aspect 24, wherein the adjusting comprises:

[0240] adjusting a positive bias voltage applied to the positive transistor and a negative bias voltage applied to the negative transistor to reduce a difference between the positive voltage and the negative voltage.

[0241] Example Aspect 26: The method of example aspect 24 or 25, wherein the adjusting comprises:

[0242] adjusting the at least one bias voltage applied to at least one of the positive transistor or the negative transistor to reduce a current offset between a positive current flowing through the positive transistor and a negative current flowing through the negative transistor.

[0243] Example Aspect 27: An apparatus, the apparatus comprising:

[0244] a communication chain, the communication chain comprising:

[0245] a mixer, the mixer comprising:

[0246] a positive transistor comprising a positive channel terminal and a positive gate terminal; and

[0247] a negative transistor comprising a negative channel terminal and a negative gate terminal;

[0248] at least one resistor;

[0249] a positive switch coupled in series with the at least one resistor between the positive channel terminal of the positive transistor and a power distribution node, a positive node being coupled between the positive switch and the at least one resistor;

[0250] a negative switch coupled in series with the at least one resistor between the negative channel terminal of the negative transistor and the power distribution node, a negative node being coupled between the negative switch and the at least one resistor;

[0251] at least one bias voltage generator coupled to the positive gate terminal of the positive transistor and the negative gate terminal of the negative transistor; and

[0252] a calibration circuit coupled between the positive node and the at least one bias voltage generator and between the negative node and the at least one bias voltage generator.

[0253] Example Aspect 28: The apparatus of Example Aspect 27, wherein:

[0254] the at least one resistor comprises a positive resistor and a negative resistor;

[0255] the positive switch is coupled in series with the positive resistor between the positive channel terminal of the positive transistor and the power distribution node; and

[0256] the negative switch is coupled in series with the negative resistor between the negative channel terminal of the negative transistor and the power distribution node.

[0257] Example Aspect 29: The apparatus of Example Aspect 27 or 28, wherein:

[0258] the positive gate terminal of the positive transistor comprises a positive back gate terminal of the positive transistor; and

[0259] the negative gate terminal of the negative transistor comprises a negative back gate terminal of the negative transistor.

[0260] Example Aspect 30: The apparatus of any of Example Aspects 27 to 29, wherein:

[0261] the calibration circuit comprises at least one comparator having at least one input;

[0262] the positive node and the negative node comprise a common node; and

[0263] The at least one input of the at least one comparator is coupled to the common node.

[0264] Conclusion

[0265] As used herein, the term “coupled” refers to a relationship between two or more components in which the two or more components are operatively in communication such that they carry out some feature or implement some capability described herein. For example, a coupling can be achieved by physical wire, such as a metal trace or lead, or by electromagnetic coupling, such as a transformer. A coupling can include a direct coupling or an indirect coupling. A direct coupling refers to a connection of discrete circuit elements via a same node without intervening elements. An indirect coupling refers to a connection of discrete circuit elements via one or more other devices or other discrete circuit elements, including two or more different nodes.

[0266] The term “node” (e.g., including “first node” or “mixer node”) refers to at least a point of electrical connection between two or more components (e.g., circuit elements). Although a node can sometimes be visually depicted in a figure as a single point, the node can represent a connection portion of a physical circuit or network that has about the same voltage potential at or along the connection portion between the two or more components. In other words, a node can represent at least one of a plurality of points along a conductive medium (e.g., a lead or trace) that exists between electrically connected components. Similarly, a “terminal” or “port” can represent one or more points having at least about the same voltage potential with respect to an input or output of a component (e.g., a transistor).

[0267] The terms “first,” “second,” “third,” and other numerical related designators are used herein to identify or distinguish items that are similar or analogous to each other in a given context, such as a particular implementation, an individual figure, a given component, or a claim. Thus, a first item in one context can be different from a first item in another context. For example, an item identified as a “first node” in one context can be identified as a “second node” in another context. Similarly, a “first resistor” or a “first switch” in one claim can be recited as a “second resistor” or a “third switch,” respectively, in a different claim (e.g., in a separate set of claims). Similar interpretations apply to differential related terms, such as “positive resistor” and “negative resistor” or “positive voltage” and “negative voltage.”

[0268] Unless otherwise defined, the use of the word "or" herein can be considered as an "inclusive or" or the use of the term "and" can be considered as an "inclusive and" (e.g., the phrase "A or B" can be interpreted to permit "A" or "B" or both A and B). Also, as used herein, phrases such as "at least one of," when preceding the list of two or more items, denote any combination of those items (including single members one at a time, even though multiple memberships are recited). For example, "at least one of a, b, or c" can cover a, b, c, a-b, a-c, b-c, and a-b-c, as well as any combination with multiples of the same element (e.g., a-a, a-a-a, a-a-b, a-a-c, a-b-b, a-c-c, b-b, b-b-b, b-b-c, c-c, and c-c-c, or any other ordering of a, b, and c). Further, items represented in the accompanying figures and discussed herein can represent one or more items or terms, and thus the singular or plural form of these items and terms can be referred to interchangeably throughout the written description.

[0269] Although specific implementations of oscillator leakage calibration have been described in language specific to certain features and / or methods, the subject of the appended claims is not necessarily limited to the specific features or methods described. Rather, the specific features and methods are disclosed as example implementations of oscillator leakage calibration.

Claims

1. An apparatus, the apparatus comprising: A mixer circuit, the mixer circuit comprising: The first stage includes at least one transistor coupled between the mixer input and the mixer output; The second stage includes one or more transistors coupled between the at least one transistor of the first stage and the mixer output, the one or more transistors being coupled between the local oscillator signal input and the mixer output; and A tuning circuit, the tuning circuit being coupled to at least one transistor of the first stage; and The calibration circuit includes: At least one resistor is coupled between a power distribution node and at least one mixer node, and the at least one mixer node is coupled between at least one transistor of the first stage and one or more transistors of the second stage; At least one switch, said at least one switch being coupled between the power distribution node and the at least one mixer node; and A controller circuit, which is coupled between the at least one mixer node and the tuning circuit.

2. The apparatus according to claim 1, wherein: The at least one switch is coupled in series with the at least one resistor between the power distribution node and the at least one mixer node; and The at least one switch is coupled between the at least one resistor and the at least one mixer node.

3. The apparatus according to claim 2, wherein: The controller circuit is coupled between the tuning circuit and another node, which is coupled between the at least one switch and the at least one resistor.

4. The apparatus according to claim 1, wherein: The controller circuit includes a comparator having a first input and a second input; The first input of the comparator is coupled to the at least one mixer node; and The second input of the comparator is coupled to a node configured to provide a reference voltage.

5. The apparatus according to claim 4, wherein: The comparator has an output coupled to the tuning circuit; and The controller circuit is configured as follows: Provide control signals to the tuning circuit; as well as The control signal is adjusted based on the reference voltage at the second input of the comparator and the voltage present at the first input of the comparator.

6. The apparatus according to claim 5, wherein: The controller circuit is configured to adjust the control signal until the voltage present at the first input of the comparator is substantially equal to the reference voltage at the second input of the comparator; and The voltage present at the first input of the comparator represents the current flowing through the at least one transistor of the first stage of the mixer circuit.

7. The apparatus according to claim 5, wherein: The tuning circuit includes at least one bias voltage generator; The at least one bias voltage generator is configured to apply at least one bias voltage to at least one gate of the at least one transistor of the first stage of the mixer circuit. and The controller circuit is configured to adjust the control signal to change the at least one bias voltage of the at least one gate of the at least one transistor of the first stage of the mixer circuit, which is applied by the at least one bias voltage generator to the mixer circuit.

8. The apparatus according to claim 7, wherein: The at least one transistor in the first stage of the mixer circuit includes a positive transistor and a negative transistor in the first stage of the mixer circuit. The at least one bias voltage includes a positive bias voltage and a negative bias voltage; The controller circuit is configured to adjust the control signal to change the positive bias voltage based on the positive current flowing through the positive transistor; and The controller circuit is configured to adjust the control signal to change the negative bias voltage based on the negative current flowing through the negative transistor.

9. The apparatus according to claim 1, wherein: The at least one resistor includes a positive resistor and a negative resistor.

10. The apparatus according to claim 9, wherein: The at least one transistor in the first stage of the mixer circuit includes a positive transistor and a negative transistor; and The controller circuit is configured as follows: Measure the positive voltage corresponding to the positive resistor and the positive transistor, and the negative voltage corresponding to the negative resistor and the negative transistor; Provide control signals to the tuning circuit; as well as The control signal is adjusted based on the positive voltage and the negative voltage.

11. The apparatus according to claim 10, wherein: The positive voltage represents the positive current flowing through the positive transistor of the first stage of the mixer circuit, and the negative voltage represents the negative current flowing through the negative transistor of the first stage of the mixer circuit; and The controller circuit is configured to adjust the control signal to reduce the difference between the positive voltage and the negative voltage.

12. The apparatus according to claim 9, wherein: The controller circuit includes at least one analog-to-digital converter having at least one input, the at least one input of which is coupled to the positive resistor and the negative resistor.

13. The apparatus according to claim 1, wherein: The tuning circuit includes at least one bias voltage generator; The first stage's at least one transistor includes a gate terminal; and The at least one bias voltage generator of the tuning circuit is coupled to the gate terminal of the at least one transistor of the first stage.

14. The apparatus according to claim 13, wherein: The gate terminal of the at least one transistor in the first stage includes a front gate terminal.

15. The apparatus according to claim 13, wherein: The gate terminal of the at least one transistor in the first stage includes a back gate terminal.

16. The apparatus according to claim 1, wherein: The tuning circuit includes at least one bias voltage generator, the at least one bias voltage generator comprising: One or more current sources, said one or more current sources coupled between a first power distribution node and a second power distribution node; and One or more resistors, the one or more resistors being coupled in series with the one or more current sources between the first power distribution node and the second power distribution node.

17. The apparatus of claim 16, wherein the one or more current sources comprise at least one adjustable current source.

18. The apparatus of claim 16, wherein the one or more resistors comprise at least one adjustable resistor.

19. The apparatus according to claim 1, wherein: The first transistor of the first stage includes a positive first transistor and a negative first transistor; The one or more transistors of the second stage include a positive second transistor and a negative second transistor; The at least one mixer node includes a positive mixer node and a negative mixer node, the positive mixer node being coupled between the positive first transistor and the positive second transistor, and the negative mixer node being coupled between the negative first transistor and the negative second transistor; and The at least one switch includes a positive switch and a negative switch, the positive switch being coupled in series with the at least one resistor between the power distribution node and the positive mixer node, and the negative switch being coupled in series with the at least one resistor between the power distribution node and the negative mixer node.

20. The apparatus of claim 1, further comprising: A wireless interface device, the wireless interface device including the mixer circuit and the calibration circuit; Display screen; and At least one processor, operatively coupled to at least a portion of the display screen and the wireless interface device, the at least one processor being configured to present one or more graphic images on the display screen based on one or more wireless signals transmitted using the mixer circuitry of the wireless interface device.

21. An apparatus comprising: A mixer circuit, the mixer circuit comprising: The first stage includes at least one transistor coupled between the mixer input and the mixer output; The second stage includes one or more transistors coupled between the at least one transistor of the first stage and the mixer output; and Components for tuning the at least one transistor of the first stage; and The calibration circuit includes: At least one resistor is coupled between a power distribution node and at least one mixer node, and the at least one mixer node is coupled between at least one transistor of the first stage and one or more transistors of the second stage; At least one switch, said at least one switch being series coupled to said at least one resistor between said power distribution node and said at least one mixer node; and A component for controlling the component for tuning based on at least one voltage associated with the at least one resistor.

22. The apparatus according to claim 21, wherein: The first stage includes at least one transistor, comprising a positive transistor and a negative transistor; The at least one voltage includes a positive voltage corresponding to the positive transistor and a negative voltage corresponding to the negative transistor; and The control components include components for controlling the tuning components based on the positive voltage and the negative voltage.

23. The apparatus according to claim 22, wherein: The tuning components include components for adjusting the positive bias voltage of the positive transistor and the negative bias voltage of the negative transistor; and The control components include components for controlling the tuning components to reduce the difference between the positive voltage and the negative voltage by adjusting the positive bias voltage of the positive transistor and the negative bias voltage of the negative transistor.

24. A method for mixer calibration, the method comprising: Close the positive switch to connect at least one resistor to a positive mixer node, the positive mixer node being coupled between the positive transistor of the first stage of the mixer circuit and the second stage of the mixer circuit; The at least one resistor is used to measure the positive voltage corresponding to the positive transistor of the first stage of the mixer circuit; Disconnect the positive switch to disconnect the at least one resistor from the positive mixer node; Close the negative switch to connect the at least one resistor to the negative mixer node, the negative mixer node being coupled between the negative transistor of the first stage of the mixer circuit and the second stage of the mixer circuit. The at least one resistor is used to measure the negative voltage corresponding to the negative transistor of the first stage of the mixer circuit; as well as The bias voltage of at least one of the positive transistor or the negative transistor of the first stage of the mixer circuit is adjusted based on the positive voltage and the negative voltage.

25. The method of claim 24, wherein the adjustment comprises: Adjust the positive bias voltage applied to the positive transistor and the negative bias voltage applied to the negative transistor to reduce the difference between the positive voltage and the negative voltage.

26. The method of claim 24, wherein the adjustment comprises: Adjust the at least one bias voltage applied to at least one of the positive transistor or the negative transistor to reduce the current offset between the positive current flowing through the positive transistor and the negative current flowing through the negative transistor.

27. An apparatus comprising: The communication link includes: A mixer, the mixer comprising: A positive transistor, the positive transistor including a positive channel terminal and a positive gate terminal; and A negative transistor, the negative transistor including a negative channel terminal and a negative gate terminal; At least one resistor; A positive switch, wherein the positive switch is coupled in series with at least one resistor between the positive channel terminal and the power distribution node of the positive transistor, and the positive node is coupled between the positive switch and the at least one resistor; A negative switch, wherein the negative switch is coupled in series with at least one resistor between the negative channel terminal of the negative transistor and the power distribution node, and the negative node is coupled between the negative switch and the at least one resistor; At least one bias voltage generator, said at least one bias voltage generator being coupled to the positive gate terminal of the positive transistor and the negative gate terminal of the negative transistor; and A calibration circuit coupled between the positive node and the at least one bias voltage generator, and between the negative node and the at least one bias voltage generator.

28. The apparatus according to claim 27, wherein: The at least one resistor includes a positive resistor and a negative resistor; The positive switch is coupled in series with the positive resistor between the positive channel terminal of the positive transistor and the power distribution node; and The negative switch is coupled in series with the negative resistor between the negative channel terminal of the negative transistor and the power distribution node.

29. The apparatus according to claim 27, wherein: The positive gate terminal of the positive transistor includes the positive back gate terminal of the positive transistor; and The negative gate terminal of the negative transistor includes the negative back gate terminal of the negative transistor.

30. The apparatus according to claim 29, wherein: The calibration circuit includes at least one comparator having at least one input; The positive node and the negative node include a common node; and The at least one input of the at least one comparator is coupled to the common node.

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