Method for inhibiting overgrowth of base polysilicon connectors into emitter cavities during silicon germanium selective epitaxial growth
By employing fully self-aligned selective epitaxial growth technology in heterojunction bipolar transistors, the problem of excessive polysilicon growth at the base-emitter junction was solved, achieving stable contact and miniaturization of HBTs, reducing manufacturing complexity and cost, and improving frequency response and carrier mobility.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- TEXAS INSTRUMENTS INC
- Filing Date
- 2024-10-28
- Publication Date
- 2026-04-10
AI Technical Summary
Existing technologies for manufacturing heterojunction bipolar transistors (HBTs) present challenges such as high manufacturing complexity, high cost, difficulty in miniaturization, and thermal management, especially the problem of excessive polysilicon growth at the junction between the base and emitter.
The fully self-aligned selective epitaxial growth (FSA SEG) technique is employed. By forming a monocrystalline silicon base layer and a polycrystalline silicon base layer on the collector, and using an emitter spacer made of dielectric material to laterally separate the emitter from the intrinsic base layer, the vertical offset of the spacer-intrinsic base and the bottom width of the emitter spacer are designed to prevent polycrystalline material from growing into the emitter window, thus ensuring complete contact between the base link and the monocrystalline base layer.
It effectively prevents polycrystalline materials from entering the emitter window, ensures stable contact between the base and emitter, reduces the area of the HBT, lowers manufacturing complexity and cost, and improves frequency response and carrier mobility.
Smart Images
Figure CN121844722A_ABST
Abstract
Description
[0001] The present disclosure relates to the field of semiconductor devices. More specifically, but not exclusively, the present disclosure relates to heterojunction bipolar transistors in semiconductor devices. BACKGROUND
[0002] Heterojunction bipolar transistors (HBTs) in semiconductor devices are important components that are widely used in high frequency and high power applications such as wireless communication systems and power amplifiers due to their superior performance characteristics. An HBT is a bipolar junction transistor that uses different semiconductor materials for the emitter region and the base region, creating a heterojunction. HBTs improve upon homojunction bipolar junction transistors, which have the same semiconductor material for both the emitter region and the base region, because they can handle higher frequency signals up to several hundred GHz. HBTs take advantage of the interface between different semiconductor materials with different band gap energies. This difference in band gap energies enables HBTs to exhibit higher carrier mobility, reduced base transit time, and improved frequency response. Researchers have explored various semiconductor materials, epitaxial growth techniques, and device geometries to optimize HBTs for specific applications. While these efforts have led to significant improvements, there remain challenges such as reducing the manufacturing complexity and cost associated with HBT integration while achieving desired levels of power efficiency, miniaturization, and thermal management. SUMMARY
[0003] A semiconductor device includes a fully self-aligned (FSA) selective epitaxial growth (SEG) heterojunction bipolar transistor (HBT), hereinafter HBT, having a collector, a base on the collector, and an emitter on the base. The collector includes monocrystalline silicon. The base includes a monocrystalline base layer on the collector including monocrystalline silicon germanium and an extrinsic base layer extending partially over the monocrystalline base layer including polycrystalline silicon. The base further includes a base link connecting the monocrystalline base layer vertically to the extrinsic base layer including polycrystalline germanium. The HBT further includes an emitter spacer of dielectric material laterally separating the emitter from the extrinsic base layer. The monocrystalline base layer extends laterally beyond the emitter spacer under the polycrystalline silicon extrinsic base layer. The HBT has a spacer-extrinsic base vertical offset between a bottom of the emitter spacer and a bottom surface of the extrinsic base layer adjacent to the emitter spacer. The emitter spacer has a bottom width at a bottom of the emitter spacer closest to the monocrystalline base layer. A sum of the spacer-extrinsic base vertical offset and the bottom width of the emitter spacer is greater than a thickness of the monocrystalline base layer. The base link laterally abuts the emitter spacer opposite the emitter. BRIEF DESCRIPTION OF DRAWINGS
[0004] Figures 1A-1T is a cross-section of an example semiconductor device having an HBT depicted in a stage of an example formation method.
[0005] Figures 2A-2L is a cross-section of another example semiconductor device having an HBT depicted in a stage of another example formation method.
[0006] Figures 3A-3L is a cross-section of another example semiconductor device having an HBT depicted in a stage of another example formation method. DETAILED DESCRIPTION
[0007] The present disclosure is described with reference to the accompanying drawings. The drawings are not drawn to scale, and each drawing is provided merely to illustrate aspects of the present disclosure. Several aspects of the present disclosure are described below with reference to example implementations. It should be understood that numerous specific details, relationships, and methods are set forth to provide a full understanding of the present disclosure. The present disclosure is not limited by the order of acts or events, as some acts can occur in different orders and / or concurrently with other acts or events. Furthermore, not all illustrated acts or events are required to implement methods in accordance with the present disclosure.
[0008] Additionally, although some examples shown herein are presented in two-dimensional views with various regions having depth and width, it should be clearly understood that these regions are merely illustrations of portions of devices that are actually three-dimensional structures. Thus, when fabricated on actual devices, these regions will have three dimensions, including length, width, and depth. Furthermore, although the present disclosure is shown by way of example for active devices, these illustrations are not intended to limit the scope or applicability of the present disclosure. Moreover, it is not intended to limit the scope of active devices of the present disclosure to the physical structures shown. These structures are included to demonstrate the utility and application of various implementations.
[0009] A semiconductor device, such as an integrated circuit, includes a heterojunction bipolar transistor (HBT) having a collector, a base, and an emitter. The collector includes monocrystalline silicon and has a first conductivity type.
[0010] The base includes an intrinsic monocrystalline base layer on the collector that contacts the monocrystalline silicon of the collector. The monocrystalline base layer includes monocrystalline silicon germanium and can include monocrystalline silicon. The base also includes an extrinsic base layer that extends partially over the monocrystalline base layer. The extrinsic base layer includes polycrystalline silicon. The base further includes a base link connecting the extrinsic base layer to the monocrystalline base layer. The base link includes polycrystalline silicon germanium. If the monocrystalline base layer includes monocrystalline silicon, the base link includes polycrystalline silicon. The monocrystalline base layer, the extrinsic base layer, and the base link have a second conductivity type opposite the first conductivity type.
[0011] The emitter includes silicon and has the first conductivity type. The HBT further includes an emitter spacer of dielectric material laterally separating the emitter from the extrinsic base layer. The emitter spacer is electrically non-conductive. The emitter spacer has a bottom width at a bottom of the emitter spacer closest to the single-crystalline base layer. The single-crystalline base layer laterally extends beyond the emitter spacer below the extrinsic base layer.
[0012] The HBT has a spacer-extrinsic base vertical offset, which is a vertical distance between a bottom of the emitter spacer and a bottom surface of the extrinsic base layer adjacent to the emitter spacer. The emitter spacer has a bottom width, which is a width of the emitter spacer at a bottom of the emitter spacer closest to the single-crystalline base layer. A sum of the spacer-extrinsic base vertical offset and the bottom width of the emitter spacer is greater than a thickness of the single-crystalline base layer, which is referred to herein as a base thickness. The base link laterally adjoins the emitter spacer opposite the emitter.
[0013] In some aspects, the spacer-extrinsic base vertical offset is less than the base thickness. In some aspects, a bottom surface of the extrinsic base layer in contact with the base link is concave. In some aspects, a boundary between the extrinsic base layer and the base link is planar and parallel to a top surface of the collector.
[0014] For purposes of the present disclosure, the term“vertical” refers to a direction perpendicular to a planar portion of a top surface of a collector, i.e., a planar portion of a boundary between the collector and the single-crystalline base layer. The term“lateral” refers to a direction parallel to a planar portion of a top surface of a collector.
[0015] Figures 1A-1T is a cross-section of an example semiconductor device having an HBT depicted in a stage of an example formation method. Reference is made to Figure 1A and Figure 1B , Figure 1B is a close-up view of a portion of Figure 1A A semiconductor device 100 includes a substrate 102 of single-crystalline silicon. For example, the substrate 102 can be implemented as a silicon wafer or a silicon-on-insulator (SOI) wafer. In this example, the HBT 104 is described as a PNP HBT. An NPN version of the HBT 104 can be formed by appropriate changes in conductivity type and dopant species.
[0016] The HBT 104 includes a collector 106 in the substrate 102. The collector 106 has a first conductivity type; in this example, the first conductivity type is p-type. The collector 106 can be laterally isolated by a field oxide 108. The field oxide 108 can be formed by a shallow trench isolation (STI) process, which features silicon dioxide in a trench in the substrate 102, as indicated in Figure 1A and Figure 1B . Alternatively, the field oxide 108 can be formed by a local oxidation of silicon (LOCOS) process, which features a tapered edge, commonly referred to as a bird’s beak.
[0017] A base spacer layer 110 is formed over the collector 106, and can extend over the field oxide 108 adjacent to the collector 106. The base spacer layer 110 can primarily include silicon dioxide, formed by a plasma-enhanced chemical vapor deposition (PECVD) process using tetraethyl orthosilicate (TEOS), the formal name for tetraethoxysilane. Alternatively, the base spacer layer 110 can primarily include silicon nitride, formed, for example, by a low pressure chemical vapor deposition (LPCVD) process using dichlorosilane (SiCl2H2) and ammonia, by a LPCVD process using bis(tert-butyiamino)silane (BTBAS) and ammonia, or by a PECVD process using BTBAS and ammonia. Other compositions for the base spacer layer 110 and processes for forming the base spacer layer 110 are within the scope of this example. The base spacer layer 110 is thicker than a single-crystal base layer, which is not shown in Figure 1A and Figure 1B , is formed in a later step, and is shown in Figure 1Q and Figure 1R .
[0018] An extrinsic base layer 112 is formed over the base spacer layer 110. The extrinsic base layer 112 includes polysilicon, referred to herein as polysilicon. The extrinsic base layer 112 has a second conductivity type opposite the first conductivity type. In this example, the second conductivity type is n-type.
[0019] A base-emitter separation dielectric layer 114 can be formed over the extrinsic base layer 112. The base-emitter separation dielectric layer 114 is non-conductive and can include silicon nitride, and can be formed by a LPCVD process or by PECVD. Alternatively, the base-emitter separation dielectric layer 114 can include silicon dioxide, and can be formed, for example, by a PECVD process using TEOS or a high-aspect-ratio process (HARP) using TEOS and ozone.
[0020] Referring to Figure 1C and Figure 1D , Figure 1D isFigure 1C FIG. 6 is a cross-sectional view of a portion of FIG. 5, with an emitter window etch mask 116 formed over 114. Openings in the emitter window etch mask 116 expose the base-emitter separation dielectric layer 114 in the regions of the emitter window 118. The emitter window etch mask 116 can include photoresist and can be formed by a photolithography process. The emitter window etch mask 116 can also include an antireflective material, such as a bottom antireflective coating (BARC). The emitter window etch mask 116 can further include a hardmask material, such as silicon nitride or amorphous carbon
[0021] The base-emitter separation dielectric layer 114 and the extrinsic base layer 112 are removed from the emitter window 118, where exposed through the openings in the emitter window etch mask 116. The base-emitter separation dielectric layer 114 and the extrinsic base layer 112 can be removed by a sequential reactive ion etch (RIE) process or an inductively coupled plasma (ICP) process. The base-emitter separation dielectric layer 114 can be removed using fluorine radicals and argon ions to provide chemical and physical etching, respectively. The removal of the base-emitter separation dielectric layer 114 can also use a hydrocarbon to provide sidewall passivation on the base-emitter separation dielectric layer 114 in the emitter window 118 to reduce lateral etching. The extrinsic base layer 112 can be removed using chlorine radicals and / or bromine radicals to provide etch selectivity to the underlying base spacer layer 110. As depicted in FIG. 7, the base-emitter separation dielectric layer 114 and the extrinsic base layer 112 are removed from the emitter window 118, where exposed through the openings in the emitter window etch mask 116. Figure 1C and Figure 1D As depicted in FIG. 8, a small amount of the base spacer layer 110 can be removed in an over-etch phase to provide full etching in the entire substrate 102.
[0022] After the base-emitter separation dielectric layer 114 and the extrinsic base layer 112 are removed from the emitter window 118, the emitter window etch mask 116 is removed. The organic materials in the emitter window etch mask 116, such as photoresist and BARC, can be removed by oxygen radicals in an ashing process. The inorganic materials in the emitter window etch mask 116, such as silicon nitride or amorphous carbon, can be removed by a suitable plasma etch process.
[0023] Referring to FIG. 9, Figure 1E and Figure 1F , Figure 1F is Figure 1EA partially enlarged view shows that an emitter spacer layer 120 is formed over the base-emitter separation dielectric layer 114, extending into the emitter window 118 and onto the base spacer layer 110. The emitter spacer layer 120 is continuous and at least partially conformal, covering the sidewalls of the non-intrinsic base layer 112 in the emitter window 118. In this example version where the base spacer layer 110 primarily comprises silicon dioxide, the emitter spacer layer 120 may primarily comprise silicon nitride having a hydrogen content of 5 to 15 atomic percent, formed, for example, by using an LPCVD process with dichlorosilane and ammonia, an LPCVD process with BTBAS and ammonia, or a PECVD process with BTBAS and ammonia. In this example version where the base spacer layer 110 primarily comprises silicon nitride, the emitter spacer layer 120 may primarily comprise silicon dioxide formed by an LPCVD process or a PECVD process. The emitter spacer layer 120 on the sidewall of the extrinsic base layer 112 in the emitter window 118 may have a lateral thickness of 25% to 100% of the vertical thickness of the monocrystalline base layer, referred to herein as the monocrystalline base thickness 140, for example... Figure 1S and Figure 1T As shown in the image.
[0024] refer to Figure 1G and Figure 1H , Figure 1H yes Figure 1G A partial enlarged view shows an anisotropic etching process used to remove the emitter spacer layer 120 above the base spacer layer 110 in the central region of the emitter window 118, leaving the emitter spacer layer 120 on the sidewall of the non-intrinsic base layer 112 in the emitter window 118 to provide an emitter spacer 122 extending to the base spacer layer 110. The anisotropic etching process can also remove the emitter spacer layer 120 from above the base-emitter separation dielectric layer 114, such as... Figure 1G and Figure 1H As depicted in the figure. The anisotropic etching process can be implemented as a RIE process using fluorine radicals and hydrogen. The anisotropic etching process can remove a small amount of the base spacer layer 110 to ensure complete removal of the emitter spacer layer 120 in the central region of the emitter window 118.
[0025] refer to Figure 1I and Figure 1J , Figure 1J yes Figure 1IFIG. 2 is an enlarged view of a portion of FIG. 1, removing a portion of the base spacer layer 110 to expose the collector 106 below the emitter window 118 and to expose a portion of the lower surface of the extrinsic base layer 112 adjacent to the emitter spacer 122. In this example version where the base spacer layer 110 primarily comprises silicon dioxide, a portion of the base spacer layer 110 can be removed by a timed wet etch process using buffered dilute hydrofluoric acid aqueous solution. In this example version where the base spacer layer 110 primarily comprises silicon nitride, a portion of the base spacer layer 110 can be removed by a timed wet etch process using aqueous phosphoric acid at 140 °C to 180 °C.
[0026] Referring to Figure 1K and Figure 1L , Figure 1L is Figure 1K an enlarged view of a portion of FIG. 1, removing a portion of the base spacer layer 110 to expose the collector 106 below the emitter window 118 and to expose a portion of the lower surface of the extrinsic base layer 112 adjacent to the emitter spacer 122. In this example version where the base spacer layer 110 primarily comprises silicon dioxide, a portion of the base spacer layer 110 can be removed by a timed wet etch process using buffered dilute hydrofluoric acid aqueous solution. In this example version where the base spacer layer 110 primarily comprises silicon nitride, a portion of the base spacer layer 110 can be removed by a timed wet etch process using aqueous phosphoric acid at 140 °C to 180 °C. Figures 1M-1T Referring to Figure 1K and Figure 1L , a portion of the extrinsic base layer 112 can be removed by a vapor phase etch process using a vapor phase etchant comprising one or more halogen species, such as chlorine, fluorine, or bromine. The vapor phase etch process can be performed in an epitaxial reactor used to subsequently form the monocrystalline base layer 124, as shown in FIG. 3, a downstream etcher that generates halogen radicals, or a plasmaless vapor phase etcher that generates hydrogen-halogen vapor, such as hydrogen chloride vapor or xenon difluoride vapor. A portion of the collector 106 can be removed by the vapor phase etch process, as depicted in FIG. 4, while removing the portion of the extrinsic base layer 112. For example, the removed portion of the extrinsic base layer 112 can have a vertical thickness of 40% to 75% of the monocrystalline base thickness 140, as shown in FIG. 5. Figure 1S and Figure 1T
[0027] Referring to Figure 1M and Figure 1N , Figure 1N is Figure 1M FIG. 2 is an enlarged view of a portion of FIG. 1, a first base sublayer 124a of the single-crystalline base layer 124 is formed over the collector 106, and a first base link sublayer 126a of the base link 126 is simultaneously formed on the ex-situ base layer 112 at the lower surface adjacent to the emitter spacer 122. The first base sublayer 124a and the first base link sublayer 126a can be formed by a first vapor phase epitaxy process using a silicon-containing and / or germanium-containing gas reagent (e.g., dichlorosilane and germane (GeH4)). The first base sublayer 124a is single-crystalline, has the second conductivity type, in this example p-type, and includes silicon or silicon-germanium. The first base link sublayer 126a is polycrystalline and has a composition similar to the first base sublayer 124a due to being formed simultaneously with the first base sublayer 124a. The first base sublayer 124a grows upward from the collector 106, while the first base link sublayer 126a grows downward from the lower surface of the ex-situ base layer 112 at approximately the same rate as the first base sublayer 124a. The single-crystalline base layer 124 extends laterally beyond the emitter spacer 122 below the ex-situ base layer 112.
[0028] Referring to Figure 1O and Figure 1P , Figure 1P is Figure 1O FIG. 3 is an enlarged view of a portion of FIG. 1, a second base sublayer 124b of the single-crystalline base layer 124 is formed over the first base sublayer 124a, and a second base link sublayer 126b of the base link 126 is simultaneously formed on the first base link sublayer 126a adjacent to the emitter spacer 122. The second base sublayer 124b and the second base link sublayer 126b can be formed by a second vapor phase epitaxy process. The second base sublayer 124b is single-crystalline, has the second conductivity type, and includes silicon or silicon-germanium. The second base link sublayer 126b is polycrystalline and has a composition similar to the second base sublayer 124b due to being formed simultaneously with the second base sublayer 124b. The second base sublayer 124b can have a different composition, dopant density, and / or thickness than the first base sublayer 124a. The second base sublayer 124b grows upward from the first base sublayer 124a, while the second base link sublayer 126b grows downward from the first base link sublayer 126a at approximately the same rate as the second base sublayer 124b.
[0029] Referring to Figure 1Q and Figure 1R , Figure 1R is Figure 1QFIG. 1 is a diagram of a portion of the HBT 104, a third base sublayer 124c of the single-crystalline base layer 124 is formed over the second base sublayer 124b, and a third base link sublayer 126c of the base link 126 is formed over the second base link sublayer 126b adjacent to the emitter spacer 122. The third base sublayer 124c and the third base link sublayer 126c can be formed by a third vapor-phase epitaxy process. The third base sublayer 124c is single-crystalline, has the second conductivity type, and includes silicon or silicon-germanium. The third base link sublayer 126c is polycrystalline and has a composition similar to the third base sublayer 124c due to being formed simultaneously with the third base sublayer 124c. The third base sublayer 124c can have a different composition, dopant density, and / or thickness than the first base sublayer 124a and / or the second base sublayer 124b. The third base sublayer 124c grows upward from the second base sublayer 124b, while the third base link sublayer 126c grows downward from the second base link sublayer 126b at approximately the same rate as the third base sublayer 124c.
[0030] The first base sublayer 124a, the second base sublayer 124b, and the third base sublayer 124c provide the single-crystalline base layer 124 of this example. At least one of the first base sublayer 124a, the second base sublayer 124b, and the third base sublayer 124c includes silicon-germanium. The first base link sublayer 126a, the second base link sublayer 126b, and the third base link sublayer 126c provide the base link 126 of this example. The base link 126 connects the extrinsic base layer 112 to the single-crystalline base layer 124. The single-crystalline base layer 124, the base link 126, and the extrinsic base layer 112 provide the base 134 of the HBT 104.
[0031] In other versions of this example, the single-crystalline base layer 124 can include fewer or more base sublayers. Accordingly, the base link 126 would include the same number of sublayers as the single-crystalline base layer 124.
[0032] Reference is made to Figure 1S and Figure 1T , Figure 1T is Figure 1S a diagram of a portion of the HBT 104, the emitter liner 128 is formed over the single-crystalline base layer 124 and the emitter spacer 122 in the emitter window 118. The emitter liner 128 exposes the single-crystalline base layer 124 in the emitter window 118. The emitter liner 128 is non-conductive. For example, the emitter liner 128 can include two or more sublayers of a dielectric material (e.g., silicon dioxide and silicon nitride).
[0033] An emitter 130 is formed in the emitter window 118, on the emitter liner 128, and on the single-crystalline base layer 124 exposed by the emitter liner 128. The emitter 130 can extend outside the emitter window 118, as depicted in FIG. 1. Figure 1S The emitter 130 of this example is single-crystalline and primarily comprises silicon. The emitter 130 has a first conductivity type, in this example n-type. The emitter 130 can be formed by a silicon vapor-phase epitaxy process using silane. Figure 1S A metal silicide, such as cobalt silicide, not shown in FIG. 1, can be formed on the emitter 130. An emitter contact 132 forms an electrically conductive connection with the emitter 130. The emitter contact 132 can comprise tungsten formed by a metal-organic chemical vapor deposition (MOCVD) process.
[0034] Figure 1S and Figure 1T depicts the semiconductor device 100 of Figure 1Q and Figure 1R with the single-crystalline base layer 124 and the internal sub-layers of the base link 126 omitted so as to more clearly illustrate the dimensional relationships of the HBT 104. That is, the base sub-layers 124a, 124b, and 124c and the base link sub-layers 126a, 126b, and 126c are not shown in Figure 1S and Figure 1T .
[0035] The base link 126 laterally abuts the emitter spacer 122. In this example, the bottom surface of the extrinsic base layer 112 that contacts the base link 126 is recessed. The HBT 104 has a spacer-extrinsic base vertical offset 136 that is a vertical distance between a bottom of the emitter spacer 122 and a bottom surface of the extrinsic base layer 112 adjacent to the emitter spacer 122. The emitter spacer 122 has a bottom width 138 that is a width of the emitter spacer 122 at a bottom of the emitter spacer 122 closest to the monocrystalline base layer 124. The monocrystalline base layer 124 has a monocrystalline base thickness 140 that is a thickness of the monocrystalline base layer 124 in the vertical direction. For example, the spacer-extrinsic base vertical offset 136 of this example can be 50% to 75% of the monocrystalline base thickness 140. For example, the bottom width 138 of the emitter spacer 122 of this example can be 25% to 100% of the monocrystalline base thickness 140. The sum of the spacer-extrinsic base vertical offset 136 and the bottom width 138 is greater than the monocrystalline base thickness 140. This characteristic can prevent polycrystalline material of the base link 126 from growing through the emitter spacer 122 into the emitter window 118, advantageously providing a consistent contact area between the emitter 130 and the monocrystalline base layer 124, and enabling a reduction in area of the HBT 104 compared to HBTs having polycrystalline material that protrudes into the emitter window.
[0036] The base link 126 grows downward at approximately the same rate as the monocrystalline base layer 124 grows upward. A base link cavity height 142 that is a vertical distance between the collector 106 and the extrinsic base layer 112 adjacent to the emitter spacer 122 can be less than twice the monocrystalline base thickness 140, enabling full contact between the base link 126 and the monocrystalline base layer 124. Full contact between the base link 126 and the monocrystalline base layer 124 can advantageously provide a low resistance connection through the base link 126 between the extrinsic base layer 112 and the monocrystalline base layer 124. As the monocrystalline base layer 124 grows, a gap 146 can exist between the bottom of the emitter spacer 122 and a transient top surface of the monocrystalline base layer 124, enabling epitaxial reagent gas (e.g., silane and germane) to enter the base link 126 as it grows, further advantageously providing full contact between the base link 126 and the monocrystalline base layer 124. In the completed semiconductor device 100, a vertical distance between the collector 106 and the bottom of the emitter spacer 122 can be greater than the monocrystalline base thickness 140 of the monocrystalline base layer 124.
[0037] Figures 2A-2L is a cross-section of another example semiconductor device having an HBT at a stage of another example formation method. Reference is made to Figure 2A andFigure 2B , Figure 2B is Figure 2A a magnified view of a portion of semiconductor device 200, which includes a substrate 202 of single crystalline silicon. In this example, HBT 204 is described as a PNP HBT. An NPN version of HBT 204 can be formed by appropriate changes in conductivity type and dopant species. HBT 204 includes a collector 206 having a first conductivity type in substrate 202. In this example, the first conductivity type is p-type. Collector 206 can be laterally isolated by field oxide 208.
[0038] A base spacer layer 210 is formed over collector 206. Base spacer layer 210 can include primarily silicon dioxide. Base spacer layer 210 of this example can have a spacer thickness 244 that is, for example, 150% to 175% of a single crystalline base thickness 240 of a single crystalline base layer 224 that is formed in a later step and shown in Figure 2A and Figure 2B is not shown in Figure 2I and Figure 2J . An extrinsic base layer 212 is formed over base spacer layer 210. Extrinsic base layer 212 includes polysilicon having a second conductivity type that is opposite the first conductivity type. In this example, the second conductivity type is n-type. A base-emitter separation dielectric layer 214 can be formed over extrinsic base layer 212. Base-emitter separation dielectric layer 214 is non-conductive.
[0039] An emitter window etch mask 216 is formed over base-emitter separation dielectric layer 214 and has openings that expose base-emitter separation dielectric layer 214 in areas of an emitter window 218. Base-emitter separation dielectric layer 214 and extrinsic base layer 212 are removed from emitter window 218, where exposed through openings in emitter window etch mask 216. After extrinsic base layer 212 is removed from emitter window 218, a portion of base spacer layer 210 is removed from emitter window 218. The portion of base-emitter separation dielectric layer 214, extrinsic base layer 212, and base spacer layer 210 can be removed by a sequential RIE process or an ICP process. For example, the vertical depth of the removed portion of base spacer layer 210 can be 40% to 75% of single crystalline base thickness 240 of single crystalline base layer 224. After base-emitter separation dielectric layer 214 and extrinsic base layer 212 are removed from emitter window 218, emitter window etch mask 216 is removed.
[0040] Reference is made to Figure 2C and Figure 2D , Figure 2D is Figure 2Cenlarged view of a portion of Figures 1E-1H As disclosed with reference to Figure 2I and Figure 2J ,
[0041] With reference to Figure 2E and Figure 2F , Figure 2F is Figure 2E an enlarged view of a portion of Figure 1I and Figure 1J ,
[0042] With reference to Figure 2G and Figure 2H , Figure 2H is Figure 2G an enlarged view of a portion of
[0043] With reference to Figure 2I and Figure 2J , Figure 2J is Figure 2IFIG. 2B depicts a zoomed-in view of a portion of FIG. 2A, a second base sublayer 224b of the single-crystalline base layer 224 is formed over the first base sublayer 224a, and a second base link sublayer 226b of the base link 226 is formed over the first base link sublayer 226a adjacent to the emitter spacer 222. The second base sublayer 224b and the second base link sublayer 226b can be formed by a second vapor-phase epitaxy process. The second base sublayer 224b is single-crystalline, has the second conductivity type, and includes silicon or silicon-germanium. The second base link sublayer 226b is polycrystalline and has a composition similar to the second base sublayer 224b due to being formed simultaneously with the second base sublayer 224b. The second base sublayer 224b can have a different composition, dopant density, and / or thickness than the first base sublayer 224a. The second base sublayer 224b grows upward from the first base sublayer 224a, while the second base link sublayer 226b grows downward from the first base link sublayer 226a at approximately the same rate as the second base sublayer 224b.
[0044] The first base sublayer 224a and the second base sublayer 224b provide the single-crystalline base layer 224 of this example. At least one of the first base sublayer 224a and the second base sublayer 224b includes silicon-germanium. The first base link sublayer 226a and the second base link sublayer 226b provide the base link 226 of this example. The base link 226 connects the extrinsic base layer 212 to the single-crystalline base layer 224. The single-crystalline base layer 224, the base link 226, and the extrinsic base layer 212 provide the base 234 of the HBT 204.
[0045] In other versions of this example, the single-crystalline base layer 224 and the base link 226 can include fewer or more base sublayers. The base link 226 will include the same number of sublayers as the single-crystalline base layer 224.
[0046] Referring to Figure 2K and Figure 2L , Figure 2L is Figure 2K a zoomed-in view of a portion of FIG. 2A, the emitter 230 is formed in the emitter window 218, on the emitter spacer 222, and on the single-crystalline base layer 224 exposed by the emitter spacer 222. The emitter 230 can extend outside of the emitter window 218, as depicted in Figure 2K This example of the emitter 230 is single-crystalline and primarily includes silicon. The emitter 230 has the first conductivity type, which in this example is n-type. The emitter 230 can be formed by a silicon vapor-phase epitaxy process. The emitter contact 232 forms an electrically conductive connection with the emitter 230.
[0047] Figure 2K and Figure 2L depicts Figure 1Q and Figure 1Rsemiconductor device 200, in which the single-crystalline base layer 224 and internal sub-layers of the base link 226 are omitted to more clearly illustrate the dimensional relationships of the HBT 204. That is, the base sub-layers 224a and 224b and the base link sub-layers 226a and 226b are not shown in Figure 2K and Figure 2L .
[0048] The base link 226 laterally abuts the emitter spacer 222. In this example, the boundary between the extrinsic base layer 212 and the base link 226 is flat and parallel to the top surface of the collector 206. In this example, the extrinsic base layer 212 can have a uniform thickness throughout the HBT 204. The HBT 204 has a spacer-extrinsic base vertical offset 236, which is the vertical distance between the bottom of the emitter spacer 222 and the bottom surface of the extrinsic base layer 212 adjacent to the emitter spacer 222. The emitter spacer 222 has a bottom width 238, which is the width of the emitter spacer 222 at the bottom of the emitter spacer 222 closest to the single-crystalline base layer 224. The single-crystalline base layer 224 has a single-crystalline base thickness 240, which is the thickness of the single-crystalline base layer 224 in the vertical direction. For example, the spacer-extrinsic base vertical offset 236 of this example can be 50% to 75% of the single-crystalline base thickness 240. For example, the bottom width 238 of the emitter spacer 222 of this example can be 25% to 100% of the single-crystalline base thickness 240. The sum of the spacer-extrinsic base vertical offset 236 and the bottom width 238 is greater than the single-crystalline base thickness 240, which can prevent the polycrystalline material of the base link 226 from growing beyond the emitter spacer 222 into the emitter window 218, advantageously providing a consistent contact area between the emitter 230 and the single-crystalline base layer 224, and enabling a reduction in the area of the HBT 204 compared to an HBT having polycrystalline material protruding into the emitter window.
[0049] The base link 226 grows downward at approximately the same rate as the single-crystalline base layer 224 grows upward. A base link cavity height 242, which is the vertical distance between the collector 206 and the extrinsic base layer 212 adjacent to the emitter spacer 222, can be less than twice the single-crystalline base thickness 240, enabling full contact between the base link 226 and the single-crystalline base layer 224. Full contact between the base link 226 and the single-crystalline base layer 224 can advantageously provide a low resistance connection through the base link 226 between the extrinsic base layer 212 and the single-crystalline base layer 224. As the single-crystalline base layer 224 grows, a gap 246 can exist between the bottom of the emitter spacer 222 and the instantaneous top surface of the single-crystalline base layer 224, enabling epitaxial reagent gases (e.g., silane and germane) to enter the base link 226 as it grows, further advantageously providing full contact between the base link 226 and the single-crystalline base layer 224.
[0050] Figures 3A-3L is a cross-section of another example semiconductor device with an HBT, depicted in a stage of another example formation method. Reference is made to Figure 3A and Figure 3B , Figure 3B is a close-up view of a portion of Figure 3A , the semiconductor device 300 includes a substrate 302 of single-crystalline silicon. In this example, the HBT 304 is described as an NPN HBT. A PNP version of the HBT 304 can be formed with appropriate changes in conductivity type and dopant species. The HBT 304 includes a collector 306 in the substrate 302 having a first conductivity type. In this example, the first conductivity type is n-type. The collector 306 can be laterally isolated by a field oxide 308.
[0051] A base spacer layer 310 is formed over the collector 306. The base spacer layer 310 can include primarily silicon dioxide. The base spacer layer 310 of this example can have a spacer thickness 344 that is, for example, 125% to 150% of the single-crystalline base thickness 340 of the single-crystalline base layer 324, which is formed in Figure 3A and Figure 3B is not shown in Figure 3I and Figure 3J . An extrinsic base layer 312 is formed over the base spacer layer 310. The extrinsic base layer 312 includes polysilicon having a second conductivity type that is opposite the first conductivity type. In this example, the second conductivity type is p-type. A base-emitter separation dielectric layer 314 can be formed over the extrinsic base layer 312. The base-emitter separation dielectric layer 314 is non-conductive.
[0052] An emitter window etch mask 316 is formed over the base-emitter separation dielectric layer 314, with openings exposing the base-emiter separation dielectric layer 314 in the area of the emitter window 318. The base-emitter separation dielectric layer 314 and the extrinsic base layer 312 are removed from the emitter window 318, where exposed through the openings in the emitter window etch mask 316. After the extrinsic base layer 312 is removed from the emitter window 318, a portion of the base spacer layer 310 is removed from the emitter window 318. The base-emitter separation dielectric layer 314, the extrinsic base layer 312, and the portion of the base spacer layer 310 can be removed by a sequential RIE process or an ICP process. For example, the vertical depth of the removed portion of the base spacer layer 310 can be 25% to 50% of the single crystalline base thickness 340 of the single crystalline base layer 324. After the base-emitter separation dielectric layer 314 and the extrinsic base layer 312 are removed from the emitter window 318, the emitter window etch mask 316 is removed.
[0053] Referring to Figure 3C and Figure 3D , Figure 3D is a close-up view of a portion of Figure 3C , the emitter spacer 322 is formed on the sidewall of the extrinsic base layer 312 in the emitter window 318. As disclosed with reference to the emitter spacer 122 of Figures 1E-1H , the emitter spacer 322 can be formed. The emitter spacer 322 extends vertically beyond the bottom surface of the extrinsic base layer 312 adjacent to the emitter spacer 322.
[0054] Referring to Figure 3E and Figure 3F , Figure 3F is a close-up view of a portion of Figure 3E , a portion of the base spacer layer 310 is removed, exposing the collector 306 and a portion of the lower surface of the extrinsic base layer 312 adjacent to the emitter spacer 322. As disclosed with reference to the removal of the portion of the extrinsic base layer 112 of Figure 1I and Figure 1J , the portion of the base spacer layer 310 can be removed.
[0055] Referring to Figure 3G and Figure 3H , Figure 3H is a close-up view of a portion of Figure 3G , a portion of the extrinsic base layer 312 is removed adjacent to the emitter spacer 322 at the lower surface, where exposed by the removal of the portion of the base spacer layer 310. As disclosed with reference to the removal of the portion of the extrinsic base layer 112 of Figure 1K and Figure 1L , the portion of the extrinsic base layer 312 can be removed. A portion of the collector 306 can be removed by a vapor phase etching process, as disclosed with reference to the removal of the portion of the extrinsic base layer 112 of Figure 3G andFigure 3H depicted in FIG. 3B, while removing portions of the extrinsic base layer 312. For example, the removed portions of the extrinsic base layer 312 can have a vertical thickness of 25% to 50% of the monocrystalline base thickness 340, in this example, as depicted in FIG. 3B. Figure 3K and Figure 3L as shown in FIG. 3B.
[0056] Referring to Figure 3I and Figure 3J , Figure 3J is an enlarged view of a portion of Figure 3I , a monocrystalline base layer 324 is formed over the collector 306, and a base link 326 is simultaneously formed on the extrinsic base layer 312 at the lower surface adjacent to the emitter spacer 322. The monocrystalline base layer 324 can include two or more base sub-layers, and the base link 326 includes a corresponding base link sub-layer. The monocrystalline base layer 324 and the base link 326 can be formed by one or more vapor phase epitaxy processes. The monocrystalline base layer 324 is monocrystalline, has a second conductivity type, in this example n-type, and includes silicon germanium. The monocrystalline base layer 324 extends laterally under the extrinsic base layer 312 past the emitter spacer 322. The base link 326 is polycrystalline and has a composition similar to the monocrystalline base layer 324 due to being formed simultaneously with the monocrystalline base layer 324. The monocrystalline base layer 324 grows upward from the collector 306, while the base link 326 grows downward from the lower surface of the extrinsic base layer 312 at approximately the same rate as the monocrystalline base layer 324 to contact the monocrystalline base layer 324. The base link 326 connects the extrinsic base layer 312 to the monocrystalline base layer 324. The monocrystalline base layer 324, the base link 326, and the extrinsic base layer 312 provide the base 334 of the HBT 304.
[0057] Referring to Figure 3K and Figure 3L , Figure 3L is an enlarged view of a portion of Figure 3K , the emitter 330 is formed in the emitter window 318, on the emitter spacer 322, and on the monocrystalline base layer 324 exposed by the emitter spacer 322. The emitter 330 can extend outside the emitter window 318, as depicted in FIG. 3B. The emitter 330 of this example is monocrystalline and primarily includes silicon. The emitter 330 has a first conductivity type, in this example n-type. The emitter 330 can be formed by a silicon vapor phase epitaxy process. The emitter contact 332 forms an electrically conductive connection with the emitter 330. Figure 3K
[0058] The base link 326 laterally adjoins the emitter spacer 322. The HBT 304 has a spacer-extrinsic base vertical offset 336, which is a vertical distance between a bottom of the emitter spacer 322 and a bottom surface of the extrinsic base layer 312 adjacent to the emitter spacer 322. The emitter spacer 322 has a bottom width 338, which is a width of the emitter spacer 322 at a bottom of the emitter spacer 322 closest to the monocrystalline base layer 324. The monocrystalline base layer 324 has a monocrystalline base thickness 340, which is a thickness of the monocrystalline base layer 324 in a vertical direction. The sum of the spacer-extrinsic base vertical offset 336 and the bottom width 338 is greater than the monocrystalline base thickness 340, which can prevent polycrystalline material of the base link 326 from growing past the emitter spacer 322 into the emitter window 318, advantageously providing a consistent contact area between the emitter 330 and the monocrystalline base layer 324, and can reduce an area of the HBT 304 compared to an HBT having polycrystalline material protruding into the emitter window.
[0059] A base link cavity height 342, which is a vertical distance between the collector 306 and the extrinsic base layer 312 adjacent to the emitter spacer 322, can be less than twice the monocrystalline base thickness 340, such that full contact between the base link 326 and the monocrystalline base layer 324 can be possible. Full contact between the base link 326 and the monocrystalline base layer 324 can advantageously provide a low resistance connection through the base link 326 between the extrinsic base layer 312 and the monocrystalline base layer 324. When the monocrystalline base layer 324 is grown, a gap 346 can exist between the bottom of the emitter spacer 322 and a transient top surface of the monocrystalline base layer 324, such that epitaxial reagent gas (e.g., silane and germane) can enter the base link 326 as it grows, further advantageously providing full contact between the base link 326 and the monocrystalline base layer 324.
[0060] Various features of the examples disclosed herein can be combined in other manifestations of example semiconductor devices. For example, any of the monocrystalline base layers 124, 224, and 324 can have one or more sub-layers of monocrystalline silicon germanium or silicon with different dopant profiles and thicknesses. Any of the HBTs 104, 204, and 304 can be implemented as a PNP HBT or an NPN HBT. Any of the HBTs 104, 204, and 304 can include an emitter liner, or can be formed without an emitter liner. Any of the HBTs 104, 204, and 304 can be integrated with other electrical components (e.g., FETs, resistors, capacitors, or inductors) on a common semiconductor substrate in an integrated circuit to implement electronic functions.
[0061] While various examples of the disclosure have been described above, it should be understood that they have been presented by way of example only, and not limitation. Numerous changes to the disclosed examples can be made in accordance with the disclosure herein without departing from the spirit or scope of the disclosure. Accordingly, the breadth and scope of the present disclosure should not be limited by any of the above described examples. Rather, the particular results presented above are meant to be illustrative only and not limiting as to the scope of the disclosure.
Claims
1. A semiconductor device comprising: A heterojunction bipolar transistor, comprising: collector; The base on the collector electrode, the base comprising: A single-crystal base layer on the current collector, the single-crystal base layer comprising single-crystal silicon germanium; An intrinsic base layer extending partially above the single-crystal base layer, the intrinsic base layer comprising polycrystalline silicon; and A base link comprising a polycrystalline material connecting the monocrystalline base layer to the intrinsic base layer, the base link comprising polycrystalline silicon germanium; The emitter on the base; and An emitter spacer made of dielectric material laterally separates the emitter from the intrinsic base layer; wherein: The single-crystal base layer extends laterally from below the emitter beyond the emitter spacer and reaches below the intrinsic base layer; The sum of the vertical offset of the spacer-external base between the bottom of the emitter spacer and the bottom surface of the intrinsic base layer adjacent to the emitter spacer, and the bottom width of the emitter spacer, is greater than the single-crystal base thickness of the single-crystal base layer; and The base link is laterally adjacent to the emitter spacer relative to the emitter.
2. The semiconductor device of claim 1, wherein the base link cavity height is less than twice the thickness of the single-crystal base, and the base link cavity height is the vertical distance between the collector and the intrinsic base layer adjacent to the emitter spacer.
3. The semiconductor device of claim 1, wherein the bottom surface of the intrinsic base layer is recessed and in contact with the link.
4. The semiconductor device of claim 1, wherein the boundary between the intrinsic base layer and the base link is flat and parallel to the top surface of the collector.
5. The semiconductor device of claim 1, wherein the intrinsic base layer has a uniform thickness throughout the heterojunction bipolar transistor.
6. The semiconductor device of claim 1, wherein the vertical distance between the collector and the bottom of the emitter spacer is greater than the thickness of the single-crystal base.
7. The semiconductor device of claim 1, wherein the single-crystal base layer comprises a single-crystal silicon sublayer above the single-crystal silicon germanium.
8. The semiconductor device of claim 1, further comprising an emitter, the emitter being contained in single-crystal silicon on the single-crystal base layer.
9. The semiconductor device of claim 7, further comprising an emitter liner between the emitter and the emitter spacer.
10. A method of forming a semiconductor device, comprising: A base spacer layer is formed above the collector of a heterojunction bipolar transistor; A polycrystalline intrinsic base layer containing silicon is formed above the base spacer layer; Expose the base spacer layer in the emitter window; A dielectric emitter spacer is formed on the sidewall of the intrinsic base layer in the emitter window, the emitter spacer extending into the base spacer layer; At least a portion of the base spacer layer is removed to expose the collector below the emitter window and the portion of the lower surface of the intrinsic base layer adjacent to the emitter spacer. as well as Simultaneously, a single-crystal base layer is formed above the collector electrode, and a polycrystalline base link is formed in contact with the intrinsic base layer adjacent to the emitter spacer; wherein: The single-crystal base layer comprises silicon-germanium; The single-crystal base layer extends laterally beyond the emitter spacer and reaches below the intrinsic base layer; The base link contacts the single-crystal base layer; The base link is laterally adjacent to the emitter spacer opposite to the emitter window; and The sum of the vertical offset of the spacer's non-intrinsic base between the bottom of the emitter spacer and the bottom surface of the non-intrinsic base layer adjacent to the emitter spacer, and the bottom width of the emitter spacer, is greater than the single-crystal base thickness of the single-crystal base layer.
11. The method of claim 10, further comprising removing a portion of the intrinsic base layer from the bottom surface of the intrinsic base layer adjacent to the emitter spacer after removing at least a portion of the base spacer layer and before simultaneously forming the monocrystalline base layer and the base link.
12. The method of claim 11, wherein the portion of the intrigued base layer is removed using a halogen-containing vapor etchant.
13. The method of claim 11, wherein removing the portion of the non-intrinsic base layer further removes a portion of the current collector.
14. The method of claim 10, wherein exposing the base spacer layer in the emitter window comprises removing a first portion of the base spacer layer in the emitter window, thereby leaving a second portion of the base spacer layer above the collector in the emitter window.
15. The method of claim 14, wherein the emitter spacer extends beyond the boundary between the intrinsic base layer and the base spacer layer before at least said portion of the base spacer layer is removed.
16. The method of claim 10, wherein exposing the base spacer layer in the emitter window comprises removing the intrinsic base layer in the emitter window.
17. The method of claim 10, wherein forming the monocrystalline base layer includes maintaining a gap between the bottom of the emitter spacer and the instantaneous top surface of the monocrystalline base layer during the formation of the monocrystalline base layer.
18. The method of claim 10, wherein forming the monocrystalline base layer comprises forming a sublayer comprising monocrystalline silicon over monocrystalline silicon germanium.
19. The method of claim 10, further comprising forming a monocrystalline silicon emitter on the monocrystalline base layer in the emitter window.
20. The method of claim 19, further comprising forming an emitter liner on the monocrystalline base layer and the emitter spacer in the emitter window, the emitter liner exposing the monocrystalline base layer in the emitter window.