Method for regioselective deposition on extreme ultraviolet (EUV) photoresist

Abstract

Disclosed herein are embodiments of processes and methods that utilize a combination of extreme ultraviolet (EUV) lithography and a regioselective deposition (ASD) process to form an EUV photoresist pattern on at least one underlayer formed over a semiconductor substrate. In the disclosed embodiments, a photoresist film is deposited on the underlayer (s) and patterned using EUV lithography to form an EUV photoresist pattern on the underlayer (s). After depositing and patterning the photoresist film, a top coating film is selectively deposited on the EUV photoresist pattern using an ASD process without depositing the top coating film on the exposed surface (s) of the underlayer (s) that is not covered by the EUV photoresist pattern. A suppression layer is provided on or within the underlayer (s) before, during, or after EUV lithography to enable regioselective deposition of the topcoat film on the EUV photoresist pattern.

Description

Cross-reference of relevant patents and applications

[0001] This application claims priority and benefit to U.S. non-provisional patent application No. 18 / 369,323, filed on September 18, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to extreme ultraviolet (EUV) lithography, and in specific embodiments, to EUV photoresist and its formation method. Background Technology

[0003] Typically, semiconductor devices such as integrated circuits (ICs) are fabricated by sequentially depositing and patterning dielectric, conductive, and semiconductor layers on a semiconductor substrate to form a network of electronic components and interconnects (e.g., transistors, resistors, capacitors, metal wires, contacts, and vias) integrated into a single structure. At each successive technology node, the minimum feature size is reduced to decrease cost by approximately doubling the component packing density.

[0004] A common patterning method involves using photolithography to expose a photoresist film coating on a target layer under a photochemical radiation pattern, and then transferring the relief pattern onto the target layer or a lower hard mask layer formed on the target layer. Using this technique, the minimum feature size is limited by the resolution of the optical system. The miniaturization of feature sizes at advanced technology nodes is driving photolithography to improve resolution. For sub-10 nm technology nodes (e.g., 7 nm and 5 nm technology nodes), 13.5 nm extreme ultraviolet (EUV) lithography is typically used to pattern the photoresist film using EUV radiation.

[0005] EUV lithography offers significant advantages in patterning sub-10 nm features due to its high optical resolution. However, a major engineering challenge of EUV lithography is that photoresists developed for conventional lithography systems may not meet the cost and / or quality requirements for patterning sub-10 nm features. For example, chemically amplified resists (CARs) and similar polymeric resists commonly used for 193 nm lithography are typically produced using liquid-based spin-coating techniques, which consume large amounts of complex metal cluster precursors, resulting in very high costs. CARs also tend to have low absorption coefficients at 13.5 nm and therefore poor sensitivity. Furthermore, diffusion of photoactive materials in CARs can lead to blurring and increase line edge roughness (LER) in the subsequently formed pattern.

[0006] Due to their high etch resistance / selectivity and photoreactivity with EUV, metal oxide photoresists have attracted attention for use in EUV lithography. In a typical EUV lithography process, wet or dry processes can be used to deposit a metal oxide photoresist film on at least one substrate formed over a semiconductor substrate. The metal oxide photoresist film can be patterned using EUV lithography to form photoresist patterns on multiple substrates, which are then transferred to the substrates using an etching process. Although both wet and dry processes can be used, dry etching processes (e.g., plasma-based etching processes) are typically used to transfer the metal oxide photoresist patterns to the substrates.

[0007] Patterning substrates using metal oxide photoresists and other photoresists commonly used in EUV lithography remains challenging. When forming low aspect ratio photoresist patterns using relatively thin photoresist films (with a film thickness of < 15 nm), the etching process used to transfer the photoresist pattern to the substrate(s) can damage the photoresist pattern by significantly etching (or completely removing) portions of the thinner photoresist film. In some cases, photoresist damage can be mitigated by depositing substantially thicker photoresist films (with a film thickness of > 20 nm) on the substrate(s) to form photoresist patterns with higher aspect ratios. However, patterning thicker photoresist films presents its own challenges, often resulting in photoresist line or pillar collapse.

[0008] As IC device feature sizes continue to shrink to the angstrom level, conventional photolithography is reaching its resolution limits and may become too expensive for large-scale use. One strategy is to reduce reliance on photolithography by using chemically oriented, self-aligned, selective, bottom-up patterning. At the heart of this strategy is region-selective processing (ASP), which centers on the idea of ​​using the surface chemistry of exposed material layers to drive the selective processing of these layers. Region-selective processing techniques can be used to selectively deposit and / or remove material from desired areas of a patterned substrate, thereby avoiding the use of photolithography for patterning.

[0009] Area-selective deposition (ASD) is an example of a bottom-up, area-selective process that provides uniform deposition of material only in desired areas of a patterned substrate. Unlike conventional deposition techniques designed to achieve uniform deposition over large areas, ASD enables the selective deposition of material on a target material (or “growth surface”) while avoiding deposition on non-target materials (or “non-growth surfaces”). ASD can be used to selectively deposit a wide variety of materials on a target material. For example, ASD techniques can be used to selectively deposit dielectrics on dielectrics (DoD), dielectrics on metals (DoM), metals on dielectrics (MoD), and metals on metals (MoM). Area-selective deposition can be achieved using a wide variety of deposition techniques, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), and molecular layer deposition (MLD), which typically utilize surface modification and vapor deposition to deposit material on target areas. Surface modification is often designed to promote the adsorption of precursor molecules on the growth surface and / or inhibit the adsorption of precursor molecules on non-growth surfaces.

[0010] Figure 8 An example of a process flow 800 is shown, attempting to deposit material on a photoresist pattern formed on a semiconductor substrate 10 using region-selective deposition. For example... Figure 8 As shown, the photoresist pattern 20 is provided on at least one underlayer 30 formed over the semiconductor substrate 10. In one example, the photoresist pattern 20 may include an EUV-active photoresist film (such as, but not limited to, a metal oxide photoresist film), and the at least one underlayer 30 may include various underlayer materials commonly used for EUV patterning (such as a bottom anti-reflective coating, a hard mask layer, a carbon layer, and other organic and inorganic material layers).

[0011] exist Figure 8 In the illustrated process flow 800, the photoresist pattern 20 formed on the underlying layers 30 comprises multiple photoresist structures 25 with variable spacing (p1 and p2). When material 40 is deposited on the photoresist pattern 20 using conventional ASD technology, the spacing differences between the photoresist structures 25 result in significantly more material 40 being deposited on / between photoresist structures 25 with larger spacing (p2) than on / between photoresist structures 25 with smaller spacing (p1). This spacing dependence is a challenge in conventional ASD processes due to the suppression / selectivity of different aspect ratios.

[0012] Therefore, there is still a need for improved EUV photoresists and methods for forming such resists. Summary of the Invention

[0013] This disclosure provides improved processes and methods for forming photoresist patterns on semiconductor substrates. More specifically, this disclosure provides various embodiments of improved processes and methods that utilize a combination of extreme ultraviolet (EUV) lithography and area selective deposition (ASD) processes to form EUV photoresist patterns on at least one underlying layer formed over a semiconductor substrate.

[0014] In the disclosed embodiments, a photoresist film is deposited on at least one substrate and patterned using EUV lithography to form an EUV photoresist pattern on the substrate(s). The photoresist film deposited on the substrate(s) is a relatively thin film, for example, less than 15 nm thick. After depositing and patterning the photoresist film, a topcoat film is selectively deposited on the EUV photoresist pattern using an ASD process, without depositing the topcoat film on the exposed surfaces of the substrate(s) not covered by the EUV photoresist pattern. The topcoat film may also be a relatively thin film with a thickness of less than 10 nm. By selectively depositing the topcoat film on the EUV photoresist pattern, the topcoat film increases the aspect ratio and total thickness of the EUV photoresist pattern initially formed on the substrate(s).

[0015] In the embodiments disclosed herein, a variety of ASD processes are used to selectively deposit a topcoat film onto an EUV photoresist pattern. In each embodiment disclosed herein, a suppressor layer is provided on or within the underlying layers(s) to enable region-selective deposition of the topcoat film on the EUV photoresist pattern. The suppressor layer may be provided on or within the underlying layers(s) before, during, or after EUV lithography is used to generate the EUV photoresist pattern. When the topcoat film is selectively deposited onto the EUV photoresist pattern using ASD, the suppressor layer reduces (or substantially prevents) the deposition of the topcoat film on the exposed surfaces of the underlying layers(s). In some embodiments, the suppressor layer may prevent deposition on the underlying layers(s) by providing a hydrophobic surface, which reduces (or substantially prevents) the topcoat film adhering to the exposed surfaces of the underlying layers(s).

[0016] The processes and methods disclosed herein overcome challenges commonly encountered when forming photoresist patterns on semiconductor substrates using conventional EUV lithography or conventional ASD processes. As described in more detail below, the processes and methods disclosed herein avoid photoresist damage and photoresist line or pillar collapse that frequently occur during conventional EUV lithography processes, and eliminate the spacing dependence problem in conventional ASD processes by utilizing multiple photoresist films and a combination of EUV lithography and ASD technologies to generate EUV photoresist patterns on (multiple) layers.

[0017] Various embodiments of methods for forming EUV photoresist patterns on semiconductor substrates are provided in this disclosure. Of course, for clarity, the order of discussion of the different steps described herein has been presented. Generally, these steps can be performed in any suitable order. Additionally, although each of the different features, techniques, configurations, etc., herein may be discussed in different places, it is intended that each of the concepts can be performed independently of or in combination with each other. Accordingly, this disclosure can be implemented and viewed in many different ways.

[0018] According to one embodiment of this disclosure, a method for forming an extreme ultraviolet (EUV) photoresist pattern on a semiconductor substrate is provided. The method typically includes: (a) depositing a photoresist film on an underlayer formed over the semiconductor substrate; (b) patterning the photoresist film using EUV lithography and forming an EUV photoresist pattern on the underlayer; (c) providing a suppression layer on or within the underlayer; and (d) selectively depositing a topcoat film on the EUV photoresist pattern. In this embodiment of the method, the suppression layer provided on or within the underlayer prevents the topcoat film from depositing on exposed surfaces of the underlayer not covered by the EUV photoresist pattern.

[0019] In some embodiments, the EUV photoresist pattern may include a plurality of photoresist structures having a variable spacing between them. In such embodiments, regardless of the spacing between the photoresist structures, providing an inhibition layer on or within the substrate can prevent the topcoat film from depositing on exposed surfaces of the substrate not covered by the EUV photoresist pattern.

[0020] This disclosure envisions providing a suppression layer on or within an underlying substrate in a variety of ways. In a first embodiment of the method, after a photoresist film is deposited on and patterned to form an EUV photoresist pattern on the underlying substrate, the suppression layer is selectively deposited on an exposed surface of the underlying substrate. For example, the suppression layer can be selectively deposited on the exposed surface of the underlying substrate by exposing the semiconductor substrate to ultraviolet (UV) radiation, which allows the suppression layer to selectively adsorb onto the exposed surface of the underlying substrate rather than onto the EUV photoresist pattern. In one embodiment, the UV treatment can expose the semiconductor substrate to UV radiation in the presence of an oxidizing agent (e.g., air, ozone, or another oxidizing agent with oxygen radicals) to form hydroxyl groups on the exposed surface of the underlying substrate. In such an embodiment, the suppression layer can react with the hydroxyl groups to selectively adsorb onto the exposed surface of the underlying substrate without adsorbing onto the EUV photoresist pattern.

[0021] In a first embodiment of the method, a wide variety of materials can be used to implement the underlayer and the suppression layer. For example, the underlayer may comprise a hydrophilic material having a water contact angle of less than or equal to 60°, and the suppression layer may comprise a hydrophobic material having a water contact angle of greater than or equal to 90°. Examples of materials suitable for use as the underlayer include, but are not limited to, amorphous carbon (aC), silicon oxycarbide (SiOC), silicon carbide (SiC), amorphous silicon, silicon dioxide (SiO2), and other metal-containing materials that provide good adhesion and allow the suppression molecules to adhere to the underlayer. Examples of hydrophobic materials suitable for use as the suppression layer include, but are not limited to: materials having relatively small molecules (e.g., short-chain molecules with a carbon chain length of less than 2-3 carbon atoms); materials having methyl end groups (e.g., trimethylsilyl (Si(CH3)3) end groups), phenyl end groups, or fluorocarbon end groups; and self-assembled monolayers (SAMs) having head groups tailored to the underlayer material, such as, but not limited to, silane, carboxyl, or phosphonic acid head groups. Further examples of hydrophilic and hydrophobic materials suitable for the underlayer and suppression layer are discussed further herein.

[0022] In a second embodiment of the method, after depositing a photoresist film on the substrate and patterning it to form an EUV photoresist pattern, the substrate is transformed into a suppression layer. For example, the semiconductor substrate can be exposed to heat treatment, ultraviolet (UV) treatment, or chemical treatment to at least transform the exposed surface of the substrate from a hydrophilic surface with a water contact angle less than or equal to 60° to a hydrophobic surface with a water contact angle greater than or equal to 90°. In some embodiments, the substrate used in the second embodiment may include a substrate having the chemical formula Si. X O Y C Z N a A carbon nitride silicon oxide layer, wherein 0≤x≤1, 0≤y≤1, 0≤z≤1 and 0≤a≤1.

[0023] In a third embodiment of the method, the substrate is transformed into a suppression layer during an EUV lithography process used to pattern the photoresist film and form an EUV photoresist pattern on the substrate. For example, the semiconductor substrate can be exposed to EUV radiation during the EUV lithography process to at least transform the exposed surface of the substrate from a hydrophilic surface with a water contact angle of less than 60° to a hydrophobic surface with a water contact angle of greater than 90°. In some embodiments, the substrate used in the third embodiment may include a substrate having the chemical formula Si. X O Y C Z N aA carbon nitride silicon oxide layer, wherein 0≤x≤1, 0≤y≤1, 0≤z≤1 and 0≤a≤1. In some embodiments, inert gases such as nitrogen (N2) or argon (Ar) used during EUV exposure can cause additional surface modification.

[0024] In a fourth embodiment of the method, the underlayer formed above the semiconductor substrate comprises a hydrophobic material, rather than a hydrophilic material. When a hydrophobic underlayer is used in the fourth embodiment, the method deposits a sacrificial hydrophilic material on the underlayer before depositing the photoresist film. The sacrificial hydrophilic material is a material having a water contact angle of less than or equal to 60° and providing good adhesion to the photoresist film. After patterning the photoresist film using EUV lithography and forming the EUV photoresist pattern, and before selectively depositing the topcoat film on the EUV photoresist pattern, the fourth embodiment of the method removes portions of the sacrificial hydrophilic material not covered by the EUV photoresist pattern to expose the hydrophobic underlayer. When the topcoat film is selectively deposited on the EUV photoresist pattern, the hydrophobic underlayer acts as a suppressive layer to prevent the topcoat film from depositing on the exposed surfaces of the underlayer not covered by the EUV photoresist pattern.

[0025] In the fourth embodiment, a wide variety of hydrophobic underlayer materials and sacrificial hydrophilic materials can be utilized. Examples of hydrophobic underlayer materials include, but are not limited to, carbon (C) and silicon carbide (SiC). Sacrificial hydrophilic materials may include, but are not limited to, amorphous carbon (aC), silicon carbide (SiOC), or oxomethyl (CxOyHz, where 0≤x≤1, 0≤y≤1, and 0≤z≤1).

[0026] This document provides another method for forming an extreme ultraviolet (EUV) photoresist pattern on a semiconductor substrate according to another embodiment of this disclosure. The method typically includes: (a) depositing a photoresist film on an underlayer formed over the semiconductor substrate; (b) patterning the photoresist film using EUV lithography and forming an EUV photoresist pattern on the underlayer, wherein the EUV photoresist pattern includes a plurality of photoresist structures having variable spacing between these photoresist structures; (c) selectively depositing a suppression layer on exposed surfaces of the underlayer not covered by the EUV photoresist pattern; and (d) selectively depositing a topcoat film on the EUV photoresist pattern using area-selective deposition (ASD). In this embodiment of the method, the suppression layer prevents the topcoat film from depositing on exposed surfaces of the underlayer not covered by the EUV photoresist pattern, regardless of the spacing between the photoresist structures.

[0027] A wide variety of materials can be used to implement the underlayer and suppressor layers described in this embodiment of the method. For example, the underlayer may comprise a hydrophilic material having a water contact angle of less than or equal to 60°, and the suppressor layer may comprise a hydrophobic material having a water contact angle of greater than or equal to 90°. Examples of materials suitable for use as the underlayer include, but are not limited to, amorphous carbon (aC), silicon oxycarbide (SiOC), amorphous silicon, silicon dioxide (SiO2), and other metal-containing materials that provide good adhesion and allow suppressor molecules to adhere to the underlayer. The suppressor layer may comprise a wide variety of hydrophobic materials, such as materials with relatively small molecules, materials with methyl, phenyl, or fluorocarbon end groups, and self-assembled monolayers (SAMs) with head groups tailored to the underlayer material, such as, but not limited to, silane, carboxyl, or phosphonic acid head groups. Further examples of hydrophilic and hydrophobic materials suitable for the underlayer and suppressor layers are discussed further herein.

[0028] In some embodiments, a suppressor layer can be selectively deposited on the exposed surface of an underlying substrate by exposing the semiconductor substrate to ultraviolet (UV) light. This UV treatment allows the suppressor layer to selectively adsorb onto the exposed surface of the underlying substrate, rather than onto the EUV photoresist pattern. In one embodiment, the UV treatment can expose the semiconductor substrate to UV radiation in the presence of an oxidizing agent (e.g., air, ozone, or another oxidizing agent) to form hydroxyl groups on the exposed surface of the underlying substrate. In such embodiments, the suppressor layer can react with the hydroxyl groups to selectively adsorb onto the exposed surface of the underlying substrate, rather than onto the EUV photoresist pattern.

[0029] The photoresist film used in the above method embodiments can include a wide variety of organic and inorganic photoresist film materials. In some embodiments, the photoresist film can be a metal oxide photoresist film containing an organometallic oxide. An organometallic oxide has a central metal atom bonded to one or more organic groups. In some embodiments, the photoresist film can include an organometallic oxide having a central metal atom selected from the group consisting of tin (Sn), zirconium (Zr), indium (In), antimony (Sb), bismuth (Bi), zinc (Zn), hafnium (Hf), aluminum (Al), and combinations thereof. In one example embodiment, the photoresist film may contain an organometallic oxide including tin oxide (SnO). However, it should be understood that the photoresist films disclosed herein are not strictly limited to organometallic oxides and may include other organic and inorganic photoresist film layers suitable for EUV lithography.

[0030] The topcoat film can also comprise a wide variety of organic and inorganic materials. In some embodiments, the topcoat may comprise a metal oxide or organometallic oxide having a central metal atom, titanium (Ti). For example, the topcoat film may be titanium oxide (TiO) or an organometallic oxide comprising TiO. However, the topcoat film is not strictly limited to such examples and may include other organic and inorganic topcoat materials. Additional examples of suitable topcoat materials include, but are not limited to, titanium nitride (TiN), titanium oxynitride (TiON), hafnium oxide (HfO), zirconium oxide (ZrO), silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), amorphous carbon (aC), tin oxide (SnOx), and aluminum oxide (Al2O3).

[0031] Note that the Summary of the Invention does not specify every embodiment and / or incremental novelty aspect of this disclosure or the claimed invention. Rather, the Summary provides only a preliminary discussion of different embodiments and corresponding novelty relative to conventional techniques. For additional details and / or possible perspectives on the invention and its embodiments, the reader is directed to the Detailed Description of the Invention and the corresponding accompanying drawings, which are discussed further below. Attached Figure Description

[0032] A more complete understanding of the invention and its advantages can be obtained by referring to the following description taken in conjunction with the accompanying drawings, in which similar reference numerals indicate similar features. However, it should be noted that the drawings only illustrate exemplary embodiments of the disclosed concepts and are therefore not intended to limit the scope, as the disclosed concepts may imply other equally effective embodiments.

[0033] Figure 1 This is a flowchart illustrating one embodiment of a method for forming an extreme ultraviolet (EUV) photoresist pattern on a semiconductor substrate according to this disclosure.

[0034] Figures 2A to 2B The use of the first embodiment according to this disclosure is demonstrated. Figure 1 The method shown is an example process flow for forming EUV photoresist patterns on a semiconductor substrate.

[0035] Figure 3 It is a graph showing the effect of ultraviolet (UV) treatment (UVTA) on the adsorption of the inhibition layer.

[0036] Figures 4A to 4B The second embodiment of the present disclosure demonstrates the utilization. Figure 1 The method shown is an example process flow for forming EUV photoresist patterns on a semiconductor substrate.

[0037] Figure 5The third embodiment of the present disclosure demonstrates the utilization. Figure 1 The method shown is an example process flow for forming EUV photoresist patterns on a semiconductor substrate.

[0038] Figures 6A to 6B The fourth embodiment of the present disclosure demonstrates the utilization. Figure 1 The method shown is an example process flow for forming EUV photoresist patterns on a semiconductor substrate.

[0039] Figure 7 This is a flowchart illustrating another embodiment of a method for forming an EUV photoresist pattern on a semiconductor substrate according to this disclosure.

[0040] Figure 8 (Prior art) demonstrates a process flow for attempting to deposit materials on photoresist patterns using area selective deposition (ASD). Detailed Implementation

[0041] This disclosure provides improved processes and methods for forming photoresist patterns on semiconductor substrates. More specifically, this disclosure provides various embodiments of improved processes and methods that utilize a combination of extreme ultraviolet (EUV) lithography and area selective deposition (ASD) processes to form EUV photoresist patterns on at least one underlying layer formed over a semiconductor substrate.

[0042] In the disclosed embodiments, a photoresist film is deposited on at least one substrate and patterned using EUV lithography to form an EUV photoresist pattern on the substrate(s). The photoresist film deposited on the substrate(s) is a relatively thin film, for example, less than 15 nm thick. After depositing and patterning the photoresist film, a topcoat film is selectively deposited on the EUV photoresist pattern using an ASD process, without depositing the topcoat film on the exposed surfaces of the substrate(s) not covered by the EUV photoresist pattern. The topcoat film may also be a relatively thin film with a thickness of less than 10 nm. By selectively depositing the topcoat film on the EUV photoresist pattern, the topcoat film increases the aspect ratio and total thickness of the EUV photoresist pattern initially formed on the substrate(s).

[0043] In the embodiments disclosed herein, a variety of ASD processes are used to selectively deposit a topcoat film onto an EUV photoresist pattern. In each embodiment disclosed herein, a suppressor layer is provided on or within the underlying layers(s) to enable region-selective deposition of the topcoat film on the EUV photoresist pattern. The suppressor layer may be provided on or within the underlying layers(s) before, during, or after EUV lithography is used to generate the EUV photoresist pattern. When the topcoat film is selectively deposited onto the EUV photoresist pattern using ASD, the suppressor layer reduces (or substantially prevents) the deposition of the topcoat film on the exposed surfaces of the underlying layers(s). In some embodiments, the suppressor layer may prevent deposition on the underlying layers(s) by providing a hydrophobic surface, which reduces (or substantially prevents) the topcoat film adhering to the exposed surfaces of the underlying layers(s).

[0044] The processes and methods disclosed herein overcome challenges commonly encountered when forming photoresist patterns on semiconductor substrates using conventional EUV lithography or conventional ASD processes. As described in more detail below, the processes and methods disclosed herein avoid photoresist damage and photoresist line or pillar collapse that frequently occur during conventional EUV lithography processes, and eliminate the spacing dependence problem in conventional ASD processes by utilizing multiple photoresist films and a combination of EUV lithography and ASD technologies to generate EUV photoresist patterns on (multiple) layers.

[0045] Now turn to the attached image. Figure 1 An embodiment of a method for forming photoresist patterns on a semiconductor substrate using the techniques disclosed herein is illustrated. More specifically, Figure 1 An exemplary method 100 for forming EUV photoresist patterns on a semiconductor substrate is shown. It will be appreciated that... Figure 1 The embodiment of method 100 shown is merely exemplary, and other methods may utilize the techniques described herein. Furthermore, because the described steps are not intended to be exclusive, additional processing steps may be added. Figure 1 Method 100 is shown. Furthermore, the order of the steps is not limited to the order shown in the figure, as different orders may occur and / or various steps may be performed in combination or simultaneously.

[0046] Figure 1 The illustrated method 100 includes depositing a photoresist film on an underlayer formed over a semiconductor substrate (in step 110), and patterning the photoresist film using EUV lithography to form an EUV photoresist pattern on the underlayer (in step 120). Method 100 further includes providing a suppression layer on or within the underlayer (in step 130), and selectively depositing a topcoat film on the EUV photoresist pattern (in step 140). Figure 1In the method 100 shown, (in step 130) an inhibitor layer is provided on or within the substrate to prevent (in step 140) the topcoat film from depositing on the exposed surface of the substrate that is not covered by the EUV photoresist pattern.

[0047] exist Figure 1 In method 100 shown, a wide variety of semiconductor materials can be used to implement the substrate, bottom layer, suppression layer, photoresist film, and top coating film. Examples of suitable semiconductor materials are provided below for illustrative purposes. However, those skilled in the art who benefit from this disclosure will readily understand how other semiconductor materials not specifically mentioned herein can also be utilized.

[0048] The semiconductor substrate can be any substrate on which substrate patterning is desired. For example, the substrate can be a semiconductor substrate having one or more semiconductor processing layers formed thereon (all processing layers together can constitute the substrate). Thus, in one embodiment, the substrate can be a semiconductor substrate that has undergone multiple semiconductor processing steps that produce a wide variety of structures and layers, all of which are known in the field of substrate processing and can be considered part of the substrate. For example, in one embodiment, the substrate can be a semiconductor wafer on which one or more semiconductor processing layers are formed. The concepts disclosed herein can be used at any stage of the substrate process flow, such as any of the many deposition steps, photolithography steps, and etching steps that can be used to form a complete substrate.

[0049] Multiple layers formed on and / or over a semiconductor substrate may include one or more layers typically used for patterning. Examples of multiple layers include, but are not limited to, bottom anti-reflective coatings (BARC), hard mask layers, carbon layers, and other organic and inorganic material layers. For example, multiple layers may include carbon (C) layers, amorphous carbon layers (aC), silicon carbide (SiC) layers, silicon oxycarbide (SiOC) layers, silicon carbide (SiC) layers, amorphous silicon layers, silicon dioxide (SiO2) layers, and / or combinations thereof. Other semiconductor materials suitable for use as layers may also be utilized, as discussed further herein and known in the art.

[0050] In some embodiments, the substrate on which the photoresist film is deposited (in step 110) may comprise a hydrophilic material or another material that provides good adhesion between the substrate and the photoresist film. As used herein, a hydrophilic material is defined as a material having a water contact angle of less than or equal to 60°. Examples of suitable hydrophilic materials for use as a substrate include, but are not limited to, amorphous carbon (aC), silicon oxycarbide (SiOC), amorphous silicon, silicon dioxide (SiO2), and other metallic materials that provide good adhesion and allow inhibition of molecular adhesion to the substrate.

[0051] In other embodiments, the substrate on which the photoresist film is deposited (in step 110) may comprise a hydrophobic material having a water contact angle greater than or equal to 90°. Examples of suitable hydrophobic materials for use as the substrate include, but are not limited to, carbon (C) and silicon carbide (SiC).

[0052] The photoresist film deposited in step 110 can include a wide variety of organic and inorganic photoresist film layers. In some embodiments, the photoresist film can be a metal oxide photoresist film containing an organometallic oxide. In one example, the photoresist film can be an organometallic oxide including tin oxide (SnO). However, it should be noted that the photoresist film disclosed herein is not limited to this example and can include other organometallic oxides having a central metal atom of tin (Sn), zirconium (Zr), indium (In), antimony (Sb), bismuth (Bi), zinc (Zn), hafnium (Hf), aluminum (Al), or combinations thereof. Further note that the photoresist film disclosed herein is not strictly limited to organometallic oxides and can include other organic and inorganic photoresist film layers suitable for EUV lithography.

[0053] The topcoat film selectively deposited in step 140 may also comprise a wide variety of organic and inorganic materials. In some embodiments, the topcoat film may be a metal oxide or an organometallic oxide containing the central metal atom titanium. For example, the topcoat film may be titanium oxide (TiO) or an organometallic oxide comprising TiO. However, the topcoat film is not strictly limited to such examples and may include other organic and inorganic topcoat materials. Additional examples of suitable topcoat materials include, but are not limited to, titanium nitride (TiN), titanium oxynitride (TiON), hafnium oxide (HfO), zirconium oxide (ZrO), silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), amorphous carbon (aC), tin oxide (SnOx), and aluminum oxide (Al2O3).

[0054] In some embodiments, the inhibition layer provided in step 130 can reduce (or prevent) the deposition of the topcoat film on the exposed surface of the underlying layer by reducing (or preventing) the adsorption of the topcoat film on the exposed surface of the underlying layer (in step 140). For example, the inhibition layer may include a hydrophobic material (e.g., a material having a water contact angle greater than or equal to 90°) to reduce or prevent the adsorption of the topcoat film on the exposed surface of the underlying layer. Examples of hydrophobic materials suitable for use as inhibition layers include, but are not limited to: materials having relatively small molecules (e.g., short-chain molecules with a carbon chain length of less than 2-3 carbon atoms); materials having methyl end groups (e.g., trimethylsilyl (Si(CH3)3) end groups), phenyl end groups, or fluorocarbon end groups; and self-assembled monolayers (SAMs) having head groups tailored to the underlying material, such as, but not limited to, silane, carboxyl, or phosphonic acid head groups. Examples of hydrophobic materials suitable for use as inhibition layers are described in more detail below.

[0055] A wide variety of deposition processes can be used to form the material layers shown and described herein. For example, the underlayer, inhibition layer, photoresist film, and top layer film can be deposited using one or more deposition techniques, including but not limited to spin coating, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and / or other deposition processes.

[0056] A wide variety of wet and dry deposition techniques can also be used to form multiple underlayers on and / or over a semiconductor substrate. In some embodiments, spin-coating deposition processes can be used to deposit hydrophilic underlayers (e.g., amorphous carbon (aC), silicon carbide (SiOC), amorphous silicon, or silicon dioxide (SiO2) layers) over a semiconductor substrate using various liquids, liquid flow rates, and spin chuck speeds. In other embodiments, vapor phase deposition processes (such as PECVD) can be used to deposit hydrophobic underlayers (e.g., carbon (C) or silicon carbide (SiC) layers) over a substrate using various gaseous chemicals under various pressures, power, gas flow rates, and temperatures.

[0057] In some embodiments, photoresist films can be deposited using various dry deposition techniques. For example, photoresist films can be deposited using chemical vapor deposition (CVD), chemical vapor polymerization (CVP), or atomic layer deposition (ALD). U.S. Patent Application Serial No. 18 / 216,168, filed June 29, 2023, entitled “Methods of Forming Photosensitivity Organometallic Oxides by Chemical Vapor Polymerization,” discloses an example of a CVP process that can be used to deposit the photoresist films disclosed herein. Topcoat films can be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), or molecular layer deposition (MLD) processes. In some embodiments, topcoat films can be selectively deposited using spatial ALD or subsaturated ALD to provide additional selectivity on top of the EUV photoresist pattern or to increase the deposition thickness of the topcoat film.

[0058] The deposition techniques used for depositing photoresist films and topcoat films can utilize a variety of gaseous chemicals under various pressure, power, gas flow rate, and temperature conditions. Other operating variables can also be adjusted to control the various deposition processes described herein. Operating variables may include, for example, chamber temperature, chamber pressure, liquid and / or gas flow rate, liquid and / or gas type, and / or other operating variables used for processing steps. Variations can also be implemented while still utilizing the techniques described herein.

[0059] Figure 1 The method 100 shown utilizes a combination of EUV lithography and ASD technology to form an EUV photoresist pattern on at least one substrate formed above a semiconductor substrate. After depositing a photoresist film and patterning it using EUV lithography to form an EUV photoresist pattern on the substrate(s), a topcoat film is selectively deposited on the EUV photoresist pattern using ASD technology. The selective deposition of the topcoat film increases the aspect ratio and total thickness of the EUV photoresist pattern initially formed on the substrate(s), while a suppressor layer prevents the topcoat film from being deposited on the exposed surfaces of the substrate(s).

[0060] In step 140, a variety of ASD techniques can be used to selectively deposit the topcoat film onto the EUV photoresist pattern. Figures 2A to 2B , Figures 4A to 4B , Figure 5 and Figures 6A to 6BThe document provides example process flows for forming EUV photoresist patterns on semiconductor substrates. In each process flow discussed below, a top coating film is selectively deposited on the EUV photoresist pattern using different ASD techniques.

[0061] Figures 2A to 2B The use of the first embodiment according to this disclosure is demonstrated. Figure 1 The illustrated method 100 is an example process flow 200 for forming an EUV photoresist pattern on a semiconductor substrate. Similar to method 100 described above, process flow 200 begins by depositing a photoresist film 205 on at least one underlayer 210 formed over a semiconductor substrate 215 (in step 110). The photoresist film 205, the underlayer 210, and the semiconductor substrate 215 may comprise various materials as described in more detail above. For example, the photoresist film 205 may be a metal oxide photoresist containing an organometallic oxide (e.g., an organometallic oxide including tin oxide), and the underlayer 210 may comprise a hydrophilic material (e.g., a material having a water contact angle of less than or equal to 60°) that provides good adhesion between the underlayer 210 and the photoresist film 205.

[0062] After depositing the photoresist film 205 (in step 110), process flow 200 uses EUV lithography to pattern the photoresist film 205 and form an EUV photoresist pattern 236 on the substrate 210 (in step 120). Figure 2A As shown, in the EUV lithography process, a semiconductor substrate 215 containing a photoresist film 205 is exposed to EUV radiation 225 (e.g., at a wavelength of 13.5 nm) in the EUV exposure step 220. The EUV lithography process can utilize a photomask (not shown) such that the photoinduced reaction occurs only in the region 232 of the photoresist film 205 exposed to EUV radiation 225. The region 232 of the photoresist film 205 exposed to EUV radiation 225 is converted into reacted photoresist. The region 234 of the photoresist film 205 not exposed to EUV radiation 225 remains unreacted. After the EUV exposure step 220, an optional post-exposure bake (PEB) step 230 (or other thermal treatment step) can be performed to stabilize the photoresist after EUV exposure by completing the reaction initiated during exposure. In some embodiments, the optional thermal treatment step can prevent changes in line edge roughness (LER), line width roughness (LWR), and / or critical dimension (CD).

[0063] After completing EUV exposure step 220 and optional post-exposure baking (PEB) step 230, a development step 240 is performed to remove a portion of the photoresist film 205 for patterning, thereby providing an EUV photoresist pattern 236 on the substrate 210. Development step 240 can be a wet or dry process. For example, a portion of the photoresist film 205 can be removed by treating the substrate with a developer to dissolve the reacted areas 232 (in the case of positive resist) or the unreacted areas 234 (in the case of negative resist). Alternatively, a dry process can be used to remove the reacted or unreacted areas of the photoresist film 205. Dry processes can include, for example, selective plasma etching processes or thermal processes, advantageously eliminating the use of a developer. In some embodiments, reactive ion etching (RIE) or atomic layer etching (ALE) can be used for dry processing.

[0064] Following the development step 240, the EUV photoresist pattern 236 formed on the substrate 210 includes a plurality of photoresist structures 238. In some embodiments, the spacing (p) between the plurality of photoresist structures 238 can be varied. Figure 2A As shown, for example, some of the photoresist structures 238 may have a smaller spacing (p1), while other photoresist structures 238 have a relatively larger spacing between structures (p2).

[0065] Depositing and patterning photoresist film 205 to form EUV photoresist pattern 236 (e.g.) Figure 2A Following this (as shown), process flow 200 uses area-selective deposition to selectively deposit a topcoat film 260 on the EUV photoresist pattern 236, without depositing the topcoat film 260 on the exposed surface of the underlayer 210 (as shown). Figure 2B (As shown). To achieve regionally selective deposition, in Figure 2A After forming the EUV photoresist pattern 236, in Figure 2B An inhibition layer 256 is provided on the exposed surface of the bottom layer 210 (in step 130).

[0066] exist Figures 2A to 2B In the process flow 200 shown, a wide variety of base material 210 can be used. For example, Figure 2A The substrate 210 shown may typically include a hydrophilic material or another material that provides good adhesion between the substrate 210 and the photoresist film 205. Examples of hydrophilic materials suitable for use as the substrate 210 in process flow 200 include, but are not limited to, amorphous carbon (aC), silicon oxycarbide (SiOC), amorphous silicon, silicon dioxide (SiO2), and other metallic materials that provide good adhesion and allow inhibition of molecular adhesion to the substrate.

[0067] Figure 2B The suppression layer 256 shown may comprise a wide variety of hydrophobic materials (e.g., materials having a water contact angle greater than or equal to 90°). Examples of suitable hydrophobic materials for use as suppression layer 256 include, but are not limited to: materials having relatively small molecular weights (e.g., short-chain molecules with a carbon chain length of less than 2-3 carbon atoms); materials having methyl end groups (e.g., trimethylsilyl (Si(CH3)3) end groups), phenyl end groups, or fluorocarbon end groups; and self-assembled monolayers (SAMs) having head groups tailored to the underlying material, such as, but not limited to, silane, carboxyl, or phosphonic acid head groups. Non-limiting examples of suitable SAMs include octadecyltrichlorosilane (ODTS), dodecyl mercaptan (DDT), and octadecylphosphonic acid (ODPA). In some embodiments, suppression layer 256 may comprise silane groups, such as, but not limited to, trimethylsilanedimethylamine (TMSDMA) and octadecyltrichlorosilane (ODTS).

[0068] In some embodiments, the inhibition layer 256 can be selectively deposited on the exposed surface of the underlying layer 210 by exposing the semiconductor substrate 215 to an optional ultraviolet (UV) treatment (in step 250). When used, the optional UV treatment step 250 can allow the inhibition layer 256 to selectively adhere to the exposed surface of the underlying layer 210, rather than the EUV photoresist pattern 236. In some embodiments, the optional UV treatment step 250 can expose the semiconductor substrate 215 to UV radiation 255 in the presence of an oxidizing agent (e.g., air, ozone, or another oxygen-containing oxidizing agent) to form hydroxyl groups ( ) on the exposed surface of the underlying layer 210. Figure 2B (Not shown in the image). The inhibition layer 256 can then react with hydroxyl groups to selectively adsorb onto the exposed surface of the bottom layer 210.

[0069] Figure 3 Graph 300 is provided to illustrate the effect of UV treatment in air (UVTA) on the adsorption of the inhibition layer. As shown in Graph 300, prior to UV treatment (in step 250) and deposition of inhibition layer 256 (in step 130), the incoming EUV photoresist pattern 236 (metal oxide resist, MOR) and the incoming underlayer 210 (UL) have water contact angles of approximately 30° and 80°, respectively. Depositing inhibition layer 256 without UV treatment does not significantly affect the water contact angle of EUV photoresist pattern 236 (MOR) or underlayer 210 (UL). This demonstrates that inhibition layer 256 does not adhere to EUV photoresist pattern 236 (MOR) or underlayer 210 (UL) without UV treatment.

[0070] As shown in graph 300, when exposed to UV radiation 255 in air (or another oxidizing agent), both the EUV photoresist pattern 236 (MOR) and the substrate 210 (UL) are hydrophilic and have a water contact angle of less than 30°. After UV treatment (in step 250) and the deposition of the inhibition layer 256 (in step 130), the EUV photoresist pattern 236 (MOR) remains hydrophilic, while the substrate 210 becomes hydrophobic (with a water contact angle greater than 90°). This demonstrates that the inhibition layer 256 is selectively deposited on the substrate 210 (UL) rather than on the EUV photoresist pattern 236 (MOR). The optional UV treatment step 250 (…) is achieved by exposing the semiconductor substrate 215 to UV radiation 255 in the presence of an oxidizing agent (such as air) to form hydroxyl groups on the exposed surface of the substrate 210. Figure 2B and Figure 3 (As shown) This allows the inhibition layer 256 to selectively adsorb onto the exposed surface of the underlayer 210, while substantially preventing the inhibition layer 256 from adsorbing onto the EUV photoresist pattern 236. Although not strictly limited to this theory, the selective adsorption of the inhibition layer 256 onto the exposed surface of the underlayer 210 is most likely due to the silane groups reacting better with hydroxyl groups than with metal oxides.

[0071] After providing an inhibition layer 256 on the exposed surface of the substrate 210 (in step 130), process flow 200 selectively deposits a topcoat film 260 onto the EUV photoresist pattern 236 (in step 140) to increase the aspect ratio and total thickness of the EUV photoresist pattern 236 initially formed on the substrate 210. By providing a hydrophobic surface during the selective deposition process, the inhibition layer 256 on the substrate 210 prevents the topcoat film 260 from depositing on the exposed surface of the substrate 210 (in step 140), as... Figure 2B As shown.

[0072] exist Figures 2A to 2B In the illustrated process flow 200, the bottom layer 210 contains a hydrophilic material, and the inhibition layer 256 contains a hydrophobic material (such as TMSDMA or another silane), which reduces or substantially prevents the deposition of the top coating film 260 on the exposed surface of the bottom layer 210 located between the photoresist structures 238 (in step 140). Figures 2A to 2B In the illustrated embodiment, after the EUV photoresist pattern 236 is formed using EUV lithography (in step 120), a suppression layer 256 is provided on the substrate 210 (in step 130). However, in other embodiments, the suppression layer 256 may be provided within the substrate 210 before, during, or after the formation of the EUV photoresist pattern 236 using EUV lithography (in step 120) (in step 130).

[0073] Figures 4A to 4B The second embodiment of the present disclosure demonstrates the utilization. Figure 1 The method 100 shown is an example process flow 400 for forming EUV photoresist patterns on a semiconductor substrate. Figure 4A The process flow shown has 400 steps and Figure 2A The process flow shown has 200 identical steps, and therefore, for the sake of brevity, it will not be repeated here.

[0074] Depositing and patterning photoresist film 205 to form EUV photoresist pattern 236 (e.g.) Figure 4A (As shown) Subsequently, process flow 400 uses another area-selective deposition technique to selectively deposit a topcoat film 260 on the EUV photoresist pattern 236, without depositing the topcoat film 260 on the exposed surface of the underlayer 210. Figure 4B In the illustrated embodiment, after depositing and patterning the photoresist film 205 to form an EUV photoresist pattern 236 (in step 120), an inhibition layer 256 is provided within the underlying layer 210 by converting the underlying layer 210 into an inhibition layer 256 (in step 130).

[0075] In some embodiments, process flow 400 can transform the underlying layer 210 into an inhibition layer 256 by exposing the semiconductor substrate 215 to heat treatment, UV treatment, or chemical treatment 410 (e.g., ...). Figure 4B As shown), this treatment at least transforms the exposed surface of the bottom layer 210 from a hydrophilic surface to a hydrophobic surface. Figures 4A to 4B A wide variety of base material 210 can be used in the process flow 400 shown. For example, Figure 4A The bottom layer 210 shown may include materials with the chemical formula Si X O Y C Z N a A carbon nitride silicon oxide layer, wherein 0≤x≤1, 0≤y≤1, 0≤z≤1 and 0≤a≤1.

[0076] In some embodiments, the semiconductor substrate 215 may be exposed to Figure 4B The heat treatment in the process aims to at least convert the exposed surface of the substrate 210 from a hydrophilic surface to a hydrophobic surface. The heat treatment may expose the semiconductor substrate 215 to an elevated temperature sufficiently high to convert the exposed surface of the substrate 210 to a hydrophobic surface without causing thermal decomposition of the photoresist film 205. In one example, the substrate temperature or ambient temperature may be greater than approximately 200°C.

[0077] In other embodiments, the semiconductor substrate 215 may be exposed to Figure 4B The UV treatment in the process is used to at least convert the exposed surface of the substrate 210 from a hydrophilic surface to a hydrophobic surface. The UV treatment can be performed by exposing the semiconductor substrate 215 to UV radiation in the presence of oxygen (O2), nitrogen (N2) and / or argon (Ar) to convert the exposed surface of the substrate 210 to a hydrophobic surface.

[0078] In yet another embodiment, the semiconductor substrate 215 may be exposed to Figure 4B The chemical treatment in the substrate is used to at least convert the exposed surface of the substrate 210 from a hydrophilic surface to a hydrophobic surface. For example, the chemical treatment may expose the semiconductor substrate 215 to ozonated water to convert the exposed surface of the substrate 210 to a hydrophobic surface.

[0079] After the substrate 210 is transformed into the inhibition layer 256 using heat treatment, UV treatment, or chemical treatment 410, process flow 400 selectively deposits a topcoat film 260 onto the EUV photoresist pattern 236 (in step 140) to increase the aspect ratio and total thickness of the EUV photoresist pattern 236 initially formed on the substrate 210. By providing a hydrophobic surface during the selective deposition process, the inhibition layer 256 provided within the substrate 210 (in step 130) prevents the topcoat film 260 from depositing on the exposed surface of the substrate 210 (in step 140).

[0080] exist Figures 4A to 4B In the illustrated process flow 400, the underlying layer 210 formed over the semiconductor substrate 215 comprises a hydrophilic material, which is transformed into a hydrophobic inhibition layer 256 after the formation of the EUV photoresist pattern 236. By transforming the exposed surface of the underlying layer 210 from a hydrophilic surface to a hydrophobic surface, process flow 400 reduces or substantially prevents the deposition of the topcoat film 260 on the exposed surface of the underlying layer 210 located between the photoresist structures 238 (in step 140).

[0081] Figure 5 The third embodiment of the present disclosure demonstrates the utilization. Figure 1 The method 100 shown is an example process flow 500 for forming an EUV photoresist pattern 236 on a semiconductor substrate 215. (Compared to...) Figures 2A to 2B and Figures 4A to 4B As in the previous embodiment shown, prior to patterning the photoresist film 205 using EUV lithography and forming the EUV photoresist pattern on the substrate 210 (in step 120), process flow 500 deposits a photoresist film 205 on at least one substrate 210 formed over the semiconductor substrate 215 (in step 110). Figure 5 The process flow 500 shown can utilize a wide variety of base material 210. For example, Figure 5 The bottom layer 210 shown may include materials with the chemical formula Si X O Y C Z N a A carbon nitride silicon oxide layer, wherein 0≤x≤1, 0≤y≤1, 0≤z≤1 and 0≤a≤1. In some embodiments, inert gases such as nitrogen (N2) or argon (Ar) used during EUV exposure can cause additional surface modification.

[0082] exist Figure 5 In the illustrated process flow 500, during the EUV lithography process used to form the EUV photoresist pattern 236, a suppression layer 256 is provided within the underlying layer 210 (in step 130). When the semiconductor substrate 215 is exposed to EUV radiation 225 in the EUV exposure step 220, the regions 232 of the photoresist film 205 exposed to EUV radiation 225 (i.e., regions not covered by the photomask) become reacted photoresist, while the regions 234 of the photoresist film 205 not exposed to EUV radiation 225 remain unreacted. In addition to converting selected portions of the photoresist film 205 into reacted photoresist, Figure 5 The EUV radiation 225 shown transforms at least a portion of the bottom layer 210 from a hydrophilic material to a hydrophobic material.

[0083] For example, Figure 5 The EUV radiation 225 shown can convert the portion 231 of the substrate 210 below region 232 of the photoresist film 205 (i.e., the reacted photoresist) into a hydrophobic material, while the portion 233 of the substrate 210 below region 234 of the photoresist film 205 (i.e., the unreacted photoresist) remains hydrophilic. In some embodiments, EUV radiation 225 applied to the substrate can convert a portion 231 of the entire thickness into a hydrophobic material, such as... Figure 5 As shown. In other embodiments, EUV radiation 225 can convert a portion 231 less than the entire thickness into a hydrophobic material. After performing development step 140 to remove the reacted areas 232 of the photoresist film 205 and form an EUV photoresist pattern 236, the converted portion 231 of the underlayer 210 provides a hydrophobic surface that repels the topcoat film 260 during subsequent deposition processes.

[0084] After performing EUV lithography to form the EUV photoresist pattern 236 (in step 120) and providing a suppression layer 256 within the underlayer 210 (in step 130), process flow 500 selectively deposits a topcoat film 260 onto the EUV photoresist pattern 236 (in step 140) to increase the aspect ratio and total thickness of the EUV photoresist pattern 236 initially formed on the underlayer 210. By providing a hydrophobic surface during the selective deposition process, the suppression layer 256 within the underlayer 210 prevents the topcoat film 260 from depositing on the exposed surface of the underlayer 210 (in step 140).

[0085] exist Figure 5 In the illustrated process flow 500, the underlying layer 210 formed over the semiconductor substrate 215 comprises a hydrophilic material, which is converted into a hydrophobic inhibition layer 256 during the EUV lithography process when forming the EUV photoresist pattern 236. By converting a portion 231 of the underlying layer 210 from a hydrophilic material to a hydrophobic material, process flow 500 reduces or substantially prevents the deposition of the topcoat film 260 on the exposed surfaces of the underlying layer 210 located between the photoresist structures 238 (in step 140).

[0086] exist Figures 2A to 2B , Figures 4A to 4B and Figure 5 In the illustrated process flow, the underlayer 210 formed above the semiconductor substrate 215 comprises a hydrophilic material that provides good adhesion between the underlayer 210 and the photoresist film 205 deposited thereon. However, the underlayer 210 described herein is not strictly limited to hydrophilic materials. In other embodiments, the underlayer 210 formed above the semiconductor substrate 215 may comprise a hydrophobic material instead of a hydrophilic material. When a hydrophobic underlayer is used, a sacrificial hydrophilic layer is deposited on the underlayer 210 prior to the deposition of the photoresist film 205.

[0087] Figures 6A to 6B The fourth embodiment of the present disclosure demonstrates the utilization. Figure 1 The illustrated method 100 is an example process flow diagram 600 for forming an EUV photoresist pattern 236 on a semiconductor substrate 215. Unlike previous embodiments, process flow 600 begins by depositing a sacrificial hydrophilic layer 610 (with a water contact angle less than or equal to 60°) on a hydrophobic underlayer 210, followed by the deposition of a photoresist film 205 (in step 110). Because the underlayer 210 contains a hydrophobic material, the sacrificial hydrophilic layer 610 is required to provide good adhesion for the photoresist film 205 when it is deposited in step 110. Figure 6AA wide variety of hydrophobic underlayer materials and sacrificial hydrophilic materials can be used in the process flow 600 shown. For example, the underlayer 210 may include carbon (C) or silicon carbide (SiC), and the sacrificial hydrophilic layer 610 may include amorphous carbon (aC), silicon carbide (SiOC), or oxomethyl (CxOyHz, where 0≤x≤1, 0≤y≤1, and 0≤z≤1).

[0088] After the photoresist film 205 is deposited on the sacrificial hydrophilic layer 610, process flow 600 uses EUV lithography to pattern the photoresist film 205 and form an EUV photoresist pattern on the bottom layer 210 (in step 120). Figure 6A The EUV lithography process shown includes an EUV exposure step 220, an optional post-exposure baking (PEB) step 230, and a development step 240, similar to the reference above. Figure 2A The steps shown and described.

[0089] After forming the EUV photoresist pattern 236 (in step 120), as Figure 2A and Figure 6A As shown and described, process flow 600 uses UV or plasma treatment 620 to remove portions of the sacrificial hydrophilic layer 610 (not covered by the EUV photoresist pattern 236) and expose the hydrophobic underlayer 210, such as Figure 6B As shown. When the topcoat film 260 is selectively deposited on the EUV photoresist pattern 236 (in step 140), the hydrophobic underlayer 210 acts as an inhibition layer 256 to prevent the topcoat film 260 from depositing on the exposed surfaces of the underlayer 210 that are not covered by the EUV photoresist pattern 236.

[0090] exist Figures 6A to 6B In the illustrated process flow 600, the underlayer 210 formed above the semiconductor substrate 215 comprises a hydrophobic material, rather than a hydrophilic material. By depositing the hydrophobic underlayer 210 on the semiconductor substrate 215 prior to forming the EUV photoresist pattern 236 on the underlayer 210, process flow 600 reduces or substantially prevents the deposition of the topcoat film 260 on the exposed surfaces of the underlayer 210 located between the photoresist structures 238 (in step 140).

[0091] like Figures 2A to 2B , Figures 4A to 4B , Figure 5 and Figures 6A to 6BAs shown, the process flow disclosed herein utilizes a combination of EUV lithography and ASD technology to generate an EUV photoresist pattern 236 on at least one underlying layer 210 formed over a semiconductor substrate 215. In each process flow disclosed herein, a suppression layer 256 is provided on the underlying layer 210 (in... Figures 2A to 2B In the illustrated embodiment) or within the bottom layer 210 (in Figures 4A to 4B , Figure 5 and Figures 6A to 6B In the illustrated embodiment, this allows the topcoat film 260 to be deposited region-selectively on the EUV photoresist pattern 236, while substantially preventing the topcoat film 260 from depositing on the exposed surface of the bottom layer 210. In doing so, the process flow disclosed herein avoids photoresist damage and photoresist line or pillar collapse that frequently occur during conventional EUV lithography processes, and eliminates spacing-dependent problems (e.g., as...) that occur in conventional ASD processes. Figure 8 (As shown).

[0092] Figure 7 Another exemplary method 700 for forming an EUV photoresist pattern on a semiconductor substrate according to this disclosure is shown. It will be appreciated that... Figure 7 The embodiment of method 700 shown is merely exemplary, and other methods may utilize the techniques described herein. Furthermore, because the described steps are not intended to be exclusive, additional processing steps may be added. Figure 7 Method 100 is shown. Furthermore, the order of the steps is not limited to the order shown in the figure, as different orders may occur and / or various steps may be performed in combination or simultaneously.

[0093] Similar to Figure 1 The previous method 100 shown, Figure 7 The illustrated method 700 includes depositing a photoresist film on a substrate formed above a semiconductor substrate (in step 710), and patterning the photoresist film using EUV lithography to form an EUV photoresist pattern on the substrate (in step 720). In method 700, the EUV photoresist pattern formed in step 720 includes a plurality of photoresist structures, wherein the spacing (p) between these photoresist structures is variable. Figure 2A As shown, for example, the EUV photoresist pattern formed in step 720 may include a plurality of photoresist structures 238, wherein some of the photoresist structures 238 have a small spacing (p1), while other photoresist structures 238 have a relatively large spacing (p2) between the structures.

[0094] Method 700 further includes selectively depositing a suppression layer on the exposed surface of the underlying layer not covered by the EUV photoresist pattern (in step 730), and selectively depositing a topcoat film on the EUV photoresist pattern using area-selective deposition (ASD) (in step 740). In method 700, regardless of the spacing (p) between the photoresist structures, the suppression layer selectively deposited in step 730 prevents the topcoat film from being deposited on the exposed surface of the underlying layer not covered by the EUV photoresist pattern in step 740. Figures 2A to 2B Demonstrates the use of Figure 7 The method 700 shown is an example of a process flow 200 for forming an EUV photoresist pattern on a semiconductor substrate. However, it should be recognized that other process flows can also use method 700 to produce EUV photoresist patterns.

[0095] This disclosure provides various embodiments of improved process flows and methods for forming EUV photoresist patterns on semiconductor substrates. The disclosed embodiments improve upon conventional process flows and methods for forming EUV photoresist by generating EUV photoresist patterns on at least one underlying layer formed over the semiconductor substrate using a combination of EUV lithography and ASD technologies. By utilizing the above techniques, the process flows and methods disclosed herein provide an EUV photoresist that does not exhibit photoresist damage, photoresist line or pillar collapse, or spacing dependence issues.

[0096] As used herein, the term "semiconductor substrate" or "substrate" means and includes a base material or structure on which material is formed. It should be understood that a substrate can include a single material, multiple layers of different materials, one or more layers having different material regions or different structural regions, etc. These materials can include semiconductors, insulators, conductors, or combinations thereof. For example, a substrate can be a semiconductor substrate, a base semiconductor layer on a support structure, metal electrodes, or a semiconductor substrate having one or more layers, structures, or regions formed thereon. A substrate can be a conventional silicon substrate or other bulk substrate comprising layers of semiconductor material. As used herein, the term "bulk substrate" means and includes not only silicon wafers but also silicon-on-insulator ("SOI") substrates (such as silicon-on-sapphire ("SOS") and silicon-on-glass ("SOG") substrates), silicon epitaxial layers on a base semiconductor substrate, and other semiconductor or optoelectronic materials (such as silicon-germanium, germanium, gallium arsenide, gallium nitride, and indium phosphide). Substrates can be doped or undoped.

[0097] The substrate may also include any material portion or structure of the device (particularly semiconductor or other electronic equipment) and may be, for example, a base substrate structure (such as a semiconductor substrate) or a layer on or covering a base substrate structure. Therefore, the term “substrate” is not intended to be limited to any particular base structure, underlying or overlay layer, patterned layer or unpatterned layer, but is contemplated to include any such layer or base structure, and any combination of layers and / or base structures.

[0098] It should be noted that the reference to "one embodiment" or "embodiment" throughout this specification means that a particular feature, structure, material, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention, but does not imply that they are present in every embodiment. Therefore, the phrase "in one embodiment" or "in an embodiment" appearing throughout this specification does not necessarily refer to the same embodiment of the invention. Furthermore, these particular features, structures, materials, or characteristics can be combined in one or more embodiments in any suitable manner. In other embodiments, various additional layers and / or structures may be included, and / or the features may be omitted.

[0099] Those skilled in the art will recognize that various embodiments can be practiced in the absence of one or more specific details, or by utilizing other alternatives and / or additional methods, materials, or components. In other instances, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring aspects of the various embodiments of the invention. Similarly, specific figures, materials, and configurations are set forth for illustrative purposes to provide a thorough understanding of the invention. Nevertheless, the invention can be practiced without specific details. Furthermore, it should be understood that the various embodiments illustrated in the accompanying drawings are illustrative representations and are not necessarily drawn to scale.

[0100] In light of this description, further modifications and alternative embodiments of the methods described herein will be apparent to those skilled in the art. Therefore, it will be appreciated that the described methods are not limited to these exemplary arrangements. It should be understood that the forms of the methods shown and described herein are to be considered exemplary embodiments. Various changes may be made in the implementation. Therefore, although the invention has been described herein with reference to specific embodiments, various modifications and changes may be made without departing from the scope of the invention. Therefore, the specification and drawings are to be regarded in an illustrative rather than restrictive sense, and such modifications are intended to be included within the scope of the invention. Furthermore, any benefits, advantages, or solutions to problems described herein with respect to specific embodiments are not intended to be construed as key, essential, or fundamental features or elements of any or all claims.

Claims

1. A method for forming an extreme ultraviolet (EUV) photoresist pattern on a semiconductor substrate, the method comprising: A photoresist film is deposited on the underlying layer formed above the semiconductor substrate; EUV photolithography is used to pattern the photoresist film and form an EUV photoresist pattern on the substrate. An inhibition layer is provided on or within this underlying layer; as well as A topcoat film is selectively deposited on the EUV photoresist pattern, wherein the inhibition layer prevents the topcoat film from depositing on the exposed surface of the underlying layer that is not covered by the EUV photoresist pattern.

2. The method as described in claim 1, wherein, The EUV photoresist pattern includes multiple photoresist structures with variable spacing between them, and wherein, regardless of the spacing between these photoresist structures, the inhibition layer prevents the topcoat film from depositing on the exposed surface of the underlying layer that is not covered by the EUV photoresist pattern.

3. The method as described in claim 1, wherein, At least one of the photoresist film and the topcoat film contains an organometallic oxide.

4. The method of claim 3, wherein, The organometallic oxide has a central metal atom of tin (Sn), titanium (Ti), zirconium (Zr), indium (In), antimony (Sb), bismuth (Bi), zinc (Zn), hafnium (Hf), aluminum (Al), or a combination thereof.

5. The method of claim 1, wherein, The bottom layer comprises a hydrophilic material having a water contact angle of less than or equal to 60°, and the inhibition layer comprises a hydrophobic material having a water contact angle of greater than or equal to 90°.

6. The method of claim 5, wherein, The provision of the inhibition layer includes: After depositing and patterning the photoresist film to form the EUV photoresist pattern, the inhibition layer is selectively deposited on the exposed surface of the underlying layer.

7. The method of claim 6, wherein, The underlying layer comprises amorphous carbon (aC), silicon carbide (SiOC), amorphous silicon, or silicon dioxide (SiO2), and wherein the inhibition layer comprises a material having short-chain molecules, a material having methyl, phenyl, or fluorocarbon end groups, and a self-assembled monolayer (SAM) having silane, carboxyl, or phosphonic acid head groups.

8. The method of claim 6, wherein, Prior to the selective deposition of the suppression layer, the method includes: The semiconductor substrate is exposed to ultraviolet (UV) treatment so that the inhibition layer can be selectively adsorbed onto the exposed surface of the underlying layer during the selective deposition of the inhibition layer, rather than onto the EUV photoresist pattern.

9. The method of claim 8, wherein, The process of exposing the semiconductor substrate to the ultraviolet (UV) light includes: The semiconductor substrate is exposed to UV radiation in the presence of an oxidizing agent to form hydroxyl groups on the exposed surface of the substrate; and The inhibition layer reacts with these hydroxyl groups to selectively adsorb onto the exposed surface of the underlying layer.

10. The method of claim 5, wherein, The provision of the inhibition layer includes: After depositing and patterning the photoresist film to form the EUV photoresist pattern, the underlying layer is transformed into the inhibition layer.

11. The method of claim 10, wherein, The process of converting the bottom layer into the inhibition layer includes: The semiconductor substrate is exposed to heat treatment, ultraviolet (UV) treatment, or chemical treatment to at least transform the exposed surface of the substrate from a hydrophilic surface with a water contact angle of less than or equal to 60° to a hydrophobic surface with a water contact angle of greater than or equal to 90°.

12. The method of claim 11, wherein, The bottom layer includes Si with the chemical formula Si X O Y C Z N a A carbon nitride silicon oxide layer, wherein 0≤x≤1, 0≤y≤1, 0≤z≤1 and 0≤a≤1.

13. The method of claim 5, wherein, The provision of the inhibition layer includes: During the process of patterning the photoresist film using EUV lithography and forming the EUV photoresist pattern on the underlying layer, the underlying layer is transformed into the inhibition layer.

14. The method of claim 13, wherein, The process of converting the bottom layer into the inhibition layer includes: The semiconductor substrate is exposed to EUV radiation to transform a portion of the underlying layer from a hydrophilic surface with a water contact angle of less than 60° to a hydrophobic surface with a water contact angle of greater than 90°.

15. The method of claim 13, wherein, The bottom layer includes Si with the chemical formula Si X O Y C Z N a A carbon nitride silicon oxide layer, wherein 0≤x≤1, 0≤y≤1, 0≤z≤1 and 0≤a≤1.

16. The method of claim 1, wherein, The bottom layer comprises a hydrophobic material with a water contact angle greater than or equal to 90°.

17. The method of claim 16, further comprising: Prior to depositing the photoresist film, a sacrificial hydrophilic material with a water contact angle of less than or equal to 60° is deposited on the underlying layer; as well as After the EUV photoresist film is patterned using EUV lithography and the EUV photoresist pattern is formed, and before the top coating film is selectively deposited on the EUV photoresist pattern, the portion of the sacrificial hydrophilic material not covered by the EUV photoresist pattern is removed. During the selective deposition of the topcoat film onto the EUV photoresist pattern, the underlayer acts as a suppressor layer to prevent the topcoat film from depositing on exposed surfaces of the underlayer that are not covered by the EUV photoresist pattern.

18. The method of claim 17, wherein, The underlying layer comprises carbon (C) or silicon carbide (SiC), and wherein the sacrificial hydrophilic material comprises amorphous carbon (aC), silicon carbide (SiOC), or oxomethyl (CxOyHz, where 0≤x≤1, 0≤y≤1, and 0≤z≤1).

19. A method for forming an extreme ultraviolet (EUV) photoresist pattern on a semiconductor substrate, the method comprising: A photoresist film is deposited on the underlying layer formed above the semiconductor substrate; The photoresist film is patterned using EUV lithography to form an EUV photoresist pattern on the substrate, wherein the EUV photoresist pattern includes a plurality of photoresist structures having a variable spacing between them. A suppressor layer is selectively deposited on the exposed surface of the underlying layer that is not covered by the EUV photoresist pattern; and A topcoat film is selectively deposited on the EUV photoresist pattern using area selective deposition (ASD), wherein the inhibition layer prevents the topcoat film from depositing on the exposed surface of the underlying layer that is not covered by the EUV photoresist pattern, regardless of the spacing between these photoresist structures.

20. The method of claim 19, wherein, At least one of the photoresist film and the topcoat film contains an organometallic oxide.

21. The method of claim 20, wherein, The organometallic oxide has a central metal atom of tin (Sn), titanium (Ti), zirconium (Zr), indium (In), antimony (Sb), bismuth (Bi), zinc (Zn), hafnium (Hf), aluminum (Al), or a combination thereof.

22. The method of claim 19, wherein, The bottom layer comprises a hydrophilic material having a water contact angle of less than or equal to 60°, and the inhibition layer comprises a hydrophobic material having a water contact angle of greater than or equal to 90°.

23. The method of claim 22, wherein, The underlying layer comprises amorphous carbon (aC), silicon carbide (SiOC), amorphous silicon, or silicon dioxide (SiO2), and wherein the inhibition layer comprises a material having short-chain molecules, a material having methyl, phenyl, or fluorocarbon end groups, and a self-assembled monolayer (SAM) having silane, carboxyl, or phosphonic acid head groups.

24. The method of claim 19, wherein, Prior to the selective deposition of the suppression layer, the method includes: The semiconductor substrate is exposed to ultraviolet (UV) treatment so that the inhibition layer can be selectively adsorbed onto the exposed surface of the underlying layer during the selective deposition of the inhibition layer, rather than onto the EUV photoresist pattern.

25. The method of claim 24, wherein, The process of exposing the semiconductor substrate to the ultraviolet (UV) light includes: The semiconductor substrate is exposed to UV radiation in the presence of an oxidizing agent to form hydroxyl groups on the exposed surface of the substrate; and The inhibition layer reacts with these hydroxyl groups to selectively adsorb onto the exposed surface of the underlying layer.

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