Integrated device coupled to interposer including porous portion

Abstract

A package, the package comprising an interposer, the interposer comprising: a silicon substrate, the silicon substrate comprising a porous portion; and a plurality of via interconnects extending through the porous portion of the silicon substrate. The package includes a first integrated device coupled to an interposer through a first plurality of solder interconnects.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to U.S. Nonprovisional Application Serial No. 18 / 468,533, filed with the U.S. Patent and Trademark Office on September 15, 2023, the entire contents of which are incorporated herein by reference as fully set forth herein and for all applicable purposes. Technical Field

[0003] Various features are involved in the interlayer and substrate of the package. Background Technology

[0004] A package may include a substrate and integrated devices. These components are coupled together to provide a package capable of performing various electrical functions. The performance of the package and its components may depend on the number and / or density of interconnects that can be provided in the integrated devices, interposers, substrate, and / or package. There is a ongoing need to provide packages with higher density interconnects and / or more interconnects in a given area. Summary of the Invention

[0005] Various features are involved in the interlayer and substrate of the package.

[0006] One example provides a package including an interposer layer comprising: a silicon substrate including a porous portion; and a plurality of via interconnects extending through the porous portion of the silicon substrate. The package includes a first integrated device coupled to the interposer layer via a first plurality of solder interconnects. Attached Figure Description

[0007] The various features, essence, and advantages will become apparent when the detailed description set forth below is understood in conjunction with the accompanying drawings, in which similar reference characters are used for corresponding identification throughout.

[0008] Figure 1 A cross-sectional view of an exemplary package including a substrate and an integrated device is illustrated, the integrated device including a bare die substrate having a porous portion.

[0009] Figure 2 A cross-sectional view of an exemplary package including a substrate and an integrated device is illustrated, the integrated device including a bare die substrate having a porous portion.

[0010] Figure 3 A cross-sectional view of an exemplary package including integrated devices and an interposer layer with porous portions is shown.

[0011] Figure 4A cross-sectional view of an exemplary integrated device including a bare die substrate with porous portions and cavities is shown.

[0012] Figure 5 A close-up view of an exemplary package including a substrate and an integrated device is shown, the integrated device including a bare die substrate with porous portions.

[0013] Figure 6 An exemplary process for manufacturing an intermediate layer having at least one porous portion is illustrated.

[0014] Figure 7 An exemplary flowchart illustrating a method for manufacturing an intermediate layer having at least one porous portion is shown.

[0015] Figures 8A to 8B An exemplary process for manufacturing a package is illustrated, the package including an interposer having at least one porous portion and a plurality of integrated devices.

[0016] Figures 9A to 9F An exemplary process for manufacturing an integrated device including a bare die substrate having porous portions and cavities is illustrated.

[0017] Figure 10 An exemplary flowchart illustrating a method for manufacturing an integrated device comprising a bare die substrate having porous portions and cavities is shown.

[0018] Figure 11 Examples are shown of various electronic devices that can integrate the dies, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages and / or device packages described herein. Detailed Implementation

[0019] In the following description, specific details are set forth to provide a thorough understanding of the various aspects of this disclosure. However, those skilled in the art will understand that these aspects can be practiced without these specific details. For example, circuits may be shown as block diagrams to avoid complicating these aspects with unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail to avoid complicating these aspects of this disclosure.

[0020] This disclosure describes a package including an interposer layer comprising: a silicon substrate including a porous portion; and a plurality of via interconnects extending through the porous portion of the silicon substrate. The package includes a first integrated device coupled to the interposer layer via a first plurality of solder interconnects. The first integrated device may include a die substrate including a porous portion; a plurality of through-substrate vias extending through the porous portion of the die substrate; and a die interconnect portion coupled to the die substrate. The silicon substrate may include a non-porous portion, and the porous portion of the silicon substrate may have a lower density than the non-porous portion of the silicon substrate. In some embodiments, the porous portion includes: a first porous portion having a first density; and a second porous portion having a second density. In some implementations, the first porous portion has a first coefficient of thermal expansion (CTE), and the second porous portion has a second coefficient of thermal expansion (CTE) different from the first CTE. Because the CTE mismatch between the CTE of the plurality of via interconnects and the CTE of the silicon substrate is reduced, using porous portions in the silicon substrate allows for more through-substrate vias in the silicon substrate than would otherwise be possible. More via interconnects mean higher interconnect density, which can potentially improve the performance of the package.

[0021] An exemplary package including integrated devices and an interposer layer with porous portions.

[0022] Figure 1 A cross-sectional view of a package 101 including an interposer layer with porous portions is illustrated. The package 101 includes an interposer layer 102, a substrate 104, integrated devices 100a, 100b, 100c, 103a, 103c, and 103d.

[0023] Substrate 104 may be a package substrate. Substrate 104 is coupled to board 110 via a plurality of solder interconnects 130. Intermediate layer 102 is coupled to substrate 104 via a plurality of solder interconnects 109. Intermediate layer 102 includes silicon substrate 120 and a plurality of interconnects 132. The plurality of interconnects 132 may include a plurality of intermediate layer interconnects. The plurality of interconnects 132 may include a plurality of vias (e.g., via interconnects) and / or pads (e.g., pad interconnects). The plurality of interconnects 132 may include a plurality of interconnects 132a, a plurality of interconnects 132b, a plurality of interconnects 132c, and a plurality of interconnects 132d.

[0024] Integrated device 100a is coupled to the interposer layer 102 via multiple solder interconnects 106a. Integrated device 100b is coupled to the interposer layer 102 via multiple solder interconnects 106b. Integrated device 103c is coupled to the interposer layer 102 via multiple solder interconnects 106c. Integrated device 103d is coupled to the interposer layer 102 via multiple solder interconnects 106d.

[0025] Integrated device 103a is coupled to integrated device 100a via a plurality of solder interconnects 306a. For example, the front side of integrated device 103a is coupled to the back side of integrated device 100a via a plurality of solder interconnects 108a. Integrated device 100c is coupled to integrated device 100b via a plurality of solder interconnects 108b. For example, the back side of integrated device 100c is coupled to the back side of integrated device 100b via a plurality of solder interconnects 108b. In such an example, the plurality of solder interconnects 108b may be coupled to the metallized interconnects of integrated device 100b and the metallized interconnects of integrated device 100c.

[0026] Intermediate layer 102 includes silicon substrate 120. Silicon substrate 120 includes porous portions 130a, 130b, 130c, and 130d. Porous portions 130a, 130b, 130c, and / or 130d may be portions of silicon substrate 120 having different porosities, densities, and / or coefficients of thermal expansion compared to the bulk silicon substrate. Porous portions 130a, 130b, 130c, and / or 130d may be one or more localized portions and / or localized portions of silicon substrate 120. Porous portions of materials as used herein are portions of materials that have been porousned using a porousning process.

[0027] Porous portions 130a, 130b, 130c, and / or 130d can be formed using a porousening process. As will be further described below, porous portions 130a, 130b, 130c, and / or 130d allow for the formation of more vias (e.g., via interconnects) in the silicon substrate 120 while minimizing warpage problems due to the mismatch in the coefficients of thermal expansion (CTE) between the silicon substrate 120 and the plurality of interconnects 132. The plurality of interconnects 123 extend through the porous portions 130a, 130b, 130c, and / or 130d of the silicon substrate 120. However, in some embodiments, the plurality of interconnects 132 may also extend through non-porous portions of the silicon substrate 120.

[0028] At least some of the interconnects 132a may extend through the porous portion 130a. At least some of the interconnects 132b may extend through the porous portion 130b. At least some of the interconnects 132c may extend through the porous portion 130c. At least some of the interconnects 132d may extend through the porous portion 130d.

[0029] The non-porous portion of the silicon substrate 120 may have a coefficient of thermal expansion (CTE) of approximately 2.6 parts per million (ppm / °C). When the multiple interconnects 132 include copper (Cu), the multiple interconnects 132 may have a CTE of approximately 17 ppm / °C. A mismatch between the CTE of the silicon substrate 120 and the CTE of the multiple interconnects 132 means that the area of ​​the multiple interconnects 132 cannot exceed 1% of the area of ​​the silicon substrate 120. Any value greater than 1% may cause warpage problems in the interposer 102. To address the warpage problem and increase the ability of the silicon substrate 120 to have more multiple interconnects 132, the silicon substrate 120 may be processed to include one or more porous portions and / or portions of more holes in the silicon substrate 120. Increasing the porosity of the entire silicon substrate 120 or portions of the silicon substrate 120 makes the porous portions less dense relative to other portions of the silicon substrate 120 or the bulk silicon substrate. Increasing the porosity of a portion of the silicon substrate 120 can also increase the CTE of the porous portion of the silicon substrate 120, thereby reducing the mismatch between the CTE of the porous portion of the silicon substrate 120 and the CTE of the plurality of interconnects 132. The reduced mismatch between the CTE of the porous portion and the CTE of the plurality of interconnects 132 means that more interconnects 132 can be formed and extended in the silicon substrate 120. The number of interconnects 132 that can be formed in the porous portion of the silicon substrate 120 can depend on the porosity of the porous portion. Higher porosity can mean that more through-substrate vias can be formed in the porous portion relative to another porous portion with lower porosity. In some embodiments, one or more porous portions may have a porosity in the range of 30% to 70%. Different porous portions may have different porosities.

[0030] In some implementations, the porosity of a material can be a measure of the voids (e.g., empty spaces) within the material, and is the fraction of void volume to total volume, ranging from 0% to 100%. The porosity of a material can be quantified by measuring the weight of the material before and after porosification. Higher porosity levels result in lower mass density. As an example, the density of bulk silicon (Si) can be approximately 2.33 g / cm³ (g / cc). Silicon with 30% porosity can have a density of approximately 1.63 g / cm³ (g / cc). Silicon with 20% porosity can have a density of approximately 1.86 g / cm³ (g / cc). Silicon with X% porosity can have a density of approximately 2.33 g / cm³ (g / cc). The density is (100-X) / 100. In some embodiments, bulk silicon or an unporous portion of bulk silicon may be referred to as non-porous silicon and / or a non-porous portion of silicon. Additionally, non-porous silicon may sometimes be referred to as bulk silicon. Non-porous silicon may have a density of approximately 2.33 g / cm³ (g / cc). In some embodiments, bulk silicon may be considered to have 0% porosity.

[0031] Porous portions can be formed and / or defined in the silicon substrate 120 using a porousization process. In some embodiments, the porousization process may include immersing the silicon wafer in an electrolyte of a 1:1 mixture of hydrofluoric acid (HF) and ethanol. A platinum rod is then used as the cathode, while the silicon wafer acts as the anode, allowing current to pass through. The substrate is then annealed at 300°C to 400°C to reinforce the microstructure. An HF-resistant etch barrier layer (e.g., silicon nitride) is used for selective (masking) porousization. However, different embodiments may use porousization processes that include different steps, additional steps, and / or other materials.

[0032] In some embodiments, more than 1% (e.g., 1% to 5%, at least 2%) of the surface area of ​​the silicon substrate 120 may be occupied by a plurality of interconnects 132. In some embodiments, the porous portion 130a of the silicon substrate 120 may have a first porosity, the porous portion 130b of the silicon substrate 120 may have a second porosity, the porous portion 130c of the silicon substrate 120 may have a third porosity, and the porous portion 130d of the silicon substrate 120 may have a fourth porosity, wherein the first porosity, the second porosity, the third porosity, and / or the fourth porosity are different. In some embodiments, the porous portion 130a may have a first CTE, the porous portion 130b may have a second CTE, the porous portion 130c may have a third CTE, and the porous portion 130d may have a fourth CTE, wherein the first CTE, the second CTE, the third CTE, and the fourth CTE are different. In some specific implementations, the first CTE, the second CTE, the third CTE, and the fourth CTE may differ from the CTE of the bulk (non-porous) silicon substrate 120.

[0033] In some implementations, the porosity of the porous portion may depend on the integrated device to which it will be coupled to the interconnects located in the porous portion. For example, due to the need for high-density interconnects, an integrated device with high-density interconnects may be configured to be electrically coupled to the interconnects located in a porous portion with relatively high porosity. In another example, an integrated device with relatively low-density interconnects may be configured to be electrically coupled to the interconnects located in a porous portion with relatively low porosity.

[0034] Electrical paths to and / or from integrated device 100a may include at least one solder interconnect from a plurality of solder interconnects 106a and an interconnect from a plurality of interconnects 132a. Electrical paths to and / or from integrated device 100b may include at least one solder interconnect from a plurality of solder interconnects 106b and an interconnect from a plurality of interconnects 132b.

[0035] Electrical paths to and / or from integrated device 103c may include at least one solder interconnect from a plurality of solder interconnects 106c and an interconnect from a plurality of interconnects 132c. Electrical paths to and / or from integrated device 103d may include at least one solder interconnect from a plurality of solder interconnects 106d and an interconnect from a plurality of interconnects 132d.

[0036] Figure 1 An example of an interposer layer including localized porous portions is illustrated. However, in some specific implementations, the entire interposer layer may include porous portions. Figure 2 Package 201 is illustrated, comprising a fully porous interposer. Package 201 includes an interposer 202, a substrate 104, integrated devices 100a, 100b, 100c, 103a, 103c, and 103d. Package 201 is similar to package 101 and can be arranged and configured in a similar manner to package 101. However, the interposer 202 includes a silicon substrate 220, wherein the entire silicon substrate 220 is porous. Thus, porous portions can be included throughout the silicon substrate 220. In some embodiments, the porosity of the silicon substrate 220 may be approximately the same throughout the entire silicon substrate 220. In some embodiments, different portions of the silicon substrate 220 may have different porosities. In some embodiments, the density of the silicon substrate 220 may be approximately the same throughout the entire silicon substrate 220. In some embodiments, different portions of the silicon substrate 220 may have different densities. In some embodiments, the CTE of the silicon substrate 220 may be approximately the same across the entire silicon substrate 220. In some embodiments, different portions of the silicon substrate 220 may have different CTEs.

[0037] In some implementations, the porosity of the porous portion may depend on the integrated device to which it will be coupled to the interconnects located in the porous portion. For example, due to the need for high-density interconnects, an integrated device with high-density interconnects may be configured to be electrically coupled to the interconnects located in the relatively high-porosity porous portion. In another example, an integrated device with relatively low-density interconnects may be configured to be electrically coupled to the interconnects located in the relatively low-porosity porous portion and / or the interconnects located in the non-porous portion of the interposer.

[0038] Figure 3A cross-sectional view of an integrated device 300 including a bare substrate with a porous portion is illustrated. The integrated device 300 includes a bare substrate portion 302, a metallization portion 303, and a bare interconnect portion 304. The bare substrate portion 302 includes a bare substrate 320, an active region 308, and a plurality of through-substrate vias 323. The active region 308 may include a plurality of logic cells, a plurality of transistors, and / or a plurality of filters. Different embodiments may use different types of transistors, such as field-effect transistors (FETs), planar FETs, fin FETs, and gate-all-around FETs. In some embodiments, a front-end processing (FEOL) process may be used to fabricate the active region 308 of the bare substrate 320. The bare substrate 320 may include silicon. The plurality of through-substrate vias 323 may extend through the bare substrate 320. The metallization portion 303 includes at least one dielectric layer 330 and a plurality of metallized interconnects 332. The metallization portion 303 is coupled to the bare substrate portion 302. Multiple metallized interconnects 332 may be coupled to multiple through-substrate vias 323. The metallized portion 303 may be a back-side surface metallized portion. The multiple metallized interconnects 332 may include multiple redistributed interconnects.

[0039] Die interconnect portion 304 includes at least one dielectric layer 340 and a plurality of die interconnects 342. Die interconnect portion 304 is coupled to die substrate portion 302. Die substrate portion 302 is located between metallization portion 303 and die interconnect portion 304. The plurality of die interconnects 342 are coupled to active regions 308 of die substrate portion 302. Die interconnect portion 304 may also include a plurality of pad interconnects 307 and passivation layer 305. A plurality of solder interconnects 306 are coupled to the plurality of pad interconnects 307. In some embodiments, back-end process (BEOL) technology may be used to fabricate die interconnect portion 304.

[0040] In some implementations, electrical paths to and / or from the active region 308 may include at least one die interconnect from a plurality of die interconnects 342, at least one through-substrate via from a plurality of through-substrate vias 323, and at least one metallized interconnect from a plurality of metallized interconnects 333.

[0041] In some implementations, electrical paths to and / or from the active region 308 may include at least one die interconnect from a plurality of die interconnects 342, at least one pad interconnect from a plurality of pad interconnects 307, and at least one solder interconnect from a plurality of solder interconnects 306.

[0042] In some specific implementations, the electrical path between the solder interconnects from the plurality of solder interconnects 306 and the metallized interconnects from the plurality of metallized interconnects 332 may include at least one through-substrate via from the plurality of through-substrate vias 323 and at least one die interconnect from the plurality of die interconnects 342.

[0043] Integrated device 300 may represent any integrated device described in this disclosure, such as integrated device 100a, integrated device 100b, integrated device 100c, integrated device 103a, integrated device 103c and / or integrated device 103d.

[0044] In some implementations, the integrated device may include a bare substrate having at least one porous portion and / or one or more cavities.

[0045] Figure 4 A cross-sectional view of an integrated device 400 including a bare die substrate with porous portions and cavities is illustrated. The integrated device 400 is similar to the integrated device 300 and includes components similar to those in the integrated device 300. The integrated device 400 includes a bare die substrate portion 302, a metallization portion 303, and a bare die interconnect portion 304. The bare die substrate portion 302 includes a bare die substrate 320, an active region 308, a porous portion 422, a plurality of through-substrate vias 323, and a plurality of cavities 423. The plurality of cavities 423 are located in the bare die substrate 320. The plurality of cavities 423 may be located in the porous portion 422. The plurality of cavities 423 may have different depths and / or may have the same depth. The porous portion 422 may be a porous portion of the bare die substrate 320 (e.g., a porous portion of the bare die substrate).

[0046] The bare substrate 320 may include silicon (Si). The bare substrate 320 may include a porous portion 422. The bare substrate 320 may include bulk silicon, which includes the porous portion 422. The porous portion 422 may be a part of the bare substrate 320 having a different porosity, different density, and / or different coefficient of thermal expansion than the bulk silicon. The porous portion 422 may be a localized portion and / or a localized portion of the bare substrate 320. A porousization process may be used to form the porous portion 422. As will be further described below, the porous portion 422 allows for the formation of more through-substrate vias in the bare substrate 320 while minimizing warpage problems due to the mismatch in the coefficient of thermal expansion (CTE) of the bare substrate 320 and the plurality of through-substrate vias 323. The plurality of through-substrate vias 323 extend through the porous portion 422 of the bare substrate 320. However, in some embodiments, the plurality of through-substrate vias 323 may also extend through a non-porous portion of the bare substrate 320. The plurality of through-substrate vias 323 includes a first plurality of through-substrate vias 323a and a second plurality of through-substrate vias 323b. The first plurality of through-substrate vias 323a extend through the porous portion 422 of the die substrate 320. The second plurality of through-substrate vias 323b extend through the non-porous portion of the die substrate 320 (e.g., the body portion of the die substrate 320). The term "non-porous portion" means a portion of the die substrate 320 that has not yet undergone a porousing process to increase the porosity of the die substrate.

[0047] It should be noted that the porous portion 422 may include a plurality of porous portions. Therefore, the bare die substrate 320 may include a first porous portion, a second porous portion, a third porous portion, etc. Thus, the bare die substrate 320 may include multiple porous portions. Each porous portion may include a plurality of through-substrate vias extending through the corresponding porous portion. The size of each porous portion may vary depending on the specific implementation.

[0048] When the die substrate portion 302 comprises silicon, the non-porous portion of the die substrate 320 may have a coefficient of thermal expansion (CTE) of approximately 2.6 parts per million (ppm / °C). When the plurality of through-substrate vias 323 comprise copper (Cu), the plurality of through-substrate vias 323 may have a coefficient of thermal expansion (CTE) of approximately 17 parts per million (ppm / °C). A mismatch between the CTE of the die substrate 320 and the CTE of the plurality of through-substrate vias 323 means that the area of ​​the plurality of through-substrate vias 323 cannot exceed 1% of the area of ​​the die substrate 320. Any value greater than 1% may cause warpage problems in the integrated device 400. To address the warpage problem and increase the ability of the die substrate 320 to have more through-substrate vias 323, the die substrate 320 may be processed to include one or more porous portions and / or portions of the die substrate 320 with more holes. Increasing the porosity of the entire die substrate (e.g., 320) or portions of die substrate 320 makes the porous portions less dense relative to other portions of die substrate 320 or the bulk die substrate. Increasing the porosity of a portion of die substrate 320 also increases the CTE of the porous portion of die substrate 320, thereby reducing the mismatch between the CTE of the porous portion of die substrate 320 and the CTE of the plurality of through-substrate vias 323. The reduced mismatch between the CTE of the porous portion and the CTE of the plurality of through-substrate vias 323 means that more through-substrate vias 323 can be formed and extended in die substrate 320. The number of through-substrate vias 323 that can be formed in the porous portion of die substrate 320 may depend on the porosity of the porous portion. Higher porosity may mean that more through-substrate vias can be formed in the porous portion relative to another porous portion having lower porosity. In some embodiments, one or more porous portions may have a porosity in the range of 30% to 70%. Different porous sections can have different porosities.

[0049] Providing multiple cavities 423 in the die substrate 320 effectively reduces the overall density of the die substrate 320 and increases the effective CTE of the die substrate 320. This, in turn, helps to reduce the CTE mismatch between the CTE of the die substrate 320 and the CTE of the multiple through-substrate vias 323. Thus, more through-substrate vias 323 can be formed and / or provided in the die substrate 320, thereby enabling a higher number of interconnects in the integrated device 400. It should be noted that forming multiple cavities 423 in the die substrate 320 is different from forming porous portions in the die substrate 320.

[0050] Integrated device 400 may represent any integrated device described in this disclosure, such as integrated device 100a, integrated device 100b, integrated device 100c, integrated device 103a, integrated device 103c, and / or integrated device 103d. In some embodiments, power to the integrated device may travel through the back side of the integrated device. For example, power for integrated device 300 and / or integrated device 400 may travel through an electrical path including a plurality of metallized interconnects 332, a plurality of through-substrate vias 323, and / or a plurality of die interconnects 342. In some embodiments, power for integrated device 300 and / or integrated device 400 may travel through an electrical path including solder interconnects from a plurality of solder interconnects 306, pad interconnects from a plurality of pad interconnects 307, and / or die interconnects from a plurality of die interconnects 342. The front side of the integrated device (e.g., 300, 400) may include a side containing a plurality of pad interconnects 107. The back side of an integrated device (e.g., 300, 400) may include a side containing a bare die substrate 320 and / or a metallized portion 303.

[0051] Figure 5 Examples Figure 1 A close-up view of the package 101. (See attached image.) Figure 5 As shown, the front side of integrated device 103 is coupled to the back side of integrated device 400 via a plurality of solder interconnects 108. The plurality of solder interconnects 108 are coupled to pad interconnects of integrated device 103 and metallized interconnects 432 from the metallized portion 303 of integrated device 400. Integrated device 400 is coupled to interposer 102 via a plurality of solder interconnects 106a. The plurality of solder interconnects 106a are coupled to and contact a plurality of pad interconnects 107 and a plurality of interconnects 132a.

[0052] The electrical path between integrated device 103 and integrated device 400 may include pad interconnects from multiple pad interconnects of integrated device 103, solder interconnects from multiple solder interconnects 108, and metallized interconnects from multiple metallized interconnects 332 of integrated device 400.

[0053] Integrated devices (e.g., 300, 400) may include dies (e.g., semiconductor dies). Integrated devices may include power management integrated circuits (PMICs). Integrated devices may include application processors. Integrated devices may include modems. Integrated devices may include radio frequency (RF) devices, passive devices, filters, capacitors, inductors, antennas, transmitters, receivers, gallium arsenide (GaAs) based integrated devices, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light-emitting diode (LED) integrated devices, silicon (Si) based integrated devices, silicon carbide (SiC) based integrated devices, memories, power management processors, and / or combinations thereof. Integrated devices may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). Integrated devices may include input / output (I / O) hubs. Integrated devices may include transistors. Integrated devices may be examples of electronic components and / or electronic devices.

[0054] In some embodiments, the integrated device may be a chiplet. Chipslets can be manufactured using processes that offer better yields compared to other processes used to manufacture other types of integrated devices, which can reduce the overall cost of manufacturing chiplets. Different chiplets may have different sizes and / or shapes. Different chiplets may be configured to provide different functions. Different chiplets may have different interconnect densities (e.g., interconnects with different widths and / or pitches). In some embodiments, several chiplets may be used to perform the functionality of one or more chips (e.g., one or more integrated devices). As mentioned above, using several chiplets performing several functions reduces the overall cost of the package compared to using a single chip to perform all the functions of the package. In some embodiments, one or more chiplets and / or one or more integrated devices (e.g., 100) of the chiplets described in this disclosure may be manufactured using the same technology node or two or more different technology nodes. For example, an integrated device may be manufactured using a first technology node, and a chiplet may be manufactured using a second technology node that is less advanced than the first technology node. In such examples, the integrated device may include components (e.g., interconnects, transistors) having a first minimum size, and the chiplet may include components (e.g., interconnects, transistors) having a second minimum size, wherein the second minimum size is larger than the first minimum size. In some embodiments, the first and second integrated devices of the package may be manufactured using the same or different technology nodes. In some embodiments, the chiplets and another chiplet of the package may be manufactured using the same or different technology nodes.

[0055] A technology node can refer to a specific manufacturing process and / or technology used to manufacture integrated devices and / or chiplets. A technology node can specify the minimum possible size that can be manufactured (e.g., minimum size) (e.g., transistor size, trace width, gap between two transistors). Different technology nodes may have different yield losses. Different technology nodes may have different costs. Technology nodes for components with finer manufacturing details are more expensive and may have higher yield losses compared to technology nodes for components with less fine manufacturing details (e.g., traces, transistors). Therefore, more advanced technology nodes may be more expensive and may have higher yield losses compared to less advanced technology nodes. When all functions of a package are implemented in a single integrated device, the same technology node is used to manufacture the entire integrated device, even if some functions of the integrated device do not require that specific technology node to be used. Therefore, the integrated device is locked to a single technology node. To optimize the cost of the package, some functions can be implemented in different integrated devices and / or chiplets, where different technology nodes can be used to manufacture different integrated devices and / or chiplets to reduce the overall cost. For example, functionality requiring state-of-the-art technology nodes can be implemented in an integrated device, while functionality achievable with less advanced technology nodes can be implemented in another integrated device and / or one or more chiplets. An example would be an integrated device manufactured using a first technology node (e.g., a more advanced technology node) and configured to provide computing applications, and at least one chiplet manufactured using a second technology node and configured to provide additional functionality, wherein the second technology node is less expensive than the first technology node, and wherein the second technology node manufactures a component with a minimum size larger than the minimum size of a component manufactured using the first technology node. Examples of computing applications could include high-performance computing and / or high-performance processing, which can be achieved by manufacturing and packing as many transistors as possible into the integrated device. This is why the integrated device configured for computing applications can be manufactured using the most advanced available technology nodes, while other chiplets can be manufactured using less advanced technology nodes, as these chiplets may not require as many transistors to be manufactured in the chiplet. Therefore, using a combination of different technology nodes (which may have different associated yield losses) for different integrated devices and / or chiplets can reduce the overall cost of the package compared to using a single integrated device to perform all the functions of the package.

[0056] Another advantage of dividing functionality into several integrated devices and / or chiplets is that it allows for improvements in package performance without having to redesign each individual integrated device and / or chiplet. For example, if a package configuration uses a first integrated device and a first chiplet, it may be possible to improve package performance by changing the design of the first integrated device while keeping the design of the first chiplet unchanged. Therefore, the first chiplet can be reused along with improved and / or differently configured first integrated devices. This saves costs when manufacturing packages with improved integrated devices because the first chiplet does not need to be redesigned.

[0057] Exemplary process for manufacturing an intermediate layer including porous portions

[0058] In some specific implementations, the manufacturing intermediary layer includes several processes. Figure 6 Exemplary steps for providing or manufacturing an intermediary layer are illustrated. In some specific implementations, Figure 6 The process can be used to provide or manufacture intermediate layer 102. However, Figure 6 The process can be used to manufacture any of the intermediary layers described in this disclosure.

[0059] It should be noted that Figure 6 The processes may be combined in one or more stages to simplify and / or clarify the processes used to provide or manufacture the intermediate layer. In some embodiments, the order of the processes may be changed or modified. In some embodiments, one or more of these processes may be substituted or replaced without departing from the scope of this disclosure.

[0060] like Figure 6 As shown, stage 1 illustrates the state after the silicon substrate 120 has been provided. The silicon substrate 120 may be a silicon block and / or a silicon wafer.

[0061] Stage 2 illustrates the state after one or more porous portions have been formed in the silicon substrate 120. Porous portions can be formed and / or defined in the silicon substrate 120 using a porousening process. In some embodiments, the porousening process may include immersing a silicon wafer in an electrolyte of a 1:1 mixture of hydrofluoric acid (HF) and ethanol. A platinum rod is then used as the cathode, while the silicon wafer acts as the anode, allowing current to pass through. The substrate is then annealed at 300°C to 400°C to strengthen the microstructure. An HF-resistant etch barrier layer (e.g., silicon nitride) is used for selective (masking) porousening. However, different embodiments may use porousening processes that include different steps, additional steps, and / or other materials.

[0062] Phase 2 illustrates porous portions 130a, 130b, 130c, and 130d of the silicon substrate 120. Porous portions 130a, 130b, 130c, and / or 130d may be a portion of the silicon substrate 120 that has a different porosity, density, and / or coefficient of thermal expansion compared to the bulk silicon substrate. In some embodiments, the entire silicon substrate 120 is made porous.

[0063] Stage 3 illustrates the state after forming a plurality of via cavities 620 in the silicon substrate 120. The plurality of via cavities 620 can be formed using a laser ablation process. The plurality of via cavities 620 can be formed in porous portions and / or non-porous portions of the silicon substrate 120.

[0064] Phase 4 illustrates the state after a plurality of interconnects 132 have been formed in the plurality of cavities 620 and on the surface of the silicon substrate 120. A plating process can be used to form the plurality of interconnects 732. Phase 4 may illustrate an interposer 102 comprising the silicon substrate 120, a plurality of porous portions (e.g., 130a, 130b, 130c, 130d), and the plurality of interconnects 132. The plurality of interconnects 132 may include a plurality of interconnects 132a, a plurality of interconnects 132b, a plurality of interconnects 132c, and a plurality of interconnects 132d. A plurality of interconnects 132a may extend through the porous portion 130a. A plurality of interconnects 132b may extend through the porous portion 130b. A plurality of interconnects 132c may extend through the porous portion 130c. A plurality of interconnects 132d may extend through the porous portion 130d. In some embodiments, the plurality of interconnects may extend through non-porous portions of the silicon substrate 120. Some interconnects from multiple interconnects 132a, multiple interconnects 132b, multiple interconnects 132c and / or multiple interconnects 132d may be located on and / or coupled to one or more surfaces of the silicon substrate 120 of the interposer 102. The multiple interconnects 132 may include via interconnects, pad interconnects and / or trace interconnects.

[0065] An exemplary flowchart of a method for manufacturing an intermediate layer with porous portions.

[0066] In some specific implementations, the manufacturing intermediary layer includes several processes. Figure 7 An exemplary flowchart illustrating a method 700 for providing or manufacturing an intermediary layer is shown. In some specific implementations, Figure 7 Method 700 can be used to provide or manufacture the product described in this disclosure. Figure 1 Integrated devices (e.g., 100a, 103a). However, method 700 can be used to provide or manufacture any of the interposers described in this disclosure.

[0067] It should be noted that Figure 7The method may combine one or more processes to simplify and / or clarify the methods used to provide or manufacture the intermediate layer. In some specific implementations, the order of the processes may be changed or modified.

[0068] This method (at 705) provides a silicon substrate. Figure 6 Phase 1 illustrates and describes an example of the state after the silicon substrate 120 is provided. The silicon substrate 120 may be a silicon block and / or a silicon wafer.

[0069] This method (at 710) forms one or more porous portions in a silicon substrate. Figure 6 Stage 2 illustrates and describes an example of the state following the formation of one or more porous portions in the silicon substrate 120. Porous portions can be formed and / or defined in the silicon substrate 120 using a porousening process. In some embodiments, the porousening process may include immersing a silicon wafer in an electrolyte of a 1:1 mixture of hydrofluoric acid (HF) and ethanol. A platinum rod is then used as the cathode, while the silicon wafer acts as the anode, allowing current to pass through. The substrate is then annealed at 300°C to 400°C to reinforce the microstructure. An HF-resistant etch barrier layer (e.g., silicon nitride) is used for selective (masking) porousening. However, different embodiments may use porousening processes that include different steps, additional steps, and / or other materials. Stage 2 illustrates porous portions 130a, 130b, 130c, and 130d of the silicon substrate 120. Porous portions 130a, 130b, 130c, and / or 130d may be portions of the silicon substrate 120 that have different porosities, densities, and / or coefficients of thermal expansion compared to the bulk silicon substrate. In some embodiments, the entire silicon substrate 120 is made porous.

[0070] This method (at 715) forms a via cavity in a silicon substrate. Figure 6 Stage 3 illustrates and describes an example of the state after forming a plurality of via cavities 620 in the silicon substrate 120. The plurality of via cavities 620 can be formed using a laser ablation process. The plurality of via cavities 620 can be formed in porous portions and / or non-porous portions of the silicon substrate 120.

[0071] The method (at 720) forms vias (e.g., via interconnects) in a silicon substrate and forms interconnects (e.g., pad interconnects) on the silicon substrate. Figure 6Phase 4 illustrates and describes an example of the state following the formation of a plurality of interconnects 132 (e.g., via interconnects, pad interconnects) in a plurality of cavities 620 and on the surface of silicon substrate 120. A plating process can be used to form the plurality of interconnects 732. Phase 4 may illustrate an interposer 102 comprising silicon substrate 120, a plurality of porous portions (e.g., 130a, 130b, 130c, 130d), and a plurality of interconnects 132. The plurality of interconnects 132 may include a plurality of interconnects 132a, a plurality of interconnects 132b, a plurality of interconnects 132c, and a plurality of interconnects 132d. A plurality of interconnects 132a may extend through porous portion 130a. A plurality of interconnects 132b may extend through porous portion 130b. A plurality of interconnects 132c may extend through porous portion 130c. A plurality of interconnects 132d may extend through porous portion 130d. In some implementations, multiple interconnects may extend through non-porous portions of the silicon substrate 120. Some interconnects from multiple interconnects 132a, multiple interconnects 132b, multiple interconnects 132c and / or multiple interconnects 132d may be located on and / or coupled to one or more surfaces of the silicon substrate 120 of the interposer 102.

[0072] Exemplary process for manufacturing a package including an integrated device and an interposer layer with porous portions.

[0073] In some specific implementations, manufacturing the package involves several processes. Figures 8A to 8B Exemplary steps for providing or manufacturing a package including an interposer and integration are illustrated. In some specific implementations, Figures 8A to 8B The process can be used to provide or manufacture package 101. However, Figures 8A to 8B The process can be used to manufacture any of the packages described in this disclosure.

[0074] It should be noted that Figures 8A to 8B The processes can be combined in one or more stages to simplify and / or clarify the processes used to provide or manufacture the package. In some embodiments, the order of the processes can be changed or modified. In some embodiments, one or more of these processes can be substituted or replaced without departing from the scope of this disclosure.

[0075] like Figure 8A As shown, stage 1 illustrates the state after the interposer 102 has been provided. The interposer 102 may include a silicon substrate 120, a number of porous portions (e.g., 130a, 130b, 130c, 130d) and a number of interconnects 132.

[0076] Phase 2 illustrates the state after multiple integrated devices are coupled to the interposer 102. Multiple solder interconnects (e.g., 106a, 106b, 106c, 106d) can be used to couple integrated devices (e.g., 100a, 100b, 103c, 103d) to multiple interconnects 132 of the interposer 102. A solder reflow process can be used to form the integrated devices and couple them to the multiple interconnects 132 of the interposer 102.

[0077] like Figure 8B As shown, stage 3 illustrates the state after the interposer 102 is coupled to the substrate 104 by a plurality of solder interconnects 109. The plurality of solder interconnects 109 can be formed using a solder reflow process and coupled to (i) a plurality of interconnects 142 of the substrate 104 and (ii) a plurality of interconnects 132 of the interposer 102.

[0078] Phase 4 illustrates the state after the multiple solder interconnects 130 are coupled to the substrate 104. A solder reflow process can be used to couple the multiple solder interconnects 130 to the multiple interconnects 142 of the substrate 104.

[0079] Exemplary process for manufacturing an integrated device including a bare die substrate with porous portions.

[0080] In some specific implementations, manufacturing integrated devices involves several processes. Figures 9A to 9F Exemplary steps for providing or manufacturing an integrated device comprising a bare die substrate having porous portions and cavities are illustrated. In some specific embodiments, Figures 9A to 9F The process can be used to provide or manufacture integrated device 400. However, Figures 9A to 9F The process can be used to manufacture any integrated device described in this disclosure.

[0081] It should be noted that Figures 9A to 9F The processes can be combined in one or more stages to simplify and / or clarify the processes used to provide or manufacture integrated devices. In some embodiments, the order of the processes can be changed or modified. In some embodiments, one or more of these processes can be substituted or replaced without departing from the scope of this disclosure.

[0082] like Figure 9AAs shown, Phase 1 illustrates the state after the integrated device is provided and / or manufactured. The integrated device 400 may include a die substrate portion 302 and a die interconnect portion 304. The die substrate portion 302 includes a die substrate 320 and an active region 308. The die interconnect portion 304 includes at least one dielectric layer 340, a plurality of die interconnects 342, a plurality of pad interconnects 307, and a passivation layer 305. In some embodiments, the front side of the integrated device 400 may include a side containing the passivation layer 305 and / or the plurality of pad interconnects 307. In some embodiments, the back side of the integrated device 400 may include a side containing the die substrate 320.

[0083] Phase 2 illustrates the state after the integrated device 400 is coupled to the carrier 900. The carrier 900 may be a strip. The carrier may include an adhesive. The front side of the integrated device 400 may be coupled to and in contact with the carrier 900. For example, a passivation layer 305 and / or multiple pad interconnects 307 may be coupled to and in contact with the carrier 900.

[0084] like Figure 9B As shown, stage 3 illustrates the state after the porous portion 422 has been formed in the bare die substrate 320. In some embodiments, more than one porous portion may be formed. The porous portion 422 may have a lower density than other portions of the bare die substrate 320. The bare die substrate 320 may include silicon. In some embodiments, more than one porous portion may be formed in the bare die substrate 320. In some embodiments, the porous portions may have different thicknesses.

[0085] Porous portions can be formed and / or defined in the bare substrate 320 using a porousization process. In some embodiments, the porousization process may include immersing a silicon wafer in an electrolyte of a 1:1 mixture of hydrofluoric acid (HF) and ethanol. A platinum rod is then used as the cathode, while the silicon wafer acts as the anode, allowing current to pass through. The substrate is then annealed at 300°C to 400°C to reinforce the microstructure. An HF-resistant etch barrier layer (e.g., silicon nitride) is used for selective (masking) porousization. However, different embodiments may use porousization processes that include different steps, additional steps, and / or other materials.

[0086] Different porous portions may have the same porosity or different porosities. As a result of the porousification process, the porous portions may have different coefficients of thermal expansion (e.g., different from other porous portions, different from the non-porous portions of the bare substrate 320). The porousification process can change the density of the porous portions. In some specific embodiments, one or more porous portions 422 may have a porosity in the range of about 30% to 70%.

[0087] Stage 4 illustrates the state after a plurality of via cavities 923 have been formed in the die substrate 320. The plurality of via cavities 923 may include a first plurality of via cavities 923a and a second plurality of via cavities 923b. The first plurality of via cavities 923a may be formed through a porous portion 422 of the die substrate 320. The second plurality of via cavities 923b may be formed through a body portion of the die substrate 320 (e.g., a non-porous portion of the die substrate 320). A laser process (e.g., laser ablation) may be used to form the plurality of via cavities 923. In some embodiments, the plurality of via cavities 923 may extend into the die interconnect portion 304.

[0088] like Figure 9C As shown, stage 5 illustrates the state after the formation of a plurality of through-substrate vias 323. A plating process can be used to form the plurality of substrate vias 323. The plurality of through-substrate vias 323 may include a first plurality of through-substrate vias 323a and a second plurality of through-substrate vias 323b. The first plurality of through-substrate vias 323a may be formed in a first plurality of via cavities 923a. The first plurality of through-substrate vias 323a may extend through the porous portion 422 of the die substrate 320. The second plurality of through-substrate vias 323b may be formed in a second plurality of via cavities 923b. The second plurality of through-substrate vias 323b may extend through the non-porous portion of the die substrate 320. In some embodiments, the plurality of through-substrate vias 323 may extend into the die interconnect portion 304. The plurality of through-substrate vias 323 may be coupled to a plurality of die interconnects 342.

[0089] Stage 6 illustrates the state after a plurality of cavities 423 have been formed in the bare die substrate 320. The plurality of cavities 423 can be formed using a laser process (e.g., laser ablation). The plurality of cavities 423 may have the same depth or different depths. The plurality of cavities 423 may extend through the porous portion 422 and / or non-porous portion of the bare die substrate 320.

[0090] like Figure 9D As shown, stage 7 illustrates the state after a plurality of metallized interconnects 932 have been formed on the back surface of the bare die substrate 320. A plating process can be used to form the plurality of metallized interconnects 932. The plurality of metallized interconnects 932 can be coupled to a plurality of through-substrate vias 323.

[0091] Stage 8 illustrates the state after the dielectric layer 330 has been formed and coupled to the back surface of the bare substrate 320. The dielectric layer 330 may include a plurality of cavities 943. The dielectric layer 330 and the plurality of cavities 941 may be formed and / or provided using deposition processes, lamination processes, exposure processes and / or development processes.

[0092] like Figure 9EAs shown, stage 9 illustrates the state after the formation of multiple metallized interconnects 942. The multiple metallized interconnects 942 can be coupled to multiple metallized interconnects 932. A plating process can be used to form multiple metallized interconnects 934. The multiple metallized interconnects 932 and / or the multiple metallized interconnects 942 can be represented as multiple metallized interconnects 332.

[0093] Phase 10 illustrates the state after the carrier 900 is decoupled from the integrated device 400. The carrier 900 can be separated from and / or detached from the integrated device 400.

[0094] like Figure 9F As shown, stage 11 illustrates the state after multiple solder interconnects 306 are coupled to multiple pad interconnects 307. A solder reflow process can be used to form the multiple solder interconnects 306 and couple them to the multiple pad interconnects 307.

[0095] Flowchart of a method for manufacturing an integrated device including a bare die substrate with porous portions.

[0096] In some specific implementations, manufacturing integrated devices involves several processes. Figure 10 An exemplary flowchart illustrating a method 1000 for providing or manufacturing an integrated device is shown. In some specific implementations, Figure 10 Method 1000 can be used to provide or manufacture the product described in this disclosure. Figure 4 The integrated device 400. However, method 1000 can be used to provide or manufacture any integrated device described in this disclosure.

[0097] It should be noted that Figure 10 The method may combine one or more processes to simplify and / or clarify the methods used to provide or manufacture integrated devices. In some specific implementations, the order of the processes may be changed or modified.

[0098] The method (at 1005) provides an integrated device comprising a bare die substrate, a bare die interconnect portion, and a plurality of pads. Figure 9A Phase 1 illustrates and describes the state after the integrated device is provided and / or manufactured. The integrated device 400 may include a die substrate portion 302 and a die interconnect portion 304. The die substrate portion 302 includes a die substrate 320 and an active region 308. The die interconnect portion 304 includes at least one dielectric layer 340, a plurality of die interconnects 342, a plurality of pad interconnects 307, and a passivation layer 305. In some embodiments, the front side of the integrated device 400 may include a side containing the passivation layer 305 and / or the plurality of pad interconnects 307. In some embodiments, the back side of the integrated device 400 may include a side containing the die substrate 320.

[0099] This method (at 1010) couples the integrated device to the carrier. Figure 9A Phase 2 illustrates and describes an example of the state after the integrated device 400 is coupled to the carrier 900. The carrier 900 may be a strip. The carrier may include an adhesive. The front side of the integrated device 400 may be coupled to and in contact with the carrier 900. For example, a passivation layer 305 and / or multiple pad interconnects 307 may be coupled to and in contact with the carrier 900.

[0100] This method (at 1015) forms a porous portion in the bare die substrate. Figure 9B Stage 3 illustrates and describes an example of the state after at least one porous portion 422 has been formed in the bare die substrate 320. The porous portion 422 may have a lower density than other portions of the bare die substrate 320. The bare die substrate 320 may include silicon. In some embodiments, more than one porous portion may be formed in the bare die substrate 320. In some embodiments, the porous portions may have different thicknesses.

[0101] Porous portions can be formed and / or defined in the bare substrate 320 using a porousization process. In some embodiments, the porousization process may include immersing a silicon wafer in an electrolyte of a 1:1 mixture of hydrofluoric acid (HF) and ethanol. A platinum rod is then used as the cathode, while the silicon wafer acts as the anode, allowing current to pass through. The substrate is then annealed at 300°C to 400°C to reinforce the microstructure. An HF-resistant etch barrier layer (e.g., silicon nitride) is used for selective (masking) porousization. However, different embodiments may use porousization processes that include different steps, additional steps, and / or other materials.

[0102] Different porous portions may have the same porosity or different porosities. As a result of the porousification process, the porous portions may have different coefficients of thermal expansion (e.g., different from other porous portions, different from the non-porous portions of the bare substrate 320). The porousification process can change the density of the porous portions. In some specific embodiments, one or more porous portions 422 may have a porosity in the range of about 30% to 70%.

[0103] The method (at 1020) forms a plurality of through-substrate vias in the die substrate, including a plurality of through-substrate vias passing through a porous portion of the die substrate 320. Forming the plurality of through-substrate vias may include forming a plurality of via cavities in the die substrate 320.

[0104] Figure 9BStage 4 illustrates and describes an example of the state after forming a plurality of via cavities 923 in the die substrate 320. The plurality of via cavities 923 may include a first plurality of via cavities 923a and a second plurality of via cavities 923b. The first plurality of via cavities 923a may be formed through a porous portion 422 of the die substrate 320. The second plurality of via cavities 923b may be formed through a body portion of the die substrate 320 (e.g., a non-porous portion of the die substrate 320). A laser process (e.g., laser ablation) may be used to form the plurality of via cavities 923. In some embodiments, the plurality of via cavities 923 may extend into the die interconnect portion 304.

[0105] Figure 9C Stage 5 illustrates and describes an example of the state after the formation of a plurality of through-substrate vias 323. A plating process can be used to form the plurality of substrate vias 323. The plurality of through-substrate vias 323 may include a first plurality of through-substrate vias 323a and a second plurality of through-substrate vias 323b. The first plurality of through-substrate vias 323a may be formed in a first plurality of via cavities 923a. The first plurality of through-substrate vias 323a may extend through the porous portion 422 of the die substrate 320. The second plurality of through-substrate vias 323b may be formed in a second plurality of via cavities 923b. The second plurality of through-substrate vias 323b may extend through the non-porous portion of the die substrate 320. In some embodiments, the plurality of through-substrate vias 323 may extend into the die interconnect portion 304. The plurality of through-substrate vias 323 may be coupled to a plurality of die interconnects 342.

[0106] The method (at 1025) may optionally form multiple cavities in the bare die substrate. Figure 9C Stage 6 illustrates and describes an example of the state after forming a plurality of cavities 223 in the bare die substrate 320. The plurality of cavities 223 can be formed using a laser process (e.g., laser ablation). The plurality of cavities 223 may have the same depth or different depths. The plurality of cavities 223 may extend through the porous portion 422 and / or non-porous portion of the bare die substrate 320.

[0107] The method (at 1030) forms a metallized portion (e.g., 303) coupled to the back side of a bare die substrate portion (e.g., 302). Forming the metallized portion may include forming at least one dielectric layer and a plurality of metallized interconnects. Figure 9D Stage 7 illustrates and describes an example of the state after a plurality of metallized interconnects 932 have been formed on the back surface of the bare die substrate 320. A plating process can be used to form the plurality of metallized interconnects 932. The plurality of metallized interconnects 932 can be coupled to a plurality of through-substrate vias 323.

[0108] Figure 9DStage 8 illustrates and describes an example of the state after the dielectric layer 330 has been formed and coupled to the back surface of the bare substrate 320. The dielectric layer 330 may include a plurality of cavities 941. The dielectric layer 330 and the plurality of cavities 941 may be formed and / or provided using deposition processes, lamination processes, exposure processes and / or development processes.

[0109] Figure 9E Stage 9 illustrates and describes an example of the state after the formation of multiple metallized interconnects 942. Multiple metallized interconnects 942 may be coupled to multiple metallized interconnects 932. A plating process may be used to form multiple metallized interconnects 934. Multiple metallized interconnects 932 and / or multiple metallized interconnects 942 may be represented as multiple metallized interconnects 332.

[0110] This method (at 1035) decouples the carrier from the integrated device. Figure 9E Phase 10 illustrates and describes an example of the state after the carrier 900 is decoupled from the integrated device 400. The carrier 900 can be separated from and / or detached from the integrated device 400.

[0111] This method (at 1040) couples multiple solder interconnects to an integrated device. Figure 9F Phase 11 illustrates and describes an example of the state after multiple solder interconnects 306 are coupled to multiple pad interconnects 307. A solder reflow process can be used to form the multiple solder interconnects 306 and couple them to the multiple pad interconnects 307.

[0112] Exemplary electronic devices

[0113] Figure 11 Examples are illustrated of various electronic devices that may integrate any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, stacked packages (PoP), system-in-packages (SiP), or system-on-a-chip (SoC). For example, mobile phone device 1102, laptop computer device 1104, fixed-location terminal device 1106, wearable device 1108, or motor vehicle 1110 may include device 1100 as described herein. For example, device 1100 may be any of the devices and / or integrated circuit (IC) packages described herein. Figure 11The illustrated devices 1102, 1104, 1106, and 1108, as well as vehicle 1110, are merely exemplary. Other electronic devices may also feature device 1100, including but not limited to devices comprising, for example, the following group of devices (e.g., electronic devices): mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading devices), communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0114] Figures 1 to 7 , Figures 8A to 8B , Figures 9A to 9F And / or Figures 10 to 11 One or more of the components, processes, features, and / or functions illustrated herein may be rearranged and / or combined into a single component, process, feature, or function, or embodied in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from this disclosure. It should also be noted that... Figures 1 to 7 , Figures 8A to 8B , Figures 9A to 9F And / or Figures 10 to 11 The corresponding descriptions herein are not limited to bare dies and / or ICs. In some specific implementations, Figures 1 to 7 , Figures 8A to 8B , Figures 9A to 9F And / or Figures 10 to 11 The descriptions and their corresponding information can be used to manufacture, create, supply, and / or produce devices and / or integrated devices. In some specific implementations, the equipment may include dies, integrated devices, integrated passive devices (IPDs), die packages, integrated circuit (IC) devices, device packages, integrated circuit (IC) packages, wafers, semiconductor devices, stacked package (PoP) devices, thermal devices, and / or interposers.

[0115] It should be noted that the accompanying drawings in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some instances, the drawings may not be to scale. In some instances, not all components and / or parts are shown for clarity. In some instances, the positioning, location, size, and / or shape of the various parts and / or components in the drawings may be exemplary. In some specific embodiments, the various components and / or parts in the drawings may be optional.

[0116] The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any specific implementation or aspect described herein as “exemplary” is not necessarily to be construed as superior to or better than other aspects of this disclosure. Similarly, the term “aspect” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term “coupled” is used herein to refer to direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, objects A and C can still be considered coupled to each other, even if they are not in direct physical contact. An object coupled to another object may be coupled to at least a portion of another object. The term “electrically coupled” may mean that two objects are directly or indirectly coupled together such that current (e.g., signal, power, ground) can travel between the two objects. Electrically coupled objects may or may not have current traveling between them. The use of the terms “first,” “second,” “third,” and “fourth” (and / or anything above the fourth) is arbitrary. Any component described can be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component can be a first component, a second component, a third component, or a fourth component. The term "enclosing" means that an object can partially enclose or completely enclose another object. A first component "located" within a second component can mean that the first component is "partially located" within or "completely located" within the second component. A first component "embedded" within a second component can mean that the first component is "partially embedded" within or "completely embedded" within the second component. The terms "top" and "bottom" are arbitrary. A component located at the top can be above a component located at the bottom. A top component can be considered a bottom component, and vice versa. As described in this disclosure, a first component located "above" a second component can mean that the first component is located above or below the second component, depending on how bottom or top is arbitrarily defined. In another example, a first component can be located above (e.g., above) a first surface of a second component, and a third component can be located above (e.g., below) a second surface of a second component, where the second surface is opposite to the first surface. It should also be noted that the term "on top of" as used in this application in the context of one component being on top of another component can be used to mean that a component is on and / or in another component (e.g., on the surface of a component or embedded in a component). Thus, for example, "first component on top of second component" can mean: (1) the first component is on top of the second component but does not directly contact the second component; (2) the first component is on the second component (e.g., on the surface of the second component); and / or (3) the first component is in the second component (e.g., embedded in the second component). A first component "in" the second component can be partially or entirely located within the second component.As used in this disclosure, the terms "about 'value X'" or "approximately value X" mean within 10% of "value X". For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9 to 1.1. "A plurality of" components may include all possible components or only some of all possible components. For example, if the device comprises ten components, the use of the term "a plurality of components" may refer to all ten components or only some of those ten components.

[0117] In some embodiments, an interconnect is an element or assembly in a device or package that allows or facilitates an electrical connection between two points, elements, and / or components. In some embodiments, an interconnect may include traces, vias, pads, pillars, metallization layers, redistribution layers, and / or under-bump metallization (UBM) layers / interconnects. In some embodiments, an interconnect may include a conductive material configured to provide an electrical path for signals (e.g., data signals), ground, and / or power. An interconnect may include more than one element or assembly. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different embodiments may use different processes and / or steps to form interconnects. In some embodiments, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spraying, and / or plating processes may be used to form interconnects.

[0118] It should also be noted that the various disclosures contained herein can be described as processes depicted as work diagrams, flowcharts, structural diagrams, or block diagrams. Although flowcharts may describe operations as sequential processes, many operations within an operation can be performed in parallel or concurrently. Furthermore, the order of operations can be rearranged. The process terminates when its operations are completed.

[0119] Further examples are described below to facilitate understanding of the invention.

[0120] Aspect 1: A package comprising an interposer and a first integrated device coupled to the interposer via a first plurality of solder interconnects. The interposer comprises: a silicon substrate including a porous portion; and a plurality of via interconnects extending through the porous portion of the silicon substrate.

[0121] Aspect 2: The package according to aspect 1, wherein the silicon substrate includes a non-porous portion, and wherein the porous portion of the silicon substrate has a lower density than the non-porous portion of the silicon substrate.

[0122] Aspect 3: The package according to aspects 1 to 2, wherein the porous portion has a coefficient of thermal expansion (CTE) in the range of about 5 parts per million degrees Celsius (ppm / C) to 8 parts per million degrees Celsius (ppm / C).

[0123] Aspect 4: The package according to aspects 1 to 3, wherein the porous portion includes a first porous portion having a first density; and a second porous portion having a second density.

[0124] Aspect 5: The package according to aspect 4, wherein the first porous portion has a first coefficient of thermal expansion (CTE), and wherein the second porous portion has a second coefficient of thermal expansion (CTE).

[0125] Aspect 6: The package according to aspect 5, wherein the silicon substrate includes a non-porous portion having a third coefficient of thermal expansion (CTE) different from the first coefficient of thermal expansion (CTE) and the second coefficient of thermal expansion (CTE).

[0126] Aspect 7: The package according to aspects 1 to 6, wherein the porous portion has a porosity in the range of about 30% to 70%.

[0127] Aspect 8: The package according to aspects 1 to 7 further includes a second integrated device coupled to the interposer layer via a second plurality of solder interconnects.

[0128] Aspect 9: The package according to Aspect 8, wherein the porous portion includes a first porous portion having a first density; and a second porous portion having a second density, and wherein the plurality of via interconnects includes: a first plurality of via interconnects extending through the first porous portion of the silicon substrate; and a second plurality of via interconnects extending through the second porous portion of the silicon substrate.

[0129] Aspect 10: The package according to aspects 1 to 9, wherein the porous portion comprises the entire silicon substrate.

[0130] Aspect 11: The package according to aspects 1 to 10, wherein the first integrated device comprises: a die substrate including a porous portion; a plurality of through-substrate vias extending through the porous portion of the die substrate; and a die interconnect portion coupled to the die substrate.

[0131] Aspect 12: The package according to aspect 11, wherein the bare die substrate includes a non-porous portion, and wherein the porous portion of the bare die substrate has a lower density than the non-porous portion of the bare die substrate.

[0132] Aspect 13: According to the package of aspect 12, the porous portion of the die substrate includes: a first porous portion having a first coefficient of thermal expansion (CTE); and a second porous portion having a second coefficient of thermal expansion (CTE), wherein the non-porous portion of the die substrate has a third coefficient of thermal expansion (CTE) different from the first coefficient of thermal expansion (CTE) and the second coefficient of thermal expansion (CTE).

[0133] Aspect 14: The package according to aspects 11 to 13, wherein the first integrated device further includes a metallization portion coupled to the back side of the bare die substrate.

[0134] Aspect 15: The package according to aspect 14, wherein the metallized portion includes at least one dielectric layer; and a plurality of metallized interconnects coupled to the plurality of through-substrate vias.

[0135] Aspect 16: The package according to aspects 14 to 15 further includes a second integrated device coupled to the metallized portion of the first integrated device via a second plurality of solder interconnects.

[0136] Aspect 17: The package according to aspects 11 to 16 further includes at least one cavity located in the bare die substrate.

[0137] Aspect 18: The package according to aspects 1 to 17 further includes a second integrated device coupled to the interposer layer via a second plurality of solder interconnects.

[0138] Aspect 19: The package according to aspects 1 to 18 further includes a substrate coupled to the interposer layer via a second plurality of solder interconnects.

[0139] Aspect 20: The package according to aspects 1 to 19, wherein the package is a part of a device selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, and devices in motor vehicles.

[0140] The various features of this disclosure described herein can be implemented in different systems without departing from this disclosure. It should be noted that the foregoing aspects of this disclosure are merely illustrative and should not be construed as limiting the scope of this disclosure. The description of aspects of this disclosure is intended to be illustrative and not to limit the scope of the appended claims. Therefore, the teachings herein are readily applicable to other types of devices, and many substitutions, modifications, and variations will be apparent to those skilled in the art.

Claims

1. A package, the package comprising: Intermediary layer, the intermediary layer comprising: A silicon substrate, the silicon substrate including a porous portion; and A plurality of via interconnects extending through the porous portion of the silicon substrate; and A first integrated device is coupled to the interposer layer via a first plurality of solder interconnects.

2. The packaging component according to claim 1, The silicon substrate includes a non-porous portion, and The porous portion of the silicon substrate has a lower density than the non-porous portion of the silicon substrate.

3. The package according to claim 1, wherein the porous portion has a coefficient of thermal expansion (CTE) in the range of about 5 parts per million degrees Celsius (ppm / C) to 8 parts per million degrees Celsius (ppm / C).

4. The package according to claim 1, wherein the porous portion comprises: A first porous portion, the first porous portion having a first density; and The second porous portion has a second density.

5. The packaging component according to claim 4, The first porous portion has a first coefficient of thermal expansion (CTE), and The second porous portion has a second coefficient of thermal expansion (CTE).

6. The package of claim 5, wherein the silicon substrate includes a non-porous portion having a third coefficient of thermal expansion (CTE) different from the first coefficient of thermal expansion (CTE) and the second coefficient of thermal expansion (CTE).

7. The package according to claim 1, wherein the porous portion has a porosity in the range of about 30% to 70%.

8. The package of claim 1, further comprising a second integrated device coupled to the interposer layer via a second plurality of solder interconnects.

9. The package according to claim 8, The porous portion includes: A first porous portion, the first porous portion having a first density; and The second porous portion has a second density, and The plurality of via interconnects includes: A first plurality of via interconnects, the first plurality of via interconnects extending through the first porous portion of the silicon substrate; and A second plurality of via interconnects extends through the second porous portion of the silicon substrate.

10. The package of claim 1, wherein the porous portion comprises the entire silicon substrate.

11. The package of claim 1, wherein the first integrated device comprises: A bare die substrate, the bare die substrate including a porous portion; Multiple through-substrate vias, the multiple through-substrate vias extending through the porous portion of the bare die substrate; and A die interconnect portion, which is coupled to the die substrate.

12. The package according to claim 11, The bare substrate includes a non-porous portion, and The porous portion of the bare substrate has a lower density than the non-porous portion of the bare substrate.

13. The package of claim 12, wherein the porous portion of the bare die substrate comprises: A first porous portion having a first coefficient of thermal expansion (CTE). and The second porous portion has a second coefficient of thermal expansion (CTE). The non-porous portion of the bare die substrate has a third coefficient of thermal expansion (CTE) that is different from the first coefficient of thermal expansion (CTE) and the second coefficient of thermal expansion (CTE).

14. The package of claim 11, wherein the first integrated device further comprises a metallized portion coupled to the back side of the bare die substrate.

15. The package of claim 14, wherein the metallized portion comprises: At least one dielectric layer; and Multiple metallized interconnects coupled to multiple through-substrate vias.

16. The package of claim 14, further comprising a second integrated device coupled to the metallized portion of the first integrated device via a second plurality of solder interconnects.

17. The package of claim 11, wherein the integrated device further comprises at least one cavity located in the bare die substrate.

18. The package of claim 1, further comprising a second integrated device coupled to the interposer layer via a second plurality of solder interconnects.

19. The package of claim 1, further comprising a substrate coupled to the interposer layer via a second plurality of solder interconnects.

20. The package of claim 1, wherein the package is a part of a device selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, and devices in motor vehicles.

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