Backside bi-directional interconnect

Abstract

Techniques for semiconductor structures are disclosed. In one aspect, a semiconductor structure includes a gate stack including a first gate structure and a second gate structure offset in a first direction. The semiconductor structure includes a first source / drain (S / D) structure adjacent to the first gate structure, a second S / D structure adjacent to the second gate structure, a first backside conductive structure in contact with the first S / D structure, and a second backside conductive structure in contact with the second S / D structure. The semiconductor structure includes a third backside conductive structure disposed in a rear portion of the semiconductor structure opposite the front portion of the semiconductor structure, extending in the second direction, and in contact with the first backside conductive structure and the second backside conductive structure.

Description

Technical Field

[0001] This disclosure relates generally to semiconductor structures for integrated circuit devices, and more specifically to semiconductor structures having back-side bidirectional interconnects. Background Technology

[0002] Integrated circuit (IC) technology has made significant strides in improving computing power through the miniaturization of electrical components. IC devices can be implemented in the form of IC chips, which have a set of circuits integrated on them, including multiple active and passive components (e.g., transistors, diodes, capacitors, inductors, and / or resistors) and several layers of contacts and interconnects above the active and passive components. In some aspects, the contacts and interconnects of the IC device are formed from the front side of the IC device on the active and passive components. As the size of the IC device and the components formed thereon become smaller, the available area for forming the contacts and interconnects also becomes smaller. Thus, the routing complexity of the contacts and interconnects and / or parasitic resistance and capacitance may increase, and therefore the manufacturing cost or performance of the IC device may be negatively affected.

[0003] Therefore, in order to further reduce routing complexity and / or reduce parasitic resistance and capacitance, it is necessary to improve the structure or manufacturing method of contacts and interconnects. Summary of the Invention

[0004] The following is a simplified summary of the invention relating to one or more aspects disclosed herein. Therefore, this summary should not be considered an exhaustive overview relating to all conceived aspects, nor should it be considered to identify key or decisive elements relating to all conceived aspects or to depict the scope associated with any particular aspect. Thus, the sole purpose of this summary is to present, in a simplified form, certain concepts relating to one or more aspects involving the mechanisms disclosed herein, prior to the detailed description presented below.

[0005] In one aspect, the semiconductor structure includes: a gate stack extending in a front portion of the semiconductor structure along a first direction, the gate stack including a first gate structure and a second gate structure offset from each other in the first direction; a first source / drain (S / D) structure adjacent to the first gate structure; a second S / D structure adjacent to the second gate structure and offset from the first S / D structure in a second direction; a first back-side conductive structure contacting the first S / D structure and at least partially disposed in a rear portion of the semiconductor structure opposite to the front portion; a second back-side conductive structure contacting the second S / D structure and at least partially disposed in the rear portion of the semiconductor structure; and a third back-side conductive structure disposed in the rear portion of the semiconductor structure, extending in the second direction and contacting the first back-side conductive structure and the second back-side conductive structure.

[0006] In one aspect, a method of manufacturing a semiconductor structure includes: forming a gate stack extending in a front portion of the semiconductor structure along a first direction, the gate stack including a first gate structure and a second gate structure, the second gate structure being offset from the first gate structure in the first direction, a first S / D structure disposed adjacent to the first gate structure, a second S / D structure disposed adjacent to the second gate structure, and the first S / D structure and the second S / D structure being offset from each other in a second direction; forming a first back-side conductive structure contacting the first S / D structure and at least partially disposed in a rear portion of the semiconductor structure opposite to the front portion; forming a second back-side conductive structure contacting the second S / D structure and at least partially disposed in the rear portion of the semiconductor structure; and forming a third back-side conductive structure disposed in the rear portion of the semiconductor structure, the third back-side conductive structure extending in the second direction and contacting the first back-side conductive structure and the second back-side conductive structure.

[0007] In one aspect, an electronic device includes an integrated circuit device comprising a semiconductor structure, and the semiconductor device comprising: a gate stack extending in a front portion of the semiconductor structure along a first direction, the gate stack including a first gate structure and a second gate structure offset from each other in the first direction; a first source / drain (S / D) structure adjacent to the first gate structure; a second S / D structure adjacent to the second gate structure and offset from the first S / D structure in a second direction; a first back-side conductive structure contacting the first S / D structure and at least partially disposed in a rear portion of the semiconductor structure opposite to the front portion; a second back-side conductive structure contacting the second S / D structure and at least partially disposed in the rear portion of the semiconductor structure; and a third back-side conductive structure disposed in the rear portion of the semiconductor structure, the third back-side conductive structure extending in the second direction and contacting the first back-side conductive structure and the second back-side conductive structure.

[0008] Based on the accompanying drawings and detailed description, other objects and advantages associated with the aspects disclosed herein will be apparent to those skilled in the art. Attached Figure Description

[0009] When considered in conjunction with the accompanying drawings, a more complete understanding of the various aspects of this disclosure and its many advantages therefrom will become better understood by referring to the following detailed description, which is presented for illustrative purposes only and does not constitute any limitation on this disclosure.

[0010] Figure 1 This is a top view of a portion of the semiconductor structure of an integrated circuit (IC) device according to various aspects of this disclosure.

[0011] Figure 2A and Figure 2B This is a top view of a portion of the semiconductor structure of an IC device according to various aspects of this disclosure, emphasizing elements in its different vertical regions.

[0012] Figure 3A and Figure 3B This is a top view of a portion of the semiconductor structure of an IC device according to various aspects of this disclosure, emphasizing elements in its different vertical regions.

[0013] Figures 3C to 3E Based on all aspects of this disclosure Figure 3A and Figure 3B A cross-sectional view of a portion of a semiconductor structure.

[0014] Figure 4A and Figure 4B Manufacturing processes for manufacturing semiconductor structures according to various aspects of this disclosure are illustrated.

[0015] Figure 5A This is a top view of a portion of the semiconductor structure of an IC device according to various aspects of this disclosure.

[0016] Figure 5B Based on all aspects of this disclosure Figure 5A A cross-sectional view of a portion of a semiconductor structure.

[0017] Figure 6A and Figure 6B Manufacturing processes for manufacturing semiconductor structures according to various aspects of this disclosure are illustrated.

[0018] Figures 7A to 7K Examples of manufacturing processes according to various aspects of this disclosure are illustrated. Figures 3A to 3E The structure at each stage of the semiconductor structure.

[0019] Figures 8A to 8B Examples of manufacturing processes according to various aspects of this disclosure are illustrated. Figures 5A to 5B The structure at each stage of the semiconductor structure.

[0020] Figure 9A This is a top view of a portion of the semiconductor structure of an IC device according to various aspects of this disclosure.

[0021] Figure 9B and Figure 9C Based on all aspects of this disclosure Figure 9A A cross-sectional view of a portion of a semiconductor structure.

[0022] Figure 10 It is a cross-sectional view of a semiconductor structure according to various aspects of this disclosure.

[0023] Figure 11A and Figure 11B Manufacturing processes for manufacturing semiconductor structures according to various aspects of this disclosure are illustrated.

[0024] Figure 12 It is a cross-sectional view of a semiconductor structure according to various aspects of this disclosure.

[0025] Figure 13A and Figure 13B Manufacturing processes for manufacturing semiconductor structures according to various aspects of this disclosure are illustrated.

[0026] Figures 14A to 14E Examples of manufacturing processes according to various aspects of this disclosure are illustrated. Figures 9A to 9C The structure at each stage of the semiconductor structure.

[0027] Figures 15A to 15D Examples of manufacturing processes according to various aspects of this disclosure are illustrated. Figure 10 The structure at each stage of the semiconductor structure.

[0028] Figures 16A to 16C Examples of manufacturing processes according to various aspects of this disclosure are illustrated. Figure 12 The structure at each stage of the semiconductor structure.

[0029] Figure 17 Methods for manufacturing semiconductor structures according to various aspects of this disclosure are illustrated.

[0030] Figure 18 Examples of mobile devices according to various aspects of this disclosure are illustrated.

[0031] Figure 19 Various electronic devices that can be integrated with IC devices according to various aspects of this disclosure are illustrated.

[0032] By convention, the features depicted in the accompanying drawings may not be drawn to scale. Accordingly, for clarity, the dimensions of the depicted features may be arbitrarily enlarged or reduced. By convention, some drawings are simplified for clarity. Therefore, the drawings may not depict all components of a particular device or method. Furthermore, similar reference numerals are used throughout the specification and drawings to represent similar features. Detailed Implementation

[0033] Various aspects of this disclosure are provided in the following description and accompanying drawings of various examples provided for illustrative purposes. Alternative aspects may be devised without departing from the scope of this disclosure. Additionally, well-known elements of this disclosure will not be described in detail or will be omitted so as not to obscure the relevant details of this disclosure.

[0034] The various aspects generally relate to the semiconductor structure of integrated circuit devices and the manufacturing methods for producing such semiconductor structures. Some aspects more specifically relate to semiconductor structures with back-side bidirectional interconnects.

[0035] Specific aspects of the subject matter described in this disclosure may be implemented to achieve one or more of the following potential advantages. In some examples, by forming back-side conductive structures extending in two different directions, interconnects can be formed at the rear portion of the semiconductor structure of an integrated circuit device, which can provide additional routing capabilities or capacity for the fabrication of the integrated circuit device.

[0036] The terms “exemplary” and / or “example” are used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” and / or “example” is not necessarily to be construed as superior to or better than other aspects. Similarly, the term “aspects of this disclosure” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed.

[0037] Those skilled in the art will understand that any of a variety of different techniques and methods can be used to represent the information and signals described below. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the following description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof, depending in part on the specific application, in part on the desired design, in part on the corresponding technology, and so on.

[0038] Furthermore, many aspects are described according to a sequence of actions to be performed by elements of, for example, a computing device. It will be appreciated that the various actions described herein can be performed by specific circuitry (e.g., an application-specific integrated circuit (ASIC)), by program instructions executed by one or more processors, or by a combination of both. Additionally, the sequence of actions described herein can be considered to be entirely embodied in any form of non-transitory computer-readable storage medium storing a corresponding set of computer instructions that, when executed, will cause or command the associated processor of the device to perform the functionality described herein. Therefore, various aspects of this disclosure can be embodied in a variety of different forms, all of which are contemplated within the scope of the claimed subject matter. Furthermore, for each aspect described herein, any corresponding form of any such aspect may be described herein as, for example, "logic configured to perform the described actions."

[0039] Figure 1 This is a top view of a portion of the semiconductor structure 100 of an integrated circuit (IC) device according to various aspects of this disclosure. In some aspects, Figure 1 Some components of the semiconductor structure 100 are shown for illustrative purposes only and may be disposed in an IC device. Figure 1 Other elements above and / or below the shown element, but... Figure 1 Not shown in the image.

[0040] like Figure 1As shown, the semiconductor structure 100 includes gate stacks 102, 104, 106, and 108 extending along a first direction (e.g., the y-direction), a source / drain (S / D) structure 122 between gate stacks 102 and 104, an S / D structure 123 between gate stacks 104 and 106, an S / D structure 124 between gate stacks 102 and 108, an S / D structure 126 between gate stacks 102 and 104, an S / D structure 127 between gate stacks 104 and 106, and an S / D structure 128 between gate stacks 102 and 108. S / D structures 122 and 126 are separated from each other in the first direction, S / D structures 123 and 127 are separated from each other in the first direction, and S / D structures 124 and 128 are separated from each other in the first direction.

[0041] The portion of gate stack 102 adjacent to S / D structures 122 and 124 can be configured as a first gate structure, and a first channel structure can be formed through the first gate structure in a second direction (e.g., the x-direction). S / D structures 122 and 124 can be electrically coupled to the first channel structure. The portion of gate stack 102 adjacent to S / D structures 126 and 128 can be configured as a second gate structure, and a second channel structure can be formed through the second gate structure in a second direction. S / D structures 126 and 128 can be electrically coupled to the second channel structure.

[0042] The portion of gate stack 104 adjacent to S / D structures 122 and 123 can be configured as a third gate structure, and a third channel structure can be formed through the third gate structure in the second direction. S / D structures 122 and 123 can be electrically coupled to the third channel structure. Additionally, the portion of gate stack 104 adjacent to S / D structures 126 and 127 can be configured as a fourth gate structure, and a fourth channel structure can be formed through the fourth gate structure in the second direction. S / D structures 126 and 127 can be electrically coupled to the fourth channel structure.

[0043] In some respects, S / D structures 122, 123 and 124 may have a first doping type, and S / D structures 126, 127 and 128 may have a second doping type different from the first doping type.

[0044] In some aspects, the first gate structure, the first channel structure, S / D structure 122, and S / D structure 124 can be configured as a first type of first transistor; and the second gate structure, the second channel structure, S / D structure 126, and S / D structure 128 can be configured as a second type of second transistor. In some aspects, the third gate structure, the third channel structure, S / D structure 122, and S / D structure 123 can be configured as a first type of third transistor; and the fourth gate structure, the fourth channel structure, S / D structure 126, and S / D structure 127 can be configured as a second type of fourth transistor. In some aspects, gate stacks 106 and 108 can be configured as dummy gates, which will be biased to electrically decouple S / D structures 123, 124, 127, and 128 from adjacent S / D structures (not shown).

[0045] like Figure 1 As shown, semiconductor structure 100 includes a contact 132 electrically coupled to S / D structure 122, a contact 133 electrically coupled to S / D structure 123, a contact 134 electrically coupled to S / D structure 124, a contact 137 electrically coupled to S / D structure 127, and a contact 138 electrically coupled to S / D structure 128. Semiconductor structure 100 includes a conductive structure 142 electrically coupled to contacts 133 and 134 via corresponding via structures (not labeled, depicted as solid lines with cross-marking). Semiconductor structure 100 includes a conductive structure 144 electrically coupled to contact 137 via a via structure (not labeled, depicted as solid lines with cross-marking). Furthermore, the semiconductor structure 100 includes conductive structures 145, 146, 147, and 148 electrically coupled to contacts 132 and 138 and gate stacks 102 and 104 via corresponding via structures (unmarked, depicted as solid boxes with cross markings), respectively. Additionally, the semiconductor structure 100 includes a conductive structure 152 electrically coupled to conductive structures 145 and 146 via corresponding via structures (unmarked, depicted as dashed boxes with cross markings).

[0046] In some aspects, conductive structure 142 may be a first power supply line configured to carry a first supply voltage (e.g., VDD), and conductive structure 144 may be a second power supply line configured to carry a second supply voltage (e.g., VSS or ground). In some aspects, conductive structure 147 may be a signal line configured to carry a first gate voltage for controlling a first gate structure of a first transistor and a second gate structure of a second transistor. In some aspects, conductive structure 148 may be a signal line configured to carry a second gate voltage for controlling a third gate structure of a third transistor and a fourth gate structure of a fourth transistor. In some aspects, conductive structure 152 may be a signal line configured to carry an output voltage at the S / D structure 122 of the first transistor and the S / D structure 128 of the second transistor. In some aspects, Figure 1 A portion of the semiconductor structure 100 shown forms a NAND gate and can be used as a standard cell for manufacturing NAND gates for IC devices.

[0047] Figure 2A and Figure 2B This is a top view of a portion of the semiconductor structure 200 of an IC device according to various aspects of this disclosure, emphasizing elements in its different vertical regions. Specifically, Figure 2A The element shown illustrates that it can be located in the vertical direction (e.g., the z-direction corresponding to the direction away from the drawing plane). Figure 2B The element above the element shown. In some respects, Figure 2A and Figure 2B Some components of the semiconductor structure 200 are shown for illustrative purposes only, and may be configured... Figure 2A and Figure 2B Other elements above and / or below the shown element, but... Figure 2A and Figure 2B Not shown in the image. Furthermore, with... Figure 1 Elements that are identical or similar to the elements in the figures are given the same reference numerals, and their detailed descriptions may be omitted.

[0048] like Figure 2A As shown, compared to semiconductor structure 100, semiconductor structure 200 does not include contacts 133, 134, and 137, conductive structures 142 and 144, and corresponding via structures. In some aspects, compared to semiconductor structure 100, contacts and interconnects formed based on such omitted elements may be replaced by back-side contacts and back-side interconnects. In some aspects, back-side contacts and back-side interconnects may correspond to contacts and interconnects disposed in the vertical direction below the S / D structure and / or gate stack and formed from the back side of the semiconductor structure.

[0049] like Figure 2BAs shown, the semiconductor structure 200 includes a back-side contact 233 electrically coupling the S / D structure 123 of a third transistor to a back-side conductive structure 242, a back-side contact 234 electrically coupling the S / D structure 124 of a first transistor to the back-side conductive structure 242, and a back-side contact 237 electrically coupling the S / D structure 127 of a fourth transistor to the back-side conductive structure 244. In some aspects, the back-side conductive structure 242 may be configured to carry a first supply voltage (e.g., VDD), and the back-side conductive structure 244 may be configured to carry a second supply voltage (e.g., VSS or ground).

[0050] In some respects, scaling of logic components may become ineffective due to slowed pitch scaling and a lack of material breakthroughs. In some respects, only front-side technologies (e.g., reference) Figure 1 (Examples shown) or power supplied via embedded power rails may have higher mid-stage (MOL) capacitance, which may limit the level of power reduction that can be achieved.

[0051] In some respects, one promising future direction for continuous scaling is based on Fully All-Around Gate Back Side Power Distribution Network (GAA-BSPDN) technology (e.g., reference...). Figure 2A and Figure 2B (Example), where the contacts (i.e., S / D contacts or diffused contacts) and / or local interconnects of the S / D structure can be formed directly from the back side of the semiconductor structure. In some aspects, diffused contacts formed from the back side may be referred to as back-side contacts (BSCs), and local interconnects formed from the back side may be referred to as back-side contact local interconnects (BSCLIs). In some aspects, by implementing more than half of the diffused contacts and / or local interconnects as BSCs and / or BSCLIs, the gate-to-contact parasitic capacitance can be significantly reduced. In some aspects, the amount of capacitance improvement can be significant, for example, equivalent to about half the reduction over the entire manufacturing technology node.

[0052] Therefore, this application further describes a method of fabricating BSCLIs as jumpers (e.g., also referred to in this disclosure as "back-side bidirectional interconnects") extending in one direction to connect two BSCs and / or BSCLIs extending in another direction. In some aspects, the back-side bidirectional interconnects may be formed based on a self-aligned conductive structure. In some aspects, the back-side bidirectional interconnects may be formed based on a dielectric structure that is a region-specific deposition (ASD) structure or an etch-stop layer.

[0053] Figure 3A and Figure 3B This is a top view of a portion of the semiconductor structure 300 of an IC device according to various aspects of this disclosure, emphasizing elements in its different vertical regions. Specifically, Figure 3AThe element shown illustrates that it can be located in the vertical direction (e.g., the z-direction corresponding to the direction away from the drawing plane). Figure 3B The element above the element shown. In some respects, Figure 3A and Figure 3B Some components of the semiconductor structure 300 are shown for illustrative purposes only, and may be configured... Figure 3A and Figure 3B Other elements above and / or below the shown element, but... Figure 3A and Figure 3B Not shown in the diagram. Furthermore, in some aspects, the semiconductor structure 300 may be... Figures 1 to 2B The example depicted is a NAND gate variant. Thus, with... Figures 1 to 2B Elements that are identical or similar to the elements in the figures are given the same reference numerals, and their detailed descriptions may be omitted.

[0054] like Figure 3A As shown, S / D structures 124 and 122 are adjacent to the first gate structure of the gate stack 102, and S / D structures 126 and 128 are adjacent to the second gate structure of the gate stack 102. Figure 3A As shown, compared to semiconductor structure 200, semiconductor structure 300 does not include contact 132, conductive structures 145 and 152, and corresponding via structures. In some aspects, compared to semiconductor structure 200, contacts and interconnects formed based on such omitted elements can be replaced by back-side contacts and back-side interconnects (e.g., back-side conductive structures).

[0055] like Figure 3B As shown, the semiconductor structure 300 includes a back-side conductive structure 332 for electrically coupling the S / D structure 122 of the first and third transistors, and a back-side conductive structure 338 for electrically coupling the S / D structure 128 of the second transistor. Additionally, the semiconductor structure 300 includes a back-side conductive structure 333 and a corresponding via structure (not shown) for electrically coupling the S / D structure 123 of the third transistor to the back-side conductive structure 242, a back-side conductive structure 334 and a corresponding via structure (not shown) for electrically coupling the S / D structure 124 of the first transistor to the back-side conductive structure 242, and a back-side conductive structure 337 and a corresponding via structure (not shown) for electrically coupling the S / D structure 127 of the fourth transistor to the back-side conductive structure 244.

[0056] In some aspects, the back-side conductive structure 332 may extend toward the S / D structure 126 along a first direction, and the back-side conductive structure 338 may extend toward the S / D structure 124 along a first direction. Furthermore, the semiconductor structure 300 also includes a back-side conductive structure 342 located below and in contact with the back-side conductive structures 332 and 338. In some aspects, the back-side conductive structure 342 may be configured as a jumper for electrically connecting the back-side conductive structures 332 and 338.

[0057] Figure 3C Based on all aspects of this disclosure Figure 3A and Figure 3B A cross-sectional view of a portion of the semiconductor structure 300 along the cutting line R1. Figure 3C Zhongyu Figure 3A and Figure 3B Elements that are identical or similar to each other are given the same reference numerals and their detailed descriptions may be omitted.

[0058] like Figure 3C As shown, the semiconductor structure 300 includes gate stacks 102, 104, 106, and 108. A magnified region 350 shows details of a portion of gate stack 102. In some aspects, gate stacks 104, 106, and 108 may have a configuration similar to that of gate stack 102. Figure 3C As shown, the gate stack 102 may include five gate portions, each gate portion including a corresponding gate electrode (also referred to as "gate metal" or "gate conductor") (e.g., gate electrode 352a or 352b) and a corresponding gate dielectric structure (e.g., gate dielectric structure 354a or 354b). In this disclosure, all gate electrodes in the gate stack may be collectively referred to as gate electrode structures. In some aspects, the top gate portion of the gate stack 102 may include a gate spacer 358 on the back sidewall of the gate dielectric structure 354a. In some aspects, the gate portions in the gate stack 102 other than the top gate portion may include internal spacers (e.g., internal spacer 356) on the sidewall of the corresponding gate dielectric structure (e.g., gate dielectric structure 354b).

[0059] Semiconductor structure 300 may include an epitaxial stop layer 362. In some aspects, the lower surface of the epitaxial stop layer 362 may be at approximately the same level as the lower surface of the gate structures of gate stacks 102, 104, 106, and 108. Semiconductor structure 300 may also include an epitaxial layer 364. The portion of epitaxial layer 364 between gate stacks 102 and 104 may define an S / D structure 122; the portion of epitaxial layer 364 between gate stacks 104 and 106 may define an S / D structure 123; and the portion of epitaxial layer 364 between gate stacks 102 and 108 may define an S / D structure 124. Furthermore, portions of gate stacks 102, 104, 106, and / or 108 between adjacent gate portions may be configured as channel members (e.g., channel members 366a and 366b). In this disclosure, all channel members in the gate stacks may be collectively referred to as channel structures. In some aspects, channel members may include multiple nanowires or nanosheets.

[0060] like Figure 3CAs shown, the semiconductor structure 300 may include a front dielectric layer 370 (e.g., a front ILD layer) on the gate stacks 102, 104, 106, and 108 and the epitaxial layer 364. In some aspects, for ease of illustration, elements located on or above the lower surface of the epitaxial stop layer 362 and / or the lower surface of the gate structures of the gate stacks 102, 104, 106, and 108 may be referred to as being in the front portion of the semiconductor structure 300; and elements located below the lower surface of the epitaxial stop layer 362 and / or the lower surface of the gate structures of the gate stacks 102, 104, 106, and 108 may be referred to as being in the rear portion of the semiconductor structure 300 relative to the front portion.

[0061] like Figure 3C As shown, the semiconductor structure 300 may further include a back-side dielectric layer 382 (e.g., a back-side ILD layer) in the rear portion of the semiconductor structure 300. Back-side conductive structures 332, 333, and 334 may be at least partially disposed in the rear portion of the semiconductor structure and pass through the back-side dielectric layer 382. Furthermore, the back-side conductive structure 332 may extend along a first direction (e.g., the y-direction) and pass through back-side conductive structures 338 and 342 (…). Figure 3C (Not shown in the image) Electrically coupled to the S / D structure 128.

[0062] like Figure 3C As shown, in some aspects, the upper portion of the back-side conductive structure (e.g., back-side conductive structure 332) may contact the bottom internal spacer of a gate structure (e.g., the gate structure of gate stack 102) and the bottom internal spacer of another gate structure (e.g., the gate structure of gate stack 104 offset from the gate structure of gate stack 102 in the x-direction). In some aspects, the back-side conductive structure may include tungsten, cobalt, molybdenum, or combinations thereof.

[0063] Figure 3D Based on all aspects of this disclosure Figure 3A and Figure 3B A cross-sectional view of a portion of the semiconductor structure 300 along a cut line R1, in which details of the gate stacks 102, 104, 106 and 108 are simplified. Figure 3E Based on all aspects of this disclosure Figure 3A and Figure 3B A cross-sectional view of a portion of the semiconductor structure 300 along a cut line R2, in which details of the gate stacks 102, 104, 106 and 108 are simplified. Figure 3D and Figure 3E Zhongyu Figures 3A to 3C Elements that are identical or similar to the elements in the figures are given the same reference numerals, and their detailed descriptions may be omitted.

[0064] like Figure 3DAs shown, the back-side conductive structure 332 is in contact with the S / D structure 122; the back-side conductive structure 333 is in contact with the S / D structure 123; and the back-side conductive structure 334 is in contact with the S / D structure 124. In some aspects, the back-side conductive structures 332, 333, and 334 are partially embedded in the back-side dielectric layer 382. In some aspects, the back-side dielectric layer 382 and the corresponding metallization structure disposed therein may be referred to as a first back-side metallization layer beneath the S / D structure.

[0065] Semiconductor structure 300 also includes via structures 393 and 394 embedded in a back-side dielectric layer 384 beneath a back-side dielectric layer 382, ​​and a back-side dielectric layer 386 embedded beneath a back-side dielectric layer 384. Figure 3E The back-side conductive structure 242 is located in the back-side conductive structure 242. In some aspects, the back-side dielectric layer 384 and the corresponding metallization structure disposed therein may be referred to as a second back-side metallization layer below the first back-side metallization layer. In some aspects, the back-side dielectric layer 386 and the corresponding metallization structure disposed therein may be referred to as a third back-side metallization layer below the second back-side metallization layer. Via structures 393 and 394 electrically connect the back-side conductive structures 332 and 334 to the back-side conductive structure 242, respectively. In addition, the back-side conductive structure 332 is electrically isolated from the back-side conductive structure 242 through the back-side dielectric layer 384.

[0066] like Figure 3E As shown, the isolation structure 368 (e.g., a shallow trench isolation (STI) structure) may be disposed in a region below the epitaxial stop layer 362 and / or the front dielectric layer 370 that does not overlap with the S / D structure and channel structure of the first, second, third, and fourth transistors (top view). The back conductive structure 332 contacts the S / D structure 122 (e.g., Figure 3D (as shown); and the back-side conductive structure 338 is in contact with the S / D structure 126 (not shown). In some aspects, the back-side conductive structures 332 and 338 are partially embedded in the back-side dielectric layer 382. The semiconductor structure 300 also includes a back-side conductive structure 342 embedded in a back-side dielectric layer 384 (e.g., in a second back-side metallization layer) beneath the back-side dielectric layer 382. In some aspects, the back-side conductive structures 332 and 338 may extend along a first direction (e.g., the y-direction). In some aspects, the back-side conductive structure 342 may extend along a second direction (e.g., the x-direction) and contact the back-side conductive structures 332 and 338.

[0067] Therefore, as Figures 3A to 3EAs shown, the semiconductor structure 300 may include a back-side conductive structure 332 that contacts the S / D structure 122 and is at least partially disposed in the rear portion of the semiconductor structure opposite to the front portion; a back-side conductive structure 338 that contacts the S / D structure 128 and is at least partially disposed in the rear portion of the semiconductor structure; and a back-side conductive structure 342 disposed in the rear portion of the semiconductor structure, extending along a second direction, and contacting the back-side conductive structures 332 and 338. In some aspects, the back-side conductive structures 332 and 338 may be disposed within a first back-side metallization layer below the S / D structures 122 and 128, and the back-side conductive structure 342 may be disposed within a second back-side metallization layer below the first back-side metallization layer. In some aspects, the back-side conductive structures (e.g., via structures 393 and 394) may be disposed within the second back-side metallization layer. In some aspects, the metallization structure (e.g., back-side conductive structure 242 or 244) may be disposed within a third back-side metallization layer beneath the second back-side metallization layer. In some aspects, one or more via structures may be configured to connect the metallization structure to another back-side conductive structure in the first back-side metallization layer.

[0068] Figure 4A and Figure 4B Examples of methods for manufacturing semiconductor structures according to various aspects of this disclosure are illustrated (e.g., Figures 3A to 3E The manufacturing process 400 of the semiconductor structure 300. In some aspects, Figure 4A The processing stage shown (labeled "Part A" of manufacturing process 400) corresponds to the front-side processing of a semiconductor structure, because such a stage corresponds to the processes performed on the front side of a wafer from which a semiconductor structure is formed. In some aspects, Figure 4B The processing stage shown (labeled as “part B” of manufacturing process 400) can correspond to the back-side processing of the wafer, because such a stage can correspond to a process performed from the back side of the wafer, which is opposite to the front side of the wafer.

[0069] At stage 405, a multilayer structure can be formed on the substrate of the wafer. In some aspects, the multilayer structure may include different silicon material layers stacked on top of each other. In some aspects, the multilayer structure may include Si layers and SiGe layers stacked on top of each other as a silicon (Si) / silicon germanium (SiGe) stack.

[0070] At stage 405, the active region of the semiconductor structure can be defined based on oxide diffusion (OD) patterning. In some aspects, an OD patterning process can be performed on a multilayer structure (e.g., a Si / SiGe stack) to shape the multilayer structure into a fin structure. At stage 405, a polysilicon material layer can be formed on the fin structure, and a polysilicon gate patterning process can be performed on the polysilicon material layer to form a patterned polysilicon structure on the fin structure. In some aspects, the patterned polysilicon structure can be along a first direction (e.g., Figures 3A to 3E The polysilicon gate structure extends in the y-direction. In some aspects, the polysilicon gate structure may be formed based on a patterned polysilicon structure and may also include a second direction (e.g., Figures 3A to 3E External spacers formed on both sides of a patterned polycrystalline silicon structure in the x-direction.

[0071] At stage 415, a source / drain (S / D) recess process is performed on the fin structure using at least a polysilicon gate structure as a mask. The resulting structure after the S / D recess process may include a trimmed multilayer structure that is substantially flush with the polysilicon gate structure on the side in a second direction. In some aspects, a plurality of internal spacers are formed by partially and selectively removing a portion of the multilayer structure exposed in the second direction (e.g., selectively removing SiGe over Si) and filling the removed portion of the multilayer structure with a dielectric material.

[0072] At stage 418, a mask patterning process is performed to form a resist pattern with openings based on the positioning where the back-side conductive structure can be formed. Because the back-side conductive structure can be formed as a self-aligned contact structure, the positioning of the back-side conductive structure can be defined based on the combination of the resist pattern and the polysilicon gate structure.

[0073] At stage 420, an etching process is performed using a resist pattern and a polysilicon gate structure as a mask to define an opening corresponding to the location where a back-side conductive structure can be formed. At stage 420, the opening is further filled with a sacrificial material. At stage 422, the portion of the sacrificial material-filled portion that may cover the sidewalls of the trimmed multilayer structure may be recessed to a degree that does not impede subsequent electrical coupling to the channel member (e.g., to expose at least the sidewalls of the trimmed multilayer structure not covered by internal spacers).

[0074] At stage 425, an S / D epitaxial formation process is performed to form an epitaxial growth structure on both sides of the polysilicon gate structure in a second direction. In some aspects, the epitaxial growth structure may include Si. In some aspects, one or more implantation processes may be performed on the epitaxial growth structure to convert the epitaxial growth structure into an S / D structure. In some aspects, an epitaxial stop layer may be formed prior to the formation of the epitaxial growth structure.

[0075] At stage 435, a polysilicon gate stripping process can be performed on the polysilicon gate structure to remove at least the polysilicon portion of the polysilicon gate structure. Subsequently, a removal process can be performed to remove the same material as the multilayer structure removed at stage 415, which converts the multilayer structure into a channel structure that may include one or more channel members. In some aspects, the multilayer structure is a Si / SiGe stack, and SiGe is removed at stage 435 (also referred to as a dummy SiGe release process). After stage 435, an opening can be defined between the outer spacer and the inner spacer, through which one or more channel members pass in a second direction from one side to the other.

[0076] At stage 445, a high-dielectric-constant (high-k or HK) metal gate structure is formed around one or more channel members in an opening from stage 435. In some aspects, the HK metal gate structure includes a gate electrode structure and one or more gate dielectric structures between the gate electrode structure and the corresponding one or more channel members. In some aspects, the one or more gate dielectric structures may include a dielectric material or dielectric structure corresponding to a dielectric constant greater than that of silicon (hence the designation HK).

[0077] At stage 455, one or more of the front-end process (FEOL), mid-end process (MOL), or back-end process (BEOL) can be performed on the structure obtained in stage 445 to form multiple metallized structural layers. In some aspects, the FEOL process may correspond to the formation of conductive vias or contacts on electrical components to fabricate electrical components for interconnection. In some aspects, the MOL process may be performed after the FEOL process and may correspond to the formation of conductive vias and conductive lines for local interconnection between adjacent electrical components. In some aspects, the BEOL process may be performed after the MOL process and may correspond to the formation of conductive vias and conductive lines for interconnection between groups of electrical components. In some aspects, the MOL process may be omitted, and local interconnection may be formed based on the FEOL process, the BEOL process, or both.

[0078] In such Figure 4A After the front-side processing of the semiconductor structure shown, the back-side processing of the semiconductor structure is as follows: Figure 4B As shown.

[0079] At stage 465, during the wafer bonding process, a carrier may be attached to the front side of the wafer from stage 455. The wafer with the carrier attached may be inverted so that the substrate on the back side of the wafer is now facing upwards. A substrate thinning process may then be performed to remove at least a portion of the substrate of the wafer.

[0080] At stage 475, the remaining substrate material can be selectively removed further during the silicon pillar removal process, leaving structures such as etch stop layers, STI structures, and / or other structures (such as placeholders or sacrificial via structures). A back-side ILD layer can then be formed by filling the back side of the wafer with ILD material. In some aspects, a further chemical mechanical polishing (CMP) process can be performed to refine the thickness of the back-side ILD layer.

[0081] At stage 480, the sacrificial structure formed at stage 422 can be exposed after stage 475 and removed from the back side of the wafer. At stage 480, a portion of the epitaxial stop layer below the S / D structure and exposed after the removal of the sacrificial structure can be further removed based on the epitaxial stop punch-through process. After stage 480, the back side opening can therefore be defined based on the removal of the sacrificial structure and the removal of the portion of the epitaxial stop layer below the S / D structure.

[0082] At stage 482, the back opening from stage 480 can be filled with a conductive or metallic material to form Figures 3A to 3E The back-side conductive structures 332, 333, 334, 337 and 338 are shown.

[0083] At stage 490, an additional back-side dielectric layer (e.g., back-side dielectric layer 384) is formed and patterned to define openings for forming via structures and jumpers (e.g., back-side conductive structure 342) during the patterning process, and the openings are filled with one or more conductive materials during the metallization process to form via structures and jumpers.

[0084] At stage 495, further back-side metallization processes may be performed to form additional metallization layers, including one or more power lines (e.g., back-side conductive structures 242 and 244) and / or one or more signal lines. In some aspects, one or more conductive pads may be formed, wherein the resulting integrated circuit device based on the semiconductor structure described herein may be attached to another integrated circuit device, an interposer, or a package substrate via one or more conductive pads.

[0085] Figure 5A This is a top view of a portion of a semiconductor structure 500 of an IC device according to various aspects of this disclosure. In some aspects, the semiconductor structure 500 may be a variation of the semiconductor structure 300, and the semiconductor structure 500 in... Figure 5A The portion above the shown element can be connected to Figure 3A This corresponds to a portion of the semiconductor structure 300 depicted in the diagram. In some respects, Figure 5A Combination Figure 3A Some components of the semiconductor structure 500 are shown for illustrative purposes only and may be set in... Figure 5A and Figure 3AOther elements above and / or below the elements shown, but... Figure 5A and Figure 3A Not shown in the image.

[0086] Additionally, in some aspects, the cross-sectional view of the semiconductor structure 500 along the dicing line R1 can be compared with... Figure 3D This corresponds to the semiconductor structure 300 depicted in the diagram. (And...) Figures 3A to 3E Elements that are identical or similar to those in the drawings are given the same reference numerals, and their detailed descriptions may be omitted.

[0087] like Figure 5A As shown, with Figure 3B Compared to the semiconductor structure 300 depicted in the diagram, the semiconductor structure 500 includes alternatives. Figure 3B The back-side conductive structure 542 of the middle back-side conductive structure 342. Compared with the back-side conductive structure 342 disposed in the back-side metallization layer below the back-side conductive structures 332 and 338, the back-side conductive structure 542 may be disposed in the same back-side metallization layer in which the conductive structures 332 and 338 are at least partially disposed.

[0088] Figure 5B Based on all aspects of this disclosure Figure 5A A cross-sectional view of a portion of the semiconductor structure 500 along dicing line R2, where details of the gate stacks 102, 104, 106, and 108 are simplified. (See diagram below.) Figure 5B As shown, the back-side conductive structure 542 may be disposed at the lower portion of the same back-side metallization layer (i.e., based on the back-side dielectric layer 382) on which the conductive structures 332 and 338 are at least partially disposed. In some aspects, the back-side conductive structure 542 may be integrally formed with the back-side conductive structures 332 and 338.

[0089] Therefore, as Figures 5A to 5BAs shown, the semiconductor structure 500 may include a back-side conductive structure 332 that contacts the S / D structure 122 and is at least partially disposed in the rear portion of the semiconductor structure opposite to the front portion; a back-side conductive structure 338 that contacts the S / D structure 128 and is at least partially disposed in the rear portion of the semiconductor structure; and a back-side conductive structure 542 disposed in the rear portion of the semiconductor structure, extending along a second direction, and contacting the back-side conductive structures 332 and 338. In some aspects, the back-side conductive structures 332 and 338 may be disposed within a first back-side metallization layer below the S / D structures 122 and 128, and the back-side conductive structure 542 may be disposed within a lower portion of the first back-side metallization layer. In some aspects, the back-side conductive structures (e.g., via structures 393 and 394) may be disposed within a second back-side metallization layer. In some aspects, the metallization structures (e.g., back-side conductive structures 242 or 244) may be disposed within a third back-side metallization layer below the second back-side metallization layer. In some aspects, one or more via structures may be configured to connect a metallized structure to another back-side conductive structure in a first back-side metallized layer.

[0090] Figure 6A and Figure 6B Examples of methods for manufacturing semiconductor structures according to various aspects of this disclosure are illustrated (e.g., Figures 5A to 5B The manufacturing process of the semiconductor structure 500 in the semiconductor is described in section 600. In some aspects, Figure 6A The processing stage shown (labeled "Part A" of manufacturing process 600) corresponds to the front-side processing of a semiconductor structure, because such a stage corresponds to the processes performed on the front side of a wafer from which a semiconductor structure is formed. In some aspects, Figure 6B The processing stage shown (labeled as “part B” of manufacturing process 600) can correspond to the back-side processing of the wafer, as such a stage can correspond to a process performed from the back side of the wafer, which is opposite to the front side of the wafer.

[0091] In some respects, process 600 can be Figures 4A to 4B A variation of process 400. (And...) Figures 4A to 4B Stages that are identical or similar to those in the accompanying drawings are given the same reference numerals, and their detailed descriptions may be omitted. In some respects, the process may include references to... Figures 4A to 4B The corresponding phases shown are 405, 415, 418, 420, 422, 425, 435, 445, 455, 465, 475 and 480, which are the same or similar in terms of their corresponding parts.

[0092] After phase 480, in Figure 6BAt stage 681, a jumper patterning process is performed to modify the back opening from stage 480 to further include a jumper opening portion for forming a back conductive structure (e.g., back conductive structure 542) configured as a jumper.

[0093] At stage 683, the modified back opening from stage 681 can be filled with a conductive or metallic material to form Figures 5A to 5B The back-side conductive structures 332, 333, 334, 337 and 338, and the back-side conductive structure 542 are shown.

[0094] At stage 688, an additional back-side dielectric layer (e.g., back-side dielectric layer 384) is formed and patterned to define an opening for forming a via structure during the patterning process, and the opening is filled with one or more conductive materials during the metallization process to form a via structure.

[0095] Following stage 688, at stage 495, further backside metallization processes may be performed to form additional metallization layers, including one or more power lines (e.g., backside conductive structures 242 and 244) and / or one or more signal lines. In some aspects, one or more conductive pads may be formed, wherein the resulting integrated circuit device based on the semiconductor structure described herein may be attached to another integrated circuit device, an interposer, or a package substrate via one or more conductive pads.

[0096] Figures 7A to 7K Examples of manufacturing processes according to various aspects of this disclosure are illustrated. Figures 3A to 3E The structure at each stage of the semiconductor structure. Figures 7A to 7K Including along and Figure 3B The left cross-sectional view (denoted as "cutting line R1") corresponding to the cutting line R1 in the diagram; and along with... Figure 3B The right-side cross-section of the cutting line corresponding to the cutting line R2 in the diagram (denoted as "cutting line R2"). Figures 7A to 7K The shown with Figures 3A to 3E Elements that are identical or similar to those in the drawings are given the same reference numerals, and their detailed descriptions may be omitted.

[0097] like Figure 7A As shown, a structure 700A is provided. Structure 700A includes four gate stacks 702, 704, 706, and 708 on a substrate 710. Additionally, an STI structure 368 may be embedded in a region of the substrate 710 outside the active region corresponding to the S / D structure and channel structure of the resulting transistor. In some aspects, the gate stacks 702, 704, 706, and 708 may be... Figure 4A The resulting structure corresponds to the gate stack at stage 415 in the middle.

[0098] like Figure 7B As shown, based on structure 700A, structure 700B is formed by forming a resist pattern 712 that defines an opening based on a positioning of a back-side conductive structure (e.g., back-side conductive structures 332, 333, 334, and 338). In some aspects, the resist pattern 712 can be formed by forming a photoresist material over structure 700A, followed by performing a photolithography process to develop exposed portions of the photoresist material, and removing one or more exposed portions of the photoresist (depending on the type of photoresist material and / or the removal process). In some aspects, structure 700B can be combined with... Figure 4A The structure obtained at point 418 in the middle stage corresponds to this.

[0099] like Figure 7C As shown, based on structure 700B, structure 700C is formed by performing an etching process using gate stacks 702, 704, 706, and 708 and resist pattern 712 as a mask to define openings 714a to 714d corresponding to the positioning of which back-side conductive structures (e.g., back-side conductive structures 332, 333, 334, and 338) can be formed. In some aspects, the etching process may include multiple steps, including a first step of removing a portion of substrate 710 not covered by STI structure 368, a second step of removing a portion of STI structure 368, and a third step of further extending the openings within substrate 710. In some aspects, the etching process may include a non-selective etching step to etch sufficiently deep into substrate 710 below STI structure 368. In some aspects, structure 700C may be associated with... Figure 4A The structure obtained in the first half of stage 420 corresponds to that obtained in the middle.

[0100] like Figure 7D As shown, based on structure 700C, structure 700D is formed by filling sacrificial material into openings 714a to 714d to form filled sacrificial material 716. In some aspects, during a subsequent sacrificial material removal process (e.g., at stage 480), the sacrificial material may have better selectivity for the dielectric material (e.g., silicon oxide) used to form the back-side dielectric layer (e.g., back-side ILD layer 382). In some aspects, the sacrificial material may be filled based on a spin-coating process. In some aspects, the sacrificial material may include silicon nitride (SiN), which may have high selectivity for Si, SiGe, and / or silicon oxide during certain etching processes. In some aspects, structure 700D may be combined with... Figure 4A The structure obtained in stage 420 corresponds to that in the middle.

[0101] like Figure 7EAs shown, based on structure 700D, a recess process is performed to remove excess sacrificial material, thereby exposing at least the sidewalls of the multilayer structure of gate stacks 702, 704, 706, and 708 corresponding to their channel members, forming structure 700E. The remaining portion of the sacrificial material from structure 700D becomes sacrificial structures 722, 723, 724, and 728. In some aspects, sacrificial structures 722, 723, 724, and 728 can be used as placeholders for back-side conductive structures 332, 333, 334, and 338, respectively. In some aspects, structure 700E can be combined with... Figure 4A The structure obtained in stage 422 corresponds to that in the middle.

[0102] like Figure 7F As shown, based on structure 700E, structure 700F is formed by performing operations corresponding to stages 425, 435, and 445. This forms an epitaxial stop layer 362, an epitaxial layer 364, gate stacks 102, 104, 106, and 108 with HK metal gate structures and channel structures, and corresponding S / D structures (e.g., S / D structures 122, 123, 124, 126, 127, and 128). In some aspects, structure 700F can be... Figure 4A The structure obtained in stage 445 corresponds to that in the middle.

[0103] like Figure 7G As shown, structure 700G is formed based on structure 700F. In some aspects, one or more of the FEOL process, MOL process, or BEOL process can be performed on structure 700F from the front side, and the wafer on which the semiconductor structure 700F is formed can be bonded to a carrier and flipped for various further processes performed from the back side. In some aspects, a substrate thinning process can be performed from the back side to remove at least a portion of substrate 710, and the remaining portion of substrate 710 can be further removed during a silicon pillar removal process. Then, a back-side dielectric layer 382 can be formed. In some aspects, the back-side dielectric layer 382 may include silicon oxide. In some aspects, structure 700G may be associated with... Figure 4B The structure obtained in stage 475 corresponds to that in the middle.

[0104] like Figure 7H As shown, based on structure 700G, structure 700H is formed by removing sacrificial structures 722, 723, 724, and 728, followed by an epitaxial stop punch-through process to remove a portion of the epitaxial stop layer 362 exposed below S / D structures 122, 123, and 124 after the removal of sacrificial structures 722, 723, 724, and 728. Figure 7HAs shown, after the sacrificial removal process and the epitaxial stop punching process, back-side openings 732a to 732d are defined. In some aspects, back-side openings 732a to 732d may correspond to the locations where back-side conductive structures 332, 333, 334, and 338 will be formed. In some aspects, structure 700H may be... Figure 4B The structure obtained in stage 480 corresponds to that in the middle.

[0105] like Figure 7I As shown, based on structure 700H, structure 700I is formed by filling the back-side openings 732a to 732d with conductive or metallic material to form back-side conductive structures 332, 333, 334, and 338. In some aspects, the conductive or metallic material may include tungsten, cobalt, molybdenum, or combinations thereof. In some aspects, structure 700I may be combined with... Figure 4B The structure obtained in stage 482 corresponds to that in the previous stage. In some respects, the back-side dielectric layer 382 and the conductive structure disposed therein may be referred to as the first back-side metallization layer.

[0106] like Figure 7J As shown, based on structure 700I, structure 700J can be formed by forming a second back-side metallization layer including a back-side dielectric layer 384 and a conductive structure disposed therein. As... Figure 7J As shown, a back-side dielectric layer 384 is formed and patterned to define openings, and via structures 393 and 394 and a back-side conductive structure 342 can be formed based on these openings. In some aspects, via structures 393 and 394 are electrically connected to back-side conductive structures 332 and 334, respectively. In some aspects, the back-side conductive structure 342 may extend along a second direction (e.g., the x-direction) and contact the back-side conductive structures 332 and 338. In some aspects, structure 700H may be connected to... Figure 4B The structure obtained in stage 490 corresponds to that in the middle.

[0107] like Figure 7K As shown, based on structure 700J, structure 700K can be formed by forming a third back-side metallization layer including a back-side dielectric layer 386 and a conductive structure disposed therein. As... Figure 7K As shown, a back-side dielectric layer 386 is formed and patterned to define an opening, and a back-side conductive structure 242 can be formed based on the opening. In some aspects, via structures 393 and 394 electrically connect back-side conductive structures 332 and 334 to back-side conductive structure 242. Additionally, back-side conductive structure 332 can be electrically isolated from back-side conductive structure 242 via back-side dielectric layer 384. In some aspects, structure 700K can be... Figure 4B The structure obtained in stage 495 corresponds to that obtained in [the previous stage]. In some respects, structure 700K can be compared with [the previous stage]. Figure 3D and Figure 3E The structure shown corresponds to 300.

[0108] Figures 8A to 8B and Figures 7A to 7H Together, examples of manufacturing processes based on various aspects of this disclosure are illustrated. Figures 5A to 5B The structure of the semiconductor structure at each stage of 500. Figures 8A to 8B The various ones in the middle include those along and Figure 5A The left cross-sectional view (denoted as "cutting line R1") corresponding to the cutting line R1 in the diagram; and along with... Figure 5A The right-hand cross-sectional view (denoted as "cutting line R2") is taken from the cutting line R2 in the diagram. Semiconductor structure 500 can be based on... Figures 7A to 7H The corresponding process is used for manufacturing, followed by reference. Figure 8A and Figure 8B The process is shown. Figure 8A and Figure 8B The shown and Figure 5A and Figure 5B as well as Figures 7A to 7H Elements that are identical or similar to those in the drawings are given the same reference numerals, and their detailed descriptions may be omitted.

[0109] like Figure 8A As shown, based on structure 700H, structure 800A can be formed by modifying openings 732a and 732b by adding jumper opening portions 802 through a jumper patterning process. The jumper opening portion 802 can correspond to the positioning of the back-side conductive structure 542, which is integrally formed with the back-side conductive structures 332 and 338. In some aspects, structure 800A can be... Figure 6B The structure obtained in stage 681 corresponds to that in the middle.

[0110] like Figure 8B As shown, based on structure 800B, structure 800B can be formed by filling the back-side openings 732a to 732d and 802 with conductive or metallic materials to form back-side conductive structures 332, 333, 334, 338, and 542. In some aspects, the conductive or metallic material may include tungsten, cobalt, molybdenum, or combinations thereof. In some aspects, structure 800B may be combined with... Figure 6B The structure obtained in stage 683 corresponds to that in the previous stage. In some respects, the back-side dielectric layer 382 and the conductive structure disposed therein may be referred to as the first back-side metallization layer.

[0111] exist Figure 8B Subsequently, one or more back-side metallization layers may be formed, including a second back-side metallization layer and a third back-side metallization layer, wherein the second back-side metallization layer includes a conductive via (e.g., as a...). Figure 6B The conductive via structures 393 and 394 resulting from stage 688), the third back-side metallization layer includes other conductive structures (e.g., as...). Figure 6BThe conductive structure 242 is the result of stage 495 in the middle. In some respects, the resulting structure can be compared with... Figure 5A and Figure 5B The structure shown corresponds to 500.

[0112] In some respects, although Figures 3A to 8B The examples shown include a back-side conductive structure formed from a sacrificial structure formed from the front side based on a self-aligned scheme, but the back-side conductive structure can be formed entirely from the back side. In some aspects, the processes corresponding to stages 418 to 422 can be omitted, and the process corresponding to stage 480 can be modified to form the back-side conductive structure opening from the back side, without relying on the sacrificial structure formed from the front side.

[0113] Figure 9A This is a top view of a portion of a semiconductor structure 900 of an IC device according to various aspects of this disclosure. In some aspects, the semiconductor structure 900 may be a variation of the semiconductor structure 300, and the semiconductor structure 900 in... Figure 9A The portion above the shown element can be connected to Figure 3A This corresponds to a portion of the semiconductor structure 300 depicted in the diagram. In some respects, Figure 9A Combination Figure 3A Some components of the semiconductor structure 900 are shown for illustrative purposes only and may be arranged in... Figure 9A and Figure 3A Other elements above and / or below the elements shown, but... Figure 9A and Figure 3A Not shown in the image. (and...) Figures 3A to 3E Elements that are identical or similar to those in the drawings are given the same reference numerals, and their detailed descriptions may be omitted.

[0114] like Figure 9A As shown, with Figure 3B Compared to the semiconductor structure 300 depicted in the diagram, the semiconductor structure 900 includes alternatives. Figure 3B The back-side conductive structures 932, 933, 934, 937, and 938 of the middle back-side conductive structures 332, 333, 334, 337, and 338; and alternatives Figure 3B The back-side conductive structure 942 of the middle back-side conductive structure 342. In some aspects, instead of the back-side conductive structures 332, 333, 334, 337 and 338 formed based on a self-aligned scheme, the back-side conductive structures 932, 933, 934, 937 and 938 are formed by patterning the corresponding back-side dielectric layers from the back side of the semiconductor structure. In some aspects, a portion of the back-side conductive structure 942 may be disposed within the same back-side metallization layer where the conductive structures 332 and 338 are at least partially disposed.

[0115] Figure 9B Based on all aspects of this disclosure Figure 9A A cross-sectional view of a portion of the semiconductor structure 900 along a cut line R1, where details of the gate stacks 102, 104, 106, and 108 are simplified. Figure 9C Based on all aspects of this disclosure Figure 9A A cross-sectional view of a portion of the semiconductor structure 900 along a cut line R2, where details of the gate stacks 102, 104, 106, and 108 are simplified.

[0116] like Figure 9B As shown, the back-side conductive structure 932 is in contact with the S / D structure 122; the back-side conductive structure 933 is in contact with the S / D structure 123; and the back-side conductive structure 934 is in contact with the S / D structure 124. In some aspects, the back-side conductive structures 932, 933, and 934 are partially embedded in the back-side dielectric layer 382. In some aspects, the back-side dielectric layer 382 and the corresponding metallization structure disposed therein may be referred to as a first back-side metallization layer beneath the S / D structure.

[0117] Semiconductor structure 900 also includes via structures 953 and 954 embedded in a back-side dielectric layer 384 beneath a back-side dielectric layer 382, ​​and a back-side dielectric layer 386 embedded beneath a back-side dielectric layer 384. Figure 9C The back-side conductive structure 242 is located in the back-side conductive structure 242. In some aspects, the back-side dielectric layer 384 and the corresponding metallization structure disposed therein may be referred to as a second back-side metallization layer below the first back-side metallization layer. In some aspects, the back-side dielectric layer 386 and the corresponding metallization structure disposed therein may be referred to as a third back-side metallization layer below the second back-side metallization layer. Via structures 953 and 954 electrically connect the back-side conductive structures 932 and 934 to the back-side conductive structure 242, respectively. In addition, the back-side conductive structure 932 is electrically isolated from the back-side conductive structure 242 through the back-side dielectric layer 384.

[0118] like Figure 9CAs shown, the semiconductor structure 900 also includes a back-side conductive structure 942 embedded in the back-side dielectric layer 382 (e.g., in the first back-side metallization layer) and extending upward and partially within the front-side dielectric layer 370. Additionally, the dielectric structure 944 is disposed below the bottom gate electrode portion of the gate stack 102 (in the connection portion of the gate stack between the first gate structure and the second gate structure) and configured to electrically isolate the back-side conductive structure 942 from the bottom gate electrode portion of the connection portion of the gate stack 102. In some aspects, the dielectric structure 944 may be formed based on region-specific deposition (ASD) and may be referred to as an ASD structure. In some aspects, the back-side conductive structures 932 and 938 may extend along a first direction (e.g., the y-direction). In some aspects, the back-side conductive structure 942 may extend along a second direction (e.g., the x-direction) and contact the back-side conductive structures 932 and 938. In some aspects, the back-side conductive structure 942 may be integrally formed with the back-side conductive structures 932 and 938.

[0119] Therefore, as Figures 9A to 9C As shown, the semiconductor structure 900 may include a back-side conductive structure 932 that contacts the S / D structure 122 and is at least partially disposed in a rear portion of the semiconductor structure opposite to the front portion; a back-side conductive structure 938 that contacts the S / D structure 128 and is at least partially disposed in the rear portion of the semiconductor structure; and a back-side conductive structure 942 disposed in the rear portion of the semiconductor structure, extending along a second direction, and contacting the back-side conductive structures 932 and 938. In some aspects, a dielectric structure 944 may be disposed below a connection portion of the gate stack between the first gate structure and the second gate structure. In some aspects, the back-side conductive structure 942 may be at least partially disposed below the connection portion of the gate stack, and the dielectric structure 944 may be configured to electrically isolate the third back-side conductive structure 942 from the bottom gate electrode portion of the connection portion of the gate stack. In some aspects, the dielectric structure 944 may contact the bottom gate electrode portion of the connection portion of the gate stack. In some aspects, at least a portion of the back-side conductive structure 942 may extend above the lower surface of the gate stack and along the internal spacers of the connection portion of the gate stack.

[0120] Figure 10 This is a cross-sectional view of a portion of a semiconductor structure 1000 according to various aspects of this disclosure. In some aspects, the semiconductor structure 1000 may be a variation of the semiconductor structure 900.

[0121] like Figure 10 As shown, compared to semiconductor structure 900, semiconductor structure 1000 includes an etch stop layer 1032 between the front dielectric layer 370 and the STI structure 368. As a result, compared to... Figures 9A to 9BThe back-side conductive structure 1042 corresponding to the middle back-side conductive structure 942 may not extend beyond the etch stop layer 1032 and may not enter the front dielectric layer 370. Thus, in some respects, the entire back-side conductive structure 1042 may be below the connection portion of the gate stack.

[0122] Figure 11A and Figure 11B Examples of methods for manufacturing semiconductor structures according to various aspects of this disclosure are illustrated (e.g., Figures 9A to 9C Semiconductor structure 900 or Figure 10 The manufacturing process 1100 of the semiconductor structure 1000. In some aspects, Figure 11A The processing stage shown (labeled "Part A" of manufacturing process 1100) can correspond to the front-side processing of a semiconductor structure, because such a stage can correspond to the processes performed on the front side of a wafer from which a semiconductor structure is formed. In some aspects, Figure 11B The processing stage shown (labeled as “part B” of manufacturing process 1100) can correspond to the back-side processing of the wafer, because such a stage can correspond to a process performed from the back side of the wafer, which is opposite to the front side of the wafer.

[0123] In some respects, process 1100 can be Figures 4A to 4B A variation of process 400. (And...) Figures 4A to 4B Stages that are identical or similar to those in the accompanying drawings are given the same reference numerals, and their detailed descriptions may be omitted. In some respects, the process may include references to... Figures 4A to 4B The corresponding phases shown are 405, 415, 425, 435, 445, 455, 465 and 475, which are the same or similar to the corresponding phases.

[0124] Following stage 425, at stage 1130, an etch stop layer (e.g., etch stop layer 1032) may be formed, followed by the formation of a front-side dielectric layer 370 based on an ILD filling process. In some aspects, the etch stop layer formation portion at stage 1130 may be performed to form a semiconductor structure 1000. In some aspects, the etch stop layer formation portion at stage 1130 may be omitted to form a semiconductor structure 900.

[0125] After stage 475, at stage 1178, based on the BSC and / or BSCLI patterning process, openings for forming back-side conductive structures (e.g., back-side conductive structures 932, 933, 934, 937 and 938, and back-side conductive structure 942 or back-side conductive structure 1042) can be defined in the back-side dielectric layer 382 and through the corresponding portions of the epitaxial stop layer 362 and / or STI structure 368.

[0126] At stage 1180, a gate dielectric penetration process is performed to further expose the bottom gate electrode portion at the location where the back-side conductive structure 942 or 1042 of the gate stack is to be formed. In some aspects, the gate dielectric penetration process may extend the opening from stage 1178 further into the front dielectric layer 370.

[0127] At stage 1182, a dielectric structure (e.g., dielectric structure 944) may be formed beneath the bottom gate electrode portion of the gate stack, electrically isolating the bottom gate electrode portion from the subsequently formed back-side conductive structure. In some aspects, the dielectric structure disposed at stage 1182 may be an ASD structure. In some aspects, an ASD process is performed at stage 1182 to selectively grow an ASD structure on the surface of the exposed bottom gate electrode portion. In some aspects, the surface of the exposed bottom gate electrode portion may include titanium nitride (TiN) or tungsten (W), and the ASD structure may include silicon oxide, hafnium oxide, zirconium oxide, silicon nitride, aluminum nitride, or any combination thereof.

[0128] At stage 1184, the back-side opening from stage 1180 having the dielectric structure provided at stage 1182 can be silicide and / or filled with conductive or metallic material to form back-side conductive structures 932, 933, 934, 937, and 938, as well as back-side conductive structure 942 or back-side conductive structure 1042. In some aspects, back-side conductive structure 942 or back-side conductive structure 1042 can be integrally formed with back-side conductive structures 932 and 938.

[0129] At stage 1188, an additional back-side dielectric layer (e.g., back-side dielectric layer 384) is formed and patterned to define an opening for forming a via structure during the patterning process, and the opening is filled with one or more conductive materials during the metallization process to form a via structure.

[0130] Following stage 1188, at stage 495, further backside metallization processes may be performed to form additional metallization layers, including one or more power lines (e.g., backside conductive structures 242 and 244) and / or one or more signal lines. In some aspects, one or more conductive pads may be formed, wherein the resulting integrated circuit device based on the semiconductor structure described herein may be attached to another integrated circuit device, an interposer, or a package substrate via one or more conductive pads.

[0131] Figure 12 This is a cross-sectional view of a portion of a semiconductor structure 1200 according to various aspects of this disclosure. In some aspects, the semiconductor structure 1200 may be another variation of the semiconductor structure 900.

[0132] like Figure 12As shown, compared to semiconductor structure 900, semiconductor structure 1200 includes an etch stop layer 1232 below the connection portion of the gate stack. As a result, compared to... Figures 9A to 9B The back-side conductive structure 1242 corresponding to the middle back-side conductive structure 942 may not extend beyond the etch stop layer 1232 and may not enter the front dielectric layer 370. In addition, the dielectric structure 944 (e.g., ASD structure) may be omitted because the etch stop layer 1232 may be configured as a dielectric structure below the connection portion of the gate stack, so that the back-side conductive structure 1242 remains separated from the bottom gate electrode portion at the connection portion of the gate stack.

[0133] Figure 13A and Figure 13B Examples of methods for manufacturing semiconductor structures according to various aspects of this disclosure are illustrated (e.g., Figure 12 The manufacturing process 1300 of the semiconductor structure 1200. In some aspects, Figure 13A The processing stage shown (labeled "Part A" of manufacturing process 1300) corresponds to the front-side processing of a semiconductor structure, because such a stage corresponds to the processes performed on the front side of a wafer from which a semiconductor structure is formed. In some aspects, Figure 13B The processing stage shown (labeled as “Part B” of manufacturing process 1300) can correspond to the back-side processing of the wafer, because such a stage can correspond to a process performed from the back side of the wafer, which is opposite to the front side of the wafer.

[0134] In some respects, process 1300 can be Figures 4A to 4B The process 400 variant or Figures 11A to 11B A variation of process 1100. (And...) Figures 11A to 11B Stages that are identical or similar to those in the accompanying drawings are given the same reference numerals, and their detailed descriptions may be omitted. In some respects, the process may include references to... Figures 4A to 4B The corresponding phases shown are the same or similar to the corresponding phases 415, 425, 435, 445, 455, 465 and 475.

[0135] Prior to stage 415, at stage 1302, a multilayer structure can be formed on the substrate of the wafer. In some aspects, the multilayer structure may include different silicon material layers stacked on top of each other. In some aspects, the multilayer structure may include Si layers and SiGe layers stacked on top of each other as a silicon (Si) / silicon germanium (SiGe) stack. Additionally, at stage 1302, the active region of the semiconductor structure can be defined based on oxide diffusion (OD) patterning. In some aspects, an OD patterning process can be performed on the multilayer structure (e.g., a Si / SiGe stack) to shape the multilayer structure into a fin-like structure. In some aspects, stage 1302 can be combined with… Figure 4A This corresponds to the first half of stage 405 in the text.

[0136] At stage 1304, an isolation structure formation process is performed to form an isolation structure (e.g., an STI structure). Then, an etch stop layer spin coating process is performed to form an etch stop layer (e.g., etch stop layer 1232) on the substrate and the STI structure.

[0137] At stage 1306, a polysilicon material layer can be formed on the fin structure from stage 1302 and the etch stop layer from stage 1304, and a polysilicon gate patterning process can be performed on the polysilicon material layer to form a patterned polysilicon structure on the fin structure. In some aspects, stage 1302 can be combined with... Figure 4A This corresponds to the latter half of stage 405. Then, process 1300 can proceed to stage 415.

[0138] Furthermore, after stage 475, at stage 1378, based on the BSC and / or BSCLI patterning process, openings for forming back-side conductive structures (e.g., back-side conductive structures 932, 933, 934, 937 and 938 and back-side conductive structure 1242) can be defined in the back-side dielectric layer 382 and through the corresponding portions of the epitaxial stop layer 362 and / or STI structure 368.

[0139] At stage 1384, the back-side opening from stage 1378 may be silicide and / or filled with conductive or metallic material to form back-side conductive structures 932, 933, 934, 937, and 938, as well as back-side conductive structure 1242. In some aspects, back-side conductive structure 1242 may be integrally formed with back-side conductive structures 932 and 938.

[0140] At stage 1388, an additional back-side dielectric layer (e.g., back-side dielectric layer 384) is formed and patterned to define an opening for forming a via structure during the patterning process, and the opening is filled with one or more conductive materials during the metallization process to form a via structure.

[0141] Following stage 1388, at stage 495, further backside metallization processes may be performed to form additional metallization layers, including one or more power lines (e.g., backside conductive structures 242 and 244) and / or one or more signal lines. In some aspects, one or more conductive pads may be formed, wherein the resulting integrated circuit device based on the semiconductor structure described herein may be attached to another integrated circuit device, an interposer, or a package substrate via one or more conductive pads.

[0142] Figures 14A to 14E Examples of manufacturing according to various aspects of this disclosure Figures 9A to 9C The structure of the semiconductor structure at each stage of 900. Figures 14A to 14E Including along and Figure 9A The left cross-sectional view (denoted as "cutting line R1") corresponding to the cutting line R1 in the diagram; and along with... Figure 9A The right-side cross-section of the cutting line corresponding to the cutting line R2 in the diagram (denoted as "cutting line R2"). Figures 14A to 14E The shown with Figures 9A to 9C Elements that are identical or similar to those in the figures are given the same reference numerals, and their detailed descriptions may be omitted.

[0143] like Figure 14A As shown, structure 1400A is provided. Structure 1400A can be fabricated based on stages 405 to 445 without the need for... Figure 11A The stage 1130 is shown. Structure 1400A may include four gate stacks 102, 104, 106 and 108 on substrate 1410, an epitaxial stop layer 362 disposed on substrate 1410, an epitaxial layer 364 disposed on epitaxial stop layer 362, and a front dielectric layer 370 (e.g., a front ILD layer) on gate stacks 102, 104, 106 and 108 and epitaxial layer 364.

[0144] Additionally, structure 1400A includes S / D structures 122, 123, and 124 defined by epitaxial layers 364 between corresponding gate stack pairs 102 and 104, 104 and 106, and 102 and 108. STI structure 368 can be embedded in a region outside the active region of substrate 1410, corresponding to the positioning of the resulting transistor's S / D structure and channel structure. Figure 7F Compared to structure 700F, structure 1400A does not include sacrificial structures 722, 723, 724 and 728.

[0145] like Figure 14B As shown, structure 1400B is formed based on structure 1400A. In some aspects, one or more of the FEOL process, MOL process, or BEOL process can be performed on structure 1400A from the front side, and the wafer on which the semiconductor structure 1400A is formed can be bonded to a carrier and flipped for various further processes performed from the back side. In some aspects, a substrate thinning process can be performed from the back side to remove at least a portion of substrate 1410, and the remaining portion of substrate 1410 can be further removed during a silicon pillar removal process. Then, a back-side dielectric layer 382 can be formed. In some aspects, the back-side dielectric layer 382 may include silicon oxide. In some aspects, structure 1400B may be combined with... Figure 11B The structure obtained in stage 475 corresponds to that in the middle.

[0146] like Figure 14CAs shown, based on structure 1400B, structure 1400C is formed by performing a BSC and / or BSCLI patterning process to define openings 1420a, 1420b, 1420c, 1420d, and 1420e for forming back-side conductive structures (e.g., back-side conductive structures 932, 933, 934, 937, and 938, and back-side conductive structure 942), followed by a gate dielectric penetration process to define an enlarged opening portion 1420f, thereby further exposing the bottom gate electrode portion of the gate stack (where the back-side conductive structure 942 is to be formed), thus forming structure 1400C. In some aspects, structure 1400C may be compatible with... Figure 11B The structure obtained in stage 1180 corresponds to this.

[0147] like Figure 14D As shown, based on structure 1400C, structure 1400D is formed by forming a dielectric structure 944 below the bottom gate electrode portion of the gate stack and electrically isolating the bottom gate electrode portion from the subsequently formed back-side conductive structure. In some aspects, an ASD process is performed to selectively grow an ASD structure as the dielectric structure 944 on the surface exposed by the bottom gate electrode portion. In some aspects, structure 1400D can be coupled with... Figure 11B The structure obtained in stage 1182 corresponds to that in the middle.

[0148] like Figure 14E As shown, based on structure 1400D, structure 1400E is formed by filling back-side openings 1420a to 1420f (where dielectric structure 944 is formed) with conductive or metallic material to form back-side conductive structures 932, 933, 934, 938, and 942, thereby forming structure 1400E. In some aspects, back-side conductive structure 942 may extend along a second direction (e.g., the x-direction) and contact back-side conductive structures 932 and 938. In some aspects, the conductive or metallic material may include tungsten, cobalt, molybdenum, or combinations thereof. In some aspects, structure 1400E may be compatible with... Figure 11B This corresponds to the structure obtained in stage 1184. In some respects, the back-side dielectric layer 382 and the conductive structure disposed therein may be referred to as the first back-side metallization layer.

[0149] exist Figure 14E Subsequently, one or more back-side metallization layers may be formed, including a second back-side metallization layer and a third back-side metallization layer, wherein the second back-side metallization layer includes a conductive via (e.g., as a...). Figure 11B The conductive vias 953 and 954 resulting from stage 1188), the third back-side metallization layer includes other conductive structures (e.g., as...). Figure 11B The conductive structure 242 is the result of stage 495 in the middle. In some respects, the resulting structure can be compared with... Figures 9A to 9C The structure shown corresponds to 900.

[0150] Figures 15A to 15D Examples of manufacturing processes according to various aspects of this disclosure are illustrated. Figure 10 The structure at each stage of the semiconductor structure 1000 is a variation of the semiconductor structure 900 in Figure 9. Figures 15A to 15D Including along and Figure 9A The left cross-sectional view (denoted as "cutting line R1") corresponding to the cutting line R1 in the diagram; and along with... Figure 9A The right-side cross-section of the cutting line corresponding to the cutting line R2 in the diagram (denoted as "cutting line R2"). Figures 15A to 15D The shown with Figures 9A to 9C and Figure 10 Elements that are identical or similar to those in the drawings are given the same reference numerals, and their detailed descriptions may be omitted.

[0151] like Figure 15A As shown, structure 1500A is provided. (The text abruptly ends here.) Figure 14B Compared to structure 1400B, structure 1500A also includes an etch stop layer 1032 on the side outside the region where the channel structure and S / D structure can be formed, between the front dielectric layer 370 and the STI structure 368, along the gate stacks 102, 104, 106 and 108.

[0152] like Figure 15B As shown, based on structure 1500A, structure 1500B is formed by performing a BSC and / or BSCLI patterning process to define openings 1520a, 1520b, 1520c, 1520d, and 1520e for forming back-side conductive structures (e.g., back-side conductive structures 932, 933, 934, 937, and 938, and back-side conductive structure 1042), followed by a gate dielectric penetration process to extend the opening portion 1520e, thereby further exposing the bottom gate electrode portion of the gate stack (where the back-side conductive structure 1042 is to be formed), thus forming structure 1500B. In some aspects, structure 1500B can be combined with... Figure 11B The structure obtained in stage 1180 corresponds to this.

[0153] like Figure 15C As shown, based on structure 1500B, structure 1500C is formed by forming a dielectric structure 944 below the bottom gate electrode portion of the gate stack and electrically isolating the bottom gate electrode portion from the subsequently formed back-side conductive structure. In some aspects, an ASD process is performed to selectively grow an ASD structure as the dielectric structure 944 on the surface exposed by the bottom gate electrode portion. In some aspects, structure 1500C can be coupled with... Figure 11B The structure obtained in stage 1182 corresponds to that in the middle.

[0154] like Figure 15DAs shown, based on structure 1500C, structure 1500D is formed by filling the back-side openings 1520a to 1520e (where a dielectric structure 944 is formed) with conductive or metallic material to form back-side conductive structures 932, 933, 934, 938, and 1042, thereby forming structure 1500D. In some aspects, the back-side conductive structure 1042 may extend along a second direction (e.g., the x-direction) and contact the back-side conductive structures 932 and 938. In some aspects, the conductive or metallic material may include tungsten, cobalt, molybdenum, or combinations thereof. In some aspects, structure 1500D may be compatible with... Figure 11B This corresponds to the structure obtained in stage 1184. In some respects, the back-side dielectric layer 382 and the conductive structure disposed therein may be referred to as the first back-side metallization layer.

[0155] In some respects, because the etch stop layer 1032 prevents the opening from extending into the front dielectric layer 370, the back conductive structure 1042 may not extend beyond the etch stop layer 1032 and may not enter the front dielectric layer 370.

[0156] exist Figure 15D Subsequently, one or more back-side metallization layers may be formed, including a second back-side metallization layer and a third back-side metallization layer, wherein the second back-side metallization layer includes a conductive via (e.g., as a...). Figure 11B The conductive vias 953 and 954 resulting from stage 1188), the third back-side metallization layer includes other conductive structures (e.g., as...). Figure 11B The conductive structure 242 is the result of stage 495 in the middle. In some respects, the resulting structure can be compared with... Figure 10 The structure shown corresponds to 1000.

[0157] Figures 16A to 16C Examples of manufacturing processes according to various aspects of this disclosure are illustrated. Figure 12 The structure at each stage of the semiconductor structure 1200 is another variation of the semiconductor structure 900 in Figure 9. Figures 16A to 16C Including along and Figure 9A The left cross-sectional view (denoted as "cutting line R1") corresponding to the cutting line R1 in the diagram; and along with... Figure 9A The right-side cross-section of the cutting line corresponding to the cutting line R2 in the diagram (denoted as "cutting line R2"). Figures 16A to 16C The shown with Figures 9A to 9C and Figure 12 Elements that are identical or similar to those in the drawings are given the same reference numerals, and their detailed descriptions may be omitted.

[0158] like Figure 16A As shown, structure 1600A is provided. (Compared to...) Figure 14BCompared to structure 1400B, structure 1600A also includes an etch stop layer 1232 between the front dielectric layer 370 and the STI structure 368, and outside the region where the channel structure and S / D structure can be formed below the gate stacks 102, 104, 106 and 108.

[0159] like Figure 16B As shown, based on structure 1600A, structure 1600B is formed by performing a BSC and / or BSCLI patterning process to define openings 1620a, 1620b, 1620c, 1620d, and 1620e for forming back-side conductive structures (e.g., back-side conductive structures 932, 933, 934, 937, and 938, and back-side conductive structure 1242). In some aspects, structure 1600B may be associated with... Figure 13B The structure obtained in stage 1378 corresponds to that in the middle.

[0160] like Figure 16C As shown, based on structure 1600B, structure 1600C is formed by filling the back-side openings 1620a to 1620e with conductive or metallic material to form back-side conductive structures 932, 933, 934, 938, and 1242. In some aspects, the back-side conductive structure 1242 may extend along a second direction (e.g., the x-direction) and contact the back-side conductive structures 932 and 938. In some aspects, the conductive or metallic material may include tungsten, cobalt, molybdenum, or combinations thereof. In some aspects, structure 1600C may be compatible with... Figure 13B This corresponds to the structure obtained in stage 1384. In some respects, the back-side dielectric layer 382 and the conductive structure disposed therein may be referred to as the first back-side metallization layer.

[0161] In some respects, because the etch stop layer 1232 prevents the opening from extending into the front dielectric layer 370, the back conductive structure 1042 may not extend beyond the etch stop layer 1032 and may not enter the front dielectric layer 370. Additionally, the dielectric structure 944 may be omitted.

[0162] exist Figure 16C Subsequently, one or more back-side metallization layers may be formed, including a second back-side metallization layer and a third back-side metallization layer, wherein the second back-side metallization layer includes a conductive via (e.g., as a...). Figure 13B The conductive vias 953 and 954 resulting from stage 1388), the third back-side metallization layer includes other conductive structures (e.g., as...). Figure 13B The conductive structure 242 is the result of stage 495 in the middle. In some respects, the resulting structure can be compared with... Figure 12 The structure shown corresponds to 1200.

[0163] Figure 17Examples of methods for manufacturing semiconductor structures (such as...) according to various aspects of this disclosure are illustrated. Figures 3A to 3E , Figures 5A to 5B , Figures 9A to 9C , Figure 10 and Figure 12 Method 1700 (example of semiconductor structure depicted in the text).

[0164] At operation 1710, a gate stack (e.g., gate stack 102) is formed, wherein the gate stack extends in the front portion of the semiconductor structure along a first direction (e.g., the y-direction). In some aspects, the gate stack may include a first gate structure and a second gate structure, and the second gate structure is offset from the first gate structure in the first direction. In some aspects, a first S / D structure (e.g., S / D structure 122) may be disposed adjacent to the first gate structure, and a second S / D structure (e.g., S / D structure 128) may be disposed adjacent to the first gate structure, and the first S / D structure and the second S / D structure are offset from each other in a second direction (e.g., the x-direction). In some aspects, it may be based on Figure 4A , Figure 6A , Figure 11A ,or Figure 13A In stages 405 to 445, the gate stack is formed, and the resulting structure can be used with... Figure 7G , Figure 14B , Figure 15A ,or Figure 16A The structure corresponds to that in the text.

[0165] At operation 1720, a first back-side conductive structure (e.g., back-side conductive structure 332 or 932) may be formed. The first back-side conductive structure may be in contact with the first S / D structure and is at least partially disposed in the rear portion of the semiconductor structure opposite to the front portion.

[0166] At operation 1730, a second back-side conductive structure (e.g., back-side conductive structure 338 or 938) may be formed. The second back-side conductive structure may contact the second S / D structure and is at least partially disposed in the rear portion of the semiconductor structure.

[0167] At operation 1740, a third back-side conductive structure (e.g., back-side conductive structure 342, 542, 942, 1042, or 1242) may be formed. The third back-side conductive structure may be disposed in the rear portion of the semiconductor structure. In some aspects, the third back-side conductive structure may extend along a second direction and contact the first and second back-side conductive structures.

[0168] In some aspects, the first and second back-side conductive structures may be formed within a first back-side metallization layer beneath the first and second S / D structures, and the third back-side conductive structure may be formed within a second back-side metallization layer beneath the first back-side metallization layer. In some aspects, method 1700 may further include forming a fourth back-side conductive structure (e.g., via structures 393, 394, 953, and / or 954) within the second back-side metallization layer, and forming a metallization structure (e.g., back-side conductive structures 242 and / or 244) disposed within a third back-side metallization layer beneath the second back-side metallization layer, the fourth back-side conductive structure connecting the metallization structure to another back-side conductive structure in the first back-side metallization layer.

[0169] In some aspects, method 1700 may further include forming a dielectric structure below the connection portion of the gate stack between the first gate structure and the second gate structure. In some aspects, a third back-side conductive structure may be formed at least partially below the connection portion of the gate stack, and the dielectric structure may be configured to electrically isolate the third back-side conductive structure from the bottom gate electrode portion of the connection portion of the gate stack.

[0170] In some aspects, forming the dielectric structure may include removing a portion of the gate dielectric portion of the gate stack connection portion to expose the bottom gate electrode portion of the gate stack connection portion; and performing a region-selective deposition process to form the dielectric structure. In some aspects, forming the third back-side conductive structure may include removing a portion of the front interlayer dielectric layer adjacent to the internal spacer of the gate stack connection portion to define an opening. In some aspects, the third back-side conductive structure is formed in the opening such that at least a portion of the third back-side conductive structure extends above the lower surface of the gate stack and along the internal spacer of the gate stack connection portion.

[0171] In some respects, the semiconductor structure obtained based on method 1700 can be compared with... Figures 3A to 3ECorresponding to the semiconductor structure 300 shown, the semiconductor structure 300 may include a back-side conductive structure 332 that contacts the S / D structure 122 and is at least partially disposed in the rear portion of the semiconductor structure opposite to the front portion; a back-side conductive structure 338 that contacts the S / D structure 128 and is at least partially disposed in the rear portion of the semiconductor structure; and a back-side conductive structure 342 disposed in the rear portion of the semiconductor structure, extending along a second direction, and contacting the back-side conductive structures 332 and 338. In some aspects, the back-side conductive structures 332 and 338 may be disposed within a first back-side metallization layer below the S / D structures 122 and 128, and the back-side conductive structure 342 may be disposed within a second back-side metallization layer below the first back-side metallization layer. In some aspects, the back-side conductive structures (e.g., via structures 393 and 394) may be disposed within the second back-side metallization layer. In some aspects, the metallization structure (e.g., back-side conductive structure 242 or 244) may be disposed within a third back-side metallization layer beneath the second back-side metallization layer. In some aspects, one or more via structures may be configured to connect the metallization structure to another back-side conductive structure in the first back-side metallization layer.

[0172] In some respects, the semiconductor structure obtained based on method 1700 can be compared with... Figures 5A to 5B Corresponding to the semiconductor structure 500 shown, the semiconductor structure 500 may include a back-side conductive structure 332 that contacts the S / D structure 122 and is at least partially disposed in the rear portion of the semiconductor structure opposite to the front portion; a back-side conductive structure 338 that contacts the S / D structure 128 and is at least partially disposed in the rear portion of the semiconductor structure; and a back-side conductive structure 542 disposed in the rear portion of the semiconductor structure, extending along a second direction, and contacting the back-side conductive structures 332 and 338. In some aspects, the back-side conductive structures 332 and 338 may be disposed within a first back-side metallization layer below the S / D structures 122 and 128, and the back-side conductive structure 542 may be disposed within a lower portion of the first back-side metallization layer. In some aspects, the back-side conductive structures (e.g., via structures 393 and 394) may be disposed within a second back-side metallization layer. In some aspects, the metallization structure (e.g., back-side conductive structure 242 or 244) may be disposed within a third back-side metallization layer beneath the second back-side metallization layer. In some aspects, one or more via structures may be configured to connect the metallization structure to another back-side conductive structure in the first back-side metallization layer.

[0173] In some respects, the semiconductor structure obtained based on method 1700 can be compared with... Figures 9A to 9CCorresponding to the semiconductor structure 900 shown, the semiconductor structure 900 may include a back-side conductive structure 932 that contacts the S / D structure 122 and is at least partially disposed in the rear portion of the semiconductor structure opposite to the front portion; a back-side conductive structure 938 that contacts the S / D structure 128 and is at least partially disposed in the rear portion of the semiconductor structure; and a back-side conductive structure 942 disposed in the rear portion of the semiconductor structure, extending along a second direction, and contacting the back-side conductive structures 932 and 938. In some aspects, a dielectric structure 944 may be disposed below the connection portion of the gate stack between the first gate structure and the second gate structure. In some aspects, the back-side conductive structure 942 may be at least partially disposed below the connection portion of the gate stack, and the dielectric structure 944 may be configured to electrically isolate the third back-side conductive structure 942 from the bottom gate electrode portion of the connection portion of the gate stack. In some aspects, the dielectric structure 944 may contact the bottom gate electrode portion of the connection portion of the gate stack. In some respects, at least a portion of the back-side conductive structure 942 may extend above the lower surface of the gate stack and along the internal spacers of the connection portion of the gate stack.

[0174] In some respects, the semiconductor structure obtained based on method 1700 can be compared with... Figure 10 Corresponding to the semiconductor structure 1000 shown, the entire back-side conductive structure 1042 of the semiconductor structure 1000 is located below the connection portion of the gate stack. In some aspects, the semiconductor structure obtained based on method 1700 can be compared with... Figure 12 Corresponding to the semiconductor structure 1200 shown, the semiconductor structure 1200 may include an etch stop layer 1232 configured as a dielectric structure below the connection portion of the gate stack, so that the back-side conductive structure 1242 remains separated from the bottom gate electrode portion at the connection portion of the gate stack.

[0175] The technical advantage of method 1700 is that it forms a back-side conductive structure (e.g., BSC and BSCLI) configured to extend in two different directions along the rear portion of the semiconductor structure used to form interconnects in the integrated circuit device (i.e., back-side bidirectional interconnects) to provide additional routing capabilities or the ability to fabricate integrated circuit devices. As a result, IC devices can be fabricated based on more compact standard cells, thereby improving their area scaling.

[0176] Figure 18 A mobile device 1800 according to various aspects of this disclosure is illustrated. In some aspects, the mobile device 1800 may be implemented by including one or more IC devices manufactured based on the examples described in this disclosure.

[0177] In some aspects, the mobile device 1800 can be configured as a wireless communication device. As shown, the mobile device 1800 includes a processor 1801. The processor 1801 is communicatively coupled to a memory 1832 via a link, which may be a die-to-die or chip-to-chip link. The mobile device 1800 also includes a display 1828 and a display controller 1826, wherein the display controller 1826 is coupled to the processor 1801 and the display 1828. The mobile device 1800 may include an input device 1830 (e.g., a physical or virtual keyboard), a power supply 1844 (e.g., a battery), a speaker 1836, a microphone 1838, and a wireless antenna 1842. In some aspects, the power supply 1844 may directly or indirectly provide power voltages for some or all of the components of the mobile device 1800.

[0178] In some respects, Figure 18 It may include a decoder / decoder (codec) 1834 (e.g., an audio and / or voice codec) coupled to processor 1801; a speaker 1836 and a microphone 1838 coupled to codec 1834; and a wireless circuit 1840 (which may include a modem, RF circuitry, filter, etc.) coupled to wireless antenna 1842 and coupled to processor 1801.

[0179] In some aspects, one or more of the processor 1801, display controller 1826, memory 1832, codec 1834, and wireless circuit 1840 may include one or more IC devices, the IC devices including semiconductor structures manufactured according to the examples described in this disclosure.

[0180] It should be noted that, although Figure 18 Mobile device 1800 is described, but devices including set-top boxes, music players, video players, entertainment units, navigation devices, personal digital assistants (PDAs), fixed location data units, computers, laptops, tablets, communication devices, mobile phones, or other similar devices can be implemented using a similar architecture.

[0181] Figure 19Examples of various electronic devices that may integrate any of the following: the aforementioned devices, semiconductor devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, electronic components, interposer packages, stacked package (PoP), system-in-package (SiP), or system-on-a-chip (SoC). For example, mobile phone device 1902, laptop computer device 1904, fixed-location terminal device 1906, wearable device 1908, or motor vehicle 1910 may include semiconductor devices 1900 as described herein (e.g., semiconductor devices including semiconductor structures 100, 200, 500, or 600). Figure 19 The devices 1902, 1904, 1906, and 1908, and the vehicle 1910 illustrated herein are merely exemplary. Other devices or apparatuses may also feature the semiconductor device 1900, including but not limited to devices comprising the group consisting of: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading devices), communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0182] Figures 1 to 19 One or more of the components, processes, features, and / or functions illustrated herein may be rearranged and / or combined into a single component, process, feature, or function, or incorporated into several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from this disclosure. In some specific embodiments, Figures 1 to 19 The corresponding descriptions can be used to manufacture, form, provide, and / or produce integrated devices. In some specific implementations, the equipment may include dies, integrated devices, die packages, ICs, device packages, IC packages, wafers, semiconductor devices, system-in-package (SiP), system-on-chip (SoC), and stacked-package (PoP) devices, etc.

[0183] As used herein, the terms “user equipment” (or “UE”), “user device,” “user terminal,” “client device,” “communication device,” “wireless device,” “wireless communication device,” “handheld device,” “mobile device,” “mobile terminal,” “mobile station,” “phone,” “access terminal,” “subscriber device,” “subscriber terminal,” “subscriber station,” “terminal,” and variations thereof may interchangeably refer to any suitable mobile or stationary device capable of receiving wireless communication and / or navigation signals. These terms include, but are not limited to, music players, video players, entertainment units, navigation devices, communication devices, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, onboard equipment in motor vehicles, and / or other types of portable electronic devices that are typically carried by an individual and / or have communication capabilities (e.g., wireless, cellular, infrared, short-range radio, etc.). These terms are also intended to include devices that communicate with another device capable of receiving wireless communication and / or navigation signals (such as via short-range wireless, infrared, wired, or other connections), regardless of whether satellite signal reception, auxiliary data reception, and / or positioning-related processing occur at that device or at that other device. The UE can be implemented using any of several types of devices, including but not limited to printed circuit (PC) cards, dense flash memory devices, external or internal modems, wireless or wired phones, smartphones, tablet devices, consumer tracking devices, asset tags, etc.

[0184] Wireless communication between electronic devices can be based on different technologies, such as Code Division Multiple Access (CDMA), W-CDMA, Time Division Multiple Access (TDMA), Frequency Division Multiple Access (FDMA), Orthogonal Frequency Division Multiplexing (OFDM), Global System for Mobile Communications (GSM), 3GPP Long Term Evolution (LTE), 5G New Radio, and Bluetooth. ® (BT), Bluetooth ® Low Energy (BLE), IEEE 802.11 (WiFi) and IEEE 802.15.4 (Zigbee) ® / Thread) or other protocols that can be used in wireless communication networks or data communication networks.

[0185] As can be seen in the detailed description above, different features are grouped together in the examples. This manner of disclosure should not be construed as an intention to have more features than those explicitly mentioned in each clause. Rather, the various aspects of this disclosure may include fewer features than those in the individual example clauses disclosed. Therefore, the following clauses should be regarded accordingly as incorporated into the description, where each clause may serve as a separate example. Although each dependent clause may refer in the clause to a specific combination with one of the other clauses, the aspect of that dependent clause is not limited to that specific combination. It should be understood that other example clauses may also include combinations of aspects of a dependent clause with the subject matter of any other dependent or independent clause, or combinations of any feature with other dependent and independent clauses. The various aspects disclosed herein explicitly include these combinations unless explicitly stated or readily inferred that a particular combination is not intended for use (e.g., contradictory aspects, such as defining an element as both an electrical insulator and an electrical conductor). Furthermore, it is contemplated that aspects of a clause may be included in any other independent clause, even if that clause does not directly depend on the independent clause.

[0186] Specific implementation examples are described in the following numbered clauses:

[0187] Clause 1. A semiconductor structure comprising: a gate stack extending in a front portion of the semiconductor structure along a first direction, the gate stack including a first gate structure and a second gate structure offset from each other in the first direction; a first source / drain (S / D) structure adjacent to the first gate structure; a second S / D structure adjacent to the second gate structure and offset from the first S / D structure in a second direction; a first back-side conductive structure contacting the first S / D structure and at least partially disposed in a rear portion of the semiconductor structure opposite to the front portion; a second back-side conductive structure contacting the second S / D structure and at least partially disposed in the rear portion of the semiconductor structure; and a third back-side conductive structure disposed in the rear portion of the semiconductor structure, the third back-side conductive structure extending in the second direction and contacting the first back-side conductive structure and the second back-side conductive structure.

[0188] Clause 2. The semiconductor structure according to Clause 1, wherein: the first back-side conductive structure and the second back-side conductive structure are disposed within a first back-side metallization layer below the first S / D structure and the second S / D structure, and the third back-side conductive structure is disposed within a second back-side metallization layer below the first back-side metallization layer.

[0189] Clause 3. The semiconductor structure according to Clause 2 further includes: a fourth back-side conductive structure, the fourth back-side conductive structure being within the second back-side metallization layer; and a metallization structure disposed within a third back-side metallization layer below the second back-side metallization layer, the fourth back-side conductive structure connecting the metallization structure to another back-side conductive structure in the first back-side metallization layer.

[0190] Clause 4. The semiconductor structure according to Clause 1, wherein: the first back-side conductive structure and the second back-side conductive structure are disposed within a first back-side metallization layer below the first S / D structure and the second S / D structure, and the third back-side conductive structure is disposed within a lower portion of the first back-side metallization layer.

[0191] Clause 5. The semiconductor structure according to Clause 4 further includes: a fourth back-side conductive structure, the fourth back-side conductive structure being located within a second back-side metallization layer below the first back-side metallization layer; and a metallization structure disposed within a third back-side metallization layer below the second back-side metallization layer, the fourth back-side conductive structure connecting the metallization structure to another back-side conductive structure in the first back-side metallization layer.

[0192] Clause 6. The semiconductor structure according to any one of Clauses 1 to 5, the semiconductor structure further comprising: a dielectric structure below the connection portion of the gate stack between the first gate structure and the second gate structure, wherein: the third back-side conductive structure is at least partially disposed below the connection portion of the gate stack, the dielectric structure being configured to electrically isolate the third back-side conductive structure from the bottom gate electrode portion of the connection portion of the gate stack.

[0193] Clause 7. The semiconductor structure according to Clause 6, wherein: the dielectric structure is in contact with the bottom gate electrode portion of the connection portion of the gate stack.

[0194] Clause 8. The semiconductor structure according to Clause 7, wherein: at least a portion of the third back-side conductive structure extends above the lower surface of the gate stack and along the internal spacers of the connection portion of the gate stack.

[0195] Clause 9. The semiconductor structure according to Clause 6 or Clause 7, wherein: the entire third back-side conductive structure is beneath the connection portion of the gate stack.

[0196] Clause 10. A semiconductor structure according to Clause 6, Clause 7, or Clause 9, wherein: the dielectric structure includes an etch stop layer beneath the connection portion of the gate stack.

[0197] Clause 11. A method of manufacturing a semiconductor structure, the method comprising: forming a gate stack extending in a front portion of the semiconductor structure along a first direction, the gate stack including a first gate structure and a second gate structure, the second gate structure being offset from the first gate structure in the first direction, a first S / D structure disposed adjacent to the first gate structure, a second S / D structure disposed adjacent to the second gate structure, and the first S / D structure and the second S / D structure being offset from each other in a second direction; forming a first back-side conductive structure contacting the first S / D structure and being at least partially disposed in a rear portion of the semiconductor structure opposite to the front portion; forming a second back-side conductive structure contacting the second S / D structure and being at least partially disposed in the rear portion of the semiconductor structure; and forming a third back-side conductive structure disposed in the rear portion of the semiconductor structure, the third back-side conductive structure extending in the second direction and contacting the first back-side conductive structure and the second back-side conductive structure.

[0198] Clause 12. The method according to Clause 11, wherein: the first back-side conductive structure and the second back-side conductive structure are formed in a first back-side metallization layer below the first S / D structure and the second S / D structure, and the third back-side conductive structure is formed in a second back-side metallization layer below the first back-side metallization layer.

[0199] Clause 13. The method according to Clause 12, the method further comprising: forming a fourth back-side conductive structure within the second back-side metallization layer; and forming a metallization structure disposed within a third back-side metallization layer below the second back-side metallization layer, the fourth back-side conductive structure connecting the metallization structure to another back-side conductive structure in the first back-side metallization layer.

[0200] Clause 14. The method according to Clause 11, wherein: the first back-side conductive structure and the second back-side conductive structure are formed within a first back-side metallization layer below the first S / D structure and the second S / D structure, and the third back-side conductive structure is formed within a lower portion of the first back-side metallization layer.

[0201] Clause 15. The method according to Clause 14, the method further comprising: forming a fourth back-side conductive structure in a second back-side metallization layer below the first back-side metallization layer; and forming a metallization structure in a third back-side metallization layer below the second back-side metallization layer, the fourth back-side conductive structure connecting the metallization structure to another back-side conductive structure in the first back-side metallization layer.

[0202] Clause 16. The method according to any one of Clauses 11 to 15, the method further comprising: forming a dielectric structure below a connection portion of the gate stack between the first gate structure and the second gate structure, wherein: the third back-side conductive structure is formed at least partially below the connection portion of the gate stack, the dielectric structure being configured to electrically isolate the third back-side conductive structure from a bottom gate electrode portion of the connection portion of the gate stack.

[0203] Clause 17. The method of Clause 16, wherein forming the dielectric structure comprises: removing a portion of the gate dielectric portion of the connection portion of the gate stack to expose the bottom gate electrode portion of the connection portion of the gate stack; and performing a region-selective deposition process to form the dielectric structure.

[0204] Clause 18. The method according to Clause 17, wherein forming the third back-side conductive structure comprises: removing a portion of a front-side interlayer dielectric layer adjacent to an internal spacer of the connection portion of the gate stack to define an opening, wherein the third back-side conductive structure is formed in the opening such that at least a portion of the third back-side conductive structure extends above the lower surface of the gate stack and along the internal spacer of the connection portion of the gate stack.

[0205] Clause 19. The method according to Clause 17, wherein: the entire third back-side conductive structure is beneath the connection portion of the gate stack.

[0206] Clause 20. The method according to Clause 16, the method further comprising: forming an etch stop layer as the dielectric structure beneath the connection portion of the gate stack.

[0207] Clause 21. An electronic device comprising: an integrated circuit device including a semiconductor structure, the semiconductor structure including: a gate stack extending in a front portion of the semiconductor structure along a first direction, the gate stack including a first gate structure and a second gate structure offset from each other in the first direction; a first source / drain (S / D) structure adjacent to the first gate structure; a second S / D structure adjacent to the second gate structure, the second S / D structure being offset from the first S / D structure in a second direction; a first back-side conductive structure contacting the first S / D structure and at least partially disposed in a rear portion of the semiconductor structure opposite to the front portion; a second back-side conductive structure contacting the second S / D structure and at least partially disposed in the rear portion of the semiconductor structure; and a third back-side conductive structure disposed in the rear portion of the semiconductor structure, the third back-side conductive structure extending in the second direction and contacting the first back-side conductive structure and the second back-side conductive structure.

[0208] Clause 22. The electronic device according to Clause 21, wherein: the first back-side conductive structure and the second back-side conductive structure are disposed within a first back-side metallization layer below the first S / D structure and the second S / D structure, and the third back-side conductive structure is disposed within a second back-side metallization layer below the first back-side metallization layer.

[0209] Clause 23. The electronic device according to Clause 22, wherein the semiconductor structure further comprises: a fourth back-side conductive structure, the fourth back-side conductive structure being within the second back-side metallization layer; and a metallization structure disposed within a third back-side metallization layer below the second back-side metallization layer, the fourth back-side conductive structure connecting the metallization structure to another back-side conductive structure in the first back-side metallization layer.

[0210] Clause 24. The electronic device according to Clause 21, wherein: the first back-side conductive structure and the second back-side conductive structure are disposed within a first back-side metallization layer below the first S / D structure and the second S / D structure, and the third back-side conductive structure is disposed within a lower portion of the first back-side metallization layer.

[0211] Clause 25. The electronic device according to Clause 24, wherein the semiconductor structure further comprises: a fourth back-side conductive structure, the fourth back-side conductive structure being disposed within a second back-side metallization layer below the first back-side metallization layer; and a metallization structure disposed within a third back-side metallization layer below the second back-side metallization layer, the fourth back-side conductive structure connecting the metallization structure to another back-side conductive structure in the first back-side metallization layer.

[0212] Clause 26. An electronic device according to any one of Clauses 21 to 25, wherein the semiconductor structure further comprises: a dielectric structure below a connection portion of the gate stack between the first gate structure and the second gate structure, wherein a third back-side conductive structure is at least partially disposed below the connection portion of the gate stack, the dielectric structure being configured to electrically isolate the third back-side conductive structure from a bottom gate electrode portion of the connection portion of the gate stack.

[0213] Clause 27. The electronic device according to Clause 26, wherein: the dielectric structure is in contact with the bottom gate electrode portion of the connection portion of the gate stack.

[0214] Clause 28. The electronic device according to Clause 27, wherein: at least a portion of the third back-side conductive structure extends above the lower surface of the gate stack and along the internal spacers of the connection portion of the gate stack.

[0215] Clause 29. An electronic device according to Clause 26 or Clause 27, wherein: the entire third back-side conductive structure is beneath the connection portion of the gate stack.

[0216] Clause 30. An electronic device according to Clause 26, Clause 27, or Clause 29, wherein: the dielectric structure includes an etch stop layer beneath the connection portion of the gate stack.

[0217] Clause 31. An electronic device pursuant to any one of Clauses 21 to 30, wherein the electronic device includes a music player, video player, entertainment unit, navigation device, communication device, mobile device, mobile phone, smartphone, personal digital assistant, fixed-location terminal, tablet computer, computer, wearable device, laptop computer, server, Internet of Things (IoT) device, or device in a motor vehicle.

[0218] It should be noted that the terms “connection,” “coupling,” or any variation thereof mean any direct or indirect connection or coupling between elements, and may cover the presence of an intermediate element between two elements through which the two elements are “connected” or “coupled” together, unless the connection is explicitly disclosed as a direct connection.

[0219] The use of designations such as "first," "second," etc., to refer to elements in this document does not limit the number and / or order of those elements. Rather, these designations are used as a convenient way to distinguish two or more elements and / or instances of elements. Moreover, unless otherwise stated, a collection of elements may include one or more elements.

[0220] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and arts. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0221] Nothing described or illustrated in this application is intended to offer any component, action, feature, benefit, advantage, or equivalent to the public, whether or not such component, action, feature, benefit, advantage, or equivalent is stated in the claims.

[0222] Furthermore, it should be noted that the methods, systems, and apparatuses disclosed in this description or claims may be implemented by devices including components for performing corresponding actions and / or functions of the disclosed methods. Moreover, while the foregoing disclosure illustrates illustrative aspects of this disclosure, it should be noted that various changes and modifications may be made herein without departing from the scope of this disclosure as defined by the appended claims. For example, the functions, steps, and / or actions of the method claims according to the aspects of this disclosure described herein do not need to be performed in any particular order.

[0223] Furthermore, no component, function, action, or instruction described or claimed herein should be construed as critical or essential unless explicitly stated otherwise. Additionally, as used herein, the terms “set” and “group,” etc., are intended to include one or more items and are interchangeable with “at least one” and “one or more,” etc. Moreover, as used herein, the terms “having,” etc., are intended to be open-ended terms that do not limit the elements they modify (e.g., an element “having” A may also have B). Furthermore, the phrase “based on” is intended to mean “at least partially based on,” unless otherwise explicitly stated. Moreover, as used herein, the term “or,” when used in a series, is intended to be open-ended and is interchangeable with “and / or,” unless otherwise explicitly stated (e.g., if used in conjunction with “any” or “only one,” or these alternatives are mutually exclusive (e.g., “one or more” should not be construed as “one and more”). Furthermore, although components, functions, actions, and instructions may be described or claimed in the singular, plural forms may also be considered unless explicitly stated as limited to the singular. Therefore, as used herein, the articles “a,” “an,” “the,” and “the” are intended to include one or more items and are interchangeable with “at least one” and “one or more.” Additionally, as used herein, the terms “at least one” and “one or more” include performing or being able to perform “one” component, function, action, or instruction of the described or claimed functionality, and also include performing or being able to perform “two or more” components, functions, actions, or instructions of the described or claimed functionality in combination. In some examples, a single action may be subdivided into one or more sub-actions or may include one or more sub-actions. Such sub-actions may be included in the disclosure of a single action and may be part of the disclosure of a single action.

[0224] Furthermore, those skilled in the art will understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in connection with the aspects disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, various exemplary components, blocks, modules, circuits, and steps have been described above in general terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be construed as departing from the scope of this disclosure.

[0225] The various exemplary logic blocks, modules, and circuits described in conjunction with the aspects disclosed herein can be implemented or executed using general-purpose processors, DSPs, ASICs, FPGAs, or other programmable logic devices, discrete gate or transistor logic elements, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but in alternatives, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0226] The methods, sequences, and / or algorithms described in conjunction with the aspects disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or a combination of both. The software module may reside in random access memory (RAM), flash memory, read-only memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art. Example storage media are coupled to a processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium may be integral with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a user terminal (e.g., a UE). Alternatively, the processor and storage medium may reside as discrete components in the user terminal.

[0227] In one or more examples, the described functionality may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functionality may be stored as one or more instructions or code on or transmitted via a computer-readable medium. A computer-readable medium includes both computer storage media and communication media, which includes any medium that facilitates the transfer of a computer program from one place to another. A storage medium may be any available medium accessible to a computer. By way of example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage, disk storage or other magnetic storage devices, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and is accessible to a computer. Furthermore, any connection is appropriately referred to as a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included within the definition of a medium. As used herein, disks and optical discs include: compact optical discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs. Disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these should also be included within the scope of computer-readable media.

[0228] While the foregoing disclosure illustrates exemplary aspects of this disclosure, it should be noted that various changes and modifications may be made herein without departing from the scope of this disclosure as defined by the appended claims. Furthermore, the functions, steps, and / or actions of the method claims according to the aspects of this disclosure described herein need not be performed in any particular order. Moreover, although elements of this disclosure may be described or claimed in the singular, the plural form may also be considered unless expressly stated as limited to the singular.

Claims

1. A semiconductor structure, the semiconductor structure comprising: A gate stack extending along a first direction in the front portion of the semiconductor structure, the gate stack including a first gate structure and a second gate structure offset from each other in the first direction; A first source / drain (S / D) structure, wherein the first source / drain (S / D) structure is adjacent to the first gate structure; A second S / D structure is adjacent to the second gate structure and is offset from the first S / D structure in a second direction. A first back-side conductive structure is in contact with the first S / D structure and is at least partially disposed in the rear portion of the semiconductor structure opposite to the front portion. A second back-side conductive structure is in contact with the second S / D structure and is at least partially disposed in the rear portion of the semiconductor structure; and A third back-side conductive structure is disposed in the rear portion of the semiconductor structure, the third back-side conductive structure extends along the second direction and contacts the first back-side conductive structure and the second back-side conductive structure.

2. The semiconductor structure according to claim 1, wherein: The first back-side conductive structure and the second back-side conductive structure are disposed within the first back-side metallization layer beneath the first S / D structure and the second S / D structure, and The third back-side conductive structure is disposed within the second back-side metallization layer below the first back-side metallization layer.

3. The semiconductor structure according to claim 2, further comprising: A fourth back-side conductive structure is located within the second back-side metallization layer; and A metallized structure is disposed within a third back-side metallized layer below the second back-side metallized layer, and a fourth back-side conductive structure connects the metallized structure to another back-side conductive structure in the first back-side metallized layer.

4. The semiconductor structure according to claim 1, wherein: The first back-side conductive structure and the second back-side conductive structure are disposed within the first back-side metallization layer beneath the first S / D structure and the second S / D structure, and The third back-side conductive structure is disposed within the lower portion of the first back-side metallization layer.

5. The semiconductor structure according to claim 4, further comprising: The fourth back-side conductive structure is located within the second back-side metallization layer below the first back-side metallization layer. and A metallized structure is disposed within a third back-side metallized layer below the second back-side metallized layer, and a fourth back-side conductive structure connects the metallized structure to another back-side conductive structure in the first back-side metallized layer.

6. The semiconductor structure according to claim 1, further comprising: A dielectric structure, wherein the dielectric structure is located beneath the connection portion of the gate stack between the first gate structure and the second gate structure. in: The third back-side conductive structure is at least partially disposed below the connection portion of the gate stack, and the dielectric structure is configured to electrically isolate the third back-side conductive structure from the bottom gate electrode portion of the connection portion of the gate stack.

7. The semiconductor structure according to claim 6, wherein: The dielectric structure contacts the bottom gate electrode portion of the connection portion of the gate stack.

8. The semiconductor structure according to claim 7, wherein: At least a portion of the third back-side conductive structure extends above the lower surface of the gate stack and along the internal spacers of the connection portion of the gate stack.

9. The semiconductor structure according to claim 6, wherein: The entire third back-side conductive structure is beneath the connection portion of the gate stack.

10. The semiconductor structure according to claim 6, wherein: The dielectric structure includes an etch stop layer beneath the connection portion of the gate stack.

11. A method for manufacturing a semiconductor structure, the method comprising: A gate stack is formed, the gate stack extending along a first direction in the front portion of the semiconductor structure, the gate stack including a first gate structure and a second gate structure, the second gate structure being offset from the first gate structure in the first direction, a first S / D structure being disposed adjacent to the first gate structure, a second S / D structure being disposed adjacent to the second gate structure, and the first S / D structure and the second S / D structure being offset from each other in a second direction; A first back-side conductive structure is formed, the first back-side conductive structure being in contact with the first S / D structure and being at least partially disposed in the rear portion of the semiconductor structure opposite to the front portion; A second back-side conductive structure is formed, the second back-side conductive structure being in contact with the second S / D structure and being disposed at least partially in the rear portion of the semiconductor structure; as well as A third back-side conductive structure is formed, the third back-side conductive structure being disposed in the rear portion of the semiconductor structure, the third back-side conductive structure extending along the second direction and contacting the first back-side conductive structure and the second back-side conductive structure.

12. The method of claim 11, wherein: The first back-side conductive structure and the second back-side conductive structure are formed within a first back-side metallization layer beneath the first S / D structure and the second S / D structure, and The third back-side conductive structure is formed within a second back-side metallization layer below the first back-side metallization layer.

13. The method according to claim 12, further comprising: A fourth back-side conductive structure is formed within the second back-side metallization layer; as well as A metallized structure is formed, which is disposed in a third back-side metallized layer below the second back-side metallized layer, and the fourth back-side conductive structure connects the metallized structure to another back-side conductive structure in the first back-side metallized layer.

14. The method of claim 11, wherein: The first back-side conductive structure and the second back-side conductive structure are formed within a first back-side metallization layer beneath the first S / D structure and the second S / D structure, and The third back-side conductive structure is formed within the lower portion of the first back-side metallization layer.

15. The method of claim 14, further comprising: A fourth back-side conductive structure is formed within a second back-side metallization layer below the first back-side metallization layer; as well as A metallization structure is formed in a third back-side metallization layer below the second back-side metallization layer, and the fourth back-side conductive structure connects the metallization structure to another back-side conductive structure in the first back-side metallization layer.

16. The method according to claim 11, further comprising: A dielectric structure is formed beneath the connection portion between the first gate structure and the second gate structure of the gate stack. in: The third back-side conductive structure is formed at least partially beneath the connection portion of the gate stack, and the dielectric structure is configured to electrically isolate the third back-side conductive structure from the bottom gate electrode portion of the connection portion of the gate stack.

17. The method of claim 16, wherein forming the dielectric structure comprises: Remove a portion of the gate dielectric portion of the connection portion of the gate stack to expose the bottom gate electrode portion of the connection portion of the gate stack; as well as A region-selective deposition process is performed to form the dielectric structure.

18. The method of claim 17, wherein forming the third back-side conductive structure comprises: Remove a portion of the front interlayer dielectric layer adjacent to the internal spacer of the connection portion of the gate stack to define an opening. The third back-side conductive structure is formed in the opening such that at least a portion of the third back-side conductive structure extends above the lower surface of the gate stack and along the internal spacers of the connection portion of the gate stack.

19. The method of claim 17, wherein: The entire third back-side conductive structure is beneath the connection portion of the gate stack.

20. The method of claim 16, further comprising: An etch stop layer is formed beneath the connection portion of the gate stack as the dielectric structure.

21. An electronic device, the electronic device comprising: An integrated circuit device, the integrated circuit device comprising a semiconductor structure, and the semiconductor structure comprising: A gate stack extending along a first direction in the front portion of the semiconductor structure, the gate stack including a first gate structure and a second gate structure offset from each other in the first direction; A first source / drain (S / D) structure, wherein the first source / drain (S / D) structure is adjacent to the first gate structure; A second S / D structure is adjacent to the second gate structure and is offset from the first S / D structure in a second direction. A first back-side conductive structure is in contact with the first S / D structure and is at least partially disposed in the rear portion of the semiconductor structure opposite to the front portion. A second back-side conductive structure, which is in contact with the second S / D structure and is at least partially disposed in the rear portion of the semiconductor structure; and A third back-side conductive structure is disposed in the rear portion of the semiconductor structure, the third back-side conductive structure extends along the second direction and contacts the first back-side conductive structure and the second back-side conductive structure.

22. The electronic device according to claim 21, wherein: The first back-side conductive structure and the second back-side conductive structure are disposed within the first back-side metallization layer beneath the first S / D structure and the second S / D structure, and The third back-side conductive structure is disposed within the second back-side metallization layer below the first back-side metallization layer.

23. The electronic device of claim 22, wherein the semiconductor structure further comprises: A fourth back-side conductive structure is located within the second back-side metallization layer; and A metallized structure is disposed within a third back-side metallized layer below the second back-side metallized layer, and a fourth back-side conductive structure connects the metallized structure to another back-side conductive structure in the first back-side metallized layer.

24. The electronic device according to claim 21, wherein: The first back-side conductive structure and the second back-side conductive structure are disposed within the first back-side metallization layer beneath the first S / D structure and the second S / D structure, and The third back-side conductive structure is disposed within the lower portion of the first back-side metallization layer.

25. The electronic device of claim 24, wherein the semiconductor structure further comprises: The fourth back-side conductive structure is located within the second back-side metallization layer below the first back-side metallization layer. and A metallized structure is disposed within a third back-side metallized layer below the second back-side metallized layer, and a fourth back-side conductive structure connects the metallized structure to another back-side conductive structure in the first back-side metallized layer.

26. The electronic device of claim 21, wherein the semiconductor structure further comprises: A dielectric structure, wherein the dielectric structure is located beneath the connection portion of the gate stack between the first gate structure and the second gate structure. The third back-side conductive structure is at least partially disposed below the connection portion of the gate stack, and the dielectric structure is configured to electrically isolate the third back-side conductive structure from the bottom gate electrode portion of the connection portion of the gate stack.

27. The electronic device according to claim 26, wherein: The dielectric structure contacts the bottom gate electrode portion of the connection portion of the gate stack.

28. The electronic device according to claim 27, wherein: At least a portion of the third back-side conductive structure extends above the lower surface of the gate stack and along the internal spacers of the connection portion of the gate stack.

29. The electronic device according to claim 26, wherein: The entire third back-side conductive structure is beneath the connection portion of the gate stack.

30. The electronic device according to claim 26, wherein: The dielectric structure includes an etch stop layer beneath the connection portion of the gate stack.

31. The electronic device of claim 21, wherein the electronic device includes a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed-location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, or a device in a motor vehicle.

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