High-temperature and high-frequency force-sensitive chip packaging structure and packaging process based on nano-silver sintering and flush packaging

Abstract

The invention discloses a high-temperature and high-frequency force-sensitive chip packaging structure based on nano-silver sintering and flush packaging, which comprises a kovar alloy shell and a chip main body, and is characterized in that a nano-silver sintering interconnection layer is arranged between an SOI force-sensitive chip in the chip main body and an aluminum nitride ceramic substrate; a low-melting-point glass sealing ring is arranged on the periphery of a back cavity of the SOI force-sensitive chip, a high-vacuum reference cavity is defined by the low-melting-point glass sealing ring, and a sensitive diaphragm of the SOI force-sensitive chip and the front end face of the kovar alloy shell are arranged in a coplanar mode. The process comprises the following steps of: 1, pre-treating and metalizing a substrate; 2, coating the nano-silver paste and inversely mounting the chip; 3, sintering and interconnecting the nano-silver; 4, glass ring sealing and vacuum cavity preparation; and 5, forming a flush structure and releasing stress. According to the invention, the sensitive diaphragm of the SOI force sensitive chip and the front end face of the shell are arranged in a coplanar manner, so that the lumen effect is eliminated, and the reliability of the sensor is improved; the process effectively inhibits thermal stress, improves structural stability and is suitable for the field of hot end monitoring.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor chip packaging technology, specifically relating to a high-temperature, high-frequency force-sensitive chip packaging structure and packaging process based on nano-silver sintering and flush packaging. Background Technology

[0002] In extreme application scenarios involving ultra-high temperature (up to 472℃) and high-frequency transient pressure measurement (≥100kHz), such as hot-end monitoring of aero-engines, combustion process control, and internal state sensing of nuclear reactors, the packaging and interconnection technologies of traditional MEMS force-sensitive chips face many challenges in terms of coordination, making it difficult to meet the stringent requirements of equipment for dynamic response capability, measurement accuracy, and long-term stability.

[0003] Traditional pressure sensors often employ non-flush packaging structures. The recessed cavity or pressure channel in front of the sensitive diaphragm is prone to forming a typical "cavity effect," equivalent to a Helmholtz resonant cavity. In dynamic pressure measurement, this manifests as an acoustic low-pass filter, which severely attenuates high-frequency pressure signals, causing phase delay, signal distortion, and a drop in the system's natural frequency. It also introduces additional static pressure errors. Furthermore, under extreme temperature conditions, the mismatch in the coefficient of thermal expansion (CTE) of the material further exacerbates performance degradation, leading to systematic deviations in static and dynamic measurements. In terms of interconnect technology, existing methods commonly used in high-temperature pressure sensors, such as gold wire bonding, glass sintering, and conventional brazing, all have significant drawbacks: gold wires are prone to grain coarsening, creep, and interface brittle fracture above 300℃, and uneven bonding point heights increase the height difference between the diaphragm and the package end face, further inducing cavity effects; glass sealing can generate large residual stress due to the mismatch between the CTE of the chip and the metal shell, which is directly transmitted to the edge of the diaphragm, causing zero-point drift and hysteresis errors, and is prone to cracking during high-temperature cycling; conventional Sn-based or AgCu-based solders will experience interface embrittlement or fatigue damage at high temperatures, and their volume shrinkage will also change the package air gap, causing cavity resonance effects, resulting in severe distortion of the high-frequency dynamic response above 10kHz, which cannot meet the bandwidth requirement of ≥100kHz. Although nano-silver sintering is widely used in high-temperature interconnect scenarios, existing technologies are mostly designed for power devices. If it is directly applied to MEMS force-sensitive chips, it will face problems such as uneven sintering shrinkage leading to uncontrolled height difference between the film and the substrate, unreasonable sintering temperature curve causing large residual stress, and without forming a co-design with flush packaging, it is still impossible to fundamentally eliminate the cavity effect.

[0004] In summary, existing technologies cannot simultaneously solve core problems such as packaging stress runaway, cavity effect interference, and packaging failure under high temperature and high frequency environments. There is an urgent need to build an innovative process system for SOI force-sensitive chips, which combines nano-silver sintering interconnection with high flatness flush packaging. Summary of the Invention

[0005] The technical problem to be solved by this invention is to address the shortcomings of the prior art by providing a high-temperature, high-frequency force-sensitive chip packaging structure based on nano-silver sintering and flush encapsulation. This packaging structure achieves zero height difference by keeping the sensitive diaphragm of the SOI force-sensitive chip and the front end face of the Kovar alloy shell coplanar, effectively eliminating the cavity effect. This enables the sensor to achieve distortion-free high-frequency pressure signal measurement, significantly improving the sensor's dynamic response characteristics, static accuracy, and reliability under high-temperature environments. It solves the problems of cavity effect, stress runaway, and insufficient reliability of traditional packaging in ultra-high temperature (up to 472℃) and high-frequency (≥100kHz) scenarios.

[0006] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: a high-temperature high-frequency force-sensitive chip packaging structure based on nano-silver sintering and flush packaging, characterized in that it includes a Kovar alloy shell and a chip body disposed within the Kovar alloy shell, a silicon nitride gasket is disposed between the Kovar alloy shell and the chip body, the chip body includes an aluminum nitride ceramic substrate and an SOI force-sensitive chip located on the aluminum nitride ceramic substrate, and a nano-silver sintered interconnect layer is provided between the aluminum nitride ceramic substrate and the SOI force-sensitive chip, a metallization layer for circuit connection is provided on the surface of the aluminum nitride ceramic substrate, a low melting point glass sealing ring is disposed on the outer periphery of the back cavity of the SOI force-sensitive chip, and the back cavity and the low melting point glass sealing ring enclose a high vacuum reference cavity, and the sensitive diaphragm of the SOI force-sensitive chip is arranged coplanarly with the front end face of the Kovar alloy shell.

[0007] Meanwhile, this invention also discloses a packaging process for a high-temperature, high-frequency force-sensitive chip packaging structure based on nano-silver sintering and flush packaging, characterized in that the process includes the following steps: Step 1, Substrate Pretreatment and Metallization: A Ti / Pt / Au metallization layer is deposited on the surface of an aluminum nitride ceramic substrate using magnetron sputtering. Then, a pre-defined circuit pattern is formed by photolithography to obtain a metallization layer for circuit connection, thus obtaining an aluminum nitride ceramic substrate. Step 2, Nano-silver paste coating and chip flipping: Nano-silver paste is coated on the pad area of ​​the aluminum nitride ceramic substrate in Step 1 using screen printing. High-precision flipping equipment is used to align and bond the circuit surface of the SOI force-sensitive chip with the pad area of ​​the aluminum nitride ceramic substrate. The bonding gap between the two is controlled by a limiting structure to form a flip-chip assembly. Step 3, Nano-silver Sintering Interconnect: Place the flip-chip assembly from Step 2 in a sintering equipment protected by a vacuum or inert atmosphere, and complete the degreasing, sintering and densification of the nano-silver paste according to the preset temperature curve to form a nano-silver sintering interconnect layer. Step 4, Glass Ring Sealing and Vacuum Cavity Preparation: The low-melting-point glass preformed ring is placed in the sealing area of ​​the outer periphery of the SOI force-sensitive chip back cavity in the flip-chip assembly in Step 3 where the nano-silver sintered interconnect layer has been formed. The whole assembly is then moved into a vacuum bonding device. After evacuation, the low-melting-point glass preformed ring is melted and sealed to form a low-melting-point glass sealing ring through precise temperature control. This ring, together with the SOI force-sensitive chip back cavity, forms a high-vacuum reference cavity, thus obtaining the chip body. Step 5, Flush Structure Forming and Stress Relief: The Kovar alloy shell and matching silicon nitride pad are obtained through precision machining, and then assembled with the chip body obtained in Step 4, so that the sensitive film of the SOI force-sensitive chip is coplanar with the front end surface of the Kovar alloy shell. Then, low-temperature annealing is performed to release the residual stress of the packaging.

[0008] This invention selects an aluminum nitride ceramic substrate with a thermal expansion coefficient matching that of the SOI force-sensitive chip as the substrate. A fine circuit pattern is formed through sputtering and photolithography processes, providing a foundation for subsequent interconnection with the chip and avoiding performance degradation due to thermal expansion coefficient mismatch in extreme high-temperature environments. Then, nano-silver paste is coated and the chip is flip-chip bonded, followed by sintering to form a nano-silver sintered interconnect layer, creating a high-temperature stable interconnect structure between the SOI force-sensitive chip and the aluminum nitride ceramic substrate. Next, by setting a low-melting-point glass preform ring and sealing it after vacuuming, the melted glass preform ring flows and fully wets the SOI force-sensitive chip and the aluminum nitride. The sealing interface of the ceramic substrate forms a dense hermetically sealed interface. After slow cooling, the high vacuum environment is permanently "captured" in the cavity on the back of the SOI force-sensitive chip, simultaneously forming the high vacuum reference cavity required by the absolute pressure sensor. Then, through precision machining, the key dimensions of each structure are ensured, and special fixtures are preferably used for precise positioning during assembly to achieve coplanarity between the sensitive diaphragm of the SOI force-sensitive chip and the front end face of the Kovar alloy shell. Furthermore, stress management technology, namely low-temperature annealing, is used to further release the microscopic residual stress at the interconnect layer and the packaging interface, minimizing the residual stress of the packaging, thereby stabilizing the zero-point output of the sensor and improving long-term reliability.

[0009] The aforementioned packaging process is characterized in that the metallization layer in step one is a Ti / Pt / Au multilayer structure, wherein the thickness of the Ti layer is 10nm~50nm, the thickness of the Pt layer is 20nm~80nm, and the thickness of the Au layer is 200nm~500nm. This invention utilizes the Ti layer in the Ti / Pt / Au multilayer structure as an adhesion layer to provide strong adhesion, improving its bonding force with the directly contacting aluminum nitride ceramic substrate. The Pt layer acts as a diffusion barrier layer, effectively blocking element interdiffusion and maintaining the stability of the multilayer structure during high-temperature sintering. The outermost Au layer acts as a wetting layer at the sintering interface, directly contacting the nano-silver paste and improving wettability, enabling the aluminum nitride ceramic substrate and the nano-silver in the nano-silver paste to form good metallic bonds. Furthermore, a Pd layer with excellent diffusion barrier properties can be used instead of the Pt layer in the Ti / Pt / Au multilayer structure.

[0010] The above-mentioned encapsulation process is characterized in that the nano-silver paste in step two comprises the following components by mass percentage: 70%~85% nano-silver particles with a particle size of 30nm~80nm, 1%~5% low-melting-point lead-free glass powder with a particle size of 100nm~300nm, 10%~20% ethylene glycol / terpineol mixed solvent, with a volume ratio of ethylene glycol to terpineol of 1:2, and 1.8%~5% dispersant, binder, and stabilizer combined. The nano-silver particles in this nano-silver paste form the main sintered structure and necking, while the low-melting-point lead-free glass powder improves interfacial wettability and sintering strength. Commonly used low-melting-point lead-free glass powder is bismuth-based borosilicate glass powder (Bi2O3–B2O3–SiO2). The ethylene glycol / terpineol mixed solvent controls the rheological properties of the nano-silver paste, and the added dispersant, binder, and stabilizer effectively prevent particle aggregation and improve printing quality. Dispersants are used to prevent the agglomeration of silver nanoparticles and ensure the uniformity and stability of the slurry. Common types include polymers such as polyvinylpyrrolidone (PVP) and polyacrylic acid (PAA), and small molecule surfactants such as sodium dodecylbenzene sulfonate (SDBS) and oleylamine. Binders enable the silver film to maintain its shape after the solvent evaporates, making it less prone to cracking or falling off the substrate. Common types include cellulose-based agents such as ethyl cellulose, resin-based agents such as acrylic resin, and phenolic resin (which must be able to completely decompose at high temperatures). Stabilizers prevent the silver nanoparticles from being oxidized or agglomerated during storage and transportation. Common types include antioxidants such as organic amines (e.g., ethanolamine), organic acids (e.g., citric acid), and complexing agents.

[0011] The above-mentioned encapsulation process is characterized in that the screen printing process parameters in step two are: screen mesh number 250-350 mesh, printing thickness 10μm-25μm, printing pressure 0.15MPa-0.30MPa, and after coating the nano silver paste, it is pre-dried in an air or nitrogen atmosphere at 80℃-120℃ for 5min-10min to remove some of the solvent in the nano silver paste.

[0012] The aforementioned packaging process is characterized in that the SOI force-sensitive chip in step two is fabricated using MEMS technology, with a device layer thickness of 50μm~150μm. Typically, the device layer thickness in the SOI force-sensitive chip is set according to the sensor's sensitivity and inherent frequency requirements.

[0013] The above-mentioned packaging process is characterized in that the preset temperature curve in step three includes four stages: the first stage is to raise the temperature to 120℃ at a heating rate of 1℃ / s to 2℃ / s and hold for 5min to 10min; the second stage is to raise the temperature to 200℃ at a heating rate of 0.5℃ / s to 1℃ / s and hold for 10min to 15min; the third stage is to raise the temperature to 260℃ to 300℃ at a heating rate of 0.5℃ / s and hold for 20min to 30min; and the fourth stage is to raise the temperature to 320℃ to 350℃ at a heating rate of 0.2℃ / s to 0.5℃ / s and hold for 15min to 20min. The process begins with a rapid increase in temperature to 120°C for a brief holding period to remove organic solvents from the silver nanoparticle paste. The temperature is then increased to 200°C and held to promote initial necking of the silver nanoparticles. Next, the temperature is slowly increased to 260°C–300°C and held for a sufficient period to achieve surface diffusion and densification of the silver particles. Finally, the temperature is slowly increased to 320°C–350°C and held to enhance interfacial metal diffusion between the SOI force-sensitive chip and the aluminum nitride ceramic substrate, forming a high-temperature stable sintered silver nanoparticle interconnect layer. Simultaneously, this sintering process is protected by a vacuum or inert atmosphere to prevent silver oxidation, reduce porosity, and increase sintering density.

[0014] The above-described packaging process is characterized in that, in step four, the vacuum bonding equipment is evacuated to a vacuum level of 1×10⁻⁶. -3 Below Pa, the sealing temperature of the low-melting-point glass preformed ring is 450℃~550℃, and the holding time is 10min~15min. Based on the composition of the low-melting-point glass preformed ring, the vacuum degree, temperature and holding time of the sealing are precisely controlled to ensure that the low-melting-point glass preformed ring fully wets the sealing interface between the SOI force-sensitive chip and the aluminum nitride ceramic substrate after melting, thereby improving the tightness of the hermetically sealed connection.

[0015] The above-mentioned packaging process is characterized in that the process conditions for the low-temperature annealing treatment in step five are: nitrogen atmosphere, annealing temperature 200℃, and holding time 30min.

[0016] Compared with the prior art, the present invention has the following advantages: 1. This invention adopts a flush packaging structure. By keeping the sensitive diaphragm of the SOI force-sensitive chip and the front end face of the Kovar alloy shell coplanar, the zero height difference between the two is achieved, effectively eliminating the cavity effect and avoiding the serious attenuation, signal distortion, and frequency drop of the high-frequency pressure signal. This enables the sensor to achieve distortion-free high-frequency pressure signal measurement, significantly improving the sensor's dynamic response characteristics, static accuracy, and reliability under high temperature environments. It meets the requirements for long-term airtightness, mechanical strength, and stress stability under ultra-high temperature (472℃) conditions and is suitable for medium and low pressure (0~250kPa) absolute pressure measurement scenarios.

[0017] 2. This invention employs a flip-chip layout to construct a flush package structure. By aligning and bonding the circuit side of the SOI force-sensitive chip downwards with the pad area of ​​the aluminum nitride ceramic substrate, and then achieving flip-chip interconnection between the SOI force-sensitive chip and the aluminum nitride ceramic substrate through nano-silver sintering, the high-temperature interconnection stability of the two is improved, thereby ensuring the stability of the flush package structure. At the same time, the high-temperature resistant glass sealing ring in this flush package structure ensures that a high-vacuum reference cavity is formed between the SOI force-sensitive chip and the aluminum nitride ceramic substrate, and can also resist mechanical extrusion, avoiding sealing failure in a confined space. This process deeply integrates nano-silver sintering and glass sealing processes, and through material composite design and process integration optimization, achieves a unified performance synergy of structural connection and hermetic packaging, breaking through the performance limitations of traditional single packaging technologies, and providing an efficient and reliable solution for high-precision MEMS device packaging.

[0018] 3. Unlike existing technologies that solidify ceramics with chips and encapsulate them to solve thermal cycling delamination problems or conventionally form vacuum cavities through vacuum electrostatic bonding to improve chip sensitivity, this invention uses a nano-silver sintering process combined with a low-melting-point glass preform ring for vacuum sealing. On the one hand, it achieves high airtightness by forming a high-vacuum reference cavity through hermetically sealed connection, suitable for absolute pressure sensors. On the other hand, it forms a material system with a thermal expansion coefficient matching with the aluminum nitride ceramic substrate, Kovar alloy shell, and SOI force-sensitive chip, effectively suppressing thermal stress and reducing zero-point drift caused by thermal stress. Combined with a flush packaging structure to suppress the "cavity effect", it ensures the measurement accuracy and long-term stability of the sensor in a wide temperature range and realizes miniaturized packaging design.

[0019] 4. This invention uses a printing method to coat nano-silver paste on an aluminum nitride ceramic substrate, which is compatible with large-scale MEMS packaging lines. This allows the flush packaging structure to be realized without complex micro-machining and can be extended to various SOI and packaging base materials.

[0020] 5. Unlike existing technologies that use water-soluble nano-silver paste containing only nano-silver particles, this invention uses nano-silver paste containing nano-silver particles, low-melting-point lead-free glass powder, and organic solvents. The glass powder component fills the gaps in the nano-silver sintered interconnect layer, enhances the interfacial bonding force, inhibits silver oxidation and migration, and enhances the connection effect of the nano-silver sintered interconnect layer. While achieving the connection of the force-sensitive chip flip-chip packaging structure and taking into account its mechanical strength, it lays the material foundation for the subsequent glass ring sealing. It ensures that after the low-melting-point glass preform ring melts, it can fully and quickly enter and wet the chip and substrate packaging interface to form a highly dense hermetically sealed connection. It is suitable for ultra-high temperature environments (up to 472℃) and wide temperature ranges (-55℃~472℃).

[0021] 6. Unlike existing technologies where force-sensitive chip packaging structures used in civilian flexible / rigid circuits and wearable devices only require conductivity, interconnection, and heat dissipation performance without addressing extreme environments, the high-temperature, high-frequency force-sensitive chip packaging structure of this invention significantly improves the dynamic response bandwidth and signal fidelity of the sensor, reduces static measurement errors, and exhibits excellent long-term stability, airtightness, and mechanical strength in extreme environments. It can withstand ultra-high temperatures, vibrations, and confined spaces, meeting the stringent requirements of extreme scenarios such as hot-end monitoring of aero-engines, and is suitable for fields such as national defense and military industries.

[0022] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the manufacturing process of the SOI force-sensitive chip used in this invention.

[0024] Figure 2 This is a schematic diagram of the SOI force-sensitive chip fabricated based on MEMS technology in this invention.

[0025] Figure 3 This is an exploded view of the high-temperature, high-frequency force-sensitive chip packaging structure based on nano-silver sintering and flush packaging according to the present invention.

[0026] Figure 4 This is a schematic diagram of the main structure of the high-temperature, high-frequency force-sensitive chip packaging structure based on nano-silver sintering and flush packaging of the present invention.

[0027] Figure 5 This is an overall schematic diagram of the high-temperature, high-frequency force-sensitive chip packaging structure based on nano-silver sintering and flush packaging according to the present invention.

[0028] Figure 6 This is the preset temperature curve in step three of embodiment 2 of the present invention.

[0029] Explanation of reference numerals in the attached figures Detailed Implementation

[0030] The SOI force-sensitive chip used in this invention is typically fabricated using MEMS technology, and its manufacturing process is as follows: Figure 1 As shown, it includes the following steps: Step 1: Clean the wafer to remove surface oxides and impurity particles. Then, use HF acid solution to remove the SiO2 layer on the surface. Next, use a surfactant to reduce the surface tension of water and further clean with water to remove dust, metal debris and polymer particles from the surface, to obtain the wafer ready for use. Step 2: Place the wafer to be used in Step 1 in a high-temperature oxidation furnace with a furnace tube temperature of 900℃, and grow a silicon dioxide layer with a thickness of 25nm on its surface through thermal oxidation, as shown in Figure (a). Step 3: Using photolithography, the silicon surface region is exposed on the silicon dioxide layer grown in Step 2 by combining positive photoresist with dry etching. Then, boron ions are implanted into the silicon surface region for light doping using an ion implantation process with an implantation dose of 2 × 10⁻⁶. 14 Ion / cm 2 The doping energy is 50keV to form a force-sensitive resistor, i.e., a lightly doped region, as shown in Figure (b). Then, it is placed in a high-temperature annealing furnace tube and held at 1000℃ for 15 minutes for annealing repair, so that the internal lattice damage is completely repaired. Step 4: A 0.4 μm thick SiO2 insulating layer is deposited on the wafer surface annealed and repaired in Step 3 using a low-pressure chemical vapor deposition (LPCVD) process, as shown in Figure (c); Step 5: On the wafer after the insulating layer is deposited in Step 4, mirror etching is performed at the via corresponding to the local force-sensitive resistor location to expose the surface silicon region. A 10nm thick silicon dioxide layer is generated by local thermal oxidation to remove etching losses and contaminants. Then, the silicon dioxide layer is removed using buffered oxide etchant (BOE). The BOE time is typically set to 10s to form a localized region. Step 6: Perform heavy boron doping by implanting boron ions into the localized region from Step 5 using an ion implantation process, with an implantation dose of 2 × 10⁻⁶. 15 Ion / cm 2 The doping energy is 20keV, forming an ohmic connection region, i.e., a heavily doped region, as shown in Figure (d). Then, the annealing repair in step 3 is performed in the same way. Step 7: Through photolithography patterning and metal deposition processes, a Cu layer with a thickness of 0.7 μm is deposited in sections of the wafer repaired by annealing in step 6 to form electrode connection areas and wiring distribution areas, as shown in Figure (e). Step 8: A 0.2 μm thick Si3N4 passivation layer is deposited on the Cu layer in step 7 using a plasma-enhanced chemical vapor deposition (PECVD) process with low residual stress to protect the device, as shown in Figure (f). Step 9: Open a window on the Si3N4 passivation layer in step 8 through photolithography and etching processes, and form an Al electrode with a thickness of 1.5μm by metal deposition on the window to form an electrode PAD, as shown in Figure (g). Step 10: Dry etching is performed on the wafer with electrodes (PADs) from Step 9 using deep reactive ion etching (DRIE) to thin the wafer to 400 μm, creating a cavity on the back side of the silicon substrate. The portion below the pre-fabricated buried oxide layer in the wafer is the silicon substrate, and the portion above it is the device layer. The preferred thickness of the device layer is 50 μm to 150 μm (see Figure (h)). Subsequent etching removes the buried oxide layer within the cavity, yielding an SOI force-sensitive chip. Figure 2 As shown ( Figure 2 The glass layer in the image is the substrate material used in chip fabrication.

[0031] In the SOI force-sensitive chip of this invention, Cu is used as a metal lead for internal information transmission. The excellent conductivity and anti-electromigration properties of Cu facilitate signal transmission within the chip. Al is used as the material for the electrode PAD to lead out the metal lead and connect it to other circuits. The bonding energy is used to break the localized alumina film formed on the Al surface, allowing the pure aluminum underneath to form a strong intermetallic compound with the bonding wires of other circuits, achieving a high-strength and high-reliability connection, thereby improving the overall performance of the SOI force-sensitive chip.

[0032] Example 1 like Figures 3-5 As shown, this embodiment is based on a high-temperature, high-frequency force-sensitive chip packaging structure using nano-silver sintering and flush packaging. It includes a Kovar alloy shell 5 and a chip body disposed within the Kovar alloy shell 5. A silicon nitride gasket 6 is disposed between the Kovar alloy shell 5 and the chip body. The chip body includes an aluminum nitride ceramic substrate 2 and an SOI force-sensitive chip 1 located on the aluminum nitride ceramic substrate 2. A nano-silver sintered interconnect layer 3 is provided between the aluminum nitride ceramic substrate 2 and the SOI force-sensitive chip 1. A metallization layer for circuit connection is provided on the surface of the aluminum nitride ceramic substrate 2. A low-melting-point glass sealing ring 4 is disposed on the outer periphery of the back cavity of the SOI force-sensitive chip 1, and the back cavity and the low-melting-point glass sealing ring 4 enclose a high-vacuum reference cavity 7. The sensitive diaphragm 11 of the SOI force-sensitive chip 1 is arranged coplanarly with the front end face of the Kovar alloy shell 5.

[0033] In the high-temperature, high-frequency force-sensitive chip packaging structure of this invention, the chip body is placed inside a Kovar alloy shell 5 with high airtightness, effectively isolating the chip body from the adverse effects of external air and moisture. By using a silicon nitride gasket 6 with high temperature resistance, excellent chemical stability, and mechanical strength between the Kovar alloy shell 5 and the chip body, not only is sealing and buffering shock absorption achieved, but the requirements for use in high-temperature and high-pressure environments are also met. An aluminum nitride ceramic substrate 2 is used as an interconnect carrier to mount the SOI force-sensitive chip 1, and a nano-silver sintered interconnect layer 3 is set between the aluminum nitride ceramic substrate 2 and the SOI force-sensitive chip 1 to achieve high-temperature stable electrical connection and mechanical fixation between the two. A low-melting-point glass sealing ring 4 is set on the outer periphery of the back cavity of the SOI force-sensitive chip 1, utilizing its thermal expansion coefficient which is lower than that of SOI. The characteristics between the force-sensitive chip and the aluminum nitride ceramic substrate enable a hermetically sealed connection. Simultaneously, the back cavity of the low-melting-point glass sealing ring 4 and the low-melting-point glass sealing ring 4 enclose each other to form the high-vacuum reference cavity 7 required for absolute pressure measurement. By keeping the sensitive diaphragm 11 of the SOI force-sensitive chip 1 and the front end face of the Kovar alloy shell 5 coplanar, zero height difference between them is achieved, forming a flush structure to eliminate the cavity effect. This avoids severe attenuation, signal distortion, and frequency drop in high-frequency pressure signals, enabling the sensor to achieve distortion-free high-frequency pressure signal measurement. This significantly improves the sensor's dynamic response characteristics, static accuracy, and reliability under high-temperature environments. The sensitive diaphragm 11 of the SOI force-sensitive chip 1 comprises all parts of the buried oxide layer.

[0034] like Figure 5 As shown, in this embodiment, the high-vacuum reference cavity 7 is also filled with a getter 71. The encapsulation structure of the high-temperature, high-frequency force-sensitive chip in this embodiment needs to maintain a vacuum environment in the high-vacuum reference cavity 7 to be suitable for absolute pressure sensors. By filling the high-vacuum reference cavity 7 with getter 71, it acts as a "gas sponge," continuously absorbing the surrounding released gas, ensuring that the high-vacuum reference cavity 7 maintains a stable and extremely low pressure throughout the entire lifespan of the sensor.

[0035] In this embodiment, the getter 71 is a non-evaporable getter, typically made of alloy powders of metals such as zirconium (Zr), vanadium (V), and iron (Fe) (e.g., Zr-V-Fe alloy). The specific preparation process is as follows: During the SOI force-sensitive chip preparation process, after forming a cavity (i.e., back cavity) on the back side of the silicon substrate of the wafer through deep reactive ion etching, a layer of alloy thin film of metals such as zirconium (Zr), vanadium (V), and iron (Fe) is deposited on the top of the back cavity (inner surface of the silicon substrate) using magnetron sputtering or electron beam evaporation, which is the getter 71, with a thickness typically of 0.5μm to 2μm. During the high-temperature process of forming the low-melting-point glass sealing ring 4 by fusion sealing in the preparation of the packaging structure, the alloy thin film is activated by heating, and a fresh metal layer with high adsorption activity is formed on the surface, which captures gas through bulk diffusion and surface adsorption.

[0036] like Figure 5 As shown, in this embodiment, a through hole is provided at the bottom of the encapsulation structure. Metal leads from the electrode PAD are led out through the through hole to connect with other circuits in the outside world, and an insulating layer is filled in the through hole.

[0037] Example 2 The packaging process for the high-temperature, high-frequency force-sensitive chip packaging structure based on nano-silver sintering and flush packaging in this embodiment includes the following steps: Step 1, Substrate Pretreatment and Metallization: A Ti / Pt / Au metallization layer is deposited on the surface of an aluminum nitride ceramic substrate using magnetron sputtering. Then, a pre-defined circuit pattern is formed by photolithography to obtain the metallization layer used for circuit connections, resulting in aluminum nitride ceramic substrate 1. The metallization layer is a Ti / Pt / Au multilayer structure, wherein the Ti layer thickness is 30nm, the Pt layer thickness is 50nm, and the Au layer thickness is 400nm. Step 2, Nano-silver paste coating and chip flip-chip bonding: Nano-silver paste is coated onto the pad area of ​​the aluminum nitride ceramic substrate 1 from Step 1 using screen printing. A high-precision flip-chip mounter is used to align and bond the SOI force-sensitive chip 1 with the circuit side down onto the pad area of ​​the aluminum nitride ceramic substrate 1. The bonding gap between the two is controlled by metal bumps to form a flip-chip assembly. The screen printing process parameters are: 325 mesh, 18 μm printing thickness, 0.20 MPa printing pressure, and a squeegee angle of 60°±5°. After coating the nano-silver paste, it is pre-dried in a nitrogen atmosphere at 100°C for 7 minutes to remove some of the solvent in the nano-silver paste. The device layer thickness of the SOI force-sensitive chip 1 is 50 μm. Step 3, Nano-silver sintering interconnect: Place the flip-chip assembly from Step 2 in a sintering equipment protected by a vacuum or inert atmosphere, and complete the degreasing, sintering and densification of the nano-silver paste according to the preset temperature curve to form the nano-silver sintering interconnect layer 3. The nano-silver paste comprises the following components by mass percentage: 78% nano-silver particles with a particle size of 30nm~80nm, 2% bismuth-based borosilicate glass powder (Bi2O3–B2O3–SiO2) with a particle size of 100nm~300nm, 17% ethylene glycol / terpineol mixed solvent with a volume ratio of ethylene glycol to terpineol of 1:2, 1% polyacrylic acid dispersant, 1% ethyl cellulose binder, and 1% polyvinylpyrrolidone stabilizer; like Figure 6As shown, the preset temperature curve includes four stages: the first stage is to raise the temperature to 120℃ at a heating rate of 1.5℃ / s and hold for 8 minutes; the second stage is to raise the temperature to 200℃ at a heating rate of 0.75℃ / s and hold for 12 minutes; the third stage is to raise the temperature to 280℃ at a heating rate of 0.5℃ / s and hold for 25 minutes; and the fourth stage is to raise the temperature to 340℃ at a heating rate of 0.35℃ / s and hold for 18 minutes. Step 4: Glass Ring Sealing and Vacuum Cavity Preparation: A low-melting-point glass preformed ring is placed in the sealing area around the back cavity of the SOI force-sensitive chip 1 in the flip-chip assembly where the nano-silver sintered interconnect layer 3 has been formed in Step 3. The entire assembly is then moved into a vacuum bonding device. After evacuation, the low-melting-point glass preformed ring is fused together with precise temperature control to form a low-melting-point glass sealing ring 4, which, together with the back cavity of the SOI force-sensitive chip 1, forms a high-vacuum reference cavity 7, thus obtaining the chip body. The vacuum bonding device is evacuated to a vacuum level of 1×10⁻⁶. -3 Below Pa, the temperature for sealing the low-melting-point glass preform ring is 470℃, and the holding time is 12min.

[0038] Step 5, Flush Structure Forming and Stress Release: The Kovar alloy shell 5 and the matching silicon nitride pad 6 are obtained through precision machining, and then assembled with the chip body obtained in Step 4, so that the sensitive diaphragm 11 of the SOI force-sensitive chip 1 is coplanar with the front end surface of the Kovar alloy shell 5. Then, a low-temperature annealing treatment is performed to release the residual stress of the encapsulation. The process conditions for the low-temperature annealing treatment are: nitrogen atmosphere, annealing temperature 200℃, holding time 30min, and the warpage of the sensitive diaphragm 11 after low-temperature annealing is <1.5μm.

[0039] Example 3 The difference between this embodiment and Embodiment 1 is that in step one, the thickness of the Ti layer is 10nm, the thickness of the Pt layer is 20nm, and the thickness of the Au layer is 200nm. The screen printing process parameters in step two are as follows: 250 mesh screen, 10 μm printing thickness, 0.15 MPa printing pressure, and pre-drying in a nitrogen atmosphere at 80°C for 5 min after coating with nano silver paste; the device layer thickness of the SOI force-sensitive chip 1 is 50 μm. The nano-silver paste described in step three comprises the following components by mass percentage: 70% nano-silver particles with a particle size of 30nm~80nm, 5% bismuth-based borosilicate glass powder (Bi2O3–B2O3–SiO2) with a particle size of 100nm~300nm, 20% ethylene glycol / terpineol mixed solvent with a volume ratio of ethylene glycol to terpineol of 1:2, 2% dispersant polyacrylic acid, 2% binder ethyl cellulose, and 1% stabilizer polyvinylpyrrolidone; the preset temperature curve includes four stages: the first stage is to heat to 120℃ at a heating rate of 1℃ / s and hold for 5min; the second stage is to heat to 200℃ at a heating rate of 0.5℃ / s and hold for 10min; the third stage is to heat to 260℃ at a heating rate of 0.5℃ / s and hold for 20min; and the fourth stage is to heat to 320℃ at a heating rate of 0.2℃ / s and hold for 15min. The temperature for sealing the low-melting-point glass preform ring in step four is 450℃, and the holding time is 10 minutes.

[0040] In this embodiment, the Ti / Pt / Au multilayer metallization layer uses a 10nm Ti layer as an adhesion layer, achieving the minimum effective thickness required to ensure a strong bond with the aluminum nitride ceramic substrate. The 20nm Pt layer serves as a diffusion barrier layer, providing the basic thickness for maintaining structural stability at high temperatures and preventing interdiffusion of elements. The 200nm Au layer acts as a sintering interface layer, providing the minimum wettable surface required for effective metallization with the nano-silver paste. This thin metallization layer design, while meeting the basic requirements for electrical connectivity and interfacial bonding, helps reduce material usage and lowers the internal stress that might be introduced by excessively thick film layers. In this embodiment, the nano-silver paste contains 70% nano-silver particles by mass, ensuring the basic formation of the conductive network after sintering. The bismuth-based borosilicate glass powder accounts for 1% by mass, playing a minimal auxiliary sintering role in promoting interfacial bonding and enhancing strength. The mixed solvent accounts for 10% by mass, providing minimal rheological properties and printability for the nano-silver paste. The total mass percentage of dispersant, binder, and stabilizer is 0.5%, meeting the basic requirements for short-term stability and pattern retention of the nano-silver paste. The preset temperature curve for the nano-silver sintering interconnect in this embodiment ensures relatively mild sintering conditions, minimizing thermal stress while completing the basic sintering densification and interfacial bonding of silver particles and achieving reliable interfacial connections.

[0041] The temperature and time for sealing the low-melting-point glass preform ring in this embodiment are the minimum process conditions for achieving sufficient softening, flow, and wetting of the sealing interface, thereby forming a reliable hermetic seal.

[0042] Finally, after completing the precise coplanar assembly of the chip body and the Kovar alloy shell, this embodiment also performs a low-temperature annealing treatment at 200°C for 30 minutes in a nitrogen atmosphere to release the residual stress accumulated at each interface.

[0043] Example 4 The difference between this embodiment and Embodiment 1 is that in step one, an electron beam evaporation process is used to deposit a Ti / Pt / Au metallization layer on the surface of an aluminum nitride ceramic plate, and then an ion etching process is used to form a preset circuit pattern; the thickness of the Ti layer is 50nm, the thickness of the Pt layer is 80nm, and the thickness of the Au layer is 500nm. The screen printing process parameters in step two are as follows: screen mesh number 350 mesh, printing thickness 25μm, printing pressure 0.30MPa, and pre-drying in a nitrogen atmosphere at 120℃ for 10min after coating with nano silver paste; the device layer thickness of the SOI force-sensitive chip 1 is 150μm. The nano-silver paste described in step three comprises the following components by mass percentage: 85% nano-silver particles with a particle size of 30nm~80nm, 1% bismuth-based borosilicate glass powder (Bi2O3–B2O3–SiO2) with a particle size of 100nm~300nm, 10% ethylene glycol / terpineol mixed solvent with a volume ratio of ethylene glycol to terpineol of 1:2, 1.5% dispersant polyacrylic acid, 1.5% binder ethyl cellulose, and 1% stabilizer polyvinylpyrrolidone; the preset temperature curve includes four stages: the first stage is to heat to 120℃ at a heating rate of 2℃ / s and hold for 10min; the second stage is to heat to 200℃ at a heating rate of 1℃ / s and hold for 15min; the third stage is to heat to 300℃ at a heating rate of 0.5℃ / s and hold for 30min; and the fourth stage is to heat to 350℃ at a heating rate of 0.2℃ / s and hold for 20min. The temperature for sealing the low-melting-point glass preform ring in step four is 550℃, and the holding time is 15 minutes.

[0044] The Ti / Pt / Au multilayer metallization structure in this embodiment employs a thick-film design. A 50nm Ti layer serves as an adhesion layer, providing strong substrate bonding for subsequent thick metal layers and withstanding potentially more severe thermal stress. An 80nm Pt layer acts as a diffusion barrier, providing a more robust barrier at higher processing temperatures, effectively preventing Au diffusion to other layers and the penetration of external elements. The 500nm Au layer serves as a sintering interface layer; the thicker Au layer provides a larger and more active metal interface for the sintering of nano-silver, facilitating a stronger metallurgical bond at high temperatures. This thick metallization system lays a solid foundation for the long-term electrical stability and mechanical reliability of the packaging structure under extreme high-temperature environments. In this embodiment, the nano-silver paste contains up to 85% nano-silver particles by mass, ensuring the formation of a dense interconnect with lower porosity and better electrical and thermal conductivity after sintering. The bismuth-based borosilicate glass powder accounts for up to 5% by mass, further enhancing the mechanical strength and creep resistance of the sintered body at high temperatures. The mixed solvent accounts for 10% by mass, and the total mass of dispersant, binder, and stabilizer accounts for 0.5%, ensuring that the high-solids-content nano-silver paste still has good printable rheological properties and stability. In this embodiment, the preset temperature curve for nano-silver sintering interconnects features a high sintering temperature and a long sintering time, allowing for more complete inter-atomic interdiffusion at the interface between the force-sensitive chip, the nano-silver sintered interconnect layer, and the aluminum nitride ceramic substrate metallization layer, forming a metallurgical bond with extremely high strength, maximizing the density, conductivity, and interfacial bonding force of the sintered body.

[0045] In this embodiment, the temperature for sealing the low-melting-point glass preform ring is increased to 550°C and the time is extended to 15 minutes. This higher thermal budget ensures that the low-melting-point glass ring can completely melt and fully flow to wet the entire sealing interface, forming a defect-free glass sealing layer with excellent airtightness. It also helps to form a more stable chemical bond between the glass and the object being sealed.

[0046] Finally, after completing the precise coplanar assembly of the chip body and the Kovar alloy shell, this embodiment also performs a low-temperature annealing treatment at 200°C for 30 minutes in a nitrogen atmosphere to release the residual stress accumulated at each interface.

[0047] Example 5 The difference between this embodiment and Embodiment 1 is that in step one, an electron beam evaporation process is used to deposit a Ti / Pd / Au metallization layer on the surface of an aluminum nitride ceramic plate, and then an ion etching process is used to form a preset circuit pattern; the metallization layer is a Ti / Pd / Au multilayer structure, with a Ti layer thickness of 28nm, a Pd layer thickness of 45nm, and an Au layer thickness of 380nm. The screen printing process parameters in step two are: 300 mesh screen, 20 μm printing thickness, 0.18 MPa printing pressure, 55° squeegee angle, and pre-drying in a nitrogen atmosphere at 110°C for 5 min after coating with nano silver paste. The nano-silver paste described in step three comprises the following components by mass percentage: 80% nano-silver particles with a particle size of 20nm~70nm, 3% bismuth-based borosilicate glass powder (Bi2O3–B2O3–SiO2) with a particle size of 150nm~300nm, 15.2% ethylene glycol / terpene alcohol mixed solvent with a volume ratio of ethylene glycol to terpene alcohol of 1:2.5, 0.8% dispersant polymethacrylic acid, 0.5% binder hydroxypropyl cellulose, and 0.5% stabilizer polyethylene glycol. The preset temperature curve includes four stages: the first stage is to heat to 130℃ at a heating rate of 1.2℃ / s and hold for 6min; the second stage is to heat to 210℃ at a heating rate of 0.8℃ / s and hold for 10min; the third stage is to heat to 290℃ at a heating rate of 0.45℃ / s and hold for 22min; and the fourth stage is to heat to 330℃ at a heating rate of 0.4℃ / s and hold for 20min. In step four, the vacuum bonding equipment is evacuated to a vacuum level of 3 × 10⁻⁶. -3 Below Pa, the temperature for sealing the low-melting-point glass preform ring is 460°C, and the holding time is 15 min; The process conditions for low-temperature annealing in step five are: nitrogen atmosphere, annealing temperature 190℃, holding time 35min, and the warpage of the sensitive membrane 11 after low-temperature annealing is <1.5μm.

[0048] In this embodiment, a Pd layer is used instead of a Pt layer in the metallization layer to form a Ti / Pd / Au multilayer structure. Both Pd and Au have excellent diffusion barrier properties, which can effectively prevent the interdiffusion of Au layer and substrate elements. Furthermore, the 28nm Ti layer, 45nm Pd layer, and 380nm Au layer can ensure the firm adhesion of the metallization layer to the aluminum nitride ceramic substrate, and provide a good wetting and bonding interface for the nano-silver paste, thus meeting the requirements for electrical connection and structural stability.

[0049] This embodiment adjusts the negative correlation between the mesh count and printing thickness of the screen printing stencil and fine-tunes the printing pressure to ensure that the amount of nano silver paste coating is consistent with that in Example 1. By increasing the pre-drying temperature and shortening the time, organic solvents can be removed efficiently without affecting the stability of the nano silver paste.

[0050] In this embodiment, the mixed solvent in the nano-silver paste is a terpene alcohol with properties equivalent to terpineol. Polymethacrylic acid, hydroxypropyl cellulose and polyethylene glycol are used to replace the original dispersant, binder and stabilizer, respectively, which can maintain the dispersibility, formability and particle stability of the nano-silver paste.

[0051] The preset temperature curve of the nano-silver sintering interconnect in this embodiment is achieved by "fine-tuning the heating rate + final temperature ±10℃ + complementary holding time" to ensure that the total heat input is consistent with that in Example 1. This not only completes the degreasing of the nano-silver paste (removal of organic components) but also achieves sufficient necking, diffusion and densification of silver particles, ensuring that the strength and conductivity of the sintered nano-silver interconnect layer reach the same level as in Example 1.

[0052] In this embodiment, the vacuum bonding equipment is evacuated to a vacuum level of 3×10⁻⁶. -3 Below Pa, it can meet the requirements of high vacuum reference cavity use without affecting the detection accuracy of the force-sensitive chip; reducing the sealing temperature of the low melting point glass preform ring by 10°C and extending the holding time by 3 minutes can ensure that the glass softens and flows fully and wets the sealing interface, achieving reliable hermetic sealing, and avoiding thermal damage to the aluminum nitride ceramic substrate and force-sensitive chip due to high temperature. It is functionally equivalent to the low melting point glass preform ring in Example 1, and can achieve vacuum sealing.

[0053] Finally, after completing the precise coplanar assembly of the chip body and the Kovar alloy shell, this embodiment performs a low-temperature annealing treatment at 190°C for 35 minutes in a nitrogen atmosphere to release the residual stress accumulated at each interface.

[0054] In summary, this embodiment uses equivalent process parameters to replace the parameters in Example 1. Under the premise of ensuring that the reliability of nano-silver sintering, vacuum sealing effect, flushing accuracy and stress control are consistent with Example 1, the final encapsulation effect can be achieved through different processes and materials.

[0055] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention in any way. Any simple modifications, alterations, and equivalent changes made to the above embodiments based on the inventive essence shall still fall within the protection scope of the present invention.

Claims

1. A high-temperature, high-frequency force-sensitive chip packaging structure based on nano-silver sintering and flush encapsulation, characterized in that, The device includes a Kovar alloy shell (5) and a chip body disposed within the Kovar alloy shell (5). A silicon nitride gasket (6) is disposed between the Kovar alloy shell (5) and the chip body. The chip body includes an aluminum nitride ceramic substrate (2) and an SOI force-sensitive chip (1) located on the aluminum nitride ceramic substrate (2). A nano-silver sintered interconnect layer (3) is provided between the aluminum nitride ceramic substrate (2) and the SOI force-sensitive chip (1). A metallization layer for circuit connection is provided on the surface of the aluminum nitride ceramic substrate (2). A low-melting-point glass sealing ring (4) is provided on the outer periphery of the back cavity of the SOI force-sensitive chip (1). The back cavity and the low-melting-point glass sealing ring (4) enclose a high vacuum reference cavity (7). The sensitive diaphragm (11) of the SOI force-sensitive chip (1) is coplanarly arranged with the front end face of the Kovar alloy shell (5).

2. A packaging process for a high-temperature, high-frequency force-sensitive chip packaging structure based on nano-silver sintering and flush packaging, characterized in that, The process includes the following steps: Step 1, Substrate pretreatment and metallization: A Ti / Pt / Au metallization layer is deposited on the surface of an aluminum nitride ceramic substrate using magnetron sputtering, and then a preset circuit pattern is formed by photolithography to obtain a metallization layer for circuit connection, thus obtaining an aluminum nitride ceramic substrate (1). Step 2, Nano silver paste coating and chip flipping: Nano silver paste is coated on the pad area of ​​the aluminum nitride ceramic substrate (1) in step 1 by screen printing. The circuit surface of the SOI force-sensitive chip (1) is aligned and bonded with the pad area of ​​the aluminum nitride ceramic substrate (1) by high-precision flipping equipment. The bonding gap between the two is controlled by the limiting structure to form a flip-chip assembly. Step 3, Nano-silver sintering interconnect: Place the flip-chip assembly from Step 2 in a sintering equipment protected by a vacuum or inert atmosphere, and complete the degreasing, sintering and densification of the nano-silver paste according to the preset temperature curve to form a nano-silver sintering interconnect layer (3). Step 4, Glass Ring Sealing and Vacuum Cavity Preparation: The low melting point glass preformed ring is placed in the sealing area of ​​the back cavity of the SOI force-sensitive chip (1) in the flip-chip assembly in Step 3 where the nano-silver sintered interconnect layer (3) has been formed. The whole assembly is moved into the vacuum bonding equipment. After vacuuming, the low melting point glass preformed ring is melted and sealed to form a low melting point glass sealing ring (4) by precise temperature control. It is then surrounded by the back cavity of the SOI force-sensitive chip (1) to form a high vacuum reference cavity (7), thus obtaining the chip body. Step 5, Flush Structure Forming and Stress Release: The Kovar alloy shell (5) and the matching silicon nitride pad (6) are obtained through precision machining. Then, they are assembled with the chip body obtained in Step 4, so that the sensitive film 11 of the SOI force-sensitive chip (1) is coplanar with the front end surface of the Kovar alloy shell (5). Then, low-temperature annealing is performed to release the residual stress of the packaging.

3. The packaging process according to claim 2, characterized in that, The metallization layer mentioned in step one is a Ti / Pt / Au multilayer structure, wherein the thickness of the Ti layer is 10nm~50nm, the thickness of the Pt layer is 20nm~80nm, and the thickness of the Au layer is 200nm~500nm.

4. The packaging process according to claim 2, characterized in that, The nano-silver paste described in step two contains the following components by mass percentage: 70% to 85% nano-silver particles with a particle size of 30nm to 80nm, 1% to 5% low-melting-point lead-free glass powder with a particle size of 100nm to 300nm, 10% to 20% ethylene glycol / terpineol mixed solvent with a volume ratio of ethylene glycol to terpineol of 1:2, and 1.8% to 5% dispersant, binder, and stabilizer combined.

5. The packaging process according to claim 2, characterized in that, The screen printing process parameters in step two are: screen mesh size 250-350 mesh, printing thickness 10μm-25μm, printing pressure 0.15MPa-0.30MPa, and after coating the nano silver paste, it is pre-dried in air or nitrogen atmosphere at 80℃-120℃ for 5min-10min to remove some of the solvent in the nano silver paste.

6. The packaging process according to claim 2, characterized in that, The SOI force-sensitive chip (1) mentioned in step two is fabricated using MEMS technology, and the device layer thickness is 50μm~150μm.

7. The packaging process according to claim 2, characterized in that, The preset temperature curve mentioned in step three includes four stages: the first stage is to raise the temperature to 120℃ at a heating rate of 1℃ / s to 2℃ / s and hold for 5 min to 10 min; the second stage is to raise the temperature to 200℃ at a heating rate of 0.5℃ / s to 1℃ / s and hold for 10 min to 15 min; the third stage is to raise the temperature to 260℃ to 300℃ at a heating rate of 0.5℃ / s and hold for 20 min to 30 min; and the fourth stage is to raise the temperature to 320℃ to 350℃ at a heating rate of 0.2℃ / s to 0.5℃ / s and hold for 15 min to 20 min.

8. The packaging process according to claim 2, characterized in that, In step four, the vacuum bonding equipment is evacuated to a vacuum level of 1×10⁻⁶. -3 For low melting point glass preforms, the sealing temperature is 450℃~550℃ and the holding time is 10min~15min.

9. The packaging process according to claim 2, characterized in that, The process conditions for the low-temperature annealing treatment in step five are: nitrogen atmosphere, annealing temperature 200℃, and holding time 30min.

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