Method and device for determining current curve of chip

Abstract

The invention relates to a method and device for determining a chip current curve. The method comprises the following steps: determining a current curve of a single subsystem in the chip; wherein the chip comprises a plurality of subsystems based on a current curve; determining the current curve time delay of each subsystem; wherein the current curve delay is the delay of the current curve of the subsystem relative to the reference time point; and fitting the current curve of the chip according to the current curve of the single subsystem and the current curve delay of each subsystem. By adopting the method, the current curve of the chip can be quickly and accurately obtained.

Description

Technical Field

[0001] This application relates to the field of chip simulation technology, and in particular to a method and apparatus for determining chip current curves. Background Technology

[0002] A PDN (Power Distribution Network) is a network that provides stable, low-noise power to all components on a chip or circuit board. PI (Power Integrity) simulation is a crucial step in ensuring that the PDN meets the chip's power specifications.

[0003] In related technologies, when performing PI simulation on a chip, the chip's current curve is obtained so that the PI simulation tool can perform simulation based on the chip's current curve and PDN model to obtain simulation results.

[0004] Therefore, in order to obtain accurate simulation results, how to quickly and accurately obtain the current curve of the chip is an urgent problem to be solved. Summary of the Invention

[0005] Based on this, a method and apparatus for determining the current curve of a chip are provided, which can quickly and accurately obtain the current curve of the chip.

[0006] Firstly, this application provides a method for determining a chip current profile. The method includes:

[0007] Determine the current profile of a single subsystem in a chip; wherein the chip comprises multiple subsystems based on current profiles;

[0008] Determine the current curve delay for each subsystem; where the current curve delay is the delay of the current curve of the subsystem relative to the reference time point.

[0009] The chip's current curve is fitted based on the current curves of individual subsystems and the delay of the current curves of each subsystem.

[0010] In one embodiment, fitting the chip's current curve based on the current curve of a single subsystem and the delay of the current curves of each subsystem includes:

[0011] Obtain the current curve coefficients corresponding to each subsystem; the current curve coefficients are used to characterize the ratio of the current of the subsystem during chip operation to the current of the subsystem when the subsystem is running alone.

[0012] The chip's current curve is fitted based on the current curve coefficients corresponding to each subsystem, the current curve of a single subsystem, and the current curve delay of each subsystem.

[0013] In one embodiment, the current curve of the chip is fitted based on the current curve coefficients corresponding to each subsystem, the current curve of a single subsystem, and the current curve delay of each subsystem, including:

[0014] For each subsystem, the delayed current curve is obtained by comparing the current curve with the current curve of the individual subsystem.

[0015] The current curve of the chip is fitted based on the delay current curve and current curve coefficients corresponding to each subsystem.

[0016] In one embodiment, determining the current profile of a single subsystem in the chip includes:

[0017] A single subsystem is simulated based on a preset simulation model, and the current curve of the single subsystem output by the preset simulation model is obtained.

[0018] In one embodiment, determining the current profile delay of each subsystem includes:

[0019] Obtain the chip layout;

[0020] Based on the chip layout, identify the reset trace length of each subsystem's reset receiver relative to the chip's reset pin;

[0021] The current curve delay for each subsystem is determined based on the reset trace length for each subsystem.

[0022] Secondly, this application also provides an apparatus for determining a chip current profile. The apparatus includes:

[0023] The curve module is used to determine the current profile of a single subsystem in the chip; wherein the chip includes multiple subsystems based on current profiles.

[0024] The delay module is used to determine the current curve delay of each subsystem; wherein, the current curve delay is the delay of the current curve of the subsystem relative to the reference time point.

[0025] The fitting module is used to fit the chip's current curve based on the current curve of a single subsystem and the delay of the current curves of each subsystem.

[0026] In one embodiment, the fitting module is specifically used for:

[0027] Obtain the current curve coefficients corresponding to each subsystem; the current curve coefficients are used to characterize the ratio of the current of the subsystem during chip operation to the current of the subsystem when the subsystem is running alone.

[0028] The chip's current curve is fitted based on the current curve coefficients corresponding to each subsystem, the current curve of a single subsystem, and the current curve delay of each subsystem.

[0029] In one embodiment, the fitting module is specifically used for:

[0030] For each subsystem, the delayed current curve is obtained by comparing the current curve with the current curve of the individual subsystem.

[0031] The current curve of the chip is fitted based on the delay current curve and current curve coefficients corresponding to each subsystem.

[0032] In one embodiment, the curve module is specifically used for:

[0033] A single subsystem is simulated based on a preset simulation model, and the current curve of the single subsystem output by the preset simulation model is obtained.

[0034] In one embodiment, the delay module is specifically used for:

[0035] Obtain the chip layout;

[0036] Based on the chip layout, identify the reset trace length of each subsystem's reset receiver relative to the chip's reset pin;

[0037] The current curve delay for each subsystem is determined based on the reset trace length for each subsystem.

[0038] The aforementioned method and apparatus for determining the chip current curve determine the current curve of a single subsystem within the chip; determine the current curve delay of each subsystem; and fit the chip's current curve based on the current curves of the individual subsystems and their delays. The chip comprises multiple subsystems operating based on their current curves; the current curve delay subsystems are defined as the delay of their current curves relative to a reference time point. This allows for the fitting of the entire chip's current curve by combining the individual current curves of each subsystem with their delays, thereby quickly and accurately determining the chip's current curve. This current curve can then be used for PI simulation, ensuring the accuracy of the PI simulation.

[0039] Other beneficial effects of this application will be further explained and illustrated in detail when combined with the accompanying drawings and specific embodiments. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a flowchart illustrating a method for determining a chip current profile in one embodiment.

[0042] Figure 2 This is a schematic diagram of the subsystem distribution in one embodiment;

[0043] Figure 3 This is a schematic diagram of the current curve of a single subsystem in one embodiment;

[0044] Figure 4 This is a flowchart illustrating the process of determining the current curve delay of each subsystem in one embodiment.

[0045] Figure 5 This is a flowchart illustrating the fitting of the current curve of the chip in one embodiment;

[0046] Figure 6 This is a flowchart illustrating a method for rapidly fitting large-scale chip current curves in one embodiment.

[0047] Figure 7 This is a schematic diagram of the current curve of a chip in one embodiment;

[0048] Figure 8 This is a structural block diagram of a device for determining a chip current profile in one embodiment;

[0049] Figure 9 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0050] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be understood that many specific details are set forth in the following description in order to provide a full understanding of this application, but this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0052] It is understandable that "at least one" refers to one or more, while "multiple" refers to two or more.

[0053] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0054] A Power Distribution Network (PDN) provides a stable, low-noise power supply to all components on a chip or circuit board. A well-designed PDN is crucial for ensuring system stability and signal integrity. PI simulation is a key step in ensuring that the PDN meets the chip's power supply specifications (SPEC). Typical steps include:

[0055] Step 1: Extract PDN parameters: Obtain the resistance, inductance, and capacitance (R / L / C) parameters of the power / ground network. Step 2: Inject current profile: Generate dynamic current excitation (e.g., SAIF, VCD files) based on the netlist, timing sequence, and toggle rate. Step 3: Simulation: Perform simulation using PI simulation tools. Step 4: Result analysis: Analyze the power supply simulation results. Step 5: Design iteration: Optimize the design based on the simulation results, and perform further simulations until the design goals are achieved.

[0056] Therefore, in the PI simulation process, the success or failure of the simulation depends on how quickly and accurately the current source (i.e., the current curve) is obtained.

[0057] Common methods for obtaining chip current curves through simulation include generating current curves based on the toggle rate and generating current curves based on full-chip service simulation. However, the former often results in a large discrepancy between the generated current curve and the actual value due to the difficulty in estimating the true toggle rate of the service, leading to low accuracy. The latter requires performing full-chip service simulation of a very large-scale chip, but this simulation process is extremely difficult and time-consuming, and may even be infeasible.

[0058] In summary, the problem of how to efficiently and accurately determine the chip current curve urgently needs to be solved.

[0059] In view of this, embodiments of this application provide a method for determining the current curve of a chip. This method can determine the current curve of a single subsystem within the chip; determine the current curve delay of each subsystem; and fit the chip's current curve based on the current curves of the individual subsystems and their current curve delays. The chip includes multiple subsystems that operate based on their current curves; the current curve delay subsystems are defined as the delay of their current curves relative to a reference time point. This allows for the fitting of the entire chip's current curve by combining the individual current curves of each subsystem and their delays, thereby quickly and accurately determining the chip's current curve. This current curve can then be used for PI simulation, ensuring the accuracy of the PI simulation. Since it eliminates the need for full-chip operational simulation and avoids the process of obtaining the toggle rate, it focuses on the individual subsystems of the chip itself, improving the efficiency and accuracy of obtaining the chip's curves.

[0060] It should be noted that the method for determining the chip current curve provided in this application can be executed by a device for determining the chip current curve. This device can be implemented as part or all of a computer device through software, hardware, or a combination of both. The computer device can be, but is not limited to, various personal computers, laptops, smartphones, tablets, and servers, etc. The server can be an independent physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing cloud computing services. This application does not limit the type of computer device. In the following method embodiments, the execution subject is described as a computer device.

[0061] In one embodiment, such as Figure 1 As shown, a method for determining the chip current profile is provided, including the following steps:

[0062] Step 101: Determine the current profile of a single subsystem in the chip.

[0063] The chip includes multiple subsystems that operate based on current curves.

[0064] This chip can be a very large-scale chip. For example, this chip is one in which the number of functional modules it contains exceeds a preset threshold.

[0065] In an optional embodiment of this application, the chip's functional modules are divided according to a preset partitioning strategy, thereby determining multiple subsystems within the chip.

[0066] The determined parameters can be the current curves of a single subsystem under preset functional scenarios. Preset functional scenarios could include, for example, chip startup, chip reset, data transmission within the chip, etc. This is not a complete list; any scenario where the chip can operate can be considered a preset functional scenario.

[0067] Optionally, the determined current curve can be that of a single subsystem under a target functional scenario. The target functional scenario can be the scenario with the greatest current curve fluctuation; in other words, the scenario where the chip current undergoes the greatest abrupt change. That is, the scenario involving switching from maximum power consumption operation to minimum power consumption operation. In this scenario, the chip faces the most severe current curve fluctuation. If this current curve is obtained, and a current curve of the chip is fitted based on it, and then PI simulation is performed, then if the PI simulation results show that the power supply noise meets the requirements, it can be determined that the PDN model can support the chip's operation under any functional scenario.

[0068] In an optional embodiment of this application, the chip may include not only multiple subsystems operating based on the same current curve, but also other subsystems.

[0069] In an optional embodiment of this application, each subsystem included in the chip operates based on the same or different current curves.

[0070] Step 102: Determine the current curve delay for each subsystem.

[0071] The current curve delay is the delay of the subsystem's current curve relative to the reference time point.

[0072] Each subsystem is located in a different position within the chip, resulting in different reset paths from the corresponding reset pin to each subsystem. The moment the reset pin initiates the reset is recorded as the reference time point. The reset signal is transmitted to each subsystem along different reset paths, corresponding to different reset delays. These reset delays constitute the current curve delays in this example. Therefore, to more accurately fit the chip's current curve, it is necessary to determine the current curve delays of each subsystem.

[0073] Optionally, the current curve delay of each subsystem can be determined based on the location of each subsystem in the chip and the length of the reset trace.

[0074] Step 103: Fit the chip's current curve based on the current curve of a single subsystem and the delay of the current curves of each subsystem.

[0075] Specifically, the delay current curve of each subsystem can be determined based on the current curve of a single subsystem and the delay of the current curve of each subsystem. Then, the delay current curve of each subsystem can be fitted to obtain the current curve of the chip.

[0076] The method for determining the chip current curve in this application embodiment can determine the current curve of a single subsystem in the chip; determine the current curve delay of each subsystem; and fit the chip's current curve based on the current curves of the individual subsystems and the current curve delays of each subsystem. The chip includes multiple subsystems based on current curves; the current curve delay subsystems are defined as the delay of their current curves relative to a reference time point. In this way, the current curve of the entire chip can be fitted by combining the individual current curves of each subsystem and the delay conditions of each subsystem, thereby quickly and accurately determining the chip's current curve. This current curve can then be used for PI simulation, ensuring the accuracy of the PI simulation.

[0077] In an optional embodiment of this application, the subsystems in each chip are arranged in an array. For example, see reference... Figure 2 As shown. It is understandable that... Figure 2 The chip consists of 40 subsystems.

[0078] In one embodiment, determining the current curve of a single subsystem in a chip includes: simulating the single subsystem based on a preset simulation model to obtain the current curve of the single subsystem output by the preset simulation model.

[0079] Pre-set simulation models can be used as software tools to determine the current curves of subsystems.

[0080] In other words, the current curve of a single subsystem can be obtained through simulation. For example, Figure 3 A schematic diagram of the current curve for a single subsystem is shown.

[0081] Alternatively, since the business functions of each subsystem are the same, only one subsystem needs to be simulated to determine the current curve. In this way, compared with the existing technology of performing business simulation on the entire ultra-large-scale chip, the simulation time is shorter, thus reducing the time required to determine the chip current curve.

[0082] In one embodiment, such as Figure 4 A flowchart illustrating the process of determining the current curve delay of each subsystem is shown. Determining the current curve delay of each subsystem includes:

[0083] Step 401: Obtain the chip layout.

[0084] Chip layout is the final output file of integrated circuit design, which directly determines the physical implementation of the chip on the silicon wafer, including the chip's layer layout, routing rules for each layer, and so on.

[0085] Step 402: Based on the chip layout, identify the reset trace length of each subsystem's reset receiver relative to the chip's reset pin.

[0086] For example, refer to Figure 2 RST_n is the chip reset pin. The reset signal can be sent to each subsystem along different reset paths via the reset tree.

[0087] Therefore, in an optional embodiment of this application, the reset trace length of the reset receiver of each subsystem relative to the chip reset pin is identified.

[0088] It should be noted that, as mentioned above, the current curve for the maximum power consumption operating scenario can be determined. One of the most demanding scenarios in PI simulation is when multiple subsystems are operating at maximum power consumption, the RST_n reset takes effect, and the chip switches from the maximum power consumption state to the reset state, causing a sudden change in chip current. In this scenario, a reset control output from the reset pin is needed to reset each subsystem.

[0089] Understandably, current curve delays can also be obtained in other scenarios, that is, the service delays of each subsystem relative to the reference time point can be obtained.

[0090] Step 403: Determine the current curve delay for each subsystem based on the reset trace length for each subsystem.

[0091] It is understandable that the longer the reset trace, the greater the current curve delay of the corresponding subsystem.

[0092] Optionally, the unit current curve delay per unit reset trace length can be determined, and the current curve delay corresponding to the subsystem can be obtained by multiplying the reset trace length by the unit current curve delay per unit reset trace length.

[0093] In an optional embodiment, determining the current profile delay of each subsystem includes: querying the current profile delay of each subsystem from the chip back-end design server.

[0094] This allows us to pinpoint scenarios of sudden current changes and quantify the subsystem's response to the power supply, thus helping to accurately generate the chip's current curve.

[0095] In one embodiment, such as Figure 5 A flowchart illustrating the fitting of the chip's current curve is shown. Based on the current curves of individual subsystems and the delays in the current curves of each subsystem, the chip's current curve is fitted, including:

[0096] Step 501: Obtain the current curve coefficients corresponding to each subsystem.

[0097] The current curve coefficient is used to characterize the ratio of the current of the subsystem during chip operation to the current of the subsystem when the subsystem is running alone.

[0098] Ideally, the current curve factor is 1. In reality, due to factors such as the actual hardware structure, the current curve factor may not be 100% accurate and may be less than 1.

[0099] Optionally, in this embodiment of the application, the current curve coefficient corresponding to each subsystem is set to 1.

[0100] Step 502: Fit the current curve of the chip based on the current curve coefficients of each subsystem, the current curve of a single subsystem, and the current curve delay of each subsystem.

[0101] In this way, the current curve of the whole chip is fitted based on the current curve coefficients of the combined subsystems. Since the individual current curve coefficients of each subsystem are combined, the current curve fitting of the whole chip is more consistent with the actual current situation of the chip, thus ensuring the accuracy of the fitted current curve of the chip.

[0102] In an optional embodiment of this application, fitting the current curve of the chip based on the current curve coefficients corresponding to each subsystem, the current curve of a single subsystem, and the current curve delay of each subsystem includes: for each subsystem, obtaining a delayed current curve based on the current curve delay and the current curve of a single subsystem; and fitting the current curve of the chip based on the delayed current curve and the current curve coefficients corresponding to each subsystem.

[0103] The current curve delays of different subsystems may be different, and there may be cases where the current curve delays of some subsystems are the same. The specific delay depends on the location of each subsystem in the chip, and no specific limitation is made here.

[0104] Based on this, the corresponding delay current curve of each subsystem can be determined according to the current curve delay and current curve of each subsystem. In this way, the delay current curve of each subsystem can be accurately determined adaptively according to its own delay situation. Then, the current curve of the whole chip can be obtained by fitting the current curve coefficient.

[0105] In this embodiment, the delay current curve of each subsystem is determined by separately determining the current curve delay of each subsystem, and then the current curve of the entire chip can be fitted by combining the current curves of the subsystems. In this way, when adding or deleting a subsystem, it is only necessary to remeasure one delay current curve of the subsystem and update its coefficients, without having to re-collect the entire operating state of the entire chip as in traditional solutions, which significantly shortens the version iteration cycle.

[0106] For ease of understanding, the following description uses a complete embodiment to illustrate the method for rapidly fitting large-scale chip current curves to determine chip current curves provided in this application. (Reference) Figure 6 As shown, the method includes:

[0107] Step 1: Obtain the current curve of each subsys through simulation. .

[0108] Step 2: Obtain the current curve delay for each subsys. .

[0109] Step 3: Obtain the current curve coefficients for each subsys. .

[0110] Step 4: Fit the current curve of the entire chip. .

[0111] In this embodiment, the ultra-large-scale chip is divided into multiple different subsystems (subsys) according to their functions. First, the current curve of each subsystem is obtained through individual simulation. Then, the current delay relationship between subsystems and the current coefficient of each subsystem are obtained. Finally, the current curve of the entire chip under this scenario is fitted using a fitting formula. The fitting formula is:

[0112]

[0113] The :subsys subscript takes values ​​from 1 to m. : Current curve coefficient of the nth subsystem. The current curve delay of the nth subsystem relative to the reference time. Delay of the nth subsystem The current curve after that.

[0114] Taking the reset current curve of a certain ultra-large chip as an example, such as Figure 2 The diagram shows a reset tree of a very large-scale chip, which is mainly composed of 40 subsystems (one module is instantiated 40 times). RST_n is the reset pin of the entire chip, which is connected to all subsystems through the reset tree.

[0115] One of the most demanding scenarios in PI simulation is when 40 subsystems are running services at maximum power consumption, RST_n reset takes effect, the chip switches from maximum power consumption state to reset state, and the chip current changes abruptly.

[0116] In this embodiment, the current curve of a single subsystem is first obtained through simulation, such as... Figure 3 As shown.

[0117] Furthermore, the current curve delay for each current curve is obtained. This can be obtained by querying the routing delay of each subsystem's reset relative to the RST_n reset pin in the backend. For example, Table 1 shows the reset delay value (i.e., the current curve delay in the reset scenario) for each subsystem:

[0118] Table 1

[0119]

[0120] Obtain the coefficients of the current curve for each subsystem. In this example, we take 1.

[0121] The reset current curve of the entire chip is fitted using the fitting formula. For example, the current curve of the chip obtained by fitting the data above is as follows: Figure 7 As shown.

[0122] Compared with methods that determine the current curve based on the assumed toggle rate and methods that perform business simulation based on the whole chip, the method provided in this application embodiment has a shorter overall chip current curve determination time, higher accuracy, and lower resource consumption.

[0123] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0124] Based on the same inventive concept, this application also provides an apparatus for determining a chip current curve to implement the method for determining a chip current curve described above. The solution provided by this apparatus is similar to the solution described in the above method; therefore, the specific limitations in one or more embodiments of the apparatus for determining a chip current curve provided below can be found in the limitations of the method for determining a chip current curve described above, and will not be repeated here.

[0125] In one embodiment, such as Figure 8 As shown, an apparatus for determining a chip current curve is provided, comprising: a curve module, a delay module, and a fitting module, wherein:

[0126] The curve module is used to determine the current profile of a single subsystem in the chip; wherein the chip includes multiple subsystems based on current profiles.

[0127] The delay module is used to determine the current curve delay of each subsystem; wherein, the current curve delay is the delay of the current curve of the subsystem relative to the reference time point.

[0128] The fitting module is used to fit the chip's current curve based on the current curve of a single subsystem and the delay of the current curves of each subsystem.

[0129] In one embodiment, the fitting module is specifically used for:

[0130] Obtain the current curve coefficients corresponding to each subsystem; the current curve coefficients are used to characterize the ratio of the current of the subsystem during chip operation to the current of the subsystem when the subsystem is running alone.

[0131] The chip's current curve is fitted based on the current curve coefficients corresponding to each subsystem, the current curve of a single subsystem, and the current curve delay of each subsystem.

[0132] In one embodiment, the fitting module is specifically used for:

[0133] For each subsystem, the delayed current curve is obtained by comparing the current curve with the current curve of the individual subsystem.

[0134] The current curve of the chip is fitted based on the delay current curve and current curve coefficients corresponding to each subsystem.

[0135] In one embodiment, the curve module is specifically used for:

[0136] A single subsystem is simulated based on a preset simulation model, and the current curve of the single subsystem output by the preset simulation model is obtained.

[0137] In one embodiment, the delay module is specifically used for:

[0138] Obtain the chip layout;

[0139] Based on the chip layout, identify the reset trace length of each subsystem's reset receiver relative to the chip's reset pin;

[0140] The current curve delay for each subsystem is determined based on the reset trace length for each subsystem.

[0141] Each module in the aforementioned device for determining the chip current curve can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the operations corresponding to each module.

[0142] In one exemplary embodiment, a computer device is provided, the internal structure of which can be as shown in the figure. Figure 9 As shown, this computer device includes a processor, memory, input / output interfaces (I / O), and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores data for determining chip current curves. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communication with external terminals via a network connection. When executed by the processor, the computer program implements a method for determining chip current curves.

[0143] Those skilled in the art will understand that Figure 9 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0144] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0145] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0146] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0147] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0148] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0149] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for determining a chip current curve, characterized in that, The method includes: Determine the current profile of a single subsystem in a chip; wherein the chip includes multiple subsystems based on the current profiles; Determine the current curve delay for each of the subsystems; wherein the current curve delay is the delay of the current curve of the subsystem relative to a reference time point; The current curve of the chip is fitted based on the current curve of the individual subsystem and the delay of the current curve of each subsystem.

2. The method according to claim 1, characterized in that, The step of fitting the current curve of the chip based on the current curve of the individual subsystem and the current curve delay of each subsystem includes: Obtain the current curve coefficients corresponding to each subsystem; the current curve coefficients are used to characterize the ratio of the current of the subsystem during chip operation to the current of the subsystem when the subsystem is running alone; The current curve of the chip is fitted based on the current curve coefficients corresponding to each subsystem, the current curve of the individual subsystem, and the current curve delay of each subsystem.

3. The method according to claim 2, characterized in that, The step of fitting the current curve of the chip based on the current curve coefficients corresponding to each subsystem, the current curve of the individual subsystem, and the current curve delay of each subsystem includes: For each of the subsystems, a delayed current curve is obtained by comparing the current curve with the current curve of the individual subsystem. The current curve of the chip is fitted based on the delay current curve and current curve coefficient corresponding to each subsystem.

4. The method according to any one of claims 1 to 3, characterized in that, The determination of the current profile of a single subsystem in the chip includes: The current curve of the single subsystem is obtained by simulating a single subsystem based on a preset simulation model.

5. The method according to any one of claims 1 to 3, characterized in that, The determination of the current curve delay for each of the subsystems includes: Obtain the layout of the chip; Based on the chip layout, identify the reset trace length of each subsystem's reset receiver relative to the chip's reset pin; The current curve delay corresponding to each subsystem is determined based on the reset trace length of each subsystem.

6. An apparatus for determining a chip current curve, characterized in that, The device includes: A curve module is used to determine the current curve of a single subsystem in a chip; wherein the chip includes multiple subsystems based on the current curves; A delay module is used to determine the current curve delay of each of the subsystems; wherein the current curve delay is the delay of the current curve of the subsystem relative to a reference time point; The fitting module is used to fit the current curve of the chip based on the current curve of the individual subsystem and the current curve delay of each subsystem.

7. The apparatus according to claim 6, characterized in that, The fitting module is specifically used for: Obtain the current curve coefficients corresponding to each subsystem; the current curve coefficients are used to characterize the ratio of the current of the subsystem during chip operation to the current of the subsystem when the subsystem is running alone; The current curve of the chip is fitted based on the current curve coefficients corresponding to each subsystem, the current curve of the individual subsystem, and the current curve delay of each subsystem.

8. The apparatus according to claim 7, characterized in that, The fitting module is specifically used for: For each of the subsystems, a delayed current curve is obtained by comparing the current curve with the current curve of the individual subsystem. The current curve of the chip is fitted based on the delay current curve and current curve coefficient corresponding to each subsystem.

9. The apparatus according to any one of claims 6 to 8, characterized in that, The curve module is specifically used for: The current curve of the single subsystem is obtained by simulating a single subsystem based on a preset simulation model.

10. The apparatus according to any one of claims 6 to 8, characterized in that, The delay module is specifically used for: Obtain the layout of the chip; Based on the chip layout, identify the reset trace length of each subsystem's reset receiver relative to the chip's reset pin; The current curve delay corresponding to each subsystem is determined based on the reset trace length of each subsystem.

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