Multiphase clock generation module, parallel-serial conversion circuit and chip

Abstract

The invention provides a multi-phase clock generation module, a parallel-serial conversion circuit and a chip, and relates to the technical field of digital signal processing.According to the multi-phase clock generation module, a simple logic unit is additionally arranged, and by means of a step-by-step synchronization mode from low frequency to high frequency, the multi-phase clock generation efficiency is improved; the multi-phase signal is started from the determined initial state during each power-on or mode switching, so that the phase relationship between the multi-phase clock and the data splicing time sequence is stable and controllable, the error code risk caused by the random multi-phase initial phase is reduced, the method can be adapted to data conversion systems of various different rate application scenes, and the data splicing efficiency is improved. And a complicated calibration control circuit is not needed. The architecture provided by the invention can be conveniently expanded to high-speed interface scenes with different parallel bit widths, different multi-phase numbers and different target rates, and has good universality and portability while keeping a low bit error rate and high time sequence robustness.

Description

Technical Field

[0001] This application relates to the field of digital signal processing technology, and in particular to a multiphase clock generation module, a parallel-to-serial conversion circuit, and a chip. Background Technology

[0002] With the rapid development of 5G communication and artificial intelligence technologies, the requirements for high-speed, efficient, and low-power data transmission links are increasing in applications such as data centers, high-speed communication networks, consumer electronics, and industrial automation. Taking video signal transmission as an example, as display resolution and refresh rates continue to improve, the throughput required for a single data link increases significantly, making high-speed serial data interfaces a key module in system design. To achieve higher data rates under limited pin resources and power consumption constraints, high-speed serial transmission is often used, achieving data bandwidth aggregation through the conversion of parallel data to serial data. Among these, the Parallel-In Serial-Out (PISO) converter circuit is one of the core units in high-speed interface circuits.

[0003] In traditional technologies, high-speed PISO structures mainly include three basic topologies: parallel, serial, and tree-type. In engineering, multiple structures are typically combined, along with multi-phase clocks, to achieve timing interleaving and splicing of multi-bit data. As the target transmission rate continues to increase, the frequency of the clock signal used to drive the PISO also rises, making the phase accuracy of the multi-phase signal and its timing relationship with the data to be spliced ​​increasingly sensitive. When the phase deviation between the multi-phase clock and the data is too large or the margin is insufficient, it can easily cause data splicing errors, increase the bit error rate of the parallel-to-serial conversion link, and affect the overall reliability and stability of the high-speed interface.

[0004] Typically, multiphase clock generation circuits can be implemented using a ring shift register connected end-to-end with set and reset terminals. In this structure, the reset signal not only sets the initial state of the ring shift register but also directly determines the initial phase relationship of the multiphase clocks when the system powers on or switches modes. If there is an asynchronous relationship between the reset signal and different clock domains, it may cause random drift in the initial phase of the multiphase clock, making it difficult to accurately control the alignment relationship between the multiphase clocks and the data to be spliced, thus increasing the bit error rate of the parallel-to-serial conversion circuit. Summary of the Invention

[0005] The technical problem to be solved by this application is to provide a multiphase clock generation module, a parallel-to-serial conversion circuit and chip to overcome the problem that in the traditional technology, there is an asynchronous relationship between the reset signal and different clock domains, which may cause random drift of the initial phase of the multiphase clock, making it difficult to accurately control the alignment relationship between the multiphase clock and the data to be spliced, resulting in an increase in the bit error rate of the parallel-to-serial conversion circuit.

[0006] Firstly, this application proposes a multiphase clock generation module, comprising: A logic unit is used to sample a reset signal sequentially from low to high frequency using multiple clock signals of different frequencies to obtain an intermediate reset signal that is related to the timing of each clock signal. The ring shift register is used to sequentially shift the effective level between each level register under the control of the intermediate reset signal, and output a multi-channel multi-phase clock signal with a preset duty cycle and sequentially staggered phases.

[0007] In one embodiment, the logic unit includes: A cascaded multi-stage flip-flop link, wherein the input and reset terminals of the multi-stage flip-flop link are connected to the reset signal; wherein, each clock signal is sequentially configured to at least one flip-flop as a sampling signal in order of frequency from low to high, so as to realize the step-by-step synchronization of the reset signal from the low-frequency clock domain to the high-frequency clock domain; A NAND gate is used to perform a NAND operation between the output signal of a multi-stage flip-flop link and the reset signal; An inverter is used to invert the result of a NAND operation to form an intermediate reset signal.

[0008] In one embodiment, the multi-level trigger link includes a first trigger, a second trigger, a third trigger, and a fourth trigger connected in sequence; the clock signals are denoted as the first clock signal, the second clock signal, and the third clock signal in descending order of frequency. The data input terminal of the first flip-flop is connected to the reset signal, and the clock input terminal is connected to the third clock signal. The clock input of the second flip-flop is connected to the second clock signal; The clock inputs of the third and fourth flip-flops are connected to the first clock signal, and the output of the fourth flip-flop is connected to a NAND gate.

[0009] In one embodiment, the logic unit further includes a first shaping subunit, which includes two inverters connected in series. The reset signal, after passing through the first shaping sub-unit, is connected to the input and reset terminals of the multi-stage trigger link, respectively.

[0010] In one embodiment, the logic unit further includes a second shaping subunit, which includes two inverters connected in series. After passing through the second shaping sub-unit, the first clock signal is connected to the logic unit and the ring shift register respectively.

[0011] Secondly, this application proposes a parallel-to-serial conversion circuit, comprising: The multiphase clock generation module described in any one of the first aspects is used to sample a reset signal sequentially from low to high frequency using multiple clock signals of different frequencies to obtain an intermediate reset signal related to the timing of each clock signal, and to use the intermediate reset signal as the reset signal of a ring shift register to generate multiple multiphase clock signals under the drive of the ring shift register. The preprocessing module is used to group the input parallel data signals to form multiple first intermediate data signals; A synchronization module is used to sample each of the first intermediate data signals based on a clock control signal to output multiple second intermediate data signals that are time-aligned with the clock control signal; wherein the clock control signal is at least two of the multi-phase clock signals, and the sampling edge of each of the multi-phase clock signals is located at a preset position within the effective range of its corresponding first intermediate data signal. The splicing module is used to select and output each bit of the second intermediate data signal based on each of the multi-phase clock signals to form a first serial data signal; The retiming module is used to retime the first serial data signal under the control of the enable control signal and output the target serial data signal.

[0012] In one embodiment, the preprocessing module groups the input parallel data signals to form multiple first intermediate data signals, including: After the reset signal is released, the preprocessing module latches the parallel data signal on the trigger edge of the second clock signal, and divides the latched parallel data signal into multiple groups of data according to a preset bit width, wherein each group of data includes at least two adjacent data signals. Within one cycle of the second clock signal, based on the level state of the third clock signal, different data signals in each group are sequentially selected to form multiple first intermediate data signals.

[0013] In one embodiment, the splicing module selects and outputs each bit of the second intermediate data signal based on each of the multi-phase clock signals to form a first serial data signal, including: After the reset signal is released, the splicing module responds to the trigger edge of the first clock signal and sequentially detects the effective level range of each multi-phase clock signal according to the phase sequence of each multi-phase clock signal within a cycle. When a certain multi-phase clock signal is detected to be at an effective level, the module generates a corresponding data strobe signal. For a multi-phase clock signal corresponding to a data strobe signal, a second intermediate data signal corresponding to the multi-phase clock signal is selected, and each bit of the second intermediate data signal is output sequentially under multiple consecutive bit beats of the first clock signal, thereby completing the bit-by-bit splicing output of all second intermediate data signals in a predetermined order within one multi-phase clock signal cycle. In one embodiment, the retiming module, under the control of an enable control signal, retims the first serial data signal and outputs a target serial data signal, including: When the enable control signal is valid, the retiming module samples the first serial data signal on the consecutive trigger edges of the output clock signal and uses the sampled data as the target serial data signal; wherein the flip time of the target serial data signal is aligned with the edge of the output clock signal, and the output clock signal is the inverse of the first clock signal.

[0014] Thirdly, this application proposes a chip comprising: the parallel-to-serial conversion circuit described in any one of the second aspects. The aforementioned multiphase clock generation module, parallel-to-serial conversion circuit, and chip have at least the following advantages: This application's multiphase clock generation module, by adding simple logic units, uses multiple clock signals of different frequencies to sample the reset signal sequentially from low to high frequency, synchronizing to obtain an intermediate reset signal, which is then used as the reset input of the ring shift register. Employing a step-by-step synchronization method from low to high frequency ensures that the multiphase signals start from a defined initial state each time power is applied or mode is switched. This results in a stable and controllable phase relationship between the multiphase clock and the data splicing timing, reducing the risk of bit errors caused by random initial phases of the multiphase signals. It is adaptable to data conversion systems in various application scenarios with different speeds and requires no complex calibration control circuitry. The architecture of this application can be easily extended to high-speed interface scenarios with different parallel bit widths, different numbers of multiphase signals, and different target speeds, maintaining low bit error rates and high timing robustness while exhibiting good versatility and portability. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of a multiphase clock generation circuit in traditional technology. Figure 2 This is a structural block diagram of a multiphase clock generation module in one embodiment; Figure 3 This is a schematic diagram of the structure of a multiphase clock generation module in one embodiment; Figure 4 This is a timing diagram illustrating the generation of the intermediate reset signal in one embodiment; Figure 5This is a timing diagram illustrating the generation of a multiphase clock signal in one embodiment; Figure 6 This is a block diagram of a parallel-to-serial conversion circuit in one embodiment; Figure 7 This is a schematic diagram of the parallel-to-serial conversion circuit in one embodiment; Figure 8 This is a timing diagram of the parallel-to-serial conversion circuit in one embodiment; Figure 9 This is a block diagram of the chip structure in one embodiment. Detailed Implementation

[0016] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0017] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0018] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0019] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0020] In this application, unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a direct connection or an indirect connection through an intermediate medium, or they can refer to the internal connection of two elements or the interaction between two elements. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0021] Please see Figure 1 , Figure 1 The diagram shows a schematic of a multiphase clock generation circuit in a traditional technique. This multiphase clock generation circuit is implemented using a ring shift register with set and reset terminals connected end-to-end. Taking a 5-channel multiphase clock generation circuit as an example, the CLK signal is passed sequentially through inverters INV1 and INV2 to serve as the clock signal for the ring shift register; the RSTB signal is passed sequentially through inverters INV3 and INV4 to serve as the reset signal for the ring shift register. The first stage DFF1 is a D flip-flop with a set terminal, and DFF2-DFF5 are D flip-flops with reset terminals.

[0022] Initially, the reset signal RSTB is low, PQ0 outputs high, and PQ1-PQ4 output low. When the reset signal RSTB changes from low to high, and the rising edge of the CLK high-frequency clock signal arrives, the output signal of PQ0 changes from high to low, the output signal of PQ1 changes from low to high, and PQ2-PQ4 remain low. Upon the next rising edge of the CLK high-frequency clock signal, the output signal of PQ1 changes from high to low, the output signal of PQ2 changes from low to high, and the other clock signals remain unchanged. This process continues, ultimately generating five multi-phase clock signals PQ0-PQ4 with a duty cycle of 20% and a frequency 1 / 5 of the CLK high-frequency clock signal. PQ0-4 and PQ0-4 have the same frequency and duty cycle.

[0023] As transmission rates continue to increase, clock frequencies become higher and higher, making it increasingly difficult to control the phase between the clock signal used for data splicing and the data itself, which in turn affects the bit error rate of the parallel-to-serial conversion circuit. Figure 1 The reset signal of the multiphase clock generation circuit will affect the initial phase of the generated multiphase clock signal. If the phase difference between the multiphase clock signal and the spliced ​​data is too large or there are timing differences, the data splicing may fail, and the parallel-to-serial conversion circuit will generate incorrect serial data, resulting in bit errors. This problem is particularly pronounced in multi-rate or combo interface sampling systems.

[0024] Based on this, this application provides a parallel-to-serial conversion circuit that uses multiple clock signals of different frequencies to sample the reset signal sequentially from low to high frequency. After synchronizing to obtain an intermediate reset signal, it is then used as the reset input of the ring shift register. By employing a step-by-step synchronization method from low to high frequency, the multi-phase signals start from a defined initial state each time they are powered on or during mode switching. This ensures that the phase relationship between the multi-phase clock and the data splicing timing is stable and controllable, reducing the risk of bit errors caused by random initial phases of the multi-phase signals.

[0025] Please see Figure 2 In one embodiment, this application provides a multiphase clock generation module, including: a logic unit and a ring shift register.

[0026] The logic unit is used to sample the reset signal sequentially from low to high frequency using multiple clock signals of different frequencies to obtain an intermediate reset signal that is related to the timing of each clock signal.

[0027] Specifically, Figure 2 The CLK, CLK_DIV5, and CLK_DIV10 shown are the clock signals. For ease of description, the clock signals are referred to as the first clock signal, the second clock signal, and the third clock signal, respectively.

[0028] In this embodiment, the input first clock signal CLK is divided to obtain a second clock signal CLK_DIV5 and a third clock signal CLK_DIV10, wherein the second clock signal CLK_DIV5 is a multiple of the third clock signal CLK_DIV10. For example, the first clock signal CLK is divided by five to obtain the second clock signal CLK_DIV5, and the second clock signal CLK_DIV5 is divided by two to obtain the third clock signal CLK_DIV10. It should be understood that in other embodiments, the division factor and the number of clock signals can be selected according to actual needs.

[0029] A ring shift register is used to cyclically shift the effective level between registers in turn under the control of an intermediate reset signal, and output multiple multi-phase clock signals with preset duty cycles and sequentially staggered phases.

[0030] Specifically, under the control of the intermediate reset signal, the ring shift register sequentially shifts the effective level among each stage of the register within multiple consecutive clock cycles of the first clock signal. This ensures that only one multi-phase clock signal is active at any given time, and the effective level windows of each multi-phase clock signal are staggered in time within a clock cycle, thus giving each multi-phase clock signal a preset duty cycle and staggering its phase. Taking a ring shift register outputting 5 multi-phase clock signals as an example, the duty cycle is 20%.

[0031] Please see Figure 3 Optionally, the logic unit includes: a multi-level flip-flop link, a NAND gate and an inverter, wherein the multi-level flip-flop link includes a first flip-flop, a second flip-flop, a third flip-flop and a fourth flip-flop connected in sequence.

[0032] The multi-level trigger links are cascaded, and each trigger is a D flip-flop. For example... Figure 3 The flip-flops DFF6-DFF9 in the above-mentioned cascaded multi-stage flip-flop link constitute the above-mentioned multi-stage flip-flop link. The output of the previous flip-flop is connected to the data input of the next flip-flop, and the first flip-flop DFF6 serves as the input of the multi-stage flip-flop link and is connected to the reset signal. Figure 3 The RSTB connection shown in the diagram uses the reset terminals of flip-flops DFF6-DFF9 as the reset terminals of the multi-stage flip-flop link, which are connected to the reset signal. Each clock signal is configured to be sampled by at least one flip-flop in order of increasing frequency, so as to realize the step-by-step synchronization of the reset signal from the low-frequency clock domain to the high-frequency clock domain.

[0033] It should be noted that the above multi-level trigger link connection method is only an example. In actual applications, the required number of triggers can be selected as needed.

[0034] Optionally, the logic unit further includes a first shaping sub-unit, which comprises two inverters connected in series ( Figure 3 (As shown in INV3 and INV4).

[0035] After the reset signal RSTB passes through the first shaping sub-unit ( Figure 3 RSTB1 shown is connected to the input and reset terminals of the multi-stage trigger link, respectively.

[0036] Optionally, the logic unit further includes a second shaping sub-unit, which comprises two inverters connected in series (…). Figure 3 (As shown in INV1 and INV2).

[0037] After the first clock signal CLK passes through the second shaping sub-unit ( Figure 3 The CK shown in the figure is connected to the logic unit and the ring shift register, respectively.

[0038] Furthermore, the data input of the first flip-flop DFF6 is connected to the reset signal RSTB1, and its clock input is connected to the clock signal CLK_DIV10B; the clock input of the second flip-flop DFF7 is connected to the clock signal CLK_DIV5B; the clock inputs of the third flip-flop DFF8 and the fourth flip-flop DFF9 are connected to the clock signal CK, and the output of the fourth flip-flop DFF9 is connected to the NAND gate NAND1. In this embodiment, the high-frequency first clock signal is sampled twice, firstly to consider the overall timing matching of the PISO circuit. At the same time, considering that the clock signal Q1 output by the second flip-flop DFF7 is asynchronous with respect to the high-frequency first clock signal CLK, it may cause the third flip-flop DFF8 to enter a metastable state. This metastable state may lead to the subsequent intermediate reset signal (…). Figure 3 As shown, edge jitter of RSTB_INT can trigger malfunctions. Two-stage synchronization also ensures that changes in clock signals Q1 and Q2 lead to the output of clock signal Q3 after at least two CLK cycles, thus ensuring signal stability.

[0039] The NAND gate NAND1 is used to perform a NAND operation between the output signal of the multi-stage flip-flop link and the reset signal. The above scheme, which connects the original reset signal to the NAND gate NAND1, takes into account that the clock signal Q3 is only updated on the rising edge of the CLK signal. This ensures that the intermediate reset signal can promptly return to the reset state when the reset signal is suddenly pulled low.

[0040] An inverter is used to invert the result of a NAND operation, forming an intermediate reset signal. The combination of an inverter and a NAND gate can prevent false triggering caused by glitches or other abnormal signals in the reset signal.

[0041] Figure 3 The flip-flops DFF1-DFF5 in the above-mentioned ring shift register constitute the ring shift register. Among them, flip-flop DFF1 is a D flip-flop with a set input, and DFF2-DFF5 are D flip-flops with reset inputs.

[0042] It should be noted that the above connection method of the ring shift register is only an example. In actual applications, the number of triggers can be selected according to the needs.

[0043] Please see Figure 4 and Figure 5 The following is combined Figure 4 and Figure 5 The timing of the multiphase clock generation module of this application is described. Figure 4 and Figure 5 In this context, Tclk represents one cycle of the first clock signal.

[0044] Figure 4 The diagram shows the timing sequence for generating the intermediate reset signal. The reset signal RSTB is passed through two inverters, INV3 and INV4, to obtain the clock signal RSTB1. The clock signal RSTB1 serves as the reset signal for flip-flops DFF6-DFF9 and the input signal for the data input terminal of flip-flop DFF6. The third clock signal CLK_DIV10 is inverted by inverter INV5 to generate the clock signal CLK_DIV10B. The clock signal CLK_DIV10B is used to sample the RSTB1 signal to generate the clock signal Q0.

[0045] After the reset signal RSTB is released, the clock signal Q0 changes from low to high after the rising edge of the clock signal CLK_DIV10B arrives.

[0046] The second clock signal CLK_DIV5 is converted into clock signal CLK_DIV5B by inverter INV6. Clock signal CLK_DIV5B is used to sample clock signal Q0 and generate clock signal Q1. That is, clock signal Q1 changes from low level to high level after the rising edge of clock signal CLK_DIV5B arrives.

[0047] The high-frequency first clock signal CLK is generated by two stages of inverters INV1 and INV2 to generate a high-frequency clock signal CK. The clock signal CK is used as the sampling clock for flip-flops DFF8 and DFF9 to sample clock signals Q1 and Q2 respectively, and finally generates clock signal Q3. The clock signal Q3 is combined with NAND gate NADN1 and inverter INV7 to generate the reset signal RSTB_INT required by the ring shift register.

[0048] Depend on Figure 4 It is evident that the intermediate reset signal RSTB_INT is not only aligned with the rising edge of the high-frequency first clock signal CLK, but also differs from the first rising edge of the third clock signal CLK_DIV10 after the RSTB reset signal is released by 9 CLK cycles, and from the second rising edge of the clock signal CLK_DIV5 by 4 CLK cycles. Therefore, there is a clear timing relationship between the intermediate reset signal RSTB_INT and the PISO internal sampling clock CLK, and a clear timing relationship also exists between the sampling clock and the data signal. This results in five sets of multi-phase clock signals PH0-PH4 with clear initial phases, which also have a clear timing relationship with the parallel data signals, enabling better parallel-to-serial conversion of data. It should be understood that the working principle of the ring shift register has been explained in detail in the multi-phase clock generation circuit section of the aforementioned traditional technology, and therefore will not be repeated here.

[0049] Figure 5 The diagram shows the timing sequence for generating multiphase clock signals. Initially, PQ0 outputs a high level, and PQ1-PQ4 output a low level. When the intermediate reset signal RSTB_INT changes from low to high, the ring shift register starts working. At the rising edge of the clock signal CK, the output signal of PQ0 changes from high to low, the output signal of PQ1 changes from low to high, and PQ2-PQ4 remain low. After the rising edge of the next clock signal CK arrives, the levels of PQ1 and PQ2 change, while the other clock signals remain unchanged. This process continues until a total of 5 multiphase clock signals PQ0-PQ4 with a duty cycle of 20% and a frequency of 1 / 5 of the high-frequency clock signal CK are generated. That is, the high level lasts for one CLK cycle, and the phase difference between two adjacent clock signals is 72°. The inverted clock signals PQB0-PQB4 of the multiphase clock signals PQ0-PQ4 are generated into multiphase clock signals PH0-PH4 after passing through an inverter. The multiphase clock signals PH0-PH4 are the same as the clock signals PQ0-PQ4.

[0050] The aforementioned multi-phase clock generation module uses multiple clock signals of different frequencies in its logic unit. It samples the reset signal sequentially from low to high frequency, synchronizing to obtain an intermediate reset signal, which is then used as the reset input to the ring shift register. This step-by-step synchronization method from low to high frequency ensures that the multi-phase signals start from a defined initial state each time power is applied or mode is switched. This results in a stable and controllable phase relationship between the multi-phase clock and the data concatenation timing, reducing the risk of bit errors caused by random initial phases of the multi-phase clocks.

[0051] Please see Figure 6 and Figure 7 In one embodiment, this application provides a parallel-to-serial conversion circuit, including: the multiphase clock generation module, preprocessing module, synchronization module, splicing module and retiming module provided in the above embodiments.

[0052] Multiphase clock generation module ( Figure 7 The MPG (as shown) is used to sample reset signals sequentially from low to high frequency using multiple clock signals of different frequencies to obtain intermediate reset signals related to the timing of each clock signal. These intermediate reset signals are then used as the reset signals for the ring shift register, which drives the generation of multiple multi-phase clock signals. Specifically, in this embodiment, the multi-phase clock generation module uses three clock signals of different frequencies with the same initial phase, along with the reset signal RSTB, to generate five multi-phase clock signals PH0-PH4.

[0053] Preprocessing module ( Figure 7 The MUX_10_5 shown is used for processing the input parallel data signal ( Figure 7 The DATA[9:0] shown is grouped to form multiple first intermediate data signals ( Figure 7 (DQ0-DQ4 shown in the diagram). Specifically, in this embodiment, MUX_10_5 concatenates 10 parallel data streams into 5 parallel data streams.

[0054] Synchronization module ( Figure 7 The S2YNC shown is used to sample each first intermediate data signal based on a clock control signal to output multiple second intermediate data signals that are time-aligned with the clock control signal. The clock control signal consists of at least two multi-phase clock signals, and the sampling edge of each multi-phase clock signal is located at a preset position within the valid range of its corresponding first intermediate data signal. Specifically, in this embodiment, S2YNC samples the five parallel data streams output from MUX_10_5 using two multi-phase clocks generated by MPG, generating synchronized data signals DC0-DC4 respectively.

[0055] splicing module ( Figure 7The MUX_5_1 shown is used to select and output each second intermediate data signal bit by bit based on each multi-phase clock signal to form a first serial data signal. Specifically, in this embodiment, the MUX_5_1 uses the 5 multi-phase clock signals generated by MPG to splice the 5 parallel data DC0-DC4, and outputs a 10-bit serial data DA and a high-frequency clock signal CKA, wherein the clock signal CKA is the inverted signal of the first clock signal CLK.

[0056] Retiming module ( Figure 7 The RETIMER shown is used to enable the control signal ( Figure 7 Under the control of the PDB shown, the first serial data signal is retimed, and the target serial data signal is output. Figure 7 (DATA10 shown in the diagram). Specifically, in this embodiment, the RETIMER uses the clock signal CKA to retime the generated 1-channel serial data DA, outputting the final 10-bit serial data DATA10. Furthermore, the RETIMER can also output 10-bit serial data DATA10_PE and DATA10_DE with different delays required by the equalization algorithm.

[0057] Among them, the multi-phase clock generation module, preprocessing module, synchronization module, and splicing module use the same reset signal RSTB, and the retiming module uses the enable signal PDB, with the enable signal PDB being released earlier than the reset signal RSTB.

[0058] The reset signal RSTB and three clock signals CLK_DIV10, CLK_DIV5 and CLK of different frequencies are used as input signals for MPG, and five multi-phase clock signals PH0-PH4 with a duty cycle of 20% and the same frequency as CLK_DIV5 are output.

[0059] The reset signal RSTB, along with 10-bit parallel data and two clock signals CLK_DIV10 and CLK_DIV5, serve as the input signals for MUX_10_5, outputting five sets of parallel data signals DQ0-DQ4 that have been spliced ​​together in 2 bits.

[0060] The reset signal RSTB, data signals DQ0-DQ4, and multiphase clocks PH1 and PH3 serve as input signals for S2YNC. After synchronization by two multiphase clocks, five sets of synchronized data signals DC0-DC4 are output. Among them, three sets of data DC0-DC2 are synchronized with the rising edge of PH1, and two sets of data DC3-DC4 are synchronized with the rising edge of PH3.

[0061] The reset signal RSTB, multi-phase clock signals PH0-PH4, data signals DC0-DC4, and the first clock signal CLK are used as input signals of MUX_5_1 to complete 10-bit data splicing and output one 10-bit serial data signal DA and a high-frequency clock signal CKA. The clock signal CKA is out of phase with the first clock signal CLK.

[0062] Please see Figure 8 , Figure 8 The figure shown is a timing diagram of the parallel-to-serial conversion circuit of this application. The following is a summary of the timing diagram. Figure 8 The working principle of each module in the parallel-to-serial conversion circuit is explained in detail.

[0063] Optionally, the preprocessing module groups the input parallel data signals to form multiple first intermediate data signals, including: after the reset signal is released, the preprocessing module latches the parallel data signals on the trigger edge of the second clock signal, and divides the latched parallel data signals into multiple groups of data according to a preset bit width, wherein each group of data includes at least two adjacent data signals; within one cycle of the second clock signal, based on the level state of the third clock signal, different data signals in each group are selected sequentially to form multiple first intermediate data signals.

[0064] The splicing module selects and outputs each bit of the second intermediate data signal based on each multi-phase clock signal to form a first serial data signal. This includes: after the reset signal is released, the splicing module responds to the trigger edge of the first clock signal and sequentially detects the effective level range of each multi-phase clock signal according to the phase sequence of each multi-phase clock signal within one cycle. When a certain multi-phase clock signal is detected to be at an effective level, a corresponding data gating signal is generated. For a multi-phase clock signal corresponding to a data gating signal, a second intermediate data signal corresponding to that multi-phase clock signal is selected, and each bit of the second intermediate data signal is sequentially output under multiple consecutive bit beats of the first clock signal, thereby completing the bit-by-bit splicing and output of all second intermediate data signals in a predetermined order within one multi-phase clock signal cycle. Under the control of the enable control signal, the first serial data signal is retimed to output the target serial data signal, including: when the enable control signal is valid, the retiming module samples the first serial data signal on the continuous trigger edges of the output clock signal, and uses the sampled data as the target serial data signal; wherein, the flip time of the target serial data signal is aligned with the edge of the output clock signal, and the output clock signal is the inverse signal of the first clock signal.

[0065] Specifically, the third clock signal CLK_DIV10 is used to latch the input parallel data signal, and the second clock signal CLK_DIV5 is the selection signal. Since the frequency of the second clock signal is twice that of the third clock signal in this embodiment, two rising edges of CLK_DIV5 will be experienced within one CLK_DIV10 cycle.

[0066] The parallel data DATA[9:0] is sampled at the rising edge of the clock signal CLK_DIV10B. The lower 5 bits of parallel data are directly output as DATA_INT[4:0] on the rising edge of CLK_DIV10B, while the higher 5 bits of parallel data are latched and output as DATA_INT[9:5] on the falling edge of CLK_DIV10B. The internal clock signal CKQ is generated by sampling the third clock signal CLK_DIV10 at the rising edge of the CLK_DIV5B clock signal. The CKQ signal acts as a switch selection control signal, selecting the output of the lower 5 bits of parallel data DQ0-DQ4 DATA0-DATA4 during the low level period of half a cycle, and selecting the output of the higher 5 bits of parallel data DQ0-DQ4 DATA5-DATA9 during the high level period of half a cycle.

[0067] The rising edge of a multi-phase clock signal PH1 samples the lower 5 bits of data DATA0-DATA4 output from DQ0-DQ4. Because the falling edge of the internal clock signal CKQ differs from the rising edge of the multi-phase clock signal PH1 by 2.5 CLK cycles, the rising edge of the multi-phase clock signal PH1 is located exactly in the middle of the lower 5 bits of data, effectively ensuring sampling quality and accuracy. Of the lower 5 bits of data DQ0-DQ4 sampled by the multi-phase clock signal PH1, the first 3 bits, DATA0-DATA2, are directly output, while the last 2 bits, DATA3-DATA4, are sampled again by the rising edge of another multi-phase clock signal PH3 before being output. Therefore, the first 3 bits, DC0-DC2, and the last 2 bits, DC3-DC4, differ by two CLK cycles.

[0068] Furthermore, this application uses the high levels of multi-phase clock signals PH2, PH3, and PH4 to sample and concatenate the lower 3 bits of data DATA0-DATA2, and uses the high levels of multi-phase clock signals PH0 and PH1 to sample and concatenate the last 2 bits of data DATA3-DATA4. Similarly, the rising edge of the next cycle of multi-phase clock signals PH1 and PH3 samples and outputs the higher 5 bits of data DATA5-DATA9, the principle of which is the same as the sampling of the lower 5 bits of data signals described above. The high levels of multi-phase clock signals PH2, PH3, and PH4 are used to sample and concatenate the first 3 bits of the higher 5 bits of data DATA5-DATA7, and the high levels of multi-phase clock signals PH0 and PH1 are used to sample and concatenate the higher 2 bits of data DATA8-DATA9, ultimately completing the concatenation of 10 bits of parallel data into a single serial data signal DA output.

[0069] The retiming module generates a high-frequency clock signal CKA by inverting the high-frequency clock signal CLK, samples the 10-bit serial data signal DA, realizes the retiming of the 10-bit serial data, and finally outputs the 10-bit serial data DATA10.

[0070] Using the above scheme, the multiphase clock generation module employs multiple clock signals of different frequencies, sampling the reset signal sequentially from low to high frequency. After synchronizing to obtain an intermediate reset signal, this signal is used as the reset input to the ring shift register. This step-by-step synchronization from low to high frequency ensures that the multiphase signals start from a defined initial state each time power is applied or mode is switched. This stabilizes and controls the phase relationship between the multiphase clock and the data concatenation timing, reducing the risk of bit errors caused by random initial phases. Furthermore, by adding simple logic units, a multiphase clock signal with a clear timing relationship between its initial phase and multiple sampled clock signals can be generated. This adaptable to data conversion systems with various application rates, without requiring complex calibration control circuits.

[0071] Furthermore, the preprocessing module groups the input parallel data signals to form multiple first intermediate data signals; the synchronization module then selects at least two multi-phase clocks as clock control signals to sample each first intermediate data signal, obtaining multiple second intermediate data signals that are time-aligned with the clock control signals. By pre-configuring the sampling edges of each multi-phase clock at preset positions within the valid data range of the corresponding first intermediate data signal, it is ensured that the sampling time is far from the data flip edge, achieving optimal sampling results to guarantee sampling accuracy, solving the problem of high-speed parallel-to-serial conversion, and reducing the bit error rate.

[0072] Furthermore, the splicing module selects and outputs the second intermediate data signal bit by bit based on the aforementioned multi-channel multi-phase clock, sequentially splicing multiple parallel data streams into a single first serial data signal. This enables fine-grained phase control of data from different time slots, ensuring the consistency of clock and data signals in the high-speed interface parallel-to-serial conversion circuit. The multi-phase clock signal in this application is used not only as the sampling clock signal for parallel data but also for splicing parallel data in the parallel-to-serial conversion circuit. The timing relationship between the multi-phase clock signal and the parallel data signal is clear, effectively ensuring the consistency of clock and data signals in the parallel-to-serial conversion circuit and achieving correct conversion from parallel data to serial data.

[0073] Furthermore, the retiming module samples and retims again before the first serial data signal is output, effectively isolating the combined delays and timing uncertainties in the preprocessing, synchronization and splicing stages. This ensures that the edges of the final output serial data are completely constrained by the output clock signal, making it easier to match with the timing of the subsequent equalization circuit and interface protocol. This helps to reduce the system bit error rate and improve the working stability under different process, temperature and voltage conditions.

[0074] Finally, by adopting the above-mentioned independent multi-functional module design, the architecture of this application can be easily extended to high-speed interface scenarios with different parallel bit widths, different numbers of multiphases and different target rates. While maintaining low bit error rate and high timing robustness, it has good versatility and portability.

[0075] Please see Figure 9 In one embodiment, this application provides a chip including the parallel-to-serial conversion circuit provided in the above embodiments. The parallel-to-serial conversion circuit includes a multi-phase clock generation module, a preprocessing module, a synchronization module, a splicing module, and a retiming module.

[0076] The multi-phase clock generation module uses multiple clock signals of different frequencies and samples the reset signal sequentially from low to high frequency to obtain intermediate reset signals related to the timing of each clock signal. These intermediate reset signals are used as the reset signal for a ring shift register, which drives the generation of multiple multi-phase clock signals. The preprocessing module groups the input parallel data signals to form multiple first intermediate data signals. The synchronization module, based on a clock control signal, samples each of the first intermediate data signals to output multiple second intermediate data signals that are timing-aligned with the clock control signal. The clock control signal consists of at least two of the multi-phase clock signals, and the sampling edge of each multi-phase clock signal is located at a preset position within the valid range of its corresponding first intermediate data signal. The splicing module, based on each of the multi-phase clock signals, selects and outputs each of the second intermediate data signals bit by bit to form a first serial data signal. The retiming module, under the control of an enable control signal, retims the first serial data signal and outputs the target serial data signal.

[0077] The aforementioned chip employs a parallel-to-serial converter circuit to convert the input parallel data signal into a serial data signal. The multi-phase clock generation module uses multiple clock signals of different frequencies, sampling the reset signal sequentially from low to high frequency. The resulting intermediate reset signal is then used as the reset input for the ring shift register. This step-by-step synchronization from low to high frequency ensures that the multi-phase signals start from a defined initial state upon each power-on or mode switch. This stabilizes and controls the phase relationship between the multi-phase clock and the data concatenation timing, reducing the risk of bit errors caused by random initial phases. Furthermore, by adding simple logic units, a multi-phase clock signal with a clear timing relationship between its initial phase and the multiple sampled clock signals can be generated. This allows for data conversion systems with various data rates to be adapted to different application scenarios without requiring complex calibration control circuits.

[0078] Furthermore, the preprocessing module groups the input parallel data signals to form multiple first intermediate data signals; the synchronization module then selects at least two multi-phase clocks as clock control signals to sample each first intermediate data signal, obtaining multiple second intermediate data signals that are time-aligned with the clock control signals. By pre-configuring the sampling edges of each multi-phase clock at preset positions within the valid data range of the corresponding first intermediate data signal, it is ensured that the sampling time is far from the data flip edge, achieving optimal sampling results to guarantee sampling accuracy, solving the problem of high-speed parallel-to-serial conversion, and reducing the bit error rate.

[0079] Furthermore, the splicing module selects and outputs the second intermediate data signal bit by bit based on the aforementioned multi-channel multi-phase clock, sequentially splicing multiple parallel data streams into a single first serial data signal. This enables fine-grained phase control of data from different time slots, ensuring the consistency of clock and data signals in the high-speed interface parallel-to-serial conversion circuit. The multi-phase clock signal in this application is used not only as the sampling clock signal for parallel data but also for splicing parallel data in the parallel-to-serial conversion circuit. The timing relationship between the multi-phase clock signal and the parallel data signal is clear, effectively ensuring the consistency of clock and data signals in the parallel-to-serial conversion circuit and achieving correct conversion from parallel data to serial data.

[0080] Furthermore, the retiming module samples and retims again before the first serial data signal is output, effectively isolating the combined delays and timing uncertainties in the preprocessing, synchronization and splicing stages. This ensures that the edges of the final output serial data are completely constrained by the output clock signal, making it easier to match with the timing of the subsequent equalization circuit and interface protocol. This helps to reduce the system bit error rate and improve the working stability under different process, temperature and voltage conditions.

[0081] Finally, by adopting the above-mentioned independent multi-functional module design, the architecture of this application can be easily extended to high-speed interface scenarios with different parallel bit widths, different numbers of multiphases and different target rates. While maintaining low bit error rate and high timing robustness, it has good versatility and portability.

[0082] Please note that the above embodiments are for illustrative purposes only and do not imply any limitation on this application.

[0083] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0084] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0085] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A multiphase clock generation module, characterized in that, include: A logic unit is used to sample a reset signal sequentially from low to high frequency using multiple clock signals of different frequencies to obtain an intermediate reset signal that is related to the timing of each clock signal. The ring shift register is used to sequentially shift the effective level between each level register under the control of the intermediate reset signal, and output a multi-channel multi-phase clock signal with a preset duty cycle and sequentially staggered phases.

2. The multiphase clock generation module according to claim 2, characterized in that, The logic unit includes: A cascaded multi-stage flip-flop link, wherein the input and reset terminals of the multi-stage flip-flop link are connected to the reset signal; wherein, each clock signal is sequentially configured to at least one flip-flop as a sampling signal in order of frequency from low to high, so as to realize the step-by-step synchronization of the reset signal from the low-frequency clock domain to the high-frequency clock domain; A NAND gate is used to perform a NAND operation between the output signal of a multi-stage flip-flop link and the reset signal; An inverter is used to invert the result of a NAND operation to form an intermediate reset signal.

3. The circuit according to claim 2, characterized in that, The multi-level trigger link includes a first trigger, a second trigger, a third trigger, and a fourth trigger connected in sequence; each clock signal is denoted as the first clock signal, the second clock signal, and the third clock signal in descending order of frequency. The data input terminal of the first flip-flop is connected to the reset signal, and the clock input terminal is connected to the third clock signal. The clock input of the second flip-flop is connected to the second clock signal; The clock inputs of the third and fourth flip-flops are connected to the first clock signal, and the output of the fourth flip-flop is connected to a NAND gate.

4. The circuit according to claim 2, characterized in that, The logic unit further includes a first shaping subunit, which includes two inverters connected in series. The reset signal, after passing through the first shaping sub-unit, is connected to the input and reset terminals of the multi-stage trigger link, respectively.

5. The circuit according to claim 3, characterized in that, The logic unit further includes a second shaping subunit, which includes two inverters connected in series; After passing through the second shaping sub-unit, the first clock signal is connected to the logic unit and the ring shift register respectively.

6. A parallel-to-serial conversion circuit, characterized in that, include: The multiphase clock generation module according to any one of claims 1-5 is used to sample a reset signal sequentially in order of frequency from low to high using multiple clock signals of different frequencies to obtain an intermediate reset signal related to the timing of each clock signal, and to use the intermediate reset signal as the reset signal of the ring shift register to generate multiple multiphase clock signals under the drive of the ring shift register. The preprocessing module is used to group the input parallel data signals to form multiple first intermediate data signals; A synchronization module is used to sample each of the first intermediate data signals based on a clock control signal to output multiple second intermediate data signals that are time-aligned with the clock control signal; wherein the clock control signal is at least two of the multi-phase clock signals, and the sampling edge of each of the multi-phase clock signals is located at a preset position within the effective range of its corresponding first intermediate data signal. The splicing module is used to select and output each bit of the second intermediate data signal based on each of the multi-phase clock signals to form a first serial data signal; The retiming module is used to retime the first serial data signal under the control of the enable control signal and output the target serial data signal.

7. The circuit according to claim 6, characterized in that, The preprocessing module groups the input parallel data signals to form multiple first intermediate data signals, including: After the reset signal is released, the preprocessing module latches the parallel data signal on the trigger edge of the second clock signal, and divides the latched parallel data signal into multiple groups of data according to a preset bit width, wherein each group of data includes at least two adjacent data signals. Within one cycle of the second clock signal, based on the level state of the third clock signal, different data signals in each group are sequentially selected to form multiple first intermediate data signals.

8. The circuit according to claim 6, characterized in that, The splicing module, based on each of the multi-phase clock signals, selects and outputs each of the second intermediate data signals bit by bit to form a first serial data signal, including: After the reset signal is released, the splicing module responds to the trigger edge of the first clock signal and sequentially detects the effective level range of each multi-phase clock signal according to the phase sequence of each multi-phase clock signal within a cycle. When a certain multi-phase clock signal is detected to be at an effective level, the module generates a corresponding data strobe signal. For a multi-phase clock signal corresponding to a data strobe signal, a second intermediate data signal corresponding to the multi-phase clock signal is selected, and each bit of the second intermediate data signal is output sequentially under multiple consecutive bit beats of the first clock signal, thereby completing the bit-by-bit splicing output of all second intermediate data signals in a predetermined order within one multi-phase clock signal cycle.

9. The circuit according to claim 6, characterized in that, Under the control of the enable control signal, the retiming module retims the first serial data signal and outputs the target serial data signal, including: When the enable control signal is valid, the retiming module samples the first serial data signal on the consecutive trigger edges of the output clock signal and uses the sampled data as the target serial data signal; wherein the flip time of the target serial data signal is aligned with the edge of the output clock signal, and the output clock signal is the inverse of the first clock signal.

10. A chip, characterized in that, include: The parallel-to-serial conversion circuit according to any one of claims 6-9.

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