Display panel, spliced display panel and display device

Abstract

The invention discloses a display panel, a tiled display panel and a display device. The display panel comprises a display area; the first non-display area and the second non-display area are arranged on the two sides of the display area in the first direction; the third non-display area and the fourth non-display area are arranged on the two sides of the display area in the second direction; the display area comprises a plurality of pixel circuits; the plurality of pixel circuits are arranged along a first direction to form pixel circuit rows; the display panel further comprises a plurality of first scanning signal lines. The first scanning signal lines are electrically connected with the pixel circuits of the corresponding pixel circuit rows; the fourth non-display area comprises a binding area; the binding area is used for binding a driving chip or a flexible circuit board; the shift register comprises a plurality of cascaded shift register units; the shift register units are used for outputting scanning signals to the corresponding first scanning signal lines; the shift register is arranged in one of the display area, the third non-display area and the fourth non-display area. According to the technical scheme provided by the invention, the narrow frame design of the display panel is realized.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel, a splicing display panel, and a display device. Background Technology

[0002] With the development and advancement of display technology, the demand for display panels is increasing.

[0003] To address the narrow bezel design requirements of existing display panels, the wiring or circuitry in the non-display area surrounding the display area is often further arranged to reduce the width of the non-display area. For example, a vertical shift register (VSR) is provided in the non-display area to provide the gate scan signal. The VSR is located on the left and right bezels of the display area, occupying a certain amount of space. Summary of the Invention

[0004] This invention provides a display panel, a splicing display panel, and a display device to further realize the narrow bezel design of the display panel.

[0005] In a first aspect, embodiments of the present invention provide a display panel, comprising: a display area; a first non-display area and a second non-display area disposed on opposite sides of the display area along a first direction; a third non-display area and a fourth non-display area disposed on opposite sides of the display area along a second direction; the first direction and the second direction intersect. The display area includes multiple pixel circuits; the multiple pixel circuits are arranged along the first direction to form a pixel circuit row; the display panel also includes multiple first scan signal lines extending along the first direction; the first scan signal lines are electrically connected to the pixel circuits corresponding to the pixel circuit rows; the fourth non-display area includes a bonding area; the bonding area is used to bond a driver chip or a flexible circuit board; The shift register includes multiple cascaded shift register units; the shift register units are used to output scan signals to the corresponding first scan signal lines; the shift register is located in one of the display area, the third non-display area, and the fourth non-display area.

[0006] Secondly, embodiments of the present invention provide a splicing display panel, the splicing display panel including the display panel provided in any embodiment of the present invention.

[0007] Thirdly, embodiments of the present invention also provide a display device, including the display panel provided in any embodiment of the present invention.

[0008] In this invention, the display panel includes a display area and a non-display area; the non-display area includes a first non-display area and a second non-display area disposed on opposite sides of the display area along a first direction; and a third non-display area and a fourth non-display area disposed on opposite sides of the display area along a second direction. The display area is provided with pixel circuit rows arranged along the first direction and a first scan signal line extending along the first direction. The first scan signal line is connected to the corresponding pixel circuit row, and a shift register unit is used to output a scan signal to the corresponding first scan signal line; the fourth non-display area includes a bonding area for bonding a driver chip or a flexible circuit board. In this invention, the shift register unit is disposed in one of the display area, the third non-display area, and the fourth non-display area, avoiding the shift register unit being disposed in the first non-display area and the second non-display area, reducing the width of the first non-display area and the second non-display area, realizing a narrow bezel design along the first direction for the display screen, especially a transparent large-size screen, and further realizing the goal of "borderless on both sides" for the transparent large-size screen. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of the structure of a display panel in the prior art; Figure 2 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention; Figure 5 for Figure 2 A partial structural diagram of the central display panel; Figure 6 A partial structural schematic diagram of another display panel provided in an embodiment of the present invention; Figure 7 for Figure 3 A magnified schematic diagram of the central display panel; Figure 8 for Figure 7 A partial structural diagram of the display area of ​​the central display panel; Figure 9 A partial structural schematic diagram of another display panel provided in an embodiment of the present invention; Figure 10 This is a partial layout diagram of a display panel provided in an embodiment of the present invention; Figure 11 for Figure 10 A schematic diagram of the third metal layer in the middle; Figure 12 for Figure 10 A schematic diagram of the fourth metal layer in the middle; Figure 13A partial layout diagram of another display panel provided in an embodiment of the present invention; Figure 14 for Figure 13 A schematic diagram of the third metal layer in the middle; Figure 15 for Figure 13 A schematic diagram of the fourth metal layer in the middle; Figure 16 for Figure 13 A schematic diagram of the fifth metal layer in the middle; Figure 17 This is a schematic diagram of another third metal layer provided in an embodiment of the present invention; Figure 18 This is a schematic diagram of another fourth metal layer provided in an embodiment of the present invention; Figure 19 This is a schematic diagram of another third metal layer provided in an embodiment of the present invention; Figure 20 This is a schematic diagram of another fourth metal layer provided in an embodiment of the present invention; Figure 21 This is a schematic diagram of another fifth metal layer provided in an embodiment of the present invention; Figure 22 This is a schematic diagram of the structure of a splicing display panel provided in an embodiment of the present invention; Figure 23 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0010] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0011] Figure 1 This is a schematic diagram of a display panel in the prior art. The display panel includes a display area AA'. Shift register circuits 11' are arranged on the left and right sides of the display area AA', resulting in a large width of the left and right bezels, which affects the screen display effect. To solve the above problems and achieve a narrow bezel or borderless design, this embodiment of the invention provides a display panel, such as... Figures 2 to 4 As shown, Figure 2 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Figure 3 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. Figure 4This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. The display panel includes: a display area AA; a first non-display area NA1 and a second non-display area NA2 disposed on opposite sides of the display area AA along a first direction X; a third non-display area NA3 and a fourth non-display area NA4 disposed on opposite sides of the display area AA along a second direction Y; the first direction X and the second direction Y intersect. The display area AA includes multiple pixel circuits 111; the multiple pixel circuits 111 are arranged along the first direction X to form a pixel circuit row 11; the display panel also includes multiple first scan signal lines 12 extending along the first direction X; the first scan signal lines 12 are electrically connected to the pixel circuits of the corresponding pixel circuit row 11; the fourth non-display area NA4 includes a bonding area 13; the bonding area 13 is used to bond a driver chip or a flexible circuit board. The shift register 14 includes multiple cascaded shift register units 141; the shift register units 141 are used to output scan signals to the corresponding first scan signal line 12; the shift register 14 is located in one of the display area AA, the third non-display area NA3, and the fourth non-display area NA4.

[0012] The display panel includes a display area AA and a non-display area NA that at least partially surrounds the display area AA. The display area AA includes a plurality of pixel circuits 111. The pixel circuits 111 include pixel driving circuits and corresponding light-emitting elements ( Figure 2 (Not shown in the image). The pixel driving circuit provides driving current to the corresponding light-emitting element. In this embodiment, the non-display area NA is arranged around the display area AA. The non-display area NA may include a first non-display area NA1, a second non-display area NA2, a third non-display area NA3, and a fourth non-display area NA4. In a plane parallel to the substrate 21, a first direction X and a second direction Y may be included. The first direction X and the second direction Y are intersecting. Optionally, the first direction X and the second direction Y may be perpendicular to each other. Along the first direction X, the first non-display area NA1 and the second non-display area NA2 are respectively arranged on opposite sides of the display area AA; along the second direction Y, the third non-display area NA3 and the fourth non-display area NA4 are respectively arranged on opposite sides of the display area AA. The fourth non-display area NA4 may be provided with a bonding area 13. The bonding area 13 is used to bond the driving chip that provides driving signals to the pixel circuit 111 of the display area AA, or the bonding area 13 is used to bond the flexible circuit board that provides driving signals to the pixel circuit 111 of the display area AA. This embodiment illustrates the bonding of the driver chip IC in the bonding area 13 as an example. The flexible circuit board (FPC) transmits the driving signal to the driver chip IC so that the driver chip IC drives the pixel circuit 111.

[0013] In the display area AA, multiple pixel circuits 111 are arranged along a first direction X to form a pixel circuit row 11. The display panel includes a first scan signal line 12 extending along the first direction X. The first scan signal line 12 is used to provide a scan signal to the corresponding pixel circuit row 11. The display panel also includes a shift register 14, which includes multiple cascaded shift register units 141. The shift register units 141 can output scan signals to the corresponding first scan signal line 12. Optionally, such as Figure 2 As shown, shift register 14 can be located within display area AA, or, as... Figure 3 As shown, shift register 14 can be located within the fourth non-display area NA4, or, as... Figure 4 As shown, shift register 14 can be located in the third non-display area NA3. In this embodiment, shift register 14 can be located in one of the display area AA, the third non-display area NA3, and the fourth non-display area NA4, instead of in the first non-display area NA1 and the second non-display area NA2. This results in a narrower "left and right bezels" on the display panel, which is beneficial for achieving the goal of "borderless left and right sides".

[0014] In this embodiment of the invention, the display panel includes a display area and a non-display area; the non-display area includes a first non-display area and a second non-display area disposed on opposite sides of the display area along a first direction; and a third non-display area and a fourth non-display area disposed on opposite sides of the display area along a second direction. The display area is provided with pixel circuit rows arranged along the first direction and a first scan signal line extending along the first direction. The first scan signal line is connected to the corresponding pixel circuit row, and a shift register unit is used to output a scan signal to the corresponding first scan signal line; the fourth non-display area includes a bonding area for bonding a driver chip or a flexible circuit board. In this invention, the shift register unit is disposed in one of the display area, the third non-display area, and the fourth non-display area, avoiding the shift register unit being disposed in the first non-display area and the second non-display area, reducing the width of the first non-display area and the second non-display area, realizing the narrow bezel design along the first direction for the display screen, especially the transparent large-size screen, and further realizing the goal of "borderless on the left and right sides" for the transparent large-size screen.

[0015] The above is the core idea of ​​this invention. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0016] Figure 5 for Figure 2 A partial structural diagram of the central display panel. (Reference) Figure 2 and Figure 5Optionally, the shift register 14 can be located in the display area AA; multiple cascaded shift register units 141 are arranged sequentially along the second direction Y; the display area AA includes multiple pixel circuit areas 16; the pixel circuit 111 includes a device layout area 161 and a transparent area 162; along the first direction X, the difference between the center spacing L1 of adjacent pixel circuit areas 16 and the size D1 of the pixel circuit 111 is greater than a first set threshold. When the shift register 14 is located in the display area AA, the shift register units 141 are cascaded sequentially along the second direction Y. In this embodiment, the display area AA can be divided into multiple pixel circuit areas 16. It should be noted that the pixel circuit area 16 is a virtual area set for the pixel circuit 111 in this embodiment, and is not an actual existing area. In this embodiment, the display panel can be a transparent display panel, and the pixel circuit 111 includes a device layout area 161 and a transparent area 162. The device layout area 161 can be used to set pixel driving circuits and corresponding light-emitting elements. In this embodiment, the difference between the center spacing L1 (the dimension of the pixel circuit area 16 along the first direction X) of adjacent pixel circuit areas 16 and the dimension D1 of pixel circuit 111 is set to be greater than a first preset threshold, so as to reserve space for the dense compression of pixel circuits 111. In this embodiment, the value of the first preset threshold can be set according to the size of the compression space. For example Figure 5 As shown, because the shift register unit 141 occupies part of the display area, there is compression between some pixel circuits 111. This embodiment achieves this compression by adjusting the value of the first set threshold. Based on the size difference between the pixel circuit area 16 and the pixel circuits 111, it is possible to maintain the same resolution as without VSR in AA (the shift register unit is located in the display area) while achieving VSR in AA, thus improving the display effect of the display panel.

[0017] Figure 6 This is a partial structural diagram of another display panel provided in an embodiment of the present invention. Optionally, along the first direction X, the display area may include a first display area AA1 and a second display area AA2 disposed on at least one side of the first display area AA1; one pixel circuit area 16 in the first display area AA1 is provided with one pixel circuit 111; along the first direction X, M pixel circuits 111 are disposed in N adjacent pixel circuit areas 16; M>N; M and N are integers. The second display area AA2 may be disposed on one or both sides of the first display area AA1 along the first direction X. In the first display area AA1, one pixel circuit area 16 can be correspondingly provided with one pixel circuit 111, while in the second display area AA2, the pixel circuits 111 need to be densely packed and compressed to maintain a high resolution, such as... Figure 6As shown, along the first direction X, M pixel circuits 111 are provided in adjacent N pixel circuit areas 16, and the value of M must be greater than N. For example, N+1 pixel circuits 111 are provided in adjacent N pixel circuit areas 16. Figure 6 The example shown is an illustration of four pixel circuits 111 arranged in three adjacent pixel circuit areas 16. In this embodiment, the size of one pixel circuit 111 is set to be smaller than the size of one pixel circuit area 16, which facilitates the dense arrangement of the second display area AA2 and maintains the display effect of the display panel.

[0018] Figure 7 for Figure 3 A magnified structural diagram of the central display panel is provided for further reference. Figure 3 , Figure 5 and Figure 7 Optionally, the shift register 14 can be located in the third non-display area NA3 and the fourth non-display area NA4. The shift register 14 includes multiple shift register units 141 cascaded along the first direction X. The display panel also includes multiple second scan signal lines 15 extending along the second direction Y. The second scan signal lines 15 are electrically connected to the corresponding first scan signal lines 12. In this embodiment, when the shift register 14 is located in the third non-display area NA3 or the fourth non-display area NA4, the shift register 14 includes multiple shift register units 141 cascaded along the first direction X, and the display panel also includes second scan signal lines 15 extending along the second direction Y. Then, the shift register units 141 transmit scan signals to the corresponding first scan signal lines 12 through the second scan signal lines 15, so that the first scan signal lines 12 provide scan signals for the corresponding pixel circuit row 11, realizing the row-by-row scanning of the pixel circuit 111. Optionally, as... Figure 7 As shown, when the shift register 14 is located on the bottom border (fourth non-display area NA4), the shift register 14 can be located between the display area AA and the binding area 13. For example, the binding area 13 near the display area AA also has a fanout line connecting the driver chip IC and the data signal line 18. In this embodiment, it can be located in the area between the fanout line and the display area AA. When the size of the display panel along the first direction X is large, multiple shift registers 14 can be set, and the multiple shift registers 14 are set sequentially along the first direction X. When the shift register 14 is located in the third non-display area NA3 or the fourth non-display area NA4, the setting width of the first non-display area NA1 and the second non-display area NA2 can be reduced, achieving the design goal of no left or right borders.

[0019] Figure 8 for Figure 7A partial structural diagram of the display area of ​​the central display panel. Optionally, the display area may include multiple pixel circuit areas 16; the pixel circuit 111 includes a device layout area 161 and a transparent area 162; along the first direction X, the difference between the distance L1 between the centers of adjacent pixel circuit areas 16 and the size D1 of the pixel circuit 111 is less than or equal to a first set threshold; one pixel circuit 111 is provided in each pixel circuit area 16 in the display area AA. When the shift register 14 is set in the third non-display area NA3 or the fourth non-display area NA4, the pixel circuits 111 in the display area AA can be evenly arranged without dense arrangement, so the size D1 of the pixel circuit 111 can be set close to the size of the pixel circuit area 16 (the distance L1 between the centers of adjacent pixel circuit areas 16), and one pixel circuit 111 can be provided for each pixel circuit area 16. In this embodiment, the difference between L1 and D1 is less than or equal to the first set threshold, for example, as Figure 8 As shown, D1 can be close to L1, thus the device layout area 161 and the transparent area 162 have a larger setting area, which further realizes transparent display while maintaining a high resolution.

[0020] Figure 9 This is a partial structural diagram of another display panel provided in an embodiment of the present invention. Figure 10 This is a partial layout diagram of a display panel provided in an embodiment of the present invention. Optionally, the display panel may include: a substrate 21; and a pixel circuit layer disposed on one side of the substrate 21; the pixel circuit layer includes multiple metal layers for forming pixel circuits 111 (including a device layout area 161 and a transparent area 162); the display panel also includes multiple data signal lines 18 extending along a second direction Y; the multiple pixel circuits 111 are arranged along the second direction Y to form a pixel circuit column 17; the data signal lines 18 are electrically connected to the pixel circuits 111 of the corresponding pixel circuit column 17 for outputting data signals to the corresponding pixel circuits 111; the data signal lines 18 and the second scan signal lines 15 are located on different metal layers. Figure 9 and Figure 10 As shown, in a direction perpendicular to the substrate 21, the display panel may include multiple metal layers (with an insulating layer disposed between adjacent metal layers), and the multiple metal layers may form an array of pixel circuits 111. The display panel also includes data signal lines 18 extending along a second direction Y, and the pixel circuits 111 are arranged along the second direction Y to form a pixel circuit column 17, and the data signal lines 18 are used to provide data signals to the corresponding pixel circuit column 17. Figure 9To distinguish between the data signal line 18 and the second scan signal line 15, different types of line segments are used for identification. The line segment type does not represent the actual structure of the signal line. In this embodiment, the data signal line 18 and the second scan signal line 15 are located on different metal layers, thereby reducing the parasitic capacitance between the data signal line 18 and the second scan signal line 15, improving the driving accuracy of the pixel circuit, and improving the display accuracy of the display panel.

[0021] Continue to refer to Figure 10 Optionally, the display panel may include a pixel circuit layer comprising: a first metal layer 22 disposed on a substrate 21; the first metal layer 22 having a gate layer of a transistor of the pixel circuit and a first electrode of a capacitor; a capacitor metal layer 26 disposed on the side of the first metal layer 22 away from the substrate 21; the capacitor metal layer 26 having a second electrode of a capacitor; a second metal layer 23 disposed on the side of the capacitor metal layer 26 away from the substrate 21; the second metal layer 23 having a first scan signal line 12; a third metal layer 24 disposed on the side of the second metal layer 23 away from the substrate 21; the third metal layer 24 having a data signal line 18 and a first power signal line PVDD; a fourth metal layer 25 disposed on the side of the third metal layer 24 away from the substrate 21; the fourth metal layer 25 having a second scan signal line 15 and a second power signal line PVEE. In this embodiment, the pixel circuit layer may include a first metal layer 22, a capacitor metal layer 26, a second metal layer 23, a third metal layer 24, and a fourth metal layer 25 sequentially away from the substrate 21. Figure 11 for Figure 10 A schematic diagram of the third metal layer in the middle. Figure 12 for Figure 10 A schematic diagram of the fourth metal layer is shown below. Figures 10 to 12As shown, the first metal layer 22 can form the gate of each transistor and the first plate of the capacitor; the capacitor metal layer 26 can provide the second plate of the capacitor. The second metal layer 23 can be provided with a first scan signal line 12 extending along the first direction X, the third metal layer 24 can be provided with a data signal line 18 extending along the second direction Y and a first power signal line PVDD, and the fourth metal layer 25 can be provided with a second scan signal line 15 and a second power signal line PVEE extending along the second direction Y. It should be noted that when the second scan signal line 15 in the fourth metal layer 25 is electrically connected to the first scan signal line 12 in the second metal layer 23, it needs to pass through the third metal layer 24. Therefore, in this embodiment, the third metal layer 24 needs to be provided with a clearance position so that the fourth metal layer 25 and the second metal layer 23 can be connected. In this embodiment, the second scan signal line 15 is provided in the fourth metal layer 25, and the data signal line 18 is provided in the third metal layer 24, so that the second scan signal line 15 and the data signal line 18 are located in different metal layers, reducing the parasitic capacitance between the second scan signal line 15 and the data signal line 18. In another example of this embodiment, the first scan signal line 12 may also be disposed on the first metal layer 22. This embodiment does not specifically limit the specific film layer of the first scan signal line 12. When the pixel circuit needs to set multiple first scan signal lines 12 to drive different transistors, some of the first scan signal lines 12 can be disposed on the first metal layer 22, and some can be disposed on the second metal layer 23. It should be noted that when multiple first scan signal lines 12 need to be set, the fourth metal layer 25 needs to correspondingly set multiple second scan signal lines 15 to achieve electrical connection between the first scan signal lines 12 and the shift register 14 of the third non-display area NA3 or the fourth non-display area NA4.

[0022] Optionally, the capacitor metal layer 26 may also be provided with a first branch 31 of the reference voltage signal line VREF along the first direction X; the capacitor metal layer 26 may also be provided with a second branch 32 of the reference voltage signal line VREF along the second direction Y. In this embodiment, a reference voltage signal line VREF is also provided. Figure 10 As shown, the reference voltage signal line VREF can be grid-shaped. For example, the reference voltage signal line VREF may include a first branch 31 extending along a first direction X and a second branch 32 extending along a second direction Y. The grid-shaped reference voltage signal line VREF improves the display uniformity of the entire display panel and also improves the uniformity of light transmission of the entire display panel.

[0023] Optionally, the third metal layer 24 may also be provided with a first switching terminal 241; the first switching terminal 241 is disconnected from the data signal line 18 and the first power signal line PVDD; the first switching terminal 241 is used to connect the first scan signal line 12 and the second scan signal line 15; in the direction perpendicular to the substrate 21, the projections of the first scan signal line 12 and the second scan signal line 15 overlap with the projection of the first switching terminal 241. In this embodiment, the first scan signal line 12 provided on the second metal layer 23 and the second scan signal line 15 provided on the fourth metal layer 25 can be electrically connected through the first switching terminal 241 of the third metal layer 24. Since the third metal layer 24 is also provided with the data signal line 18 and the first power signal line PVDD, the data signal line 18 and the first power signal line PVDD need to be provided with clearance space to accommodate the aforementioned first switching terminal 241. In the direction perpendicular to the substrate 21, the first scan signal line 12 can at least partially overlap with the projection of the first switching terminal 241, and the second scan signal line 15 can at least partially overlap with the projection of the first switching terminal 241, facilitating the electrical connection between the first scan signal line 12 and the second scan signal line 15 by the first switching terminal 241. When the shift register 14 is set in the third non-display area NA3 or the fourth non-display area NA4, the corresponding first scan signal line 12 is connected through the second scan signal line 15 to realize the scanning of the corresponding pixel circuit row 11, reducing the bezel design of the display panel along the first direction X and achieving a bezel-less display effect.

[0024] Figure 13 This is a partial layout diagram of another display panel provided in an embodiment of the present invention. Figure 14 for Figure 13 A schematic diagram of the third metal layer in the middle. Figure 15 for Figure 13 A schematic diagram of the fourth metal layer in the middle. Figure 16 for Figure 13 The schematic diagram of the fifth metal layer shows that, optionally, the pixel circuit layer may include: a third metal layer 24, with a first power supply portion 33 provided with a data signal line 18 and a first power supply signal line PVDD; a fourth metal layer 25, disposed on the side of the third metal layer 24 away from the substrate 21; the fourth metal layer 25 is provided with a second power supply signal line PVEE; a fifth metal layer 27, disposed on the side of the fourth metal layer 25 away from the substrate 21; the fifth metal layer 27 is provided with a second power supply portion 34 provided with a second scan signal line 15 and a first power supply signal line PVDD.

[0025] In another embodiment of the present invention, the pixel circuit layer may further include a substrate 21 and a third metal layer 24, a fourth metal layer 25, and a fifth metal layer 27 disposed sequentially away from the substrate 21. Of course, a first metal layer 22, a capacitor metal layer 26, and a second metal layer 23 may also be disposed between the substrate 21 and the third metal layer 24. In this embodiment, the first metal layer 22 may also house the gate layer of the transistor in the pixel circuit, the first electrode of the capacitor, and the first scan signal line 12; the capacitor metal layer 26 may also house the second electrode of the capacitor; and the second metal layer 23 may also house the first scan signal line 12. Figures 14 to 16 As shown, the third metal layer 24 may be provided with a data signal line 18 and a first power supply portion 33 of the first power signal line PVDD; the fourth metal layer 25 may be provided with a second power signal line PVEE; and the fifth metal layer 27 may be provided with a second scan signal line 15 and a second power supply portion 34 of the first power signal line PVDD. In this embodiment, the data signal line 18 is disposed on the third metal layer 24, the second scan signal line 15 is disposed on the fifth metal layer 27, and the fourth metal layer 25 is in between. Therefore, in the direction perpendicular to the substrate, the distance between the data signal line 18 and the second scan signal line 15 is relatively large, which is beneficial to further reduce the parasitic capacitance between the data signal line 18 and the second scan signal line 15, improve the driving accuracy of the pixel circuit, and improve the display accuracy of the display panel.

[0026] Continue to refer to Figure 16 Optionally, the second power supply branch 34 may include: a second power supply branch body 341 extending along the second direction Y and a second power supply branch crossover 342 extending along the first direction X; the second power supply branch body 341 and the second power supply branch crossover 342 are electrically connected; the first power supply branch 33 and the second power supply branch body 341 are electrically connected through the second power supply branch crossover 342. In this embodiment, the second power supply branch 34 of the first power signal line PVDD includes a second power supply branch body 341 extending along the second direction Y, such as... Figure 16As shown, the width of the second power supply branch body 341 is greater than that of the second scan signal line 15. Furthermore, the second power supply branch 34 also includes a second power supply branch crossover line 342, which connects the second power supply branch body 341 and the first power supply branch 33. Thus, the first power supply branch 33 of the first power signal line PVDD of the third metal layer 24 is electrically connected to the second power supply branch 34 of the first power signal line PVDD of the fifth metal layer 27, increasing the installation area of ​​the first power signal line PVDD, improving the stability of the first power signal, and thereby improving the display effect of the display panel. Optionally, the first power supply branch 33 of the first power signal line PVDD, in addition to including a trace extending along the second direction Y, also includes an auxiliary structure. This auxiliary structure, in a plane parallel to the substrate, can overlap with the second power supply branch crossover line 342 to achieve electrical connection between the second power supply branch 34 and the first power supply branch 33.

[0027] Continue to refer to Figure 14 Optionally, the first power distribution 33 may include: a first power distribution auxiliary block 331 extending along a first direction X and a first power distribution main body 332 extending along a second direction Y; the first power distribution auxiliary block 331 and the second power distribution crossover line 342 are electrically connected through a first via 41. In this embodiment, the first power distribution 33 includes a first power distribution main body 332 (trace) extending along the second direction Y and a first power distribution auxiliary block 331 extending along the first direction X. In a direction perpendicular to the substrate, the first power distribution auxiliary block 331 and the second power distribution crossover line 342 may at least partially overlap, facilitating the electrical connection of the first power distribution auxiliary block 331 and the second power distribution crossover line 342 through the first via 41. Since the first via 41 needs to pass through the fourth metal layer 25, the fourth metal layer 25 is also provided with a clearance space 251 to form the first via 41 and to prevent the first via 41 from being electrically connected to the second power signal line PVEE of the fourth metal layer 25. In this embodiment, the first power distribution auxiliary block 331, the first power distribution main body 332, and the second power distribution 34 form a grid-like structure of the first power signal line PVDD, which improves the stability of the first power signal. Furthermore, because the first power signal line PVDD is uniformly arranged, the display uniformity of the entire display panel is improved.

[0028] Continue to refer to Figure 15Optionally, the second power signal line PVEE may include a first branch 35 extending along the first direction X and a second branch 36 extending along the second direction Y; the first branch 35 and the second branch 36 are electrically connected. The fourth metal layer 25 is provided with the second power signal line PVEE, which may include a first branch 35 extending along the first direction X and a second branch 36 extending along the second direction Y. The first branch 35 and the second branch 36 are electrically connected to form a grid-like second power signal line PVEE, improving the stability of the second power signal and enhancing the display uniformity of the display panel.

[0029] Optionally, along the first direction X, a first gap S1 is formed between two adjacent pixel circuit columns; a first power supply branch body 332, a second power supply branch body 341, and a second branch 36 are disposed in the first gap S1; in a direction perpendicular to the substrate, the second branch 36 of the same first gap S1 at least partially overlaps with the first power supply branch body 332; and / or, in a direction perpendicular to the substrate, the second branch 36 of the same first gap S1 at least partially overlaps with the second power supply branch body 341. In this embodiment, the pixel circuits are arranged along the second direction Y to form pixel circuit columns, continuing to refer to... Figure 13 A first gap S1 is formed between two adjacent pixel circuit columns. The first power branch body 332 and the second power branch body 341 of the first power signal line PVDD and the second branch 36 of the second power signal line PVEE can all be disposed in the first gap S1. The first power branch body 332, the second power branch body 341 and the second branch 36 are all in different metal layers. In the direction perpendicular to the substrate, the second branch 36 can at least partially overlap with the first power branch body 332 and the second branch 36 can also at least partially overlap with the second power branch body 341, thereby reducing the width of the first gap S1, saving the planar area occupied by the metal layer and increasing the light transmittance of the display panel.

[0030] Continue to refer to Figure 13Optionally, the pixel circuit layer may further include: a first metal layer 22 disposed on the side of the third metal layer 24 near the substrate 21; the first metal layer 22 is provided with a first scan signal line 12; the third metal layer 24 includes a second switching terminal 231; the fourth metal layer 25 includes a third switching terminal 232; the first scan signal line 12 is electrically connected to the second scan signal line 15 in sequence through the second switching terminal 231 and the third switching terminal 232; in the direction perpendicular to the substrate 21, the projection of the second switching terminal 231 overlaps with the projection of the third switching terminal 232. When the first power signal line PVDD is disposed on the third metal layer 24 and the fifth metal layer 27, and the second power signal line PVEE is disposed on the fourth metal layer 25, the first scan signal line 12 can be disposed on the first metal layer 22, and the second scan signal line 15 can be disposed on the fifth metal layer 27. The third metal layer 24 and the fourth metal layer 25 are further disposed between the first metal layer 22 and the fifth metal layer 27. The third metal layer 24 has clearance holes for the second switching terminal 231, and the fourth metal layer 25 has clearance holes for the third switching terminal 232. Thus, the first scan signal line 12 sequentially passes through the second switching terminal 231 and the third switching terminal 232 to electrically connect with the second scan signal line 15. In this embodiment, the second switching terminal 231 and the third switching terminal 232 at least partially overlap, facilitating the first scan signal line 12 to cross at least one film layer to electrically connect with the second scan signal line 15, thereby enabling the shift register to be disposed on the top and bottom edges, achieving a narrow bezel design on the left and right sides.

[0031] Optionally, a first gap S1 is formed between two adjacent pixel circuit columns 17 along the first direction X; a first power supply branch body 332, a second power supply branch body 341, and a second branch 36 are disposed in the first gap S1; the first gap S1 includes a first scan signal switching hole setting area 252; the first scan signal switching hole setting area 252 is used to set a second through hole 42; the second through hole 42 is used to set a second switching terminal 231 and a third switching terminal 232; in the direction perpendicular to the substrate, the first power supply branch body 332, the second power supply branch body 341, and the second branch 36 do not overlap with the first scan signal switching hole setting area 252. In this embodiment, the trace extending along the second direction Y can be disposed within the first gap S1 formed between two adjacent pixel circuit columns 17. The first power supply branch body 332 and the second power supply branch body 341 that transmit the first power signal, as well as the second branch 36 that transmits the second power signal, are all disposed in the first gap S1, reducing the width of the first gap and increasing the light transmittance of the display panel. In order to connect the first scan signal line 12 and the second scan signal line 15 through the second through hole 42, the first power supply branch body 332 and the second branch 36 are both provided with a first scan signal switching hole setting area 252. In this way, space is reserved for setting the second through hole 42 by sacrificing the trace width, so as to achieve insulation between the first power supply branch body 332 or the second branch 36 and the second through hole 42. In this embodiment, the first power supply branch body 332, the second power supply branch body 341 and the second branch 36 do not overlap with the first scan signal switching hole setting area 252, so as to achieve electrical insulation between the second switching terminal 231 and the first power supply branch body 332, and to achieve electrical insulation between the third switching terminal 232 and the second branch 36.

[0032] Optionally, along the first direction X, the data signal line 18 can be disposed on the first side of the first power supply main body 332; along the first direction X, the second scan signal line 15 can be disposed on the second side of the second power supply main body 341; the second side is the side opposite to the first side. In this embodiment, one of the opposite sides of the first power supply main body 332 and the second power supply main body 341 along the first direction X can be referred to as the first side, and similarly, one of the opposite sides of the first power supply main body 332 and the second power supply main body 341 along the first direction X can be referred to as the second side. In the third metal layer 24, the data signal line 18 can be disposed on the first side of the first power supply main body 332; in the fifth metal layer 27, the second scan signal line 15 can be disposed on the second side of the second power supply main body 341. Then, in a plane parallel to the substrate, the lateral spacing between the data signal line 18 and the second scan signal line 15 is larger, reducing the voltage drop (IR drop), improving the accuracy of the data signal and the scan signal, and thus improving the display effect of the display panel.

[0033] Optionally, a first passivation layer may be disposed on the side of the fifth metal layer 27 away from the fourth metal layer 25. In this embodiment, a first passivation layer may be disposed on the side of the fifth metal layer 27 away from the substrate. The first passivation layer is an inorganic material with high density and physical stability, which takes into account both insulation and process compatibility, improves the protection performance of the pixel circuit, and effectively prevents water and oxygen intrusion. Optionally, a first insulating layer may be disposed between the fourth metal layer 25 and the fifth metal layer 27; the first insulating layer includes a first planarization layer; or, the first insulating layer includes a first planarization layer and a second passivation layer. A first insulating layer is also disposed between the fourth metal layer 25 and the fifth metal layer 27. The first insulating layer can be a single layer or a multi-layer stacked structure. For example, the first insulating layer may include a first planarization layer, or it may include a first planarization layer and a second passivation layer. The second passivation layer can further protect the pixel circuit and improve the reliability of the display panel.

[0034] Figure 17 This is a schematic diagram of another third metal layer provided in an embodiment of the present invention. Figure 18 This is a schematic diagram of another fourth metal layer provided in an embodiment of the present invention. Optionally, the pixel circuit layer may include: a third metal layer 24, having a first power supply portion 33 of a data signal line 18 and a first power supply signal line PVDD; a fourth metal layer 25, disposed on the side of the third metal layer 24 away from the substrate; the fourth metal layer 25 having a second power supply portion 34 of a second scan signal line 15 and a first power supply signal line PVDD; and a fifth metal layer ( Figure 17 and Figure 18 (Not shown in the image) is disposed on the side of the fourth metal layer 25 away from the substrate; the fifth metal layer is provided with the second power signal line PVEE. In another example of this embodiment, the data signal line 18 and the first power portion 33 are disposed on the third metal layer 24, and the second scan signal line 15 and the second power portion 34 are disposed on the fourth metal layer 25. The data signal line 18 and the second scan signal line 15 are located on different film layers, which reduces the parasitic capacitance between the data signal line 18 and the second scan signal line 15, avoids signal crosstalk, improves the driving accuracy of the pixel circuit, and improves the display accuracy of the display panel. The second power signal line PVEE can be disposed on the fifth metal layer. This embodiment also implements a mesh structure of the first power signal line PVDD and the second power signal line PVEE to improve the uniformity of the panel.

[0035] Figure 19 This is a schematic diagram of another third metal layer provided in an embodiment of the present invention. Figure 20 This is a schematic diagram of another fourth metal layer provided in an embodiment of the present invention. Figure 21This is a schematic diagram of another fifth metal layer provided in an embodiment of the present invention. Optionally, the pixel circuit layer may include: a third metal layer 24, on which a third power portion 37 of a data signal line 18 and a second power signal line PVEE is disposed; a fourth metal layer 25, disposed on the side of the third metal layer 24 away from the substrate; the fourth metal layer 25 is disposed on the side of the fourth metal layer 25 away from the substrate; the fifth metal layer 27 is disposed on the side of the fourth metal layer 25 away from the substrate; the fifth metal layer 27 is disposed on the side of the fourth metal layer 25 away from the substrate; the fifth metal layer 27 is disposed on the side of the fifth metal layer 27 with a second scan signal line 15 and a fourth power portion 38 of the second power signal line PVEE. In another example of this embodiment, the third power portion 37 of the second power signal line PVEE can be disposed on the third metal layer 24, and the fourth power portion 38 of the second power signal line PVEE can be disposed on the fifth metal layer 27. Then, the second power signal line PVEE forms a network structure, and the first power signal line PVDD forms a network structure on the fourth metal layer 25, thereby achieving uniform light transmission of the display panel. Furthermore, the data signal line 18 and the second scan signal line 15 are located in different film layers, which reduces the parasitic capacitance between the data signal line 18 and the second scan signal line 15, avoids crosstalk between signals, improves the driving accuracy of the pixel circuit, and improves the display accuracy of the display panel.

[0036] Continue to refer to Figure 19 and Figure 21 Optionally, the fourth power supply section 38 may include: a fourth power supply section body 381 extending along the second direction Y and a fourth power supply section crossover 382 extending along the first direction X; the third power supply section 37 includes: a third power supply section auxiliary block 371 extending along the first direction X and a third power supply section body 372 extending along the second direction Y; the third power supply section auxiliary block 371 and the fourth power supply section body 381 are electrically connected through the fourth power supply section crossover 382. When the third power supply section 37 of the second power signal line PVEE is disposed on the third metal layer 24, and the fourth power supply section 38 of the second power signal line PVEE is disposed on the fifth metal layer 27, the third power supply section 37 and the fourth power supply section 38 are electrically connected through the fourth power supply section crossover 382. Specifically, the fourth power supply section 38 includes the fourth power supply section main body 381 and the fourth power supply section crossover line 382; the third power supply section 37 includes the third power supply section auxiliary block 371 and the third power supply section main body 372. The third power supply section auxiliary block 371 and the fourth power supply section main body 381 are electrically connected through the fourth power supply section crossover line 382, ​​so that the second power signal line PVEE forms a grid, improving the uniformity of the display panel.

[0037] This invention also provides a splicing display panel. Figure 22 This is a schematic diagram of the structure of a splicing display panel provided in an embodiment of the present invention, as shown below. Figure 22As shown, the splicing display panel provided in this embodiment of the invention includes the display panel 200 described in any embodiment of the invention. The splicing display panel may include multiple display panels 200, such as... Figure 22 As shown, in this embodiment, the shift register 14 of the display panel 200 is located on the top and bottom bezels, and a borderless design can also be achieved after splicing. The spliced ​​display panel can be used to realize large-size transparent or non-transparent screens for use in shop window displays, advertising walls, and cultural relic displays, etc.

[0038] This invention also provides a display device. Figure 23 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, such as... Figure 23 As shown, the display device provided in this embodiment of the invention includes the display panel 200 described in any embodiment of the invention. The display device in this embodiment of the invention includes the technical features of the display panel provided in any embodiment of the invention, and possesses the beneficial effects of the corresponding technical features, which will not be elaborated here.

[0039] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that, include: Display area; a first non-display area and a second non-display area disposed on opposite sides of the display area along a first direction; a third non-display area and a fourth non-display area disposed on opposite sides of the display area along a second direction; the first direction and the second direction intersect; The display area includes multiple pixel circuits; the multiple pixel circuits are arranged along the first direction to form a pixel circuit row; the display panel also includes multiple first scan signal lines extending along the first direction; the first scan signal lines are electrically connected to the pixel circuits corresponding to the pixel circuit rows; the fourth non-display area includes a bonding area; the bonding area is used to bond a driver chip or a flexible circuit board; The shift register includes multiple cascaded shift register units; the shift register units are used to output scan signals to the corresponding first scan signal lines; the shift register is located in one of the display area, the third non-display area, and the fourth non-display area.

2. The display panel according to claim 1, characterized in that, The shift register is located in the display area; multiple cascaded shift register units are arranged sequentially along the second direction; the display area includes multiple pixel circuit areas; the pixel circuit includes a device layout area and a transparent area; Along the first direction, the difference between the distance between the centers of adjacent pixel circuit regions and the size of the pixel circuit is greater than a first set threshold.

3. The display panel according to claim 2, characterized in that, Along the first direction, the display area includes a first display area and a second display area disposed on at least one side of the first display area; In the first display area, one pixel circuit is provided in each pixel circuit area; Along the first direction, M pixel circuits are disposed in adjacent N pixel circuit regions; M>N; M and N are integers.

4. The display panel according to claim 1, characterized in that, The shift register is located in the third non-display area and the fourth non-display area; The shift register includes multiple shift register units cascaded along the first direction; the display panel also includes multiple second scan signal lines extending along the second direction; the second scan signal lines are electrically connected to the corresponding first scan signal lines.

5. The display panel according to claim 4, characterized in that, The display area includes multiple pixel circuit areas; the pixel circuit includes a device layout area and a transparent area. Along the first direction, the difference between the distance between the centers of adjacent pixel circuit regions and the size of the pixel circuit is less than or equal to a first set threshold. The display area has one pixel circuit in each pixel circuit area.

6. The display panel according to claim 4, characterized in that, include: A substrate; and a pixel circuit layer disposed on one side of the substrate; the pixel circuit layer includes a plurality of metal layers for forming the pixel circuit; The display panel further includes multiple data signal lines extending along the second direction; multiple pixel circuits are arranged along the second direction to form a pixel circuit column; the data signal lines are electrically connected to the pixel circuits corresponding to the pixel circuit columns, and are used to output data signals to the corresponding pixel circuits; The data signal line and the second scan signal line are located in different metal layers.

7. The display panel according to claim 6, characterized in that, include: The pixel circuit layer includes: A first metal layer is disposed on the substrate; the first metal layer is provided with the gate layer of the transistor of the pixel circuit and the first plate of the capacitor; A capacitor metal layer is disposed on the side of the first metal layer away from the substrate; the capacitor metal layer is provided with the second electrode of the capacitor; A second metal layer is disposed on the side of the capacitor metal layer away from the substrate; the second metal layer is provided with the first scan signal line; A third metal layer is disposed on the side of the second metal layer away from the substrate; the third metal layer is provided with the data signal line and the first power signal line; A fourth metal layer is disposed on the side of the third metal layer away from the substrate; the fourth metal layer is provided with the second scan signal line and the second power signal line.

8. The display panel according to claim 7, characterized in that, The capacitor metal layer is further provided with a first branch of the reference voltage signal line along the first direction; The capacitor metal layer is further provided with a second branch of the reference voltage signal line along the second direction.

9. The display panel according to claim 7, characterized in that, The third metal layer is further provided with a first switching terminal; the first switching terminal is disconnected from the data signal line and the first power signal line; the first switching terminal is used to connect the first scan signal line and the second scan signal. In a direction perpendicular to the substrate, both the first scan signal line and the second scan signal overlap with the projection of the first switching terminal.

10. The display panel according to claim 6, characterized in that, The pixel circuit layer includes: The third metal layer is provided with a first power supply portion of the data signal line and the first power supply signal line; A fourth metal layer is disposed on the side of the third metal layer away from the substrate; the fourth metal layer is provided with a second power signal line; A fifth metal layer is disposed on the side of the fourth metal layer away from the substrate; the fifth metal layer is provided with a second power supply portion of the second scan signal line and the first power supply signal line.

11. The display panel according to claim 10, characterized in that, The second power supply section includes: a second power supply section body extending along the second direction and a second power supply section crossover extending along the first direction; the second power supply section body and the second power supply section crossover are electrically connected. The first power supply section and the main body of the second power supply section are electrically connected via a cross-line connection of the second power supply section.

12. The display panel according to claim 11, characterized in that, The first power supply section includes: a first power supply section auxiliary block extending along the first direction and a first power supply section main body extending along the second direction; The first power supply auxiliary block and the second power supply crossover are electrically connected through the first through hole.

13. The display panel according to claim 11, characterized in that, The second power signal line includes a first branch extending along the first direction and a second branch extending along the second direction; the first branch and the second branch are electrically connected.

14. The display panel according to claim 13, characterized in that, Along the first direction, a first gap is formed between two adjacent pixel circuit columns; the first power supply branch body, the second power supply branch body, and the second branch are disposed in the first gap; In a direction perpendicular to the substrate, the second branch of the same first gap at least partially overlaps with the main body of the first power supply section; And / or, In a direction perpendicular to the substrate, the second branch of the same first gap at least partially overlaps with the main body of the second power supply portion.

15. The display panel according to claim 14, characterized in that, The pixel circuit layer further includes: A first metal layer is disposed on the side of the third metal layer near the substrate; the first metal layer is provided with the first scan signal line; The third metal layer includes a second switching terminal; the fourth metal layer includes a third switching terminal; the first scan signal line is electrically connected to the second scan signal line in sequence through the second switching terminal and the third switching terminal; In a direction perpendicular to the substrate, the projection of the second switching terminal overlaps with the projection of the third switching terminal.

16. The display panel according to claim 15, characterized in that, Along the first direction, a first gap is formed between two adjacent pixel circuit columns; the first power supply branch body, the second power supply branch body, and the second branch are disposed in the first gap; The first gap includes a first scan signal switching hole setting area; the first scan signal switching hole setting area is used to set a second through hole; the second through hole is used to set the second switching terminal and the third switching terminal; In the direction perpendicular to the substrate, the first power supply branch body, the second power supply branch body, and the second branch do not overlap with the first scan signal switching hole setting area.

17. The display panel according to claim 12, characterized in that, Along the first direction, the data signal line is disposed on the first side of the first power supply section body; Along the first direction, the second scanning signal line is disposed on the second side of the second power supply body; the second side is the side opposite to the first side.

18. The display panel according to claim 10, characterized in that, The fifth metal layer is further provided with a first passivation layer on the side away from the fourth metal layer.

19. The display panel according to claim 10, characterized in that, A first insulating layer is disposed between the fourth metal layer and the fifth metal layer; The first insulating layer includes a first planarization layer; or, The first insulating layer includes a first planarization layer and a second passivation layer.

20. The display panel according to claim 6, characterized in that, The pixel circuit layer includes: The third metal layer is provided with a first power supply portion of the data signal line and the first power supply signal line; A fourth metal layer is disposed on the side of the third metal layer away from the substrate; the fourth metal layer is provided with a second power supply portion of the second scan signal line and the first power supply signal line; A fifth metal layer is disposed on the side of the fourth metal layer away from the substrate; the fifth metal layer is provided with a second power signal line.

21. The display panel according to claim 6, characterized in that, The pixel circuit layer includes: The third metal layer is provided with a third power supply portion of the data signal line and the second power supply signal line; A fourth metal layer is disposed on the side of the third metal layer away from the substrate; the fourth metal layer is provided with a first power signal line; A fifth metal layer is disposed on the side of the fourth metal layer away from the substrate; the fifth metal layer is provided with a fourth power supply portion of the second scan signal line and the second power supply signal line.

22. The display panel according to claim 21, characterized in that, The fourth power supply section includes: a fourth power supply section body extending along the second direction and a fourth power supply section crossover extending along the first direction; the third power supply section includes: a third power supply section auxiliary block extending along the first direction and a third power supply section body extending along the second direction. The third power supply auxiliary block and the fourth power supply main body are electrically connected via the fourth power supply cross-line.

23. A splicing display panel, characterized in that, It includes the display panel as described in any one of claims 1-22.

24. A display device, characterized in that, The display panel includes any one of claims 1-22.

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